Unified Coverage Report :: Group Instance : salt_1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3050

1

T2

7

T4

3

T5

4

auto[1]

276

1

T78

9

T118

8

T119

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	113	1			T5	1		T85	1		T76	1
auto[134217728:268435455]	93	1			T4	1		T5	1		T78	1
auto[268435456:402653183]	100	1			T28	1		T50	1		T78	1
auto[402653184:536870911]	100	1			T18	1		T142	1		T6	1
auto[536870912:671088639]	103	1			T16	2		T18	1		T76	1
auto[671088640:805306367]	103	1			T47	1		T6	1		T119	2
auto[805306368:939524095]	127	1			T29	3		T78	2		T6	3
auto[939524096:1073741823]	103	1			T99	1		T54	1		T213	1
auto[1073741824:1207959551]	119	1			T6	3		T118	1		T207	1
auto[1207959552:1342177279]	95	1			T6	1		T212	1		T144	2
auto[1342177280:1476395007]	84	1			T47	1		T28	1		T6	2
auto[1476395008:1610612735]	99	1			T6	2		T119	1		T62	5
auto[1610612736:1744830463]	103	1			T17	1		T119	1		T222	1
auto[1744830464:1879048191]	131	1			T5	1		T78	1		T6	2
auto[1879048192:2013265919]	110	1			T2	1		T18	1		T78	1
auto[2013265920:2147483647]	104	1			T4	1		T85	1		T37	1
auto[2147483648:2281701375]	103	1			T37	1		T76	1		T6	1
auto[2281701376:2415919103]	104	1			T18	1		T6	1		T45	1
auto[2415919104:2550136831]	108	1			T2	1		T16	1		T47	2
auto[2550136832:2684354559]	95	1			T2	1		T17	1		T76	1
auto[2684354560:2818572287]	94	1			T29	1		T77	1		T6	3
auto[2818572288:2952790015]	111	1			T2	2		T47	2		T29	1
auto[2952790016:3087007743]	108	1			T17	1		T29	1		T76	1
auto[3087007744:3221225471]	102	1			T85	1		T6	4		T54	2
auto[3221225472:3355443199]	115	1			T37	1		T28	2		T76	1
auto[3355443200:3489660927]	112	1			T17	1		T18	1		T28	1
auto[3489660928:3623878655]	103	1			T5	1		T78	1		T6	1
auto[3623878656:3758096383]	105	1			T2	1		T29	1		T6	3
auto[3758096384:3892314111]	98	1			T17	1		T6	2		T156	1
auto[3892314112:4026531839]	96	1			T18	1		T141	1		T6	1
auto[4026531840:4160749567]	96	1			T4	1		T16	1		T85	1
auto[4160749568:4294967295]	89	1			T2	1		T17	1		T6	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	103	1			T5	1		T85	1		T76	1
auto[0:134217727]	auto[1]	10	1			T78	2		T146	1		T148	1
auto[134217728:268435455]	auto[0]	81	1			T4	1		T5	1		T78	1
auto[134217728:268435455]	auto[1]	12	1			T213	1		T148	1		T104	2
auto[268435456:402653183]	auto[0]	94	1			T28	1		T50	1		T54	1
auto[268435456:402653183]	auto[1]	6	1			T78	1		T242	1		T104	1
auto[402653184:536870911]	auto[0]	91	1			T18	1		T142	1		T6	1
auto[402653184:536870911]	auto[1]	9	1			T118	2		T375	1		T259	1
auto[536870912:671088639]	auto[0]	92	1			T16	2		T18	1		T76	1
auto[536870912:671088639]	auto[1]	11	1			T78	2		T119	1		T144	1
auto[671088640:805306367]	auto[0]	93	1			T47	1		T6	1		T119	1
auto[671088640:805306367]	auto[1]	10	1			T119	1		T213	1		T383	1
auto[805306368:939524095]	auto[0]	122	1			T29	3		T78	1		T6	3
auto[805306368:939524095]	auto[1]	5	1			T78	1		T156	1		T144	1
auto[939524096:1073741823]	auto[0]	94	1			T99	1		T54	1		T213	1
auto[939524096:1073741823]	auto[1]	9	1			T273	2		T384	1		T385	1
auto[1073741824:1207959551]	auto[0]	110	1			T6	3		T207	1		T66	1
auto[1073741824:1207959551]	auto[1]	9	1			T118	1		T156	1		T148	1
auto[1207959552:1342177279]	auto[0]	88	1			T6	1		T212	1		T110	2
auto[1207959552:1342177279]	auto[1]	7	1			T144	2		T385	2		T391	1
auto[1342177280:1476395007]	auto[0]	76	1			T47	1		T28	1		T6	2
auto[1342177280:1476395007]	auto[1]	8	1			T118	1		T119	1		T144	1
auto[1476395008:1610612735]	auto[0]	89	1			T6	2		T62	5		T67	1
auto[1476395008:1610612735]	auto[1]	10	1			T119	1		T199	1		T148	1
auto[1610612736:1744830463]	auto[0]	92	1			T17	1		T119	1		T222	1
auto[1610612736:1744830463]	auto[1]	11	1			T145	1		T213	2		T199	1
auto[1744830464:1879048191]	auto[0]	119	1			T5	1		T6	2		T118	1
auto[1744830464:1879048191]	auto[1]	12	1			T78	1		T119	1		T260	2
auto[1879048192:2013265919]	auto[0]	102	1			T2	1		T18	1		T141	1
auto[1879048192:2013265919]	auto[1]	8	1			T78	1		T118	1		T199	1
auto[2013265920:2147483647]	auto[0]	99	1			T4	1		T85	1		T37	1
auto[2013265920:2147483647]	auto[1]	5	1			T118	1		T144	1		T375	1
auto[2147483648:2281701375]	auto[0]	93	1			T37	1		T76	1		T6	1
auto[2147483648:2281701375]	auto[1]	10	1			T213	1		T273	1		T242	1
auto[2281701376:2415919103]	auto[0]	93	1			T18	1		T6	1		T45	1
auto[2281701376:2415919103]	auto[1]	11	1			T144	1		T213	1		T242	1
auto[2415919104:2550136831]	auto[0]	104	1			T2	1		T16	1		T47	2
auto[2415919104:2550136831]	auto[1]	4	1			T387	1		T370	1		T259	1
auto[2550136832:2684354559]	auto[0]	86	1			T2	1		T17	1		T76	1
auto[2550136832:2684354559]	auto[1]	9	1			T144	1		T199	1		T283	1
auto[2684354560:2818572287]	auto[0]	87	1			T29	1		T77	1		T6	3
auto[2684354560:2818572287]	auto[1]	7	1			T213	1		T375	1		T273	1
auto[2818572288:2952790015]	auto[0]	101	1			T2	2		T47	2		T29	1
auto[2818572288:2952790015]	auto[1]	10	1			T199	1		T273	1		T104	1
auto[2952790016:3087007743]	auto[0]	99	1			T17	1		T29	1		T76	1
auto[2952790016:3087007743]	auto[1]	9	1			T148	2		T104	1		T260	1
auto[3087007744:3221225471]	auto[0]	94	1			T85	1		T6	4		T54	2
auto[3087007744:3221225471]	auto[1]	8	1			T213	1		T273	1		T277	2
auto[3221225472:3355443199]	auto[0]	103	1			T37	1		T28	2		T76	1
auto[3221225472:3355443199]	auto[1]	12	1			T146	1		T273	2		T104	1
auto[3355443200:3489660927]	auto[0]	102	1			T17	1		T18	1		T28	1
auto[3355443200:3489660927]	auto[1]	10	1			T118	1		T144	1		T385	1
auto[3489660928:3623878655]	auto[0]	93	1			T5	1		T6	1		T156	1
auto[3489660928:3623878655]	auto[1]	10	1			T78	1		T104	1		T387	1
auto[3623878656:3758096383]	auto[0]	96	1			T2	1		T29	1		T6	3
auto[3623878656:3758096383]	auto[1]	9	1			T118	1		T156	1		T273	1
auto[3758096384:3892314111]	auto[0]	90	1			T17	1		T6	2		T145	1
auto[3758096384:3892314111]	auto[1]	8	1			T156	1		T248	1		T375	2
auto[3892314112:4026531839]	auto[0]	91	1			T18	1		T141	1		T6	1
auto[3892314112:4026531839]	auto[1]	5	1			T258	1		T282	2		T388	1
auto[4026531840:4160749567]	auto[0]	91	1			T4	1		T16	1		T85	1
auto[4026531840:4160749567]	auto[1]	5	1			T144	1		T213	1		T147	1
auto[4160749568:4294967295]	auto[0]	82	1			T2	1		T17	1		T6	2
auto[4160749568:4294967295]	auto[1]	7	1			T145	1		T347	1		T385	1