Unified Coverage Report :: Group Instance : salt_6

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3053

1

T2

7

T4

3

T5

4

auto[1]

246

1

T78

1

T118

1

T156

7

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	90	1			T2	1		T18	1		T6	2
auto[134217728:268435455]	115	1			T37	1		T28	1		T6	2
auto[268435456:402653183]	87	1			T37	1		T6	1		T99	1
auto[402653184:536870911]	114	1			T18	1		T28	1		T119	2
auto[536870912:671088639]	105	1			T28	1		T56	1		T144	1
auto[671088640:805306367]	85	1			T29	1		T6	1		T54	1
auto[805306368:939524095]	83	1			T50	1		T6	2		T118	1
auto[939524096:1073741823]	111	1			T47	1		T6	3		T144	1
auto[1073741824:1207959551]	100	1			T17	1		T6	1		T118	1
auto[1207959552:1342177279]	99	1			T4	1		T76	1		T144	2
auto[1342177280:1476395007]	90	1			T5	1		T28	1		T6	4
auto[1476395008:1610612735]	108	1			T2	2		T17	1		T29	1
auto[1610612736:1744830463]	99	1			T17	1		T207	1		T156	1
auto[1744830464:1879048191]	88	1			T76	1		T78	1		T141	1
auto[1879048192:2013265919]	116	1			T6	2		T99	1		T118	1
auto[2013265920:2147483647]	105	1			T2	1		T5	1		T47	1
auto[2147483648:2281701375]	99	1			T2	1		T17	1		T76	1
auto[2281701376:2415919103]	99	1			T16	1		T85	1		T76	1
auto[2415919104:2550136831]	106	1			T47	1		T29	1		T6	2
auto[2550136832:2684354559]	110	1			T17	1		T78	1		T6	1
auto[2684354560:2818572287]	109	1			T6	3		T207	1		T255	1
auto[2818572288:2952790015]	101	1			T5	1		T18	1		T85	2
auto[2952790016:3087007743]	119	1			T4	1		T16	1		T85	1
auto[3087007744:3221225471]	102	1			T16	1		T78	1		T6	1
auto[3221225472:3355443199]	110	1			T18	1		T6	1		T156	2
auto[3355443200:3489660927]	94	1			T37	1		T29	1		T6	1
auto[3489660928:3623878655]	113	1			T4	1		T16	1		T17	1
auto[3623878656:3758096383]	112	1			T18	1		T6	1		T86	1
auto[3758096384:3892314111]	106	1			T2	1		T6	2		T207	1
auto[3892314112:4026531839]	101	1			T18	1		T28	1		T77	1
auto[4026531840:4160749567]	117	1			T5	1		T47	2		T29	1
auto[4160749568:4294967295]	106	1			T2	1		T37	1		T6	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	85	1			T2	1		T18	1		T6	2
auto[0:134217727]	auto[1]	5	1			T384	1		T385	1		T277	1
auto[134217728:268435455]	auto[0]	107	1			T37	1		T28	1		T6	2
auto[134217728:268435455]	auto[1]	8	1			T273	1		T244	1		T384	1
auto[268435456:402653183]	auto[0]	78	1			T37	1		T6	1		T99	1
auto[268435456:402653183]	auto[1]	9	1			T199	1		T381	1		T370	1
auto[402653184:536870911]	auto[0]	105	1			T18	1		T28	1		T119	2
auto[402653184:536870911]	auto[1]	9	1			T144	1		T213	1		T258	1
auto[536870912:671088639]	auto[0]	97	1			T28	1		T56	1		T62	2
auto[536870912:671088639]	auto[1]	8	1			T144	1		T248	1		T384	1
auto[671088640:805306367]	auto[0]	80	1			T29	1		T6	1		T54	1
auto[671088640:805306367]	auto[1]	5	1			T213	2		T248	1		T394	1
auto[805306368:939524095]	auto[0]	78	1			T50	1		T6	2		T118	1
auto[805306368:939524095]	auto[1]	5	1			T156	1		T383	1		T386	1
auto[939524096:1073741823]	auto[0]	105	1			T47	1		T6	3		T63	1
auto[939524096:1073741823]	auto[1]	6	1			T144	1		T248	1		T370	1
auto[1073741824:1207959551]	auto[0]	95	1			T17	1		T6	1		T119	1
auto[1073741824:1207959551]	auto[1]	5	1			T118	1		T248	1		T347	1
auto[1207959552:1342177279]	auto[0]	94	1			T4	1		T76	1		T131	1
auto[1207959552:1342177279]	auto[1]	5	1			T144	2		T394	1		T393	1
auto[1342177280:1476395007]	auto[0]	84	1			T5	1		T28	1		T6	4
auto[1342177280:1476395007]	auto[1]	6	1			T156	2		T144	1		T390	1
auto[1476395008:1610612735]	auto[0]	102	1			T2	2		T17	1		T29	1
auto[1476395008:1610612735]	auto[1]	6	1			T145	1		T283	1		T260	1
auto[1610612736:1744830463]	auto[0]	84	1			T17	1		T207	1		T54	1
auto[1610612736:1744830463]	auto[1]	15	1			T156	1		T199	1		T248	2
auto[1744830464:1879048191]	auto[0]	85	1			T76	1		T78	1		T141	1
auto[1744830464:1879048191]	auto[1]	3	1			T144	1		T213	1		T370	1
auto[1879048192:2013265919]	auto[0]	109	1			T6	2		T99	1		T118	1
auto[1879048192:2013265919]	auto[1]	7	1			T156	1		T283	1		T260	1
auto[2013265920:2147483647]	auto[0]	95	1			T2	1		T5	1		T47	1
auto[2013265920:2147483647]	auto[1]	10	1			T144	1		T347	1		T384	2
auto[2147483648:2281701375]	auto[0]	87	1			T2	1		T17	1		T76	1
auto[2147483648:2281701375]	auto[1]	12	1			T144	1		T273	2		T242	1
auto[2281701376:2415919103]	auto[0]	93	1			T16	1		T85	1		T76	1
auto[2281701376:2415919103]	auto[1]	6	1			T242	1		T244	1		T260	1
auto[2415919104:2550136831]	auto[0]	102	1			T47	1		T29	1		T6	2
auto[2415919104:2550136831]	auto[1]	4	1			T145	1		T199	1		T384	1
auto[2550136832:2684354559]	auto[0]	98	1			T17	1		T6	1		T25	1
auto[2550136832:2684354559]	auto[1]	12	1			T78	1		T213	1		T199	1
auto[2684354560:2818572287]	auto[0]	98	1			T6	3		T207	1		T255	1
auto[2684354560:2818572287]	auto[1]	11	1			T242	1		T347	1		T384	2
auto[2818572288:2952790015]	auto[0]	94	1			T5	1		T18	1		T85	2
auto[2818572288:2952790015]	auto[1]	7	1			T156	1		T213	1		T147	1
auto[2952790016:3087007743]	auto[0]	110	1			T4	1		T16	1		T85	1
auto[2952790016:3087007743]	auto[1]	9	1			T148	1		T259	1		T382	1
auto[3087007744:3221225471]	auto[0]	93	1			T16	1		T78	1		T6	1
auto[3087007744:3221225471]	auto[1]	9	1			T144	1		T199	1		T147	1
auto[3221225472:3355443199]	auto[0]	102	1			T18	1		T6	1		T156	1
auto[3221225472:3355443199]	auto[1]	8	1			T156	1		T273	1		T260	1
auto[3355443200:3489660927]	auto[0]	85	1			T37	1		T29	1		T6	1
auto[3355443200:3489660927]	auto[1]	9	1			T199	1		T147	1		T148	1
auto[3489660928:3623878655]	auto[0]	106	1			T4	1		T16	1		T17	1
auto[3489660928:3623878655]	auto[1]	7	1			T213	1		T383	1		T258	1
auto[3623878656:3758096383]	auto[0]	107	1			T18	1		T6	1		T86	1
auto[3623878656:3758096383]	auto[1]	5	1			T144	1		T244	1		T383	1
auto[3758096384:3892314111]	auto[0]	97	1			T2	1		T6	2		T207	1
auto[3758096384:3892314111]	auto[1]	9	1			T144	1		T104	1		T347	1
auto[3892314112:4026531839]	auto[0]	93	1			T18	1		T28	1		T77	1
auto[3892314112:4026531839]	auto[1]	8	1			T144	1		T213	1		T148	1
auto[4026531840:4160749567]	auto[0]	107	1			T5	1		T47	2		T29	1
auto[4026531840:4160749567]	auto[1]	10	1			T199	1		T148	1		T383	1
auto[4160749568:4294967295]	auto[0]	98	1			T2	1		T37	1		T6	2
auto[4160749568:4294967295]	auto[1]	8	1			T144	1		T104	1		T381	1