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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1581 1 T2 3 T5 2 T16 1
auto[1] 1849 1 T2 4 T4 3 T5 3


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 111 1 T2 1 T4 1 T17 1
auto[134217728:268435455] 104 1 T16 1 T76 1 T6 3
auto[268435456:402653183] 102 1 T2 1 T207 2 T119 1
auto[402653184:536870911] 116 1 T85 1 T28 1 T54 2
auto[536870912:671088639] 120 1 T29 1 T6 2 T118 1
auto[671088640:805306367] 99 1 T6 1 T212 1 T119 2
auto[805306368:939524095] 101 1 T29 1 T78 1 T6 4
auto[939524096:1073741823] 106 1 T47 1 T29 1 T78 1
auto[1073741824:1207959551] 115 1 T4 1 T6 2 T45 1
auto[1207959552:1342177279] 101 1 T141 1 T6 1 T222 1
auto[1342177280:1476395007] 104 1 T2 1 T47 1 T28 1
auto[1476395008:1610612735] 98 1 T5 1 T18 1 T29 1
auto[1610612736:1744830463] 121 1 T18 1 T85 1 T77 1
auto[1744830464:1879048191] 101 1 T18 1 T28 1 T76 1
auto[1879048192:2013265919] 92 1 T207 1 T46 2 T144 1
auto[2013265920:2147483647] 103 1 T2 2 T85 1 T76 1
auto[2147483648:2281701375] 111 1 T17 1 T37 1 T76 1
auto[2281701376:2415919103] 123 1 T2 1 T76 1 T6 3
auto[2415919104:2550136831] 123 1 T16 2 T6 2 T110 1
auto[2550136832:2684354559] 110 1 T4 1 T5 1 T18 1
auto[2684354560:2818572287] 111 1 T17 1 T47 1 T29 1
auto[2818572288:2952790015] 99 1 T18 1 T6 3 T45 1
auto[2952790016:3087007743] 109 1 T5 1 T17 1 T50 1
auto[3087007744:3221225471] 92 1 T17 1 T37 1 T28 1
auto[3221225472:3355443199] 100 1 T16 1 T17 1 T37 1
auto[3355443200:3489660927] 109 1 T6 2 T118 1 T25 1
auto[3489660928:3623878655] 117 1 T2 1 T47 1 T141 1
auto[3623878656:3758096383] 102 1 T6 1 T56 1 T45 1
auto[3758096384:3892314111] 102 1 T5 1 T29 1 T6 3
auto[3892314112:4026531839] 106 1 T29 1 T99 1 T156 1
auto[4026531840:4160749567] 92 1 T6 4 T210 1 T215 1
auto[4160749568:4294967295] 130 1 T5 1 T47 2 T28 1


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 51 1 T29 1 T119 1 T62 2
auto[0:134217727] auto[1] 60 1 T2 1 T4 1 T17 1
auto[134217728:268435455] auto[0] 58 1 T16 1 T76 1 T6 3
auto[134217728:268435455] auto[1] 46 1 T110 1 T271 1 T62 1
auto[268435456:402653183] auto[0] 53 1 T207 1 T119 1 T156 1
auto[268435456:402653183] auto[1] 49 1 T2 1 T207 1 T255 1
auto[402653184:536870911] auto[0] 63 1 T28 1 T269 1 T26 1
auto[402653184:536870911] auto[1] 53 1 T85 1 T54 2 T62 2
auto[536870912:671088639] auto[0] 55 1 T6 2 T207 1 T119 1
auto[536870912:671088639] auto[1] 65 1 T29 1 T118 1 T110 1
auto[671088640:805306367] auto[0] 45 1 T119 2 T63 1 T54 2
auto[671088640:805306367] auto[1] 54 1 T6 1 T212 1 T54 1
auto[805306368:939524095] auto[0] 45 1 T6 1 T99 1 T25 1
auto[805306368:939524095] auto[1] 56 1 T29 1 T78 1 T6 3
auto[939524096:1073741823] auto[0] 44 1 T47 1 T29 1 T78 1
auto[939524096:1073741823] auto[1] 62 1 T207 1 T63 1 T54 1
auto[1073741824:1207959551] auto[0] 57 1 T6 2 T45 1 T156 1
auto[1073741824:1207959551] auto[1] 58 1 T4 1 T54 1 T62 2
auto[1207959552:1342177279] auto[0] 48 1 T222 1 T63 2 T215 1
auto[1207959552:1342177279] auto[1] 53 1 T141 1 T6 1 T100 1
auto[1342177280:1476395007] auto[0] 55 1 T2 1 T47 1 T28 1
auto[1342177280:1476395007] auto[1] 49 1 T142 1 T6 4 T212 1
auto[1476395008:1610612735] auto[0] 49 1 T18 1 T29 1 T208 1
auto[1476395008:1610612735] auto[1] 49 1 T5 1 T6 1 T145 1
auto[1610612736:1744830463] auto[0] 58 1 T18 1 T6 1 T45 1
auto[1610612736:1744830463] auto[1] 63 1 T85 1 T77 1 T6 1
auto[1744830464:1879048191] auto[0] 40 1 T18 1 T28 1 T6 1
auto[1744830464:1879048191] auto[1] 61 1 T76 1 T25 1 T110 1
auto[1879048192:2013265919] auto[0] 47 1 T46 2 T54 1 T62 1
auto[1879048192:2013265919] auto[1] 45 1 T207 1 T144 1 T54 2
auto[2013265920:2147483647] auto[0] 44 1 T2 1 T76 1 T45 1
auto[2013265920:2147483647] auto[1] 59 1 T2 1 T85 1 T78 1
auto[2147483648:2281701375] auto[0] 45 1 T54 3 T26 1 T58 1
auto[2147483648:2281701375] auto[1] 66 1 T17 1 T37 1 T76 1
auto[2281701376:2415919103] auto[0] 57 1 T156 1 T54 2 T210 1
auto[2281701376:2415919103] auto[1] 66 1 T2 1 T76 1 T6 3
auto[2415919104:2550136831] auto[0] 54 1 T54 1 T269 1 T62 1
auto[2415919104:2550136831] auto[1] 69 1 T16 2 T6 2 T110 1
auto[2550136832:2684354559] auto[0] 48 1 T18 1 T54 1 T62 1
auto[2550136832:2684354559] auto[1] 62 1 T4 1 T5 1 T37 1
auto[2684354560:2818572287] auto[0] 52 1 T29 1 T202 1 T59 2
auto[2684354560:2818572287] auto[1] 59 1 T17 1 T47 1 T76 1
auto[2818572288:2952790015] auto[0] 45 1 T18 1 T269 1 T62 2
auto[2818572288:2952790015] auto[1] 54 1 T6 3 T45 1 T255 1
auto[2952790016:3087007743] auto[0] 41 1 T5 1 T50 1 T6 1
auto[2952790016:3087007743] auto[1] 68 1 T17 1 T141 1 T6 1
auto[3087007744:3221225471] auto[0] 38 1 T37 1 T54 1 T58 1
auto[3087007744:3221225471] auto[1] 54 1 T17 1 T28 1 T208 1
auto[3221225472:3355443199] auto[0] 44 1 T37 1 T6 1 T63 1
auto[3221225472:3355443199] auto[1] 56 1 T16 1 T17 1 T6 1
auto[3355443200:3489660927] auto[0] 49 1 T118 1 T54 2 T215 1
auto[3355443200:3489660927] auto[1] 60 1 T6 2 T25 1 T131 1
auto[3489660928:3623878655] auto[0] 51 1 T2 1 T47 1 T141 1
auto[3489660928:3623878655] auto[1] 66 1 T6 2 T56 1 T67 1
auto[3623878656:3758096383] auto[0] 40 1 T45 1 T54 2 T213 1
auto[3623878656:3758096383] auto[1] 62 1 T6 1 T56 1 T144 1
auto[3758096384:3892314111] auto[0] 44 1 T5 1 T29 1 T6 1
auto[3758096384:3892314111] auto[1] 58 1 T6 2 T156 1 T208 1
auto[3892314112:4026531839] auto[0] 55 1 T29 1 T99 1 T217 1
auto[3892314112:4026531839] auto[1] 51 1 T156 1 T54 1 T217 1
auto[4026531840:4160749567] auto[0] 47 1 T6 1 T58 1 T67 1
auto[4026531840:4160749567] auto[1] 45 1 T6 3 T210 1 T215 1
auto[4160749568:4294967295] auto[0] 59 1 T54 1 T217 1 T269 1
auto[4160749568:4294967295] auto[1] 71 1 T5 1 T47 2 T28 1

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