Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.75 99.04 98.07 98.46 100.00 99.02 98.41 91.29


Total test records in report: 1084
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T181 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3502820531 Jul 14 05:33:42 PM PDT 24 Jul 14 05:33:47 PM PDT 24 159440102 ps
T1009 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1308318651 Jul 14 05:33:40 PM PDT 24 Jul 14 05:33:44 PM PDT 24 243197262 ps
T1010 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2778845031 Jul 14 05:33:37 PM PDT 24 Jul 14 05:33:40 PM PDT 24 348689683 ps
T1011 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.2335866667 Jul 14 05:33:50 PM PDT 24 Jul 14 05:33:54 PM PDT 24 14937603 ps
T1012 /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.1920813007 Jul 14 05:33:44 PM PDT 24 Jul 14 05:33:48 PM PDT 24 15907940 ps
T1013 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.2300573616 Jul 14 05:33:40 PM PDT 24 Jul 14 05:33:50 PM PDT 24 130377107 ps
T1014 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3022778641 Jul 14 05:33:33 PM PDT 24 Jul 14 05:33:35 PM PDT 24 70480433 ps
T1015 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3595381692 Jul 14 05:33:47 PM PDT 24 Jul 14 05:33:50 PM PDT 24 27506662 ps
T1016 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.880890123 Jul 14 05:33:37 PM PDT 24 Jul 14 05:33:44 PM PDT 24 698692294 ps
T1017 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2754290731 Jul 14 05:33:31 PM PDT 24 Jul 14 05:33:33 PM PDT 24 91038965 ps
T1018 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1882996809 Jul 14 05:33:37 PM PDT 24 Jul 14 05:33:40 PM PDT 24 266106597 ps
T1019 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.1849846502 Jul 14 05:33:34 PM PDT 24 Jul 14 05:33:40 PM PDT 24 398770640 ps
T1020 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2484692091 Jul 14 05:33:45 PM PDT 24 Jul 14 05:33:51 PM PDT 24 163758828 ps
T1021 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1095134784 Jul 14 05:33:33 PM PDT 24 Jul 14 05:33:42 PM PDT 24 183561321 ps
T1022 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.1100952575 Jul 14 05:33:39 PM PDT 24 Jul 14 05:33:45 PM PDT 24 233292981 ps
T1023 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2125922491 Jul 14 05:33:44 PM PDT 24 Jul 14 05:33:48 PM PDT 24 99954418 ps
T1024 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1164417572 Jul 14 05:33:49 PM PDT 24 Jul 14 05:33:56 PM PDT 24 144784975 ps
T1025 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.4143367992 Jul 14 05:33:39 PM PDT 24 Jul 14 05:33:42 PM PDT 24 124864816 ps
T1026 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.731423540 Jul 14 05:33:36 PM PDT 24 Jul 14 05:33:39 PM PDT 24 92429376 ps
T1027 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3113967111 Jul 14 05:33:46 PM PDT 24 Jul 14 05:33:51 PM PDT 24 115410382 ps
T1028 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2670808444 Jul 14 05:33:43 PM PDT 24 Jul 14 05:33:47 PM PDT 24 56472759 ps
T182 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2310636824 Jul 14 05:33:55 PM PDT 24 Jul 14 05:34:01 PM PDT 24 436197577 ps
T175 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.258812144 Jul 14 05:33:44 PM PDT 24 Jul 14 05:33:50 PM PDT 24 125959864 ps
T1029 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1978185069 Jul 14 05:33:38 PM PDT 24 Jul 14 05:33:41 PM PDT 24 57403213 ps
T1030 /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1029260979 Jul 14 05:33:31 PM PDT 24 Jul 14 05:33:33 PM PDT 24 28912580 ps
T1031 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2085246332 Jul 14 05:33:46 PM PDT 24 Jul 14 05:33:50 PM PDT 24 62495969 ps
T1032 /workspace/coverage/cover_reg_top/4.keymgr_intr_test.743704534 Jul 14 05:33:37 PM PDT 24 Jul 14 05:33:39 PM PDT 24 10668640 ps
T1033 /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.3016831839 Jul 14 05:33:51 PM PDT 24 Jul 14 05:33:56 PM PDT 24 436608933 ps
T1034 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.108870615 Jul 14 05:33:35 PM PDT 24 Jul 14 05:33:37 PM PDT 24 71286363 ps
T176 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.1822464072 Jul 14 05:33:46 PM PDT 24 Jul 14 05:33:52 PM PDT 24 909663120 ps
T1035 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.421162960 Jul 14 05:33:54 PM PDT 24 Jul 14 05:33:57 PM PDT 24 12034803 ps
T1036 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.3728035411 Jul 14 05:33:49 PM PDT 24 Jul 14 05:33:54 PM PDT 24 56781509 ps
T1037 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1682871441 Jul 14 05:33:57 PM PDT 24 Jul 14 05:33:58 PM PDT 24 38531525 ps
T1038 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2594592853 Jul 14 05:33:43 PM PDT 24 Jul 14 05:33:45 PM PDT 24 13064000 ps
T166 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.4201824697 Jul 14 05:33:43 PM PDT 24 Jul 14 05:33:49 PM PDT 24 370075952 ps
T1039 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.3110476765 Jul 14 05:33:50 PM PDT 24 Jul 14 05:33:55 PM PDT 24 281652047 ps
T1040 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.4265845920 Jul 14 05:33:46 PM PDT 24 Jul 14 05:33:50 PM PDT 24 20402208 ps
T1041 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.4169661916 Jul 14 05:33:39 PM PDT 24 Jul 14 05:33:50 PM PDT 24 473061091 ps
T1042 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1075748421 Jul 14 05:33:41 PM PDT 24 Jul 14 05:33:44 PM PDT 24 99248807 ps
T1043 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3966078679 Jul 14 05:33:48 PM PDT 24 Jul 14 05:33:59 PM PDT 24 944903864 ps
T1044 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3915046840 Jul 14 05:33:47 PM PDT 24 Jul 14 05:33:51 PM PDT 24 16184487 ps
T1045 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.3418768910 Jul 14 05:33:58 PM PDT 24 Jul 14 05:34:00 PM PDT 24 84938555 ps
T1046 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.814626284 Jul 14 05:33:39 PM PDT 24 Jul 14 05:33:41 PM PDT 24 50802369 ps
T1047 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1253086018 Jul 14 05:33:54 PM PDT 24 Jul 14 05:33:58 PM PDT 24 591060280 ps
T1048 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2275842915 Jul 14 05:33:47 PM PDT 24 Jul 14 05:33:55 PM PDT 24 178483497 ps
T1049 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.344329421 Jul 14 05:33:45 PM PDT 24 Jul 14 05:33:59 PM PDT 24 392521067 ps
T1050 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1862255976 Jul 14 05:33:50 PM PDT 24 Jul 14 05:34:02 PM PDT 24 689847730 ps
T1051 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.388521431 Jul 14 05:34:07 PM PDT 24 Jul 14 05:34:09 PM PDT 24 14732246 ps
T1052 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.3352098376 Jul 14 05:33:40 PM PDT 24 Jul 14 05:33:50 PM PDT 24 287161069 ps
T1053 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2098514039 Jul 14 05:34:07 PM PDT 24 Jul 14 05:34:09 PM PDT 24 20704216 ps
T1054 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.1412601227 Jul 14 05:33:42 PM PDT 24 Jul 14 05:33:44 PM PDT 24 47487276 ps
T1055 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.720596052 Jul 14 05:33:58 PM PDT 24 Jul 14 05:34:00 PM PDT 24 36280250 ps
T1056 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.288224247 Jul 14 05:33:49 PM PDT 24 Jul 14 05:33:53 PM PDT 24 24615499 ps
T1057 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2982675783 Jul 14 05:33:33 PM PDT 24 Jul 14 05:33:37 PM PDT 24 161051079 ps
T1058 /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2301372912 Jul 14 05:33:48 PM PDT 24 Jul 14 05:33:53 PM PDT 24 29725520 ps
T1059 /workspace/coverage/cover_reg_top/15.keymgr_intr_test.4208468466 Jul 14 05:33:44 PM PDT 24 Jul 14 05:33:48 PM PDT 24 45362755 ps
T1060 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1754244242 Jul 14 05:33:56 PM PDT 24 Jul 14 05:33:57 PM PDT 24 65727056 ps
T1061 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1415366557 Jul 14 05:33:44 PM PDT 24 Jul 14 05:33:49 PM PDT 24 51142044 ps
T1062 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.1993319192 Jul 14 05:33:56 PM PDT 24 Jul 14 05:33:57 PM PDT 24 21041131 ps
T1063 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1283548900 Jul 14 05:33:47 PM PDT 24 Jul 14 05:33:50 PM PDT 24 39595043 ps
T1064 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1877615002 Jul 14 05:33:33 PM PDT 24 Jul 14 05:33:35 PM PDT 24 15161425 ps
T170 /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.4282501933 Jul 14 05:33:32 PM PDT 24 Jul 14 05:33:37 PM PDT 24 328220345 ps
T1065 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.568498643 Jul 14 05:33:53 PM PDT 24 Jul 14 05:33:55 PM PDT 24 14127537 ps
T1066 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.201303879 Jul 14 05:33:40 PM PDT 24 Jul 14 05:33:45 PM PDT 24 86791037 ps
T1067 /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1170919499 Jul 14 05:34:07 PM PDT 24 Jul 14 05:34:09 PM PDT 24 24399154 ps
T1068 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2108144433 Jul 14 05:33:46 PM PDT 24 Jul 14 05:33:50 PM PDT 24 79542997 ps
T1069 /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3264778960 Jul 14 05:33:39 PM PDT 24 Jul 14 05:33:48 PM PDT 24 515337552 ps
T1070 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2791415447 Jul 14 05:34:07 PM PDT 24 Jul 14 05:34:09 PM PDT 24 48067742 ps
T1071 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2017572235 Jul 14 05:33:45 PM PDT 24 Jul 14 05:33:51 PM PDT 24 467358894 ps
T1072 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.4164818853 Jul 14 05:33:40 PM PDT 24 Jul 14 05:33:44 PM PDT 24 676603028 ps
T1073 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3580619623 Jul 14 05:33:46 PM PDT 24 Jul 14 05:33:50 PM PDT 24 117600052 ps
T1074 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.905846223 Jul 14 05:33:40 PM PDT 24 Jul 14 05:33:44 PM PDT 24 75698316 ps
T1075 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2227203445 Jul 14 05:33:38 PM PDT 24 Jul 14 05:33:39 PM PDT 24 13811001 ps
T1076 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.240141771 Jul 14 05:33:32 PM PDT 24 Jul 14 05:33:35 PM PDT 24 21368374 ps
T1077 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1367163493 Jul 14 05:33:44 PM PDT 24 Jul 14 05:33:50 PM PDT 24 374343880 ps
T1078 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1011761463 Jul 14 05:33:49 PM PDT 24 Jul 14 05:33:53 PM PDT 24 80886001 ps
T1079 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2092740442 Jul 14 05:33:43 PM PDT 24 Jul 14 05:33:46 PM PDT 24 56321938 ps
T1080 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.837389085 Jul 14 05:33:57 PM PDT 24 Jul 14 05:33:58 PM PDT 24 49012078 ps
T180 /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1636359979 Jul 14 05:33:41 PM PDT 24 Jul 14 05:33:51 PM PDT 24 1484557439 ps
T1081 /workspace/coverage/cover_reg_top/22.keymgr_intr_test.3793993124 Jul 14 05:33:49 PM PDT 24 Jul 14 05:33:53 PM PDT 24 10151751 ps
T178 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2133099029 Jul 14 05:33:42 PM PDT 24 Jul 14 05:33:50 PM PDT 24 714901906 ps
T1082 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3525022726 Jul 14 05:33:34 PM PDT 24 Jul 14 05:33:46 PM PDT 24 1008615382 ps
T1083 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3608393517 Jul 14 05:33:57 PM PDT 24 Jul 14 05:33:59 PM PDT 24 152890061 ps
T1084 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.73497029 Jul 14 05:33:58 PM PDT 24 Jul 14 05:34:00 PM PDT 24 29216494 ps

Test location /workspace/coverage/default/22.keymgr_lc_disable.4090256085
Short name T5
Test name
Test status
Simulation time 352034878 ps
CPU time 4.92 seconds
Started Jul 14 06:53:19 PM PDT 24
Finished Jul 14 06:53:24 PM PDT 24
Peak memory 220256 kb
Host smart-1f18095c-3dec-403b-8b47-455a30ef37a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090256085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.4090256085
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.2895642755
Short name T6
Test name
Test status
Simulation time 6459524623 ps
CPU time 70.4 seconds
Started Jul 14 06:54:31 PM PDT 24
Finished Jul 14 06:55:45 PM PDT 24
Peak memory 222048 kb
Host smart-64a9a8ce-0afe-4f82-8f18-ac40e916c402
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895642755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.2895642755
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.4165522830
Short name T54
Test name
Test status
Simulation time 1252757607 ps
CPU time 30.85 seconds
Started Jul 14 06:54:26 PM PDT 24
Finished Jul 14 06:54:58 PM PDT 24
Peak memory 215844 kb
Host smart-720f90e3-069b-4c9d-9e58-1a1f01a812a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165522830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.4165522830
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.376947061
Short name T17
Test name
Test status
Simulation time 476732049 ps
CPU time 16.21 seconds
Started Jul 14 06:52:30 PM PDT 24
Finished Jul 14 06:52:48 PM PDT 24
Peak memory 218360 kb
Host smart-c06cb740-66a9-4367-ac13-d25fdd0b4efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376947061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.376947061
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.4224679658
Short name T13
Test name
Test status
Simulation time 798622305 ps
CPU time 9.57 seconds
Started Jul 14 06:52:22 PM PDT 24
Finished Jul 14 06:52:34 PM PDT 24
Peak memory 233648 kb
Host smart-153be3ae-7eb5-491f-b041-9393ecb9b315
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224679658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.4224679658
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.4144892014
Short name T111
Test name
Test status
Simulation time 302317950 ps
CPU time 11.51 seconds
Started Jul 14 06:53:17 PM PDT 24
Finished Jul 14 06:53:30 PM PDT 24
Peak memory 222572 kb
Host smart-7c813078-0cf3-44b3-a3ff-d3f996811581
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144892014 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.4144892014
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.3615514974
Short name T2
Test name
Test status
Simulation time 847814755 ps
CPU time 3.49 seconds
Started Jul 14 06:52:27 PM PDT 24
Finished Jul 14 06:52:31 PM PDT 24
Peak memory 214516 kb
Host smart-1fa3cf3a-38e1-43d2-af2e-35e774971240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615514974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.3615514974
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2286037219
Short name T144
Test name
Test status
Simulation time 1460783544 ps
CPU time 74.91 seconds
Started Jul 14 06:53:46 PM PDT 24
Finished Jul 14 06:55:05 PM PDT 24
Peak memory 214580 kb
Host smart-8939d457-ba44-4fbe-857e-2dff46577dc4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2286037219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2286037219
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3379264183
Short name T113
Test name
Test status
Simulation time 1461330616 ps
CPU time 13.94 seconds
Started Jul 14 05:33:55 PM PDT 24
Finished Jul 14 05:34:10 PM PDT 24
Peak memory 213888 kb
Host smart-ef79af83-4f90-4b3a-9c40-3e66cca8c23e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379264183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.3379264183
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.3128106196
Short name T9
Test name
Test status
Simulation time 303596471 ps
CPU time 3.51 seconds
Started Jul 14 06:54:18 PM PDT 24
Finished Jul 14 06:54:25 PM PDT 24
Peak memory 214784 kb
Host smart-66e05f6f-ee9b-49a5-a1b8-31cbb5f755f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128106196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.3128106196
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.831803181
Short name T62
Test name
Test status
Simulation time 2879750248 ps
CPU time 43.53 seconds
Started Jul 14 06:52:33 PM PDT 24
Finished Jul 14 06:53:19 PM PDT 24
Peak memory 221080 kb
Host smart-fbe9f1cf-d212-400d-8b2a-739e27c2d428
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831803181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.831803181
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.1881277734
Short name T385
Test name
Test status
Simulation time 1916453611 ps
CPU time 96.22 seconds
Started Jul 14 06:53:45 PM PDT 24
Finished Jul 14 06:55:25 PM PDT 24
Peak memory 222508 kb
Host smart-b9889611-0df7-499e-8785-038745ffd56c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1881277734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.1881277734
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.4084582295
Short name T123
Test name
Test status
Simulation time 132877059 ps
CPU time 6.95 seconds
Started Jul 14 06:53:52 PM PDT 24
Finished Jul 14 06:54:03 PM PDT 24
Peak memory 222640 kb
Host smart-1c33b222-7443-41ad-a64a-01fd7f5fdce8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084582295 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.4084582295
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.3367816396
Short name T3
Test name
Test status
Simulation time 61809595 ps
CPU time 2.63 seconds
Started Jul 14 06:54:18 PM PDT 24
Finished Jul 14 06:54:24 PM PDT 24
Peak memory 210108 kb
Host smart-0a1fd57b-4428-4d60-b1b3-919b6a938bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367816396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.3367816396
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.1835477726
Short name T59
Test name
Test status
Simulation time 5212872546 ps
CPU time 152.71 seconds
Started Jul 14 06:53:48 PM PDT 24
Finished Jul 14 06:56:25 PM PDT 24
Peak memory 216740 kb
Host smart-1515826b-44f0-4fa6-82a7-1aa3903c684e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835477726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.1835477726
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.2293055302
Short name T87
Test name
Test status
Simulation time 55224368 ps
CPU time 3.48 seconds
Started Jul 14 06:52:53 PM PDT 24
Finished Jul 14 06:52:57 PM PDT 24
Peak memory 214340 kb
Host smart-ff9ac72d-6cd4-4761-ab07-c436b7758f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293055302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.2293055302
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.3255757173
Short name T282
Test name
Test status
Simulation time 1895336170 ps
CPU time 48.43 seconds
Started Jul 14 06:53:36 PM PDT 24
Finished Jul 14 06:54:29 PM PDT 24
Peak memory 215664 kb
Host smart-573258f3-6536-4688-8339-abdf1dff77d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3255757173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.3255757173
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.1763194109
Short name T78
Test name
Test status
Simulation time 44009310 ps
CPU time 3.26 seconds
Started Jul 14 06:53:36 PM PDT 24
Finished Jul 14 06:53:44 PM PDT 24
Peak memory 215332 kb
Host smart-3d1121de-0847-44a1-aebd-0186aae2cd4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1763194109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.1763194109
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.411292836
Short name T126
Test name
Test status
Simulation time 1297293091 ps
CPU time 19.89 seconds
Started Jul 14 06:53:33 PM PDT 24
Finished Jul 14 06:53:56 PM PDT 24
Peak memory 222560 kb
Host smart-0abbc738-2e81-4ebc-be71-0477ccd0dd8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411292836 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.411292836
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.2868532346
Short name T382
Test name
Test status
Simulation time 2596305718 ps
CPU time 23.75 seconds
Started Jul 14 06:54:28 PM PDT 24
Finished Jul 14 06:54:55 PM PDT 24
Peak memory 214420 kb
Host smart-a584d2f6-8c51-401e-8b00-aeb7c5d6e3e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2868532346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.2868532346
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.2032174611
Short name T67
Test name
Test status
Simulation time 2123599669 ps
CPU time 61.03 seconds
Started Jul 14 06:53:04 PM PDT 24
Finished Jul 14 06:54:06 PM PDT 24
Peak memory 215032 kb
Host smart-b64f8a00-686a-4199-a57f-96b14fe188ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032174611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.2032174611
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.1639968461
Short name T24
Test name
Test status
Simulation time 76464244 ps
CPU time 2.96 seconds
Started Jul 14 06:54:28 PM PDT 24
Finished Jul 14 06:54:34 PM PDT 24
Peak memory 222880 kb
Host smart-eee3ea11-6b23-4427-b697-4c7f0df63de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639968461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.1639968461
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.3990335484
Short name T260
Test name
Test status
Simulation time 348636758 ps
CPU time 17.95 seconds
Started Jul 14 06:52:25 PM PDT 24
Finished Jul 14 06:52:44 PM PDT 24
Peak memory 215732 kb
Host smart-a4eb49a2-4dd6-4239-856c-7f407e3ecca1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3990335484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.3990335484
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.2212846355
Short name T157
Test name
Test status
Simulation time 348269104 ps
CPU time 3.16 seconds
Started Jul 14 06:53:35 PM PDT 24
Finished Jul 14 06:53:42 PM PDT 24
Peak memory 217756 kb
Host smart-7846f50f-ea98-484c-bf16-9dbd15884310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212846355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.2212846355
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.3224953400
Short name T58
Test name
Test status
Simulation time 5397142283 ps
CPU time 69.67 seconds
Started Jul 14 06:53:02 PM PDT 24
Finished Jul 14 06:54:14 PM PDT 24
Peak memory 222644 kb
Host smart-2d0905e1-f5e3-4dc6-b8eb-20e39d72ba03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224953400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.3224953400
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.2707303299
Short name T347
Test name
Test status
Simulation time 393662083 ps
CPU time 6.03 seconds
Started Jul 14 06:52:49 PM PDT 24
Finished Jul 14 06:52:56 PM PDT 24
Peak memory 214320 kb
Host smart-17ceb59b-1c55-4c08-83a7-3e2c8ac67086
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2707303299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.2707303299
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.2504979662
Short name T800
Test name
Test status
Simulation time 493807438 ps
CPU time 3.75 seconds
Started Jul 14 06:54:32 PM PDT 24
Finished Jul 14 06:54:39 PM PDT 24
Peak memory 209208 kb
Host smart-345d8c5f-e6a2-4fda-8e6a-d1a77004217e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504979662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2504979662
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.4181335372
Short name T915
Test name
Test status
Simulation time 234280708 ps
CPU time 4.28 seconds
Started Jul 14 06:52:45 PM PDT 24
Finished Jul 14 06:52:51 PM PDT 24
Peak memory 214392 kb
Host smart-2eacc6fb-2f7c-4188-846e-d2e472d71a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181335372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.4181335372
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.2162204942
Short name T33
Test name
Test status
Simulation time 46940076 ps
CPU time 2.4 seconds
Started Jul 14 06:53:16 PM PDT 24
Finished Jul 14 06:53:21 PM PDT 24
Peak memory 209824 kb
Host smart-4d52f3b2-5d51-491e-8059-bf22044d3c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162204942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2162204942
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.3074711648
Short name T392
Test name
Test status
Simulation time 571848966 ps
CPU time 8.71 seconds
Started Jul 14 06:53:06 PM PDT 24
Finished Jul 14 06:53:16 PM PDT 24
Peak memory 215948 kb
Host smart-d51def82-2e2e-4120-a976-ae0a885b9062
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3074711648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.3074711648
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.1820029398
Short name T196
Test name
Test status
Simulation time 7162798793 ps
CPU time 48.9 seconds
Started Jul 14 06:54:28 PM PDT 24
Finished Jul 14 06:55:19 PM PDT 24
Peak memory 216008 kb
Host smart-b9f11aee-6f4f-4b13-a65e-00422a428e6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820029398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.1820029398
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2950793734
Short name T120
Test name
Test status
Simulation time 2400546019 ps
CPU time 4.84 seconds
Started Jul 14 05:33:33 PM PDT 24
Finished Jul 14 05:33:39 PM PDT 24
Peak memory 213964 kb
Host smart-e22a9dcf-623e-4315-9a84-b9a9c2bc975f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950793734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.2950793734
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.1846603568
Short name T219
Test name
Test status
Simulation time 807330697 ps
CPU time 36.75 seconds
Started Jul 14 06:53:48 PM PDT 24
Finished Jul 14 06:54:29 PM PDT 24
Peak memory 221756 kb
Host smart-93b728cc-6e46-428c-a41d-e336d9d0b3ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846603568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.1846603568
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.3615765480
Short name T15
Test name
Test status
Simulation time 2864161372 ps
CPU time 21.22 seconds
Started Jul 14 06:53:14 PM PDT 24
Finished Jul 14 06:53:38 PM PDT 24
Peak memory 209280 kb
Host smart-a16ff375-6a4f-4cf1-bdf3-a7a55dddd183
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615765480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.3615765480
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.1514829811
Short name T424
Test name
Test status
Simulation time 19482173 ps
CPU time 0.7 seconds
Started Jul 14 06:53:07 PM PDT 24
Finished Jul 14 06:53:09 PM PDT 24
Peak memory 205972 kb
Host smart-aff9a67e-dc4d-4967-812e-0c48a7a48c08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514829811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1514829811
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.4282501933
Short name T170
Test name
Test status
Simulation time 328220345 ps
CPU time 4.29 seconds
Started Jul 14 05:33:32 PM PDT 24
Finished Jul 14 05:33:37 PM PDT 24
Peak memory 213640 kb
Host smart-a0fdaf1d-6227-4cd8-a3e8-0a71a54f5956
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282501933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.4282501933
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.1910345122
Short name T85
Test name
Test status
Simulation time 296276925 ps
CPU time 2.6 seconds
Started Jul 14 06:54:03 PM PDT 24
Finished Jul 14 06:54:06 PM PDT 24
Peak memory 214064 kb
Host smart-48dafe10-9742-4f09-aba5-2c84accf0c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910345122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.1910345122
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.2871426632
Short name T395
Test name
Test status
Simulation time 1626381103 ps
CPU time 14.7 seconds
Started Jul 14 06:53:12 PM PDT 24
Finished Jul 14 06:53:29 PM PDT 24
Peak memory 214340 kb
Host smart-9f0f3978-2b9f-4350-9769-4ca1aad41cc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2871426632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.2871426632
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.1278296458
Short name T268
Test name
Test status
Simulation time 226534403 ps
CPU time 4.18 seconds
Started Jul 14 06:53:34 PM PDT 24
Finished Jul 14 06:53:41 PM PDT 24
Peak memory 214252 kb
Host smart-e2e0ef38-4387-43a7-a8f3-f559e43e17a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278296458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.1278296458
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.1386638048
Short name T49
Test name
Test status
Simulation time 669046327 ps
CPU time 19.93 seconds
Started Jul 14 06:52:44 PM PDT 24
Finished Jul 14 06:53:05 PM PDT 24
Peak memory 215720 kb
Host smart-8a16ea91-1027-43db-a239-cfdcb00f16de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386638048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1386638048
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3534494942
Short name T173
Test name
Test status
Simulation time 373900160 ps
CPU time 4.26 seconds
Started Jul 14 05:33:44 PM PDT 24
Finished Jul 14 05:33:51 PM PDT 24
Peak memory 213584 kb
Host smart-697fed2c-69b6-4945-bca8-72233f0d68b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534494942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.3534494942
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.4201824697
Short name T166
Test name
Test status
Simulation time 370075952 ps
CPU time 5.34 seconds
Started Jul 14 05:33:43 PM PDT 24
Finished Jul 14 05:33:49 PM PDT 24
Peak memory 213644 kb
Host smart-e9bb130c-406e-4669-ada8-4d385acad6b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201824697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.4201824697
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.4029614820
Short name T272
Test name
Test status
Simulation time 642124148 ps
CPU time 9.04 seconds
Started Jul 14 06:53:46 PM PDT 24
Finished Jul 14 06:53:59 PM PDT 24
Peak memory 222492 kb
Host smart-24385e44-2fb3-4c88-996d-849bb1973731
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4029614820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.4029614820
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.603315968
Short name T73
Test name
Test status
Simulation time 7985710502 ps
CPU time 77.12 seconds
Started Jul 14 06:54:17 PM PDT 24
Finished Jul 14 06:55:37 PM PDT 24
Peak memory 216228 kb
Host smart-35839ae7-da1d-4e5c-9842-ab9211a7099c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603315968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.603315968
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.384778496
Short name T53
Test name
Test status
Simulation time 93106583 ps
CPU time 3.33 seconds
Started Jul 14 06:52:21 PM PDT 24
Finished Jul 14 06:52:26 PM PDT 24
Peak memory 214344 kb
Host smart-bc8caa17-bd7f-43b9-b519-740146040c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384778496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.384778496
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.2575368781
Short name T276
Test name
Test status
Simulation time 50350133444 ps
CPU time 595.34 seconds
Started Jul 14 06:52:23 PM PDT 24
Finished Jul 14 07:02:20 PM PDT 24
Peak memory 218984 kb
Host smart-48961e51-8a6a-416c-b1a5-669c032d3574
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575368781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.2575368781
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.655673317
Short name T127
Test name
Test status
Simulation time 1932627082 ps
CPU time 22.19 seconds
Started Jul 14 06:53:39 PM PDT 24
Finished Jul 14 06:54:05 PM PDT 24
Peak memory 222632 kb
Host smart-118ec473-0d43-44a0-a6cb-8c4d611222e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655673317 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.655673317
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1515903220
Short name T168
Test name
Test status
Simulation time 133400128 ps
CPU time 5.67 seconds
Started Jul 14 05:33:45 PM PDT 24
Finished Jul 14 05:33:53 PM PDT 24
Peak memory 213612 kb
Host smart-96b8c9b4-b9a8-4cd5-91f4-b35fe968658e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515903220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.1515903220
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.3621890484
Short name T79
Test name
Test status
Simulation time 99425139 ps
CPU time 5 seconds
Started Jul 14 06:52:55 PM PDT 24
Finished Jul 14 06:53:02 PM PDT 24
Peak memory 214260 kb
Host smart-1e45a5b8-2b15-46eb-a1ab-efbaed148cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621890484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3621890484
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.2343741344
Short name T161
Test name
Test status
Simulation time 141951704 ps
CPU time 4.34 seconds
Started Jul 14 06:52:45 PM PDT 24
Finished Jul 14 06:52:51 PM PDT 24
Peak memory 218300 kb
Host smart-9b0be0f9-5df5-40a8-b6f2-294ef8bafdd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343741344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.2343741344
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.1958042465
Short name T160
Test name
Test status
Simulation time 435846598 ps
CPU time 2.06 seconds
Started Jul 14 06:53:06 PM PDT 24
Finished Jul 14 06:53:10 PM PDT 24
Peak memory 216404 kb
Host smart-33c78a94-e51f-4ff1-87ef-0f940f28d55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958042465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1958042465
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.904777357
Short name T162
Test name
Test status
Simulation time 341452813 ps
CPU time 2.81 seconds
Started Jul 14 06:54:00 PM PDT 24
Finished Jul 14 06:54:03 PM PDT 24
Peak memory 222696 kb
Host smart-8a5cd32a-b8b0-47d4-8f46-b4486f0e3961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904777357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.904777357
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.3558246149
Short name T326
Test name
Test status
Simulation time 52900790 ps
CPU time 3.9 seconds
Started Jul 14 06:53:15 PM PDT 24
Finished Jul 14 06:53:21 PM PDT 24
Peak memory 215348 kb
Host smart-e54931f9-a8f9-4259-a720-b3ab309dd870
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3558246149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.3558246149
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.2713130121
Short name T659
Test name
Test status
Simulation time 317234486 ps
CPU time 3.47 seconds
Started Jul 14 06:53:29 PM PDT 24
Finished Jul 14 06:53:34 PM PDT 24
Peak memory 215248 kb
Host smart-cd392973-3917-4154-ab88-f788ec3fe28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713130121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.2713130121
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.4178763863
Short name T248
Test name
Test status
Simulation time 128826612 ps
CPU time 4.51 seconds
Started Jul 14 06:53:59 PM PDT 24
Finished Jul 14 06:54:05 PM PDT 24
Peak memory 215832 kb
Host smart-ce196299-e30c-4afd-b8ae-89c068580977
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4178763863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.4178763863
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.2627852690
Short name T147
Test name
Test status
Simulation time 57173325 ps
CPU time 3.7 seconds
Started Jul 14 06:54:25 PM PDT 24
Finished Jul 14 06:54:30 PM PDT 24
Peak memory 215348 kb
Host smart-f26dea91-732f-44f3-8253-6b1d4efa66aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2627852690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.2627852690
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.1594037569
Short name T368
Test name
Test status
Simulation time 127010378 ps
CPU time 3.05 seconds
Started Jul 14 06:54:18 PM PDT 24
Finished Jul 14 06:54:24 PM PDT 24
Peak memory 210532 kb
Host smart-4e02bcc4-0ec5-4441-96cf-4079341d93fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594037569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.1594037569
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1636359979
Short name T180
Test name
Test status
Simulation time 1484557439 ps
CPU time 8.57 seconds
Started Jul 14 05:33:41 PM PDT 24
Finished Jul 14 05:33:51 PM PDT 24
Peak memory 213628 kb
Host smart-e19215d7-9565-4852-82db-8aed20cd9a26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636359979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.1636359979
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.3415710458
Short name T83
Test name
Test status
Simulation time 122850408 ps
CPU time 3.11 seconds
Started Jul 14 06:52:22 PM PDT 24
Finished Jul 14 06:52:27 PM PDT 24
Peak memory 215648 kb
Host smart-4f1dfa70-1878-4452-a7eb-d84cc1ebd933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415710458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.3415710458
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.2105175148
Short name T384
Test name
Test status
Simulation time 120980865 ps
CPU time 6.4 seconds
Started Jul 14 06:53:36 PM PDT 24
Finished Jul 14 06:53:47 PM PDT 24
Peak memory 215180 kb
Host smart-b8ee187e-74ba-4c5a-9ec4-0f34c1b6e0fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2105175148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.2105175148
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.622663574
Short name T297
Test name
Test status
Simulation time 10783008911 ps
CPU time 217.37 seconds
Started Jul 14 06:54:21 PM PDT 24
Finished Jul 14 06:58:02 PM PDT 24
Peak memory 222404 kb
Host smart-6879e42b-dd6a-43aa-bec5-345db65952c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622663574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.622663574
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2133099029
Short name T178
Test name
Test status
Simulation time 714901906 ps
CPU time 6.35 seconds
Started Jul 14 05:33:42 PM PDT 24
Finished Jul 14 05:33:50 PM PDT 24
Peak memory 213736 kb
Host smart-b2f1194c-792e-4186-bdc6-9672e0589e84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133099029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.2133099029
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.2804520025
Short name T436
Test name
Test status
Simulation time 173063615 ps
CPU time 3.11 seconds
Started Jul 14 06:53:01 PM PDT 24
Finished Jul 14 06:53:07 PM PDT 24
Peak memory 209972 kb
Host smart-ddeb15b7-3074-4311-a841-f88bad91fe3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804520025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.2804520025
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.363781838
Short name T158
Test name
Test status
Simulation time 272197483 ps
CPU time 3.56 seconds
Started Jul 14 06:54:08 PM PDT 24
Finished Jul 14 06:54:13 PM PDT 24
Peak memory 218388 kb
Host smart-9c7842ed-c1b9-40e3-aa17-d94aebde9f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363781838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.363781838
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.821812066
Short name T223
Test name
Test status
Simulation time 1662431751 ps
CPU time 19.96 seconds
Started Jul 14 06:52:51 PM PDT 24
Finished Jul 14 06:53:12 PM PDT 24
Peak memory 216672 kb
Host smart-5ac33927-ecd9-4451-be97-1191085dae11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821812066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.821812066
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.3351746103
Short name T244
Test name
Test status
Simulation time 72329937 ps
CPU time 3 seconds
Started Jul 14 06:53:02 PM PDT 24
Finished Jul 14 06:53:07 PM PDT 24
Peak memory 214988 kb
Host smart-9b5a8945-4708-495b-8885-9a4212d93dad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3351746103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.3351746103
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.2515557591
Short name T281
Test name
Test status
Simulation time 77939016 ps
CPU time 2.28 seconds
Started Jul 14 06:53:00 PM PDT 24
Finished Jul 14 06:53:04 PM PDT 24
Peak memory 214324 kb
Host smart-4e57511d-8330-4061-b5ba-3c8aaed6b684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515557591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.2515557591
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.2854708931
Short name T227
Test name
Test status
Simulation time 1411741277 ps
CPU time 19.65 seconds
Started Jul 14 06:53:24 PM PDT 24
Finished Jul 14 06:53:45 PM PDT 24
Peak memory 215476 kb
Host smart-41844904-c329-47d7-9b0a-7f8af6f9f989
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854708931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.2854708931
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.3657554544
Short name T294
Test name
Test status
Simulation time 7951362899 ps
CPU time 163.54 seconds
Started Jul 14 06:53:28 PM PDT 24
Finished Jul 14 06:56:13 PM PDT 24
Peak memory 216724 kb
Host smart-c106a9ab-cbd1-40ca-acd3-a5a062d9a469
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657554544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.3657554544
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.269504036
Short name T7
Test name
Test status
Simulation time 9705261793 ps
CPU time 103.4 seconds
Started Jul 14 06:53:33 PM PDT 24
Finished Jul 14 06:55:20 PM PDT 24
Peak memory 217060 kb
Host smart-de668df1-5fdd-49bc-883e-3b0dedf520ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269504036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.269504036
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.3445003488
Short name T64
Test name
Test status
Simulation time 2143063864 ps
CPU time 46.27 seconds
Started Jul 14 06:53:34 PM PDT 24
Finished Jul 14 06:54:23 PM PDT 24
Peak memory 219616 kb
Host smart-6d039fd6-1bd2-4531-9739-e5c7fd9d266b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445003488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.3445003488
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.1522203463
Short name T307
Test name
Test status
Simulation time 249438971 ps
CPU time 2.7 seconds
Started Jul 14 06:53:36 PM PDT 24
Finished Jul 14 06:53:43 PM PDT 24
Peak memory 222404 kb
Host smart-b93e63b1-3530-439f-b40e-2c9eecc03417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522203463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.1522203463
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.2192944118
Short name T527
Test name
Test status
Simulation time 347110060 ps
CPU time 2.85 seconds
Started Jul 14 06:53:47 PM PDT 24
Finished Jul 14 06:53:54 PM PDT 24
Peak memory 214244 kb
Host smart-53811fb0-b719-45e2-88ed-6b43372358d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192944118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.2192944118
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.2266459560
Short name T310
Test name
Test status
Simulation time 112754774 ps
CPU time 5.35 seconds
Started Jul 14 06:54:01 PM PDT 24
Finished Jul 14 06:54:07 PM PDT 24
Peak memory 214260 kb
Host smart-adf2298b-edc9-4271-97ec-a4649b56d07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266459560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.2266459560
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.3437354669
Short name T90
Test name
Test status
Simulation time 922236888 ps
CPU time 5.93 seconds
Started Jul 14 06:54:11 PM PDT 24
Finished Jul 14 06:54:20 PM PDT 24
Peak memory 214192 kb
Host smart-1507a6e9-63e8-457a-9bea-7161de7befa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437354669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.3437354669
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.3907901380
Short name T469
Test name
Test status
Simulation time 112053800 ps
CPU time 1.89 seconds
Started Jul 14 06:54:32 PM PDT 24
Finished Jul 14 06:54:38 PM PDT 24
Peak memory 207140 kb
Host smart-1b415ce2-4d4d-4ec7-9f6d-578234c94cba
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907901380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.3907901380
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2337905152
Short name T165
Test name
Test status
Simulation time 2380742784 ps
CPU time 8.15 seconds
Started Jul 14 05:33:47 PM PDT 24
Finished Jul 14 05:33:58 PM PDT 24
Peak memory 213856 kb
Host smart-8381e34b-6492-4a89-892d-fc6d950cf0e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337905152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.2337905152
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.1906293227
Short name T179
Test name
Test status
Simulation time 425471996 ps
CPU time 4.89 seconds
Started Jul 14 05:33:42 PM PDT 24
Finished Jul 14 05:33:48 PM PDT 24
Peak memory 213784 kb
Host smart-3861b2d3-6020-4f83-9bc4-2dea344a83e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906293227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.1906293227
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.2238649734
Short name T35
Test name
Test status
Simulation time 53002910 ps
CPU time 2.11 seconds
Started Jul 14 06:52:47 PM PDT 24
Finished Jul 14 06:52:49 PM PDT 24
Peak memory 222784 kb
Host smart-be65c6ac-23fb-4b32-846a-cd3bed1ccd76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238649734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.2238649734
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.499283225
Short name T163
Test name
Test status
Simulation time 362131086 ps
CPU time 3.29 seconds
Started Jul 14 06:52:28 PM PDT 24
Finished Jul 14 06:52:31 PM PDT 24
Peak memory 222740 kb
Host smart-e3e16385-918d-4cf6-abd7-af897d64a791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499283225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.499283225
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.3506049966
Short name T94
Test name
Test status
Simulation time 654333038 ps
CPU time 4.65 seconds
Started Jul 14 06:52:49 PM PDT 24
Finished Jul 14 06:52:55 PM PDT 24
Peak memory 222440 kb
Host smart-7c643fd2-5bdf-487a-890c-58870fa64802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506049966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.3506049966
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.314420312
Short name T159
Test name
Test status
Simulation time 300073734 ps
CPU time 4.6 seconds
Started Jul 14 06:52:45 PM PDT 24
Finished Jul 14 06:52:51 PM PDT 24
Peak memory 218300 kb
Host smart-9215f9a6-c15d-4689-a8e6-b3cbdd5c9cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314420312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.314420312
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.3738547846
Short name T885
Test name
Test status
Simulation time 1049632534 ps
CPU time 57.69 seconds
Started Jul 14 06:52:15 PM PDT 24
Finished Jul 14 06:53:14 PM PDT 24
Peak memory 214680 kb
Host smart-1ce3d0a9-bdf0-4c54-a6f7-7d7a82cbd906
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3738547846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3738547846
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.3407391956
Short name T810
Test name
Test status
Simulation time 1066527486 ps
CPU time 10.95 seconds
Started Jul 14 06:52:13 PM PDT 24
Finished Jul 14 06:52:24 PM PDT 24
Peak memory 210332 kb
Host smart-b36a1fbf-5f1d-432f-8ea2-dfa4071e8ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407391956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.3407391956
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.1590776259
Short name T39
Test name
Test status
Simulation time 250871335 ps
CPU time 4.36 seconds
Started Jul 14 06:53:00 PM PDT 24
Finished Jul 14 06:53:07 PM PDT 24
Peak memory 214308 kb
Host smart-c033c798-4edb-431f-b106-b91a34248006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590776259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.1590776259
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.1847419005
Short name T242
Test name
Test status
Simulation time 189108105 ps
CPU time 6.14 seconds
Started Jul 14 06:52:59 PM PDT 24
Finished Jul 14 06:53:07 PM PDT 24
Peak memory 222424 kb
Host smart-c3f6c1fc-f6cc-4bc7-941e-f9ecde0d9c33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1847419005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.1847419005
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3650157921
Short name T283
Test name
Test status
Simulation time 71494110 ps
CPU time 4.61 seconds
Started Jul 14 06:53:01 PM PDT 24
Finished Jul 14 06:53:08 PM PDT 24
Peak memory 215852 kb
Host smart-ceed3561-8517-4d39-9850-10ad9afb7701
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3650157921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3650157921
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.1788866283
Short name T199
Test name
Test status
Simulation time 52615791 ps
CPU time 3.7 seconds
Started Jul 14 06:53:12 PM PDT 24
Finished Jul 14 06:53:19 PM PDT 24
Peak memory 214344 kb
Host smart-aaf8b72a-4ea8-4f2b-a352-735583f7b248
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1788866283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.1788866283
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.889147137
Short name T345
Test name
Test status
Simulation time 4344148662 ps
CPU time 23.97 seconds
Started Jul 14 06:53:12 PM PDT 24
Finished Jul 14 06:53:38 PM PDT 24
Peak memory 214468 kb
Host smart-aa78e057-ebc4-41cc-9079-228124b939c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889147137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.889147137
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.174503501
Short name T344
Test name
Test status
Simulation time 101094929 ps
CPU time 3.15 seconds
Started Jul 14 06:53:12 PM PDT 24
Finished Jul 14 06:53:17 PM PDT 24
Peak memory 214272 kb
Host smart-3d876338-8ed7-42aa-afd3-23dc40c35052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174503501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.174503501
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.4062986717
Short name T235
Test name
Test status
Simulation time 430749137 ps
CPU time 3.48 seconds
Started Jul 14 06:53:25 PM PDT 24
Finished Jul 14 06:53:29 PM PDT 24
Peak memory 214684 kb
Host smart-3e87d317-ba92-4827-b169-e528684bef13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062986717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.4062986717
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.2321235555
Short name T353
Test name
Test status
Simulation time 150241465 ps
CPU time 2.72 seconds
Started Jul 14 06:53:26 PM PDT 24
Finished Jul 14 06:53:30 PM PDT 24
Peak memory 208144 kb
Host smart-f6d942fd-73e7-4f20-885f-eecf5e8a304a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321235555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.2321235555
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.601659819
Short name T239
Test name
Test status
Simulation time 286336852 ps
CPU time 2.96 seconds
Started Jul 14 06:53:44 PM PDT 24
Finished Jul 14 06:53:50 PM PDT 24
Peak memory 214324 kb
Host smart-4fcc04c4-82e9-4843-bce6-4cea7deb67f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601659819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.601659819
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.3934602270
Short name T334
Test name
Test status
Simulation time 209494367 ps
CPU time 10.66 seconds
Started Jul 14 06:53:44 PM PDT 24
Finished Jul 14 06:53:58 PM PDT 24
Peak memory 222804 kb
Host smart-ec1fb844-71b1-45f7-b20c-0b7710833737
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934602270 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.3934602270
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.207110916
Short name T305
Test name
Test status
Simulation time 10937741305 ps
CPU time 243.68 seconds
Started Jul 14 06:53:49 PM PDT 24
Finished Jul 14 06:57:57 PM PDT 24
Peak memory 222620 kb
Host smart-c51cf9c1-256b-403c-aa9c-abe7b663a439
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207110916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.207110916
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.4001324673
Short name T202
Test name
Test status
Simulation time 345139739 ps
CPU time 2.9 seconds
Started Jul 14 06:53:53 PM PDT 24
Finished Jul 14 06:54:00 PM PDT 24
Peak memory 215224 kb
Host smart-8a0640a4-4969-47cb-8356-aef1a59a9e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001324673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.4001324673
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1095134784
Short name T1021
Test name
Test status
Simulation time 183561321 ps
CPU time 7.83 seconds
Started Jul 14 05:33:33 PM PDT 24
Finished Jul 14 05:33:42 PM PDT 24
Peak memory 205536 kb
Host smart-cf4cf122-52a6-4c8c-8fe1-ea95e235fb75
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095134784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1
095134784
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1560216933
Short name T929
Test name
Test status
Simulation time 2692871060 ps
CPU time 8.7 seconds
Started Jul 14 05:33:35 PM PDT 24
Finished Jul 14 05:33:44 PM PDT 24
Peak memory 205584 kb
Host smart-96ee1250-9a00-4a1c-9894-329dcb1d6f43
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560216933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.1
560216933
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.871527368
Short name T957
Test name
Test status
Simulation time 49859858 ps
CPU time 0.88 seconds
Started Jul 14 05:33:28 PM PDT 24
Finished Jul 14 05:33:30 PM PDT 24
Peak memory 205388 kb
Host smart-9cac389d-6342-4d18-befa-63146693c50a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871527368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.871527368
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3202793819
Short name T980
Test name
Test status
Simulation time 34057475 ps
CPU time 1.73 seconds
Started Jul 14 05:33:32 PM PDT 24
Finished Jul 14 05:33:35 PM PDT 24
Peak memory 213832 kb
Host smart-0de44b96-fd68-4bdb-b25d-d4f7643be59e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202793819 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.3202793819
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1877615002
Short name T1064
Test name
Test status
Simulation time 15161425 ps
CPU time 1.11 seconds
Started Jul 14 05:33:33 PM PDT 24
Finished Jul 14 05:33:35 PM PDT 24
Peak memory 205512 kb
Host smart-af87c74d-395a-4f89-ac2a-7d0b2c6b3b6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877615002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1877615002
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2387206385
Short name T936
Test name
Test status
Simulation time 35619009 ps
CPU time 0.8 seconds
Started Jul 14 05:33:31 PM PDT 24
Finished Jul 14 05:33:32 PM PDT 24
Peak memory 205148 kb
Host smart-54683803-a540-4e4f-8ded-ff6dca3bcd3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387206385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.2387206385
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3096069731
Short name T973
Test name
Test status
Simulation time 192017241 ps
CPU time 2.64 seconds
Started Jul 14 05:33:31 PM PDT 24
Finished Jul 14 05:33:35 PM PDT 24
Peak memory 205416 kb
Host smart-db9cf1f6-3a26-4959-b1fa-493fbd656dd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096069731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.3096069731
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.507909476
Short name T1001
Test name
Test status
Simulation time 56051745 ps
CPU time 1.97 seconds
Started Jul 14 05:33:25 PM PDT 24
Finished Jul 14 05:33:28 PM PDT 24
Peak memory 213992 kb
Host smart-c1161e78-4326-4baf-a2f4-0d58522aed12
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507909476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow
_reg_errors.507909476
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.2317846863
Short name T151
Test name
Test status
Simulation time 382665204 ps
CPU time 12.76 seconds
Started Jul 14 05:33:27 PM PDT 24
Finished Jul 14 05:33:41 PM PDT 24
Peak memory 214080 kb
Host smart-cb391308-4caf-4e64-b151-4c53db83287a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317846863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.2317846863
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.3264257350
Short name T994
Test name
Test status
Simulation time 44247032 ps
CPU time 2.33 seconds
Started Jul 14 05:33:28 PM PDT 24
Finished Jul 14 05:33:31 PM PDT 24
Peak memory 221876 kb
Host smart-175acf5f-d87f-4714-8ffd-ccd81b919bce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264257350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.3264257350
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.580995232
Short name T183
Test name
Test status
Simulation time 537277151 ps
CPU time 4.1 seconds
Started Jul 14 05:33:28 PM PDT 24
Finished Jul 14 05:33:33 PM PDT 24
Peak memory 205524 kb
Host smart-9d322274-f573-42af-8eba-38134918a70a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580995232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.
580995232
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3525022726
Short name T1082
Test name
Test status
Simulation time 1008615382 ps
CPU time 10.2 seconds
Started Jul 14 05:33:34 PM PDT 24
Finished Jul 14 05:33:46 PM PDT 24
Peak memory 205444 kb
Host smart-71a78b8c-2513-45f9-afd1-cacb71027314
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525022726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.3
525022726
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.791016797
Short name T930
Test name
Test status
Simulation time 651325522 ps
CPU time 16.62 seconds
Started Jul 14 05:33:35 PM PDT 24
Finished Jul 14 05:33:52 PM PDT 24
Peak memory 205508 kb
Host smart-6642886a-a41f-444a-b5b1-62197b5bd389
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791016797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.791016797
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3022778641
Short name T1014
Test name
Test status
Simulation time 70480433 ps
CPU time 0.93 seconds
Started Jul 14 05:33:33 PM PDT 24
Finished Jul 14 05:33:35 PM PDT 24
Peak memory 205328 kb
Host smart-e1f0c4f1-d801-4894-8ea4-23bf23f3e40a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022778641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.3
022778641
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.731423540
Short name T1026
Test name
Test status
Simulation time 92429376 ps
CPU time 1.54 seconds
Started Jul 14 05:33:36 PM PDT 24
Finished Jul 14 05:33:39 PM PDT 24
Peak memory 213780 kb
Host smart-64bf92fa-0a69-4753-b2b8-3dba0f367c43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731423540 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.731423540
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.4246591735
Short name T997
Test name
Test status
Simulation time 35074293 ps
CPU time 1.1 seconds
Started Jul 14 05:33:34 PM PDT 24
Finished Jul 14 05:33:36 PM PDT 24
Peak memory 205432 kb
Host smart-1e3a99d1-6abc-463b-abb1-d394f93f4cc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246591735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.4246591735
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1671135953
Short name T990
Test name
Test status
Simulation time 44689760 ps
CPU time 0.81 seconds
Started Jul 14 05:33:32 PM PDT 24
Finished Jul 14 05:33:34 PM PDT 24
Peak memory 205228 kb
Host smart-6f42a756-0a35-4558-bb6e-cb8c98e7a1f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671135953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1671135953
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.452228954
Short name T150
Test name
Test status
Simulation time 67428599 ps
CPU time 1.39 seconds
Started Jul 14 05:33:30 PM PDT 24
Finished Jul 14 05:33:32 PM PDT 24
Peak memory 205412 kb
Host smart-409be45a-8526-4261-98d6-cd2f26d69de5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452228954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sam
e_csr_outstanding.452228954
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2418897506
Short name T937
Test name
Test status
Simulation time 1411590310 ps
CPU time 4.92 seconds
Started Jul 14 05:33:32 PM PDT 24
Finished Jul 14 05:33:38 PM PDT 24
Peak memory 220160 kb
Host smart-a5df5dae-3327-4dbd-b459-8be74807650a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418897506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.2418897506
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1075748421
Short name T1042
Test name
Test status
Simulation time 99248807 ps
CPU time 1.99 seconds
Started Jul 14 05:33:41 PM PDT 24
Finished Jul 14 05:33:44 PM PDT 24
Peak memory 213500 kb
Host smart-55263498-88a0-41d0-8ec7-be140a1ebdba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075748421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1075748421
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1415366557
Short name T1061
Test name
Test status
Simulation time 51142044 ps
CPU time 1.64 seconds
Started Jul 14 05:33:44 PM PDT 24
Finished Jul 14 05:33:49 PM PDT 24
Peak memory 205664 kb
Host smart-1722a1df-7ab1-44d3-9f22-de917e68954f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415366557 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1415366557
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.288224247
Short name T1056
Test name
Test status
Simulation time 24615499 ps
CPU time 1.42 seconds
Started Jul 14 05:33:49 PM PDT 24
Finished Jul 14 05:33:53 PM PDT 24
Peak memory 205504 kb
Host smart-f3890928-b3f5-41bb-9fc1-469adc2ca0e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288224247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.288224247
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1069974241
Short name T924
Test name
Test status
Simulation time 11445294 ps
CPU time 0.87 seconds
Started Jul 14 05:33:44 PM PDT 24
Finished Jul 14 05:33:48 PM PDT 24
Peak memory 205260 kb
Host smart-e71b5f0d-fadb-4a32-8aee-242453efcfd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069974241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.1069974241
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2661181804
Short name T959
Test name
Test status
Simulation time 90000630 ps
CPU time 1.97 seconds
Started Jul 14 05:33:46 PM PDT 24
Finished Jul 14 05:33:50 PM PDT 24
Peak memory 205396 kb
Host smart-77f9e549-9e0e-4228-924b-163437d17a48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661181804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.2661181804
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.1080918414
Short name T114
Test name
Test status
Simulation time 104493043 ps
CPU time 1.6 seconds
Started Jul 14 05:33:49 PM PDT 24
Finished Jul 14 05:33:53 PM PDT 24
Peak memory 213972 kb
Host smart-d83982a4-a2fb-4501-aaa3-ec5a4b30bc88
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080918414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.1080918414
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1862255976
Short name T1050
Test name
Test status
Simulation time 689847730 ps
CPU time 8.78 seconds
Started Jul 14 05:33:50 PM PDT 24
Finished Jul 14 05:34:02 PM PDT 24
Peak memory 220140 kb
Host smart-63a34f0b-7417-476a-8489-c9e5024ed610
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862255976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.1862255976
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2489362595
Short name T951
Test name
Test status
Simulation time 323202402 ps
CPU time 3.15 seconds
Started Jul 14 05:33:49 PM PDT 24
Finished Jul 14 05:33:55 PM PDT 24
Peak memory 213572 kb
Host smart-8465bef6-c083-4269-8c93-8ac8bf204be5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489362595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2489362595
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2301372912
Short name T1058
Test name
Test status
Simulation time 29725520 ps
CPU time 1.85 seconds
Started Jul 14 05:33:48 PM PDT 24
Finished Jul 14 05:33:53 PM PDT 24
Peak memory 213868 kb
Host smart-26c83d5e-1da0-47e9-bdb9-db7ab1529721
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301372912 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.2301372912
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3595381692
Short name T1015
Test name
Test status
Simulation time 27506662 ps
CPU time 0.99 seconds
Started Jul 14 05:33:47 PM PDT 24
Finished Jul 14 05:33:50 PM PDT 24
Peak memory 205256 kb
Host smart-969ea898-3130-4ab9-bf93-43f1a9cf6f8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595381692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.3595381692
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2132162589
Short name T947
Test name
Test status
Simulation time 66909190 ps
CPU time 0.77 seconds
Started Jul 14 05:33:43 PM PDT 24
Finished Jul 14 05:33:46 PM PDT 24
Peak memory 205344 kb
Host smart-cc9532a2-3e6c-4426-bced-d8f5f5fd34cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132162589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.2132162589
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.2624720416
Short name T991
Test name
Test status
Simulation time 61421704 ps
CPU time 1.22 seconds
Started Jul 14 05:33:45 PM PDT 24
Finished Jul 14 05:33:50 PM PDT 24
Peak memory 205380 kb
Host smart-c19af6c7-5f02-48d4-a889-0ab8f3efe1f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624720416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.2624720416
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2085246332
Short name T1031
Test name
Test status
Simulation time 62495969 ps
CPU time 1.42 seconds
Started Jul 14 05:33:46 PM PDT 24
Finished Jul 14 05:33:50 PM PDT 24
Peak memory 214012 kb
Host smart-5a16fcd0-cb09-4343-a5f8-3f47b663ed00
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085246332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.2085246332
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3065217168
Short name T982
Test name
Test status
Simulation time 698857767 ps
CPU time 12.4 seconds
Started Jul 14 05:33:44 PM PDT 24
Finished Jul 14 05:33:59 PM PDT 24
Peak memory 220200 kb
Host smart-a3d63789-4042-4222-8239-6667a6886b12
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065217168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.3065217168
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.323194938
Short name T954
Test name
Test status
Simulation time 223959258 ps
CPU time 2.96 seconds
Started Jul 14 05:33:50 PM PDT 24
Finished Jul 14 05:33:55 PM PDT 24
Peak memory 213732 kb
Host smart-ecec9332-5c6e-48bb-9940-78e8a41ad23f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323194938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.323194938
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.258812144
Short name T175
Test name
Test status
Simulation time 125959864 ps
CPU time 3.52 seconds
Started Jul 14 05:33:44 PM PDT 24
Finished Jul 14 05:33:50 PM PDT 24
Peak memory 213712 kb
Host smart-74eb2d23-1d32-4df2-84fc-1911fd0faa24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258812144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err
.258812144
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2185986465
Short name T1004
Test name
Test status
Simulation time 89642085 ps
CPU time 2.17 seconds
Started Jul 14 05:33:44 PM PDT 24
Finished Jul 14 05:33:49 PM PDT 24
Peak memory 205548 kb
Host smart-92321bad-81ce-441e-9b45-896dd770c31b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185986465 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.2185986465
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1283548900
Short name T1063
Test name
Test status
Simulation time 39595043 ps
CPU time 1.03 seconds
Started Jul 14 05:33:47 PM PDT 24
Finished Jul 14 05:33:50 PM PDT 24
Peak memory 205556 kb
Host smart-6da877a8-cfb1-4ca7-b88b-f8527e6b1dba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283548900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1283548900
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2853160528
Short name T916
Test name
Test status
Simulation time 10756420 ps
CPU time 0.88 seconds
Started Jul 14 05:33:50 PM PDT 24
Finished Jul 14 05:33:54 PM PDT 24
Peak memory 205196 kb
Host smart-2e8e2008-67e4-42b4-bd94-c0e1d3c5db5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853160528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.2853160528
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3915125646
Short name T965
Test name
Test status
Simulation time 245414999 ps
CPU time 1.35 seconds
Started Jul 14 05:33:50 PM PDT 24
Finished Jul 14 05:33:54 PM PDT 24
Peak memory 205496 kb
Host smart-5d11f689-84af-48ab-b31e-1c7585753a4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915125646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3915125646
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3019137168
Short name T1000
Test name
Test status
Simulation time 136377917 ps
CPU time 2.66 seconds
Started Jul 14 05:33:46 PM PDT 24
Finished Jul 14 05:33:52 PM PDT 24
Peak memory 214032 kb
Host smart-33c51715-271b-4545-929d-3f68936829ee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019137168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.3019137168
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.3086083752
Short name T115
Test name
Test status
Simulation time 151981244 ps
CPU time 8.23 seconds
Started Jul 14 05:33:45 PM PDT 24
Finished Jul 14 05:33:56 PM PDT 24
Peak memory 213972 kb
Host smart-718aa65e-7934-40cf-b30e-f102149591a8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086083752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.3086083752
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.1907100460
Short name T989
Test name
Test status
Simulation time 42568413 ps
CPU time 2.85 seconds
Started Jul 14 05:33:44 PM PDT 24
Finished Jul 14 05:33:50 PM PDT 24
Peak memory 215764 kb
Host smart-8c733da4-7b13-4195-a73c-5ba512251ef9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907100460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.1907100460
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.1822464072
Short name T176
Test name
Test status
Simulation time 909663120 ps
CPU time 3.57 seconds
Started Jul 14 05:33:46 PM PDT 24
Finished Jul 14 05:33:52 PM PDT 24
Peak memory 205400 kb
Host smart-81d35f00-4f9b-49fc-b1e9-37f5994d8a02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822464072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.1822464072
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2125922491
Short name T1023
Test name
Test status
Simulation time 99954418 ps
CPU time 1.28 seconds
Started Jul 14 05:33:44 PM PDT 24
Finished Jul 14 05:33:48 PM PDT 24
Peak memory 213696 kb
Host smart-0920c88f-ed0f-4f10-9946-544eaf17f8c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125922491 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.2125922491
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2108144433
Short name T1068
Test name
Test status
Simulation time 79542997 ps
CPU time 1.23 seconds
Started Jul 14 05:33:46 PM PDT 24
Finished Jul 14 05:33:50 PM PDT 24
Peak memory 205480 kb
Host smart-5a1250d8-3ed4-48d0-8db3-a44d98ef3343
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108144433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.2108144433
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.678200705
Short name T992
Test name
Test status
Simulation time 15549600 ps
CPU time 0.92 seconds
Started Jul 14 05:33:45 PM PDT 24
Finished Jul 14 05:33:49 PM PDT 24
Peak memory 205232 kb
Host smart-ca92d801-7950-4fcd-ac52-4f5af5a29b41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678200705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.678200705
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2654148442
Short name T1005
Test name
Test status
Simulation time 2036821832 ps
CPU time 3.63 seconds
Started Jul 14 05:33:44 PM PDT 24
Finished Jul 14 05:33:50 PM PDT 24
Peak memory 205620 kb
Host smart-306f0462-5ca4-49f4-ad00-5a97c69e0277
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654148442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2654148442
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1367163493
Short name T1077
Test name
Test status
Simulation time 374343880 ps
CPU time 3.34 seconds
Started Jul 14 05:33:44 PM PDT 24
Finished Jul 14 05:33:50 PM PDT 24
Peak memory 214100 kb
Host smart-4df5269d-9bc6-4225-a588-6a4f4d2ad25b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367163493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.1367163493
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.344329421
Short name T1049
Test name
Test status
Simulation time 392521067 ps
CPU time 11.17 seconds
Started Jul 14 05:33:45 PM PDT 24
Finished Jul 14 05:33:59 PM PDT 24
Peak memory 214024 kb
Host smart-bad96648-d14f-4528-8898-ab5637f97a34
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344329421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
keymgr_shadow_reg_errors_with_csr_rw.344329421
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.4265845920
Short name T1040
Test name
Test status
Simulation time 20402208 ps
CPU time 1.69 seconds
Started Jul 14 05:33:46 PM PDT 24
Finished Jul 14 05:33:50 PM PDT 24
Peak memory 213744 kb
Host smart-c4a5c421-101e-4335-ad66-090019b69bfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265845920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.4265845920
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2484692091
Short name T1020
Test name
Test status
Simulation time 163758828 ps
CPU time 3.13 seconds
Started Jul 14 05:33:45 PM PDT 24
Finished Jul 14 05:33:51 PM PDT 24
Peak memory 213760 kb
Host smart-7cbc54ce-1458-4d4a-8b52-eb3c2e611cae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484692091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.2484692091
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3202849834
Short name T950
Test name
Test status
Simulation time 158948528 ps
CPU time 1.57 seconds
Started Jul 14 05:33:44 PM PDT 24
Finished Jul 14 05:33:48 PM PDT 24
Peak memory 213628 kb
Host smart-aef2227e-2494-48f4-a727-44e12e9426d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202849834 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.3202849834
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2878386058
Short name T155
Test name
Test status
Simulation time 27263397 ps
CPU time 1.17 seconds
Started Jul 14 05:33:44 PM PDT 24
Finished Jul 14 05:33:48 PM PDT 24
Peak memory 205560 kb
Host smart-a059aeb6-5523-46cb-9405-837a03f806e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878386058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.2878386058
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.1412601227
Short name T1054
Test name
Test status
Simulation time 47487276 ps
CPU time 0.82 seconds
Started Jul 14 05:33:42 PM PDT 24
Finished Jul 14 05:33:44 PM PDT 24
Peak memory 205332 kb
Host smart-521a9846-3c22-4b3b-8a08-f9a2482c2657
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412601227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.1412601227
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.1405369248
Short name T978
Test name
Test status
Simulation time 567899158 ps
CPU time 2.74 seconds
Started Jul 14 05:33:50 PM PDT 24
Finished Jul 14 05:33:55 PM PDT 24
Peak memory 205464 kb
Host smart-179e215c-670d-43dc-b927-c5c62cf0e7f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405369248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.1405369248
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3939479248
Short name T925
Test name
Test status
Simulation time 99890293 ps
CPU time 1.45 seconds
Started Jul 14 05:33:46 PM PDT 24
Finished Jul 14 05:33:50 PM PDT 24
Peak memory 214032 kb
Host smart-78349396-a9ee-4595-94ab-8ec9e96d8c28
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939479248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.3939479248
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2594656364
Short name T153
Test name
Test status
Simulation time 745979659 ps
CPU time 4.73 seconds
Started Jul 14 05:33:44 PM PDT 24
Finished Jul 14 05:33:52 PM PDT 24
Peak memory 214024 kb
Host smart-78f000f7-e83a-42c0-9bcd-3af0cca42aa5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594656364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.2594656364
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.3049883006
Short name T969
Test name
Test status
Simulation time 150433452 ps
CPU time 1.96 seconds
Started Jul 14 05:33:44 PM PDT 24
Finished Jul 14 05:33:48 PM PDT 24
Peak memory 213944 kb
Host smart-89dec56b-66b8-484a-b69b-2cfdbd52633b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049883006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.3049883006
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3915046840
Short name T1044
Test name
Test status
Simulation time 16184487 ps
CPU time 1.25 seconds
Started Jul 14 05:33:47 PM PDT 24
Finished Jul 14 05:33:51 PM PDT 24
Peak memory 205560 kb
Host smart-081adf5f-4fdb-44a9-9da3-dcd3638e54ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915046840 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.3915046840
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1257765621
Short name T928
Test name
Test status
Simulation time 62913553 ps
CPU time 1.18 seconds
Started Jul 14 05:33:47 PM PDT 24
Finished Jul 14 05:33:51 PM PDT 24
Peak memory 205512 kb
Host smart-58567502-20c6-4634-81ca-2e8d69d32e93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257765621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1257765621
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.4208468466
Short name T1059
Test name
Test status
Simulation time 45362755 ps
CPU time 0.77 seconds
Started Jul 14 05:33:44 PM PDT 24
Finished Jul 14 05:33:48 PM PDT 24
Peak memory 205192 kb
Host smart-aeb05cf8-c426-4628-b169-44a1dc5662b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208468466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.4208468466
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3818002453
Short name T149
Test name
Test status
Simulation time 327712403 ps
CPU time 2.71 seconds
Started Jul 14 05:33:47 PM PDT 24
Finished Jul 14 05:33:52 PM PDT 24
Peak memory 205524 kb
Host smart-94c58159-2641-4d83-8197-6c3c3cc4eb79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818002453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.3818002453
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3784824947
Short name T1008
Test name
Test status
Simulation time 283372879 ps
CPU time 4.13 seconds
Started Jul 14 05:33:46 PM PDT 24
Finished Jul 14 05:33:53 PM PDT 24
Peak memory 213980 kb
Host smart-d95770f3-c815-441a-9492-1422d388ff5a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784824947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.3784824947
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2017572235
Short name T1071
Test name
Test status
Simulation time 467358894 ps
CPU time 3.83 seconds
Started Jul 14 05:33:45 PM PDT 24
Finished Jul 14 05:33:51 PM PDT 24
Peak memory 214068 kb
Host smart-7517adbc-fc04-4cff-802d-e875f131f631
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017572235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.2017572235
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.3016831839
Short name T1033
Test name
Test status
Simulation time 436608933 ps
CPU time 3.1 seconds
Started Jul 14 05:33:51 PM PDT 24
Finished Jul 14 05:33:56 PM PDT 24
Peak memory 213660 kb
Host smart-5d5f4622-3573-491f-a533-ec26ea21f6fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016831839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.3016831839
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1403997892
Short name T967
Test name
Test status
Simulation time 98295313 ps
CPU time 1.5 seconds
Started Jul 14 05:33:50 PM PDT 24
Finished Jul 14 05:33:54 PM PDT 24
Peak memory 213700 kb
Host smart-601e94f1-640e-4595-b55f-e6f19b5ef446
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403997892 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.1403997892
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.1920813007
Short name T1012
Test name
Test status
Simulation time 15907940 ps
CPU time 1.11 seconds
Started Jul 14 05:33:44 PM PDT 24
Finished Jul 14 05:33:48 PM PDT 24
Peak memory 205564 kb
Host smart-ebf4016b-51d5-4140-aaf1-710145bffccb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920813007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.1920813007
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1990826155
Short name T981
Test name
Test status
Simulation time 12977647 ps
CPU time 0.86 seconds
Started Jul 14 05:33:50 PM PDT 24
Finished Jul 14 05:33:54 PM PDT 24
Peak memory 205312 kb
Host smart-d83b2952-6fdc-4a13-8089-5f42396352e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990826155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1990826155
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2822279573
Short name T943
Test name
Test status
Simulation time 344084880 ps
CPU time 2.59 seconds
Started Jul 14 05:33:46 PM PDT 24
Finished Jul 14 05:33:52 PM PDT 24
Peak memory 205528 kb
Host smart-99f4f1eb-5914-4394-a5da-51b5aab6cea8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822279573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.2822279573
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3113967111
Short name T1027
Test name
Test status
Simulation time 115410382 ps
CPU time 2.31 seconds
Started Jul 14 05:33:46 PM PDT 24
Finished Jul 14 05:33:51 PM PDT 24
Peak memory 213972 kb
Host smart-764016e1-c1f1-45e8-a238-a33b931340e7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113967111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3113967111
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3966078679
Short name T1043
Test name
Test status
Simulation time 944903864 ps
CPU time 7.92 seconds
Started Jul 14 05:33:48 PM PDT 24
Finished Jul 14 05:33:59 PM PDT 24
Peak memory 213940 kb
Host smart-039919c6-6b82-4fcf-ab0b-46fd6215f477
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966078679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3966078679
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.3110476765
Short name T1039
Test name
Test status
Simulation time 281652047 ps
CPU time 2.96 seconds
Started Jul 14 05:33:50 PM PDT 24
Finished Jul 14 05:33:55 PM PDT 24
Peak memory 216760 kb
Host smart-c233fe1c-126c-4ffe-89a4-53d4147cc187
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110476765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.3110476765
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.4120896519
Short name T953
Test name
Test status
Simulation time 186834896 ps
CPU time 2.13 seconds
Started Jul 14 05:33:48 PM PDT 24
Finished Jul 14 05:33:53 PM PDT 24
Peak memory 213788 kb
Host smart-7d675b4c-f8ad-400d-aa8e-78f3da0aab4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120896519 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.4120896519
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2532834794
Short name T1006
Test name
Test status
Simulation time 101781888 ps
CPU time 1.28 seconds
Started Jul 14 05:33:51 PM PDT 24
Finished Jul 14 05:33:54 PM PDT 24
Peak memory 205384 kb
Host smart-bc62e794-fe44-446f-aec6-7d4f37da85e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532834794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.2532834794
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.873691681
Short name T946
Test name
Test status
Simulation time 32823592 ps
CPU time 0.69 seconds
Started Jul 14 05:33:53 PM PDT 24
Finished Jul 14 05:33:55 PM PDT 24
Peak memory 205216 kb
Host smart-d9600c4c-ec33-4ec6-ab62-7391e4f41de7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873691681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.873691681
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.4066822512
Short name T986
Test name
Test status
Simulation time 395895225 ps
CPU time 2.71 seconds
Started Jul 14 05:33:49 PM PDT 24
Finished Jul 14 05:33:54 PM PDT 24
Peak memory 205484 kb
Host smart-50455441-09a1-4afd-8185-5d4cff2be1de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066822512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.4066822512
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.4054276087
Short name T976
Test name
Test status
Simulation time 100459695 ps
CPU time 3.46 seconds
Started Jul 14 05:33:49 PM PDT 24
Finished Jul 14 05:33:55 PM PDT 24
Peak memory 213900 kb
Host smart-14593b15-c236-4d22-92d4-dedc62b1bcb6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054276087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.4054276087
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.1716067889
Short name T955
Test name
Test status
Simulation time 904065454 ps
CPU time 5.45 seconds
Started Jul 14 05:33:47 PM PDT 24
Finished Jul 14 05:33:55 PM PDT 24
Peak memory 213876 kb
Host smart-e8f9868e-ee2e-4431-b225-dec862833b04
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716067889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.1716067889
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.2881622942
Short name T958
Test name
Test status
Simulation time 224269919 ps
CPU time 3.1 seconds
Started Jul 14 05:33:55 PM PDT 24
Finished Jul 14 05:33:59 PM PDT 24
Peak memory 221744 kb
Host smart-0bda01fe-e994-4762-bc12-e19de51eca55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881622942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.2881622942
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2275842915
Short name T1048
Test name
Test status
Simulation time 178483497 ps
CPU time 5.29 seconds
Started Jul 14 05:33:47 PM PDT 24
Finished Jul 14 05:33:55 PM PDT 24
Peak memory 205740 kb
Host smart-5d6e9f7e-3301-4193-a2bd-3ce8ba77d6f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275842915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.2275842915
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.4011524999
Short name T934
Test name
Test status
Simulation time 52361228 ps
CPU time 1.18 seconds
Started Jul 14 05:33:48 PM PDT 24
Finished Jul 14 05:33:52 PM PDT 24
Peak memory 213836 kb
Host smart-43b44126-6bdd-4b0a-ad6e-39c66f7af368
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011524999 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.4011524999
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3580619623
Short name T1073
Test name
Test status
Simulation time 117600052 ps
CPU time 1.01 seconds
Started Jul 14 05:33:46 PM PDT 24
Finished Jul 14 05:33:50 PM PDT 24
Peak memory 205428 kb
Host smart-0aa14a4c-f9b3-48d6-aa40-af73f717e1d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580619623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.3580619623
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.231359618
Short name T918
Test name
Test status
Simulation time 18968048 ps
CPU time 0.95 seconds
Started Jul 14 05:33:50 PM PDT 24
Finished Jul 14 05:33:53 PM PDT 24
Peak memory 205324 kb
Host smart-d82e38ec-6b83-4a6a-84e9-1814f0f5c2fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231359618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.231359618
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.4179384449
Short name T154
Test name
Test status
Simulation time 433370061 ps
CPU time 3.65 seconds
Started Jul 14 05:33:52 PM PDT 24
Finished Jul 14 05:33:58 PM PDT 24
Peak memory 205520 kb
Host smart-7b158320-7034-4446-8f3e-41dfaa335c7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179384449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.4179384449
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2443491802
Short name T122
Test name
Test status
Simulation time 217345332 ps
CPU time 3.57 seconds
Started Jul 14 05:33:54 PM PDT 24
Finished Jul 14 05:33:58 PM PDT 24
Peak memory 213888 kb
Host smart-4722d2f4-3c07-4037-a280-900567757249
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443491802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.2443491802
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1253086018
Short name T1047
Test name
Test status
Simulation time 591060280 ps
CPU time 2.88 seconds
Started Jul 14 05:33:54 PM PDT 24
Finished Jul 14 05:33:58 PM PDT 24
Peak memory 216764 kb
Host smart-483e3ac8-dcfe-4067-b2b8-f880ab28e3fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253086018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.1253086018
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2310636824
Short name T182
Test name
Test status
Simulation time 436197577 ps
CPU time 4.92 seconds
Started Jul 14 05:33:55 PM PDT 24
Finished Jul 14 05:34:01 PM PDT 24
Peak memory 213580 kb
Host smart-375a2d3b-d9c4-440b-9c70-9c17721c312f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310636824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.2310636824
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.149360940
Short name T189
Test name
Test status
Simulation time 78199276 ps
CPU time 1.67 seconds
Started Jul 14 05:33:49 PM PDT 24
Finished Jul 14 05:33:53 PM PDT 24
Peak memory 216232 kb
Host smart-bf9279db-e848-4cc5-a08f-543d7aff68d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149360940 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.149360940
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.2335866667
Short name T1011
Test name
Test status
Simulation time 14937603 ps
CPU time 1.29 seconds
Started Jul 14 05:33:50 PM PDT 24
Finished Jul 14 05:33:54 PM PDT 24
Peak memory 205348 kb
Host smart-235d6b5f-ad96-4efb-8a17-40a7090d3871
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335866667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.2335866667
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.243127876
Short name T919
Test name
Test status
Simulation time 25659067 ps
CPU time 0.83 seconds
Started Jul 14 05:33:50 PM PDT 24
Finished Jul 14 05:33:53 PM PDT 24
Peak memory 205196 kb
Host smart-3250f0aa-9bc9-456f-b1f5-de9531113e36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243127876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.243127876
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2118427953
Short name T949
Test name
Test status
Simulation time 72397015 ps
CPU time 2.49 seconds
Started Jul 14 05:33:55 PM PDT 24
Finished Jul 14 05:33:59 PM PDT 24
Peak memory 205480 kb
Host smart-6a82e375-496c-41cb-a380-0161f3f3c3d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118427953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.2118427953
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2877596502
Short name T961
Test name
Test status
Simulation time 278570998 ps
CPU time 1.53 seconds
Started Jul 14 05:33:53 PM PDT 24
Finished Jul 14 05:33:56 PM PDT 24
Peak memory 214032 kb
Host smart-71e67ad5-b6ca-4d4a-adba-e2b4ee2359ab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877596502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.2877596502
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1164417572
Short name T1024
Test name
Test status
Simulation time 144784975 ps
CPU time 3.43 seconds
Started Jul 14 05:33:49 PM PDT 24
Finished Jul 14 05:33:56 PM PDT 24
Peak memory 214052 kb
Host smart-98a329ab-1a36-4d31-8c19-d15a3c90e019
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164417572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.1164417572
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.1620133782
Short name T195
Test name
Test status
Simulation time 101426544 ps
CPU time 2.52 seconds
Started Jul 14 05:33:50 PM PDT 24
Finished Jul 14 05:33:55 PM PDT 24
Peak memory 214896 kb
Host smart-ba38d385-ce51-4060-ab7a-97f5316290b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620133782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.1620133782
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.246872760
Short name T177
Test name
Test status
Simulation time 172612869 ps
CPU time 2.55 seconds
Started Jul 14 05:33:47 PM PDT 24
Finished Jul 14 05:33:52 PM PDT 24
Peak memory 205572 kb
Host smart-0b39b631-73f5-4787-8eec-887331d6aa60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246872760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err
.246872760
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.2300573616
Short name T1013
Test name
Test status
Simulation time 130377107 ps
CPU time 7.64 seconds
Started Jul 14 05:33:40 PM PDT 24
Finished Jul 14 05:33:50 PM PDT 24
Peak memory 205352 kb
Host smart-6c772784-ef83-4257-a977-c58a7bc3fc07
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300573616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.2
300573616
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3264778960
Short name T1069
Test name
Test status
Simulation time 515337552 ps
CPU time 6.82 seconds
Started Jul 14 05:33:39 PM PDT 24
Finished Jul 14 05:33:48 PM PDT 24
Peak memory 205512 kb
Host smart-c3f0ab4b-d80f-4b2d-87c1-de358b41d904
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264778960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.3
264778960
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3191635793
Short name T962
Test name
Test status
Simulation time 141359232 ps
CPU time 1.48 seconds
Started Jul 14 05:33:34 PM PDT 24
Finished Jul 14 05:33:36 PM PDT 24
Peak memory 205436 kb
Host smart-8769080d-a5b0-4bbb-b9f2-1ccd75da0e80
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191635793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.3
191635793
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1029260979
Short name T1030
Test name
Test status
Simulation time 28912580 ps
CPU time 1.69 seconds
Started Jul 14 05:33:31 PM PDT 24
Finished Jul 14 05:33:33 PM PDT 24
Peak memory 205648 kb
Host smart-5b29abe2-efc7-47b0-ac96-c5a7cbf25e6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029260979 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.1029260979
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.108870615
Short name T1034
Test name
Test status
Simulation time 71286363 ps
CPU time 1.15 seconds
Started Jul 14 05:33:35 PM PDT 24
Finished Jul 14 05:33:37 PM PDT 24
Peak memory 205272 kb
Host smart-0958f9fa-0f41-42e7-9419-d1e9b0d5695c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108870615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.108870615
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.3373474147
Short name T1003
Test name
Test status
Simulation time 32883533 ps
CPU time 0.76 seconds
Started Jul 14 05:33:31 PM PDT 24
Finished Jul 14 05:33:33 PM PDT 24
Peak memory 205300 kb
Host smart-7bcc5dd4-0894-4940-987f-216f7cf67535
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373474147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.3373474147
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.504421097
Short name T998
Test name
Test status
Simulation time 72120186 ps
CPU time 2.52 seconds
Started Jul 14 05:33:33 PM PDT 24
Finished Jul 14 05:33:37 PM PDT 24
Peak memory 205476 kb
Host smart-cd2253d8-75ee-4b93-895b-29dba520cb7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504421097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sam
e_csr_outstanding.504421097
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2754290731
Short name T1017
Test name
Test status
Simulation time 91038965 ps
CPU time 1.97 seconds
Started Jul 14 05:33:31 PM PDT 24
Finished Jul 14 05:33:33 PM PDT 24
Peak memory 213976 kb
Host smart-8cf54fc7-4059-4311-9cb3-f54bd653d415
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754290731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.2754290731
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.1849846502
Short name T1019
Test name
Test status
Simulation time 398770640 ps
CPU time 5.54 seconds
Started Jul 14 05:33:34 PM PDT 24
Finished Jul 14 05:33:40 PM PDT 24
Peak memory 213996 kb
Host smart-1806f053-2901-4290-bd0b-10f97a961a46
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849846502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.1849846502
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2982675783
Short name T1057
Test name
Test status
Simulation time 161051079 ps
CPU time 2.94 seconds
Started Jul 14 05:33:33 PM PDT 24
Finished Jul 14 05:33:37 PM PDT 24
Peak memory 221792 kb
Host smart-51cbeb19-c157-4a00-b698-55893f53e26a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982675783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.2982675783
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2929581132
Short name T164
Test name
Test status
Simulation time 52314410 ps
CPU time 2.79 seconds
Started Jul 14 05:33:33 PM PDT 24
Finished Jul 14 05:33:37 PM PDT 24
Peak memory 215176 kb
Host smart-b36a453c-0f74-497b-85db-98ead9680b32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929581132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.2929581132
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1011761463
Short name T1078
Test name
Test status
Simulation time 80886001 ps
CPU time 0.79 seconds
Started Jul 14 05:33:49 PM PDT 24
Finished Jul 14 05:33:53 PM PDT 24
Peak memory 205332 kb
Host smart-13952fdb-f688-415a-9c55-672fee1f8438
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011761463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.1011761463
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3695907054
Short name T995
Test name
Test status
Simulation time 172119974 ps
CPU time 0.86 seconds
Started Jul 14 05:33:50 PM PDT 24
Finished Jul 14 05:33:53 PM PDT 24
Peak memory 205332 kb
Host smart-7472373f-975b-4651-b393-8887fe3a97d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695907054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.3695907054
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.3793993124
Short name T1081
Test name
Test status
Simulation time 10151751 ps
CPU time 0.85 seconds
Started Jul 14 05:33:49 PM PDT 24
Finished Jul 14 05:33:53 PM PDT 24
Peak memory 205336 kb
Host smart-c5a4b451-1d06-4c49-923a-e257e1630040
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793993124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.3793993124
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2166145801
Short name T938
Test name
Test status
Simulation time 12860101 ps
CPU time 0.81 seconds
Started Jul 14 05:33:50 PM PDT 24
Finished Jul 14 05:33:54 PM PDT 24
Peak memory 205132 kb
Host smart-828f3b2d-ffcb-4d8f-84d6-cb762143fdec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166145801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2166145801
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.837389085
Short name T1080
Test name
Test status
Simulation time 49012078 ps
CPU time 0.8 seconds
Started Jul 14 05:33:57 PM PDT 24
Finished Jul 14 05:33:58 PM PDT 24
Peak memory 205260 kb
Host smart-6074e156-91fc-4b71-9b41-c0ffa2f5a2ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837389085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.837389085
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.73497029
Short name T1084
Test name
Test status
Simulation time 29216494 ps
CPU time 0.77 seconds
Started Jul 14 05:33:58 PM PDT 24
Finished Jul 14 05:34:00 PM PDT 24
Peak memory 205236 kb
Host smart-ee250777-e9bb-4224-8993-538fb4cd3974
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73497029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.73497029
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3197768432
Short name T917
Test name
Test status
Simulation time 13985334 ps
CPU time 0.76 seconds
Started Jul 14 05:33:56 PM PDT 24
Finished Jul 14 05:33:57 PM PDT 24
Peak memory 205312 kb
Host smart-79988f10-7925-413e-8c4e-d1375f3a7058
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197768432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.3197768432
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3501732741
Short name T1007
Test name
Test status
Simulation time 37159979 ps
CPU time 0.69 seconds
Started Jul 14 05:33:58 PM PDT 24
Finished Jul 14 05:34:00 PM PDT 24
Peak memory 205232 kb
Host smart-54d1be0b-d563-4f0a-93e7-f57539c137ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501732741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3501732741
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.3418768910
Short name T1045
Test name
Test status
Simulation time 84938555 ps
CPU time 0.95 seconds
Started Jul 14 05:33:58 PM PDT 24
Finished Jul 14 05:34:00 PM PDT 24
Peak memory 205396 kb
Host smart-1051d4d1-4a2b-473e-9c93-1902ac4bcd57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418768910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.3418768910
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2609523718
Short name T948
Test name
Test status
Simulation time 12643056 ps
CPU time 0.74 seconds
Started Jul 14 05:33:57 PM PDT 24
Finished Jul 14 05:33:59 PM PDT 24
Peak memory 205228 kb
Host smart-d1c92797-ac5a-42bd-bf6d-9f7efca9afd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609523718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.2609523718
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.1100952575
Short name T1022
Test name
Test status
Simulation time 233292981 ps
CPU time 4.65 seconds
Started Jul 14 05:33:39 PM PDT 24
Finished Jul 14 05:33:45 PM PDT 24
Peak memory 205580 kb
Host smart-4b91d17c-f0da-4c63-b384-336246ac09c6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100952575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.1
100952575
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1492669331
Short name T945
Test name
Test status
Simulation time 136241380 ps
CPU time 7.43 seconds
Started Jul 14 05:33:32 PM PDT 24
Finished Jul 14 05:33:41 PM PDT 24
Peak memory 205520 kb
Host smart-ce3eedc9-d1bc-4691-95fa-13222506963e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492669331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.1
492669331
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3452022599
Short name T999
Test name
Test status
Simulation time 12800235 ps
CPU time 0.94 seconds
Started Jul 14 05:33:33 PM PDT 24
Finished Jul 14 05:33:35 PM PDT 24
Peak memory 205468 kb
Host smart-7f9f726b-5a79-46dd-86d6-18b8b168f937
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452022599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.3
452022599
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2544623467
Short name T926
Test name
Test status
Simulation time 71813338 ps
CPU time 2.38 seconds
Started Jul 14 05:33:35 PM PDT 24
Finished Jul 14 05:33:38 PM PDT 24
Peak memory 213844 kb
Host smart-49fa8020-de5e-4b72-b2b4-236ada1ec294
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544623467 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2544623467
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3724725922
Short name T963
Test name
Test status
Simulation time 14329748 ps
CPU time 0.92 seconds
Started Jul 14 05:33:40 PM PDT 24
Finished Jul 14 05:33:43 PM PDT 24
Peak memory 205192 kb
Host smart-45e5a3e5-7a5a-470d-a4e9-1cb4f46ad39d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724725922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3724725922
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.2624537277
Short name T952
Test name
Test status
Simulation time 53903089 ps
CPU time 0.77 seconds
Started Jul 14 05:33:35 PM PDT 24
Finished Jul 14 05:33:36 PM PDT 24
Peak memory 205320 kb
Host smart-b34e644c-00b7-4bd7-b6f2-cf2c7cb63782
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624537277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.2624537277
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.240141771
Short name T1076
Test name
Test status
Simulation time 21368374 ps
CPU time 1.73 seconds
Started Jul 14 05:33:32 PM PDT 24
Finished Jul 14 05:33:35 PM PDT 24
Peak memory 205432 kb
Host smart-ccb81476-aa42-43d9-8c6e-858bca72e635
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240141771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sam
e_csr_outstanding.240141771
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3540659444
Short name T939
Test name
Test status
Simulation time 121338306 ps
CPU time 1.93 seconds
Started Jul 14 05:33:32 PM PDT 24
Finished Jul 14 05:33:35 PM PDT 24
Peak memory 213840 kb
Host smart-4723edc6-bd47-4a49-b3a6-f1b651b9505b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540659444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.3540659444
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1191851142
Short name T935
Test name
Test status
Simulation time 694384878 ps
CPU time 8 seconds
Started Jul 14 05:33:39 PM PDT 24
Finished Jul 14 05:33:49 PM PDT 24
Peak memory 214100 kb
Host smart-c0c624b3-c5f6-465b-941f-deac0865a9cc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191851142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1191851142
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.201303879
Short name T1066
Test name
Test status
Simulation time 86791037 ps
CPU time 3.3 seconds
Started Jul 14 05:33:40 PM PDT 24
Finished Jul 14 05:33:45 PM PDT 24
Peak memory 216628 kb
Host smart-2c466d2a-3a4e-40b6-8aa5-18cb36ec8fcb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201303879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.201303879
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.1334364473
Short name T169
Test name
Test status
Simulation time 502269638 ps
CPU time 10.39 seconds
Started Jul 14 05:33:31 PM PDT 24
Finished Jul 14 05:33:43 PM PDT 24
Peak memory 216244 kb
Host smart-2725db58-4588-4592-a687-f3f45c7ff9e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334364473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.1334364473
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3608393517
Short name T1083
Test name
Test status
Simulation time 152890061 ps
CPU time 0.81 seconds
Started Jul 14 05:33:57 PM PDT 24
Finished Jul 14 05:33:59 PM PDT 24
Peak memory 205232 kb
Host smart-d8a71d80-03c2-43fa-9929-f08f64b1f140
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608393517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3608393517
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.1101817997
Short name T923
Test name
Test status
Simulation time 14910924 ps
CPU time 0.8 seconds
Started Jul 14 05:33:57 PM PDT 24
Finished Jul 14 05:33:59 PM PDT 24
Peak memory 205308 kb
Host smart-47c7d852-9172-4876-86ad-96fd78fcf02e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101817997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.1101817997
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.720596052
Short name T1055
Test name
Test status
Simulation time 36280250 ps
CPU time 0.75 seconds
Started Jul 14 05:33:58 PM PDT 24
Finished Jul 14 05:34:00 PM PDT 24
Peak memory 205260 kb
Host smart-291ce95f-fd0d-4aab-a34a-c7436e616341
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720596052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.720596052
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.421162960
Short name T1035
Test name
Test status
Simulation time 12034803 ps
CPU time 0.92 seconds
Started Jul 14 05:33:54 PM PDT 24
Finished Jul 14 05:33:57 PM PDT 24
Peak memory 205304 kb
Host smart-7e9ddc65-8487-4685-955a-a0f710c47f54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421162960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.421162960
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.568498643
Short name T1065
Test name
Test status
Simulation time 14127537 ps
CPU time 0.86 seconds
Started Jul 14 05:33:53 PM PDT 24
Finished Jul 14 05:33:55 PM PDT 24
Peak memory 205408 kb
Host smart-e56ee378-94ae-460f-acfd-f39c6c42e328
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568498643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.568498643
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1682871441
Short name T1037
Test name
Test status
Simulation time 38531525 ps
CPU time 0.74 seconds
Started Jul 14 05:33:57 PM PDT 24
Finished Jul 14 05:33:58 PM PDT 24
Peak memory 205344 kb
Host smart-cb57a6a2-fd30-4ed1-a6dc-805ad3423e9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682871441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.1682871441
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1754244242
Short name T1060
Test name
Test status
Simulation time 65727056 ps
CPU time 0.7 seconds
Started Jul 14 05:33:56 PM PDT 24
Finished Jul 14 05:33:57 PM PDT 24
Peak memory 205272 kb
Host smart-9792f8da-ba6c-4cb2-a732-3a9711effb00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754244242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.1754244242
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2791415447
Short name T1070
Test name
Test status
Simulation time 48067742 ps
CPU time 0.74 seconds
Started Jul 14 05:34:07 PM PDT 24
Finished Jul 14 05:34:09 PM PDT 24
Peak memory 205192 kb
Host smart-6461d922-62e4-4a87-806c-ca895f876c3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791415447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.2791415447
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.2159391126
Short name T984
Test name
Test status
Simulation time 39503287 ps
CPU time 0.81 seconds
Started Jul 14 05:34:07 PM PDT 24
Finished Jul 14 05:34:09 PM PDT 24
Peak memory 205132 kb
Host smart-f1fdd557-2319-4f7e-a97a-8692cc43fe88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159391126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.2159391126
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.102075017
Short name T956
Test name
Test status
Simulation time 8873404 ps
CPU time 0.75 seconds
Started Jul 14 05:33:59 PM PDT 24
Finished Jul 14 05:34:01 PM PDT 24
Peak memory 205232 kb
Host smart-7ad18665-b0bf-4571-bedb-782c50c976f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102075017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.102075017
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.759022453
Short name T996
Test name
Test status
Simulation time 68816657 ps
CPU time 4.57 seconds
Started Jul 14 05:33:40 PM PDT 24
Finished Jul 14 05:33:46 PM PDT 24
Peak memory 205400 kb
Host smart-21d8394f-07af-4385-bcb7-5ba232b871e0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759022453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.759022453
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.3854257790
Short name T944
Test name
Test status
Simulation time 260536138 ps
CPU time 12.3 seconds
Started Jul 14 05:33:41 PM PDT 24
Finished Jul 14 05:33:55 PM PDT 24
Peak memory 205408 kb
Host smart-628c5e2d-7b55-4cb1-844b-a4c8524596d4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854257790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.3
854257790
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.4143367992
Short name T1025
Test name
Test status
Simulation time 124864816 ps
CPU time 1.39 seconds
Started Jul 14 05:33:39 PM PDT 24
Finished Jul 14 05:33:42 PM PDT 24
Peak memory 213720 kb
Host smart-eda2ca0d-cee8-438b-acd7-c35c8e9c2238
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143367992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.4
143367992
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.996549923
Short name T1002
Test name
Test status
Simulation time 121078293 ps
CPU time 1.13 seconds
Started Jul 14 05:33:41 PM PDT 24
Finished Jul 14 05:33:44 PM PDT 24
Peak memory 205540 kb
Host smart-cb0d7054-8d59-47a3-a01f-895c6f23e319
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996549923 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.996549923
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.2454509230
Short name T974
Test name
Test status
Simulation time 113018802 ps
CPU time 1.09 seconds
Started Jul 14 05:33:39 PM PDT 24
Finished Jul 14 05:33:41 PM PDT 24
Peak memory 205468 kb
Host smart-352674fa-2e56-4e5a-8004-b9761935e8aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454509230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.2454509230
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.743704534
Short name T1032
Test name
Test status
Simulation time 10668640 ps
CPU time 0.73 seconds
Started Jul 14 05:33:37 PM PDT 24
Finished Jul 14 05:33:39 PM PDT 24
Peak memory 205228 kb
Host smart-0f059a64-16a6-4c36-97f6-b340e36c1511
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743704534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.743704534
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1461760651
Short name T960
Test name
Test status
Simulation time 138012480 ps
CPU time 2.3 seconds
Started Jul 14 05:33:40 PM PDT 24
Finished Jul 14 05:33:44 PM PDT 24
Peak memory 205496 kb
Host smart-5e92e208-449b-4089-b30f-4750d48dbdd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461760651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.1461760651
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1308318651
Short name T1009
Test name
Test status
Simulation time 243197262 ps
CPU time 1.36 seconds
Started Jul 14 05:33:40 PM PDT 24
Finished Jul 14 05:33:44 PM PDT 24
Peak memory 213780 kb
Host smart-6a8e1f42-91e2-44c4-916e-87dd64966128
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308318651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1308318651
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.4169661916
Short name T1041
Test name
Test status
Simulation time 473061091 ps
CPU time 9.88 seconds
Started Jul 14 05:33:39 PM PDT 24
Finished Jul 14 05:33:50 PM PDT 24
Peak memory 214064 kb
Host smart-05a5544f-c684-4266-bec1-2c51297a15e0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169661916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.4169661916
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.3415766532
Short name T922
Test name
Test status
Simulation time 74294805 ps
CPU time 2.69 seconds
Started Jul 14 05:33:34 PM PDT 24
Finished Jul 14 05:33:38 PM PDT 24
Peak memory 213948 kb
Host smart-cc040f4d-4528-4781-b82c-7d9a70c78846
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415766532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.3415766532
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.1993319192
Short name T1062
Test name
Test status
Simulation time 21041131 ps
CPU time 0.84 seconds
Started Jul 14 05:33:56 PM PDT 24
Finished Jul 14 05:33:57 PM PDT 24
Peak memory 205344 kb
Host smart-68461389-fd22-44ba-a5e0-6c3d667a57cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993319192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.1993319192
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.1495795073
Short name T921
Test name
Test status
Simulation time 26855656 ps
CPU time 0.9 seconds
Started Jul 14 05:33:59 PM PDT 24
Finished Jul 14 05:34:00 PM PDT 24
Peak memory 205232 kb
Host smart-ef558297-33a5-436b-ba20-50a6c544d16a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495795073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.1495795073
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1170919499
Short name T1067
Test name
Test status
Simulation time 24399154 ps
CPU time 0.7 seconds
Started Jul 14 05:34:07 PM PDT 24
Finished Jul 14 05:34:09 PM PDT 24
Peak memory 205148 kb
Host smart-33c3a22e-f122-4094-bee7-53ad0b85759e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170919499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.1170919499
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.2276756579
Short name T993
Test name
Test status
Simulation time 9056750 ps
CPU time 0.78 seconds
Started Jul 14 05:33:54 PM PDT 24
Finished Jul 14 05:33:56 PM PDT 24
Peak memory 205324 kb
Host smart-d14e9784-80c2-4bf2-a6a4-ce7bde0f13e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276756579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.2276756579
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2098514039
Short name T1053
Test name
Test status
Simulation time 20704216 ps
CPU time 0.9 seconds
Started Jul 14 05:34:07 PM PDT 24
Finished Jul 14 05:34:09 PM PDT 24
Peak memory 205224 kb
Host smart-24f4e032-2058-4998-b04d-c578eb20f2b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098514039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.2098514039
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.4248898615
Short name T932
Test name
Test status
Simulation time 11380174 ps
CPU time 0.72 seconds
Started Jul 14 05:33:54 PM PDT 24
Finished Jul 14 05:33:56 PM PDT 24
Peak memory 205336 kb
Host smart-9225a96c-2120-4fac-baba-447eec94feca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248898615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.4248898615
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.3490456565
Short name T971
Test name
Test status
Simulation time 19860943 ps
CPU time 0.82 seconds
Started Jul 14 05:34:05 PM PDT 24
Finished Jul 14 05:34:07 PM PDT 24
Peak memory 205220 kb
Host smart-7b2dabd9-38f3-4311-9be7-c6768fce7143
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490456565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.3490456565
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3702873038
Short name T983
Test name
Test status
Simulation time 47080450 ps
CPU time 0.87 seconds
Started Jul 14 05:34:07 PM PDT 24
Finished Jul 14 05:34:09 PM PDT 24
Peak memory 205172 kb
Host smart-ffb14706-4972-434d-8e75-8d6caca36160
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702873038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3702873038
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1561418969
Short name T941
Test name
Test status
Simulation time 14291925 ps
CPU time 0.76 seconds
Started Jul 14 05:33:54 PM PDT 24
Finished Jul 14 05:33:56 PM PDT 24
Peak memory 205256 kb
Host smart-a83b5c2f-8bbd-4aee-947d-70175809db21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561418969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.1561418969
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.388521431
Short name T1051
Test name
Test status
Simulation time 14732246 ps
CPU time 0.73 seconds
Started Jul 14 05:34:07 PM PDT 24
Finished Jul 14 05:34:09 PM PDT 24
Peak memory 205016 kb
Host smart-265c57f2-649a-47c7-b9c8-37fb6085e600
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388521431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.388521431
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3999305803
Short name T188
Test name
Test status
Simulation time 53914879 ps
CPU time 1.66 seconds
Started Jul 14 05:33:38 PM PDT 24
Finished Jul 14 05:33:40 PM PDT 24
Peak memory 213784 kb
Host smart-547c14de-c16d-4cbb-9f49-a6e8c12e154f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999305803 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3999305803
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.814626284
Short name T1046
Test name
Test status
Simulation time 50802369 ps
CPU time 1.53 seconds
Started Jul 14 05:33:39 PM PDT 24
Finished Jul 14 05:33:41 PM PDT 24
Peak memory 205276 kb
Host smart-9cd2bc13-fd53-4f3e-b3a1-2b6076ec5494
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814626284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.814626284
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.225378507
Short name T985
Test name
Test status
Simulation time 12250015 ps
CPU time 0.72 seconds
Started Jul 14 05:33:42 PM PDT 24
Finished Jul 14 05:33:44 PM PDT 24
Peak memory 205228 kb
Host smart-db83cfe7-f4bf-42ba-a7fe-198849908bb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225378507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.225378507
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.2821250901
Short name T970
Test name
Test status
Simulation time 236378815 ps
CPU time 2.28 seconds
Started Jul 14 05:33:40 PM PDT 24
Finished Jul 14 05:33:44 PM PDT 24
Peak memory 205544 kb
Host smart-bfc077fc-f0e9-4c9e-ae52-29239000b519
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821250901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.2821250901
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.472552472
Short name T977
Test name
Test status
Simulation time 416580309 ps
CPU time 2.39 seconds
Started Jul 14 05:33:38 PM PDT 24
Finished Jul 14 05:33:41 PM PDT 24
Peak memory 213972 kb
Host smart-2ee43687-a9a6-48de-be65-d08e86b12703
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472552472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow
_reg_errors.472552472
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.880890123
Short name T1016
Test name
Test status
Simulation time 698692294 ps
CPU time 6.82 seconds
Started Jul 14 05:33:37 PM PDT 24
Finished Jul 14 05:33:44 PM PDT 24
Peak memory 213976 kb
Host smart-7a41d99b-916b-4ea3-97af-9b26490b621d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880890123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_shadow_reg_errors_with_csr_rw.880890123
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.1374499020
Short name T975
Test name
Test status
Simulation time 690912365 ps
CPU time 3.69 seconds
Started Jul 14 05:33:40 PM PDT 24
Finished Jul 14 05:33:45 PM PDT 24
Peak memory 216772 kb
Host smart-1403a34a-eb1b-4233-92ad-7c4da643a529
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374499020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.1374499020
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1896238030
Short name T174
Test name
Test status
Simulation time 243399252 ps
CPU time 6.69 seconds
Started Jul 14 05:33:38 PM PDT 24
Finished Jul 14 05:33:46 PM PDT 24
Peak memory 213720 kb
Host smart-c7d922e9-943d-4f14-abd9-c7a0aec67e58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896238030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.1896238030
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1882996809
Short name T1018
Test name
Test status
Simulation time 266106597 ps
CPU time 2.07 seconds
Started Jul 14 05:33:37 PM PDT 24
Finished Jul 14 05:33:40 PM PDT 24
Peak memory 213860 kb
Host smart-7a7e569d-418f-4cf6-9276-f55c8f3ab9cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882996809 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.1882996809
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1660706503
Short name T979
Test name
Test status
Simulation time 46522981 ps
CPU time 1.01 seconds
Started Jul 14 05:33:38 PM PDT 24
Finished Jul 14 05:33:39 PM PDT 24
Peak memory 205456 kb
Host smart-6c7be955-98c0-4f88-a6fc-dad211fa198f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660706503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1660706503
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2594592853
Short name T1038
Test name
Test status
Simulation time 13064000 ps
CPU time 0.7 seconds
Started Jul 14 05:33:43 PM PDT 24
Finished Jul 14 05:33:45 PM PDT 24
Peak memory 205204 kb
Host smart-48def9f3-db46-4936-bd1e-9fd22db18a0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594592853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.2594592853
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1557350328
Short name T940
Test name
Test status
Simulation time 223158832 ps
CPU time 1.5 seconds
Started Jul 14 05:33:43 PM PDT 24
Finished Jul 14 05:33:46 PM PDT 24
Peak memory 205572 kb
Host smart-98c601e2-6e6e-45c5-8963-d1e594e79a3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557350328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.1557350328
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.4164818853
Short name T1072
Test name
Test status
Simulation time 676603028 ps
CPU time 2.47 seconds
Started Jul 14 05:33:40 PM PDT 24
Finished Jul 14 05:33:44 PM PDT 24
Peak memory 214024 kb
Host smart-31f22028-b09f-4992-9adc-db696b09773c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164818853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.4164818853
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.2123159451
Short name T972
Test name
Test status
Simulation time 204234782 ps
CPU time 9.01 seconds
Started Jul 14 05:33:41 PM PDT 24
Finished Jul 14 05:33:52 PM PDT 24
Peak memory 220216 kb
Host smart-6dbf332d-41b4-484c-8436-08dacec14110
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123159451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.2123159451
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2778845031
Short name T1010
Test name
Test status
Simulation time 348689683 ps
CPU time 2.34 seconds
Started Jul 14 05:33:37 PM PDT 24
Finished Jul 14 05:33:40 PM PDT 24
Peak memory 213788 kb
Host smart-a3f2e1c0-ba2c-4995-b076-2d115deea54e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778845031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2778845031
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.1685113182
Short name T366
Test name
Test status
Simulation time 4769492330 ps
CPU time 7.8 seconds
Started Jul 14 05:33:40 PM PDT 24
Finished Jul 14 05:33:50 PM PDT 24
Peak memory 213768 kb
Host smart-4588669e-1371-4459-9ddf-b7c59828975a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685113182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.1685113182
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.4078356131
Short name T968
Test name
Test status
Simulation time 28980385 ps
CPU time 1.11 seconds
Started Jul 14 05:33:37 PM PDT 24
Finished Jul 14 05:33:39 PM PDT 24
Peak memory 205532 kb
Host smart-afec835c-8e9f-4395-ac51-fa81173c8250
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078356131 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.4078356131
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.4195624236
Short name T152
Test name
Test status
Simulation time 78372946 ps
CPU time 1 seconds
Started Jul 14 05:33:43 PM PDT 24
Finished Jul 14 05:33:46 PM PDT 24
Peak memory 205376 kb
Host smart-ae34e802-a124-40f8-995e-a97f00e390a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195624236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.4195624236
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.1235905227
Short name T966
Test name
Test status
Simulation time 60280337 ps
CPU time 0.88 seconds
Started Jul 14 05:33:43 PM PDT 24
Finished Jul 14 05:33:46 PM PDT 24
Peak memory 205312 kb
Host smart-aa5e899d-9daf-423f-b83a-c6f4fb596474
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235905227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.1235905227
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1219646529
Short name T942
Test name
Test status
Simulation time 182215006 ps
CPU time 1.71 seconds
Started Jul 14 05:33:36 PM PDT 24
Finished Jul 14 05:33:38 PM PDT 24
Peak memory 205468 kb
Host smart-7bf7865a-6f5f-4ac7-b6ac-5aa827000d0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219646529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.1219646529
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.905846223
Short name T1074
Test name
Test status
Simulation time 75698316 ps
CPU time 2.29 seconds
Started Jul 14 05:33:40 PM PDT 24
Finished Jul 14 05:33:44 PM PDT 24
Peak memory 213916 kb
Host smart-da054caf-34d7-4efc-8657-4645c6f76b23
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905846223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow
_reg_errors.905846223
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3565569447
Short name T121
Test name
Test status
Simulation time 1015031361 ps
CPU time 5.63 seconds
Started Jul 14 05:33:41 PM PDT 24
Finished Jul 14 05:33:48 PM PDT 24
Peak memory 214120 kb
Host smart-c162bd5e-ada4-4620-a44f-8215e8bcacdd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565569447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.3565569447
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1601344918
Short name T933
Test name
Test status
Simulation time 77999560 ps
CPU time 2.07 seconds
Started Jul 14 05:33:42 PM PDT 24
Finished Jul 14 05:33:46 PM PDT 24
Peak memory 213672 kb
Host smart-79b25067-d90b-4720-8eef-c9673973d3ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601344918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.1601344918
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1738225677
Short name T927
Test name
Test status
Simulation time 55378769 ps
CPU time 1.17 seconds
Started Jul 14 05:33:39 PM PDT 24
Finished Jul 14 05:33:41 PM PDT 24
Peak memory 205508 kb
Host smart-d7071d68-d5a1-4fd5-85c1-a0e1172aa21f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738225677 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.1738225677
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.4063933518
Short name T167
Test name
Test status
Simulation time 29466820 ps
CPU time 1.37 seconds
Started Jul 14 05:33:43 PM PDT 24
Finished Jul 14 05:33:45 PM PDT 24
Peak memory 205452 kb
Host smart-3b1fe8ac-4426-4f70-904a-7d05c7191545
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063933518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.4063933518
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2227203445
Short name T1075
Test name
Test status
Simulation time 13811001 ps
CPU time 0.69 seconds
Started Jul 14 05:33:38 PM PDT 24
Finished Jul 14 05:33:39 PM PDT 24
Peak memory 205316 kb
Host smart-dc027b33-5914-43ac-ab53-ea9c1c508776
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227203445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.2227203445
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1978185069
Short name T1029
Test name
Test status
Simulation time 57403213 ps
CPU time 2.4 seconds
Started Jul 14 05:33:38 PM PDT 24
Finished Jul 14 05:33:41 PM PDT 24
Peak memory 205400 kb
Host smart-9feaf0a6-493b-446c-8a92-5d50d626ffab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978185069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.1978185069
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2033695383
Short name T117
Test name
Test status
Simulation time 309021267 ps
CPU time 6.56 seconds
Started Jul 14 05:33:40 PM PDT 24
Finished Jul 14 05:33:49 PM PDT 24
Peak memory 214116 kb
Host smart-570a3e34-2af3-4989-a1fd-8c7130e13627
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033695383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.2033695383
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.3532573864
Short name T964
Test name
Test status
Simulation time 650770673 ps
CPU time 3.97 seconds
Started Jul 14 05:33:42 PM PDT 24
Finished Jul 14 05:33:47 PM PDT 24
Peak memory 219980 kb
Host smart-6b140a8a-672f-460c-98f0-6097d58facee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532573864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.3532573864
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.993612253
Short name T987
Test name
Test status
Simulation time 190846947 ps
CPU time 2.2 seconds
Started Jul 14 05:33:40 PM PDT 24
Finished Jul 14 05:33:44 PM PDT 24
Peak memory 214352 kb
Host smart-5778bf80-647c-4b77-8fbe-702a7ee115ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993612253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.993612253
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2092740442
Short name T1079
Test name
Test status
Simulation time 56321938 ps
CPU time 2.05 seconds
Started Jul 14 05:33:43 PM PDT 24
Finished Jul 14 05:33:46 PM PDT 24
Peak memory 213764 kb
Host smart-c4539077-5f06-4594-9a00-7979376bd1fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092740442 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.2092740442
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2670808444
Short name T1028
Test name
Test status
Simulation time 56472759 ps
CPU time 1.01 seconds
Started Jul 14 05:33:43 PM PDT 24
Finished Jul 14 05:33:47 PM PDT 24
Peak memory 205464 kb
Host smart-d376baa7-99e4-4f30-bfd1-b090ccfea230
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670808444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.2670808444
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1154664447
Short name T920
Test name
Test status
Simulation time 29834318 ps
CPU time 0.72 seconds
Started Jul 14 05:33:44 PM PDT 24
Finished Jul 14 05:33:47 PM PDT 24
Peak memory 205336 kb
Host smart-bc6633f8-8ee5-4ab0-8d5b-bd91ec13e228
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154664447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.1154664447
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.3728035411
Short name T1036
Test name
Test status
Simulation time 56781509 ps
CPU time 1.85 seconds
Started Jul 14 05:33:49 PM PDT 24
Finished Jul 14 05:33:54 PM PDT 24
Peak memory 205540 kb
Host smart-c1e97d02-032a-455c-8771-c7194d0002c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728035411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.3728035411
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2786973659
Short name T931
Test name
Test status
Simulation time 201384412 ps
CPU time 3.44 seconds
Started Jul 14 05:33:39 PM PDT 24
Finished Jul 14 05:33:44 PM PDT 24
Peak memory 218368 kb
Host smart-c9db6025-3a0c-4240-b636-93ba9f8b0d0f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786973659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.2786973659
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.3352098376
Short name T1052
Test name
Test status
Simulation time 287161069 ps
CPU time 8.31 seconds
Started Jul 14 05:33:40 PM PDT 24
Finished Jul 14 05:33:50 PM PDT 24
Peak memory 213984 kb
Host smart-f83e4e40-78be-492d-910d-9d6174f385d1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352098376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.3352098376
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3757580182
Short name T988
Test name
Test status
Simulation time 175613008 ps
CPU time 2.98 seconds
Started Jul 14 05:33:36 PM PDT 24
Finished Jul 14 05:33:40 PM PDT 24
Peak memory 217064 kb
Host smart-e24750c7-a5c6-4462-af45-c5ce36c8664d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757580182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3757580182
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3502820531
Short name T181
Test name
Test status
Simulation time 159440102 ps
CPU time 3.57 seconds
Started Jul 14 05:33:42 PM PDT 24
Finished Jul 14 05:33:47 PM PDT 24
Peak memory 214884 kb
Host smart-c6a6a9f9-7b73-489b-9fef-5f247d102bf5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502820531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.3502820531
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.627963570
Short name T571
Test name
Test status
Simulation time 13268047 ps
CPU time 0.8 seconds
Started Jul 14 06:52:18 PM PDT 24
Finished Jul 14 06:52:21 PM PDT 24
Peak memory 205900 kb
Host smart-77206c49-ced7-4be5-b1ef-11fe3855e430
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627963570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.627963570
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.3318773121
Short name T229
Test name
Test status
Simulation time 381966897 ps
CPU time 18.04 seconds
Started Jul 14 06:52:17 PM PDT 24
Finished Jul 14 06:52:37 PM PDT 24
Peak memory 210692 kb
Host smart-cb0ac319-9b2d-4c2d-8ad3-d43d4c16f44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318773121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.3318773121
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.3534878845
Short name T731
Test name
Test status
Simulation time 204127578 ps
CPU time 4.22 seconds
Started Jul 14 06:52:14 PM PDT 24
Finished Jul 14 06:52:19 PM PDT 24
Peak memory 210536 kb
Host smart-4d2b6cab-f256-40b6-9b97-d2ddb2906a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534878845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.3534878845
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.3699924452
Short name T309
Test name
Test status
Simulation time 92644313 ps
CPU time 1.65 seconds
Started Jul 14 06:52:14 PM PDT 24
Finished Jul 14 06:52:17 PM PDT 24
Peak memory 214296 kb
Host smart-3892a77a-1c6f-4844-a96c-9dd79de63207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699924452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.3699924452
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.463405388
Short name T602
Test name
Test status
Simulation time 2592607982 ps
CPU time 10.29 seconds
Started Jul 14 06:52:13 PM PDT 24
Finished Jul 14 06:52:24 PM PDT 24
Peak memory 211540 kb
Host smart-5e0eb581-7b6e-4638-83c3-548b12ebe631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463405388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.463405388
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.1871144265
Short name T221
Test name
Test status
Simulation time 277757654 ps
CPU time 4.01 seconds
Started Jul 14 06:52:15 PM PDT 24
Finished Jul 14 06:52:20 PM PDT 24
Peak memory 222404 kb
Host smart-1c96d54b-3141-4431-89ac-b06e0eb5d0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871144265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.1871144265
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.2163915807
Short name T633
Test name
Test status
Simulation time 716762040 ps
CPU time 5.76 seconds
Started Jul 14 06:52:15 PM PDT 24
Finished Jul 14 06:52:22 PM PDT 24
Peak memory 219708 kb
Host smart-da1b8c6f-a434-4366-abe4-2e4d698c2c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163915807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.2163915807
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.1463520511
Short name T14
Test name
Test status
Simulation time 327455174 ps
CPU time 10.7 seconds
Started Jul 14 06:52:15 PM PDT 24
Finished Jul 14 06:52:27 PM PDT 24
Peak memory 230564 kb
Host smart-f31ef307-8b0f-4776-9b16-48d038467d48
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463520511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1463520511
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.2918766923
Short name T651
Test name
Test status
Simulation time 313024692 ps
CPU time 4.36 seconds
Started Jul 14 06:52:20 PM PDT 24
Finished Jul 14 06:52:26 PM PDT 24
Peak memory 206920 kb
Host smart-44731b1b-d0a0-4813-bfaf-a0824531dc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918766923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.2918766923
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.2092623293
Short name T405
Test name
Test status
Simulation time 220800355 ps
CPU time 5.6 seconds
Started Jul 14 06:52:13 PM PDT 24
Finished Jul 14 06:52:20 PM PDT 24
Peak memory 208736 kb
Host smart-5159400d-fae0-4b67-a577-d0a42c9a788c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092623293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.2092623293
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.1017964874
Short name T809
Test name
Test status
Simulation time 295817677 ps
CPU time 2.96 seconds
Started Jul 14 06:52:13 PM PDT 24
Finished Jul 14 06:52:18 PM PDT 24
Peak memory 206976 kb
Host smart-ae8db8dc-926f-4a47-ad4c-f8c39587d430
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017964874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.1017964874
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.4233823584
Short name T829
Test name
Test status
Simulation time 2440669820 ps
CPU time 16.12 seconds
Started Jul 14 06:52:13 PM PDT 24
Finished Jul 14 06:52:31 PM PDT 24
Peak memory 208120 kb
Host smart-d31115d5-dee8-40b8-990d-a9bae599e875
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233823584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.4233823584
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.1453703593
Short name T730
Test name
Test status
Simulation time 107858510 ps
CPU time 3.22 seconds
Started Jul 14 06:52:13 PM PDT 24
Finished Jul 14 06:52:18 PM PDT 24
Peak memory 214320 kb
Host smart-1c494f34-6c8e-4c5b-92a9-60d6fd2ad7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453703593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.1453703593
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.3803822074
Short name T717
Test name
Test status
Simulation time 2045770292 ps
CPU time 6.63 seconds
Started Jul 14 06:52:09 PM PDT 24
Finished Jul 14 06:52:16 PM PDT 24
Peak memory 208728 kb
Host smart-451eca9a-1f64-4490-b6c4-f187196f3ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803822074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.3803822074
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.2554148452
Short name T758
Test name
Test status
Simulation time 22640653862 ps
CPU time 241.43 seconds
Started Jul 14 06:52:16 PM PDT 24
Finished Jul 14 06:56:19 PM PDT 24
Peak memory 214396 kb
Host smart-4bca39bd-4766-44f2-abbb-0a07200fc65b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554148452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.2554148452
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.3980834683
Short name T76
Test name
Test status
Simulation time 5562352104 ps
CPU time 26.77 seconds
Started Jul 14 06:52:15 PM PDT 24
Finished Jul 14 06:52:43 PM PDT 24
Peak memory 218388 kb
Host smart-1688240d-d363-40f5-8d75-a737f74c83e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980834683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.3980834683
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.1046299164
Short name T827
Test name
Test status
Simulation time 16727364 ps
CPU time 0.94 seconds
Started Jul 14 06:52:20 PM PDT 24
Finished Jul 14 06:52:22 PM PDT 24
Peak memory 206096 kb
Host smart-1e140af3-ff70-48d2-97c3-3b9a637fba75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046299164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.1046299164
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.1918616033
Short name T381
Test name
Test status
Simulation time 140984287 ps
CPU time 2.9 seconds
Started Jul 14 06:52:14 PM PDT 24
Finished Jul 14 06:52:18 PM PDT 24
Peak memory 215120 kb
Host smart-83af7d2f-0924-4745-8398-1081566d9d2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1918616033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.1918616033
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.4000572296
Short name T11
Test name
Test status
Simulation time 58684237 ps
CPU time 3.3 seconds
Started Jul 14 06:52:22 PM PDT 24
Finished Jul 14 06:52:27 PM PDT 24
Peak memory 221720 kb
Host smart-9f98435e-e12f-4864-92cb-10fac9d3d07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000572296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.4000572296
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.50868734
Short name T50
Test name
Test status
Simulation time 34153601 ps
CPU time 1.99 seconds
Started Jul 14 06:52:14 PM PDT 24
Finished Jul 14 06:52:17 PM PDT 24
Peak memory 209096 kb
Host smart-b8632ecc-8ada-44e1-a593-aa7cc2347261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50868734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.50868734
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.1862446255
Short name T77
Test name
Test status
Simulation time 95067765 ps
CPU time 1.76 seconds
Started Jul 14 06:52:22 PM PDT 24
Finished Jul 14 06:52:25 PM PDT 24
Peak memory 214328 kb
Host smart-ee7a665f-ba43-45ae-9441-c32d2c91f828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862446255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1862446255
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.3501226714
Short name T526
Test name
Test status
Simulation time 97005492 ps
CPU time 2.96 seconds
Started Jul 14 06:52:21 PM PDT 24
Finished Jul 14 06:52:26 PM PDT 24
Peak memory 222512 kb
Host smart-366f3222-6961-4436-a39a-785dbda145b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501226714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.3501226714
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.1267136141
Short name T483
Test name
Test status
Simulation time 425291394 ps
CPU time 5.41 seconds
Started Jul 14 06:52:16 PM PDT 24
Finished Jul 14 06:52:23 PM PDT 24
Peak memory 209000 kb
Host smart-6cc52293-9269-486b-af2f-1e10230abd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267136141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1267136141
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.4201921473
Short name T101
Test name
Test status
Simulation time 244481768 ps
CPU time 7.77 seconds
Started Jul 14 06:52:21 PM PDT 24
Finished Jul 14 06:52:30 PM PDT 24
Peak memory 233748 kb
Host smart-4ab1eb5e-3ce9-484f-9f49-5890b98ef4da
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201921473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.4201921473
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.2924568125
Short name T902
Test name
Test status
Simulation time 301204605 ps
CPU time 4.59 seconds
Started Jul 14 06:52:18 PM PDT 24
Finished Jul 14 06:52:24 PM PDT 24
Peak memory 208340 kb
Host smart-f7527360-4294-4b02-92d1-9abd6be5b777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924568125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.2924568125
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.2530950770
Short name T735
Test name
Test status
Simulation time 131591070 ps
CPU time 4.65 seconds
Started Jul 14 06:52:17 PM PDT 24
Finished Jul 14 06:52:23 PM PDT 24
Peak memory 208712 kb
Host smart-4be966bc-3003-46c3-ab98-cda7fc352c30
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530950770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.2530950770
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.2884553498
Short name T418
Test name
Test status
Simulation time 3492351816 ps
CPU time 52.35 seconds
Started Jul 14 06:52:16 PM PDT 24
Finished Jul 14 06:53:10 PM PDT 24
Peak memory 208688 kb
Host smart-59c6f4d3-4649-49d2-9b86-8e20f215db31
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884553498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.2884553498
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.1208612965
Short name T797
Test name
Test status
Simulation time 750879182 ps
CPU time 18.39 seconds
Started Jul 14 06:52:16 PM PDT 24
Finished Jul 14 06:52:36 PM PDT 24
Peak memory 208860 kb
Host smart-490e5b53-a07c-42bf-a0b2-a254e5e8f180
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208612965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.1208612965
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.2478177474
Short name T606
Test name
Test status
Simulation time 42784416 ps
CPU time 2.69 seconds
Started Jul 14 06:52:22 PM PDT 24
Finished Jul 14 06:52:26 PM PDT 24
Peak memory 215804 kb
Host smart-81d31f01-a181-41f2-a07d-16149e65e09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478177474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.2478177474
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2434935405
Short name T416
Test name
Test status
Simulation time 253444545 ps
CPU time 2.85 seconds
Started Jul 14 06:52:15 PM PDT 24
Finished Jul 14 06:52:19 PM PDT 24
Peak memory 208448 kb
Host smart-85a02a64-cb61-48bb-a914-a8df5b18d6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434935405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2434935405
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.1914842637
Short name T69
Test name
Test status
Simulation time 1002012159 ps
CPU time 26.55 seconds
Started Jul 14 06:52:24 PM PDT 24
Finished Jul 14 06:52:52 PM PDT 24
Peak memory 222604 kb
Host smart-dc61d597-abe1-4a45-9a89-15f9bc206b17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914842637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.1914842637
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.3797185971
Short name T112
Test name
Test status
Simulation time 4149541259 ps
CPU time 22.29 seconds
Started Jul 14 06:52:21 PM PDT 24
Finished Jul 14 06:52:45 PM PDT 24
Peak memory 221556 kb
Host smart-7cb6ae2c-55d7-4c5f-80ce-59911ae299ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797185971 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.3797185971
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.614273193
Short name T826
Test name
Test status
Simulation time 129124368 ps
CPU time 6.08 seconds
Started Jul 14 06:52:22 PM PDT 24
Finished Jul 14 06:52:31 PM PDT 24
Peak memory 210512 kb
Host smart-5b3318a0-2913-491b-948b-fa04a0db9612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614273193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.614273193
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.2580810839
Short name T643
Test name
Test status
Simulation time 284422180 ps
CPU time 3.46 seconds
Started Jul 14 06:52:20 PM PDT 24
Finished Jul 14 06:52:25 PM PDT 24
Peak memory 210412 kb
Host smart-dc5c200c-c71f-4fba-b844-ac3c3cde6512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580810839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2580810839
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.3918237360
Short name T645
Test name
Test status
Simulation time 15546223 ps
CPU time 0.99 seconds
Started Jul 14 06:52:51 PM PDT 24
Finished Jul 14 06:52:53 PM PDT 24
Peak memory 206096 kb
Host smart-9a61970f-d3fb-4d99-8f46-a91032bf7e5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918237360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.3918237360
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.179220874
Short name T388
Test name
Test status
Simulation time 1801380528 ps
CPU time 11.05 seconds
Started Jul 14 06:52:51 PM PDT 24
Finished Jul 14 06:53:03 PM PDT 24
Peak memory 214308 kb
Host smart-3f0b55e8-af9e-4231-8997-e2aa824afb92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=179220874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.179220874
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.697046149
Short name T407
Test name
Test status
Simulation time 580429180 ps
CPU time 5.71 seconds
Started Jul 14 06:52:42 PM PDT 24
Finished Jul 14 06:52:49 PM PDT 24
Peak memory 214432 kb
Host smart-b4a98f66-3ed5-4449-aa8d-1162c32d3108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697046149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.697046149
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.3577979219
Short name T47
Test name
Test status
Simulation time 32095282 ps
CPU time 1.88 seconds
Started Jul 14 06:52:49 PM PDT 24
Finished Jul 14 06:52:52 PM PDT 24
Peak memory 214336 kb
Host smart-8a76600d-eff9-4569-a667-b67d2db345b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577979219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.3577979219
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.3657194672
Short name T267
Test name
Test status
Simulation time 78626620 ps
CPU time 3.71 seconds
Started Jul 14 06:52:42 PM PDT 24
Finished Jul 14 06:52:47 PM PDT 24
Peak memory 214364 kb
Host smart-f72f8bde-39a0-4de7-a8bd-6ea1d7ef3af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657194672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.3657194672
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.1255130482
Short name T431
Test name
Test status
Simulation time 474373674 ps
CPU time 6.37 seconds
Started Jul 14 06:52:41 PM PDT 24
Finished Jul 14 06:52:49 PM PDT 24
Peak memory 222468 kb
Host smart-174de58b-5893-4b7e-bc80-79eebcb06856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255130482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.1255130482
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.3627992064
Short name T524
Test name
Test status
Simulation time 270141526 ps
CPU time 3.87 seconds
Started Jul 14 06:52:42 PM PDT 24
Finished Jul 14 06:52:47 PM PDT 24
Peak memory 207660 kb
Host smart-64a351d7-0ac8-4cf5-a1dc-3d480226b660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627992064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3627992064
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.3827949190
Short name T214
Test name
Test status
Simulation time 166190520 ps
CPU time 3.83 seconds
Started Jul 14 06:52:42 PM PDT 24
Finished Jul 14 06:52:47 PM PDT 24
Peak memory 208720 kb
Host smart-f03853b2-d49a-4922-87ae-6362854ef7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827949190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.3827949190
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.1072355008
Short name T555
Test name
Test status
Simulation time 113943998 ps
CPU time 2.36 seconds
Started Jul 14 06:52:42 PM PDT 24
Finished Jul 14 06:52:46 PM PDT 24
Peak memory 206884 kb
Host smart-b9bc5305-0727-4cb5-8bc3-6598d14ff8ab
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072355008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.1072355008
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.2754708649
Short name T279
Test name
Test status
Simulation time 133955306 ps
CPU time 2.49 seconds
Started Jul 14 06:52:44 PM PDT 24
Finished Jul 14 06:52:48 PM PDT 24
Peak memory 206924 kb
Host smart-573bd165-53a0-43f7-bfab-a49fbaa8ff6b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754708649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.2754708649
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.1454501837
Short name T324
Test name
Test status
Simulation time 98713068 ps
CPU time 2.65 seconds
Started Jul 14 06:52:45 PM PDT 24
Finished Jul 14 06:52:49 PM PDT 24
Peak memory 208440 kb
Host smart-d4c9d487-ca46-40f1-a236-494dff1a0013
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454501837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.1454501837
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.3900733648
Short name T701
Test name
Test status
Simulation time 21524521 ps
CPU time 1.57 seconds
Started Jul 14 06:52:45 PM PDT 24
Finished Jul 14 06:52:48 PM PDT 24
Peak memory 207584 kb
Host smart-8226130f-f77d-4609-84c9-c9ce1729bfd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900733648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.3900733648
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.400451971
Short name T373
Test name
Test status
Simulation time 4088038518 ps
CPU time 18.33 seconds
Started Jul 14 06:52:42 PM PDT 24
Finished Jul 14 06:53:01 PM PDT 24
Peak memory 208092 kb
Host smart-29ff9d9b-4907-4b66-bd49-e69c3b596735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400451971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.400451971
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3926304618
Short name T357
Test name
Test status
Simulation time 4202197486 ps
CPU time 30.15 seconds
Started Jul 14 06:52:44 PM PDT 24
Finished Jul 14 06:53:15 PM PDT 24
Peak memory 209832 kb
Host smart-76c4f27b-144d-408c-85a5-7dad030fee4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926304618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3926304618
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.3010891048
Short name T205
Test name
Test status
Simulation time 1376881393 ps
CPU time 3.9 seconds
Started Jul 14 06:52:44 PM PDT 24
Finished Jul 14 06:52:49 PM PDT 24
Peak memory 210556 kb
Host smart-5c89d7e4-ea04-43d6-8078-faf884d89a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010891048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.3010891048
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.1671638604
Short name T857
Test name
Test status
Simulation time 9977614 ps
CPU time 0.88 seconds
Started Jul 14 06:52:49 PM PDT 24
Finished Jul 14 06:52:51 PM PDT 24
Peak memory 205948 kb
Host smart-47dfa93e-2d50-4af1-b1d1-25bf509f51ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671638604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.1671638604
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.1876779004
Short name T383
Test name
Test status
Simulation time 583221899 ps
CPU time 9.48 seconds
Started Jul 14 06:52:42 PM PDT 24
Finished Jul 14 06:52:53 PM PDT 24
Peak memory 215604 kb
Host smart-acc41725-72e0-457e-9fbe-3e1f47bce090
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1876779004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1876779004
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.3962311076
Short name T442
Test name
Test status
Simulation time 18431471 ps
CPU time 1.53 seconds
Started Jul 14 06:52:44 PM PDT 24
Finished Jul 14 06:52:47 PM PDT 24
Peak memory 208472 kb
Host smart-e5c7b27d-da5f-430c-94b9-dd24d351894d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962311076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3962311076
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.214999088
Short name T86
Test name
Test status
Simulation time 74202491 ps
CPU time 3.13 seconds
Started Jul 14 06:52:49 PM PDT 24
Finished Jul 14 06:52:53 PM PDT 24
Peak memory 214332 kb
Host smart-cafdeee4-d047-4c79-ba03-59bb010c047a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214999088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.214999088
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.2577618579
Short name T271
Test name
Test status
Simulation time 265965478 ps
CPU time 5.23 seconds
Started Jul 14 06:52:53 PM PDT 24
Finished Jul 14 06:52:59 PM PDT 24
Peak memory 222332 kb
Host smart-0012164e-4953-4b5d-a256-88343f86a8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577618579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.2577618579
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.1524437452
Short name T106
Test name
Test status
Simulation time 196786906 ps
CPU time 9.48 seconds
Started Jul 14 06:52:43 PM PDT 24
Finished Jul 14 06:52:54 PM PDT 24
Peak memory 215808 kb
Host smart-7fbdaf7a-fc1a-4da1-aafc-b044aacc2010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524437452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.1524437452
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.1592584406
Short name T647
Test name
Test status
Simulation time 2353044457 ps
CPU time 27.79 seconds
Started Jul 14 06:52:44 PM PDT 24
Finished Jul 14 06:53:13 PM PDT 24
Peak memory 209044 kb
Host smart-d966ecbb-15b6-4cea-a9f4-ccee46821ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592584406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.1592584406
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.2153672571
Short name T218
Test name
Test status
Simulation time 522978972 ps
CPU time 3.7 seconds
Started Jul 14 06:52:43 PM PDT 24
Finished Jul 14 06:52:48 PM PDT 24
Peak memory 208552 kb
Host smart-299bc710-e44a-4ec6-b8f8-102a35024a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153672571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.2153672571
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.3294410533
Short name T804
Test name
Test status
Simulation time 192298698 ps
CPU time 5.48 seconds
Started Jul 14 06:52:50 PM PDT 24
Finished Jul 14 06:52:56 PM PDT 24
Peak memory 207876 kb
Host smart-e9339bbb-dda4-4541-b637-74f3a31d26e7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294410533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3294410533
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.994814112
Short name T19
Test name
Test status
Simulation time 478687678 ps
CPU time 5.29 seconds
Started Jul 14 06:52:45 PM PDT 24
Finished Jul 14 06:52:52 PM PDT 24
Peak memory 209064 kb
Host smart-f0b20371-4e4a-4e25-9b4e-47e81a1dbddb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994814112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.994814112
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.2053244317
Short name T453
Test name
Test status
Simulation time 131983150 ps
CPU time 3.51 seconds
Started Jul 14 06:52:40 PM PDT 24
Finished Jul 14 06:52:45 PM PDT 24
Peak memory 208924 kb
Host smart-fc272a7d-f8a7-4b70-84f9-c278dedcfe94
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053244317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.2053244317
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.355732371
Short name T724
Test name
Test status
Simulation time 124235327 ps
CPU time 2.83 seconds
Started Jul 14 06:52:53 PM PDT 24
Finished Jul 14 06:52:56 PM PDT 24
Peak memory 209196 kb
Host smart-aecee979-dacb-4939-94ce-1c8ef92aed9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355732371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.355732371
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.3641189912
Short name T824
Test name
Test status
Simulation time 1383767048 ps
CPU time 16.88 seconds
Started Jul 14 06:52:50 PM PDT 24
Finished Jul 14 06:53:08 PM PDT 24
Peak memory 208380 kb
Host smart-e8e5b726-dfc2-4957-866e-1d22bd02b785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641189912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3641189912
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.2110680226
Short name T286
Test name
Test status
Simulation time 26535954059 ps
CPU time 379.29 seconds
Started Jul 14 06:52:50 PM PDT 24
Finished Jul 14 06:59:10 PM PDT 24
Peak memory 222524 kb
Host smart-9ac4670e-8513-4004-8f3e-d2520be9330b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110680226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.2110680226
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.3558354407
Short name T68
Test name
Test status
Simulation time 218767390 ps
CPU time 9.39 seconds
Started Jul 14 06:52:51 PM PDT 24
Finished Jul 14 06:53:02 PM PDT 24
Peak memory 222580 kb
Host smart-33567dea-d64d-4c1c-b8aa-911329386e30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558354407 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.3558354407
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.3946361720
Short name T288
Test name
Test status
Simulation time 8613453513 ps
CPU time 62.89 seconds
Started Jul 14 06:52:49 PM PDT 24
Finished Jul 14 06:53:53 PM PDT 24
Peak memory 214564 kb
Host smart-b9f18e6f-a4f9-4c5c-b43c-ea43865a3ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946361720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.3946361720
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.1493384151
Short name T641
Test name
Test status
Simulation time 55959173 ps
CPU time 2.37 seconds
Started Jul 14 06:52:49 PM PDT 24
Finished Jul 14 06:52:53 PM PDT 24
Peak memory 214472 kb
Host smart-7944f2a1-38c8-404b-bc13-c73a79819d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493384151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.1493384151
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.4073232512
Short name T723
Test name
Test status
Simulation time 27802932 ps
CPU time 0.77 seconds
Started Jul 14 06:52:54 PM PDT 24
Finished Jul 14 06:52:57 PM PDT 24
Peak memory 205980 kb
Host smart-ed93de4b-04a1-4e6f-8bcc-5e43afb5f4e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073232512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.4073232512
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.667403052
Short name T836
Test name
Test status
Simulation time 164442418 ps
CPU time 4.5 seconds
Started Jul 14 06:52:49 PM PDT 24
Finished Jul 14 06:52:55 PM PDT 24
Peak memory 210140 kb
Host smart-68bf8c31-c4bc-46a4-936e-929f506329e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667403052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.667403052
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.362620932
Short name T864
Test name
Test status
Simulation time 1302251755 ps
CPU time 15.43 seconds
Started Jul 14 06:52:48 PM PDT 24
Finished Jul 14 06:53:04 PM PDT 24
Peak memory 208428 kb
Host smart-deb2feff-cfec-4f5c-9ffd-304e7ff768d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362620932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.362620932
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.2248656982
Short name T226
Test name
Test status
Simulation time 769709316 ps
CPU time 2.63 seconds
Started Jul 14 06:52:51 PM PDT 24
Finished Jul 14 06:52:55 PM PDT 24
Peak memory 215644 kb
Host smart-46da4171-ac5e-43c2-9a29-c64e3959bb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248656982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.2248656982
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.1662522619
Short name T847
Test name
Test status
Simulation time 349489844 ps
CPU time 3.5 seconds
Started Jul 14 06:52:48 PM PDT 24
Finished Jul 14 06:52:52 PM PDT 24
Peak memory 207216 kb
Host smart-28f6e6ef-6f0f-4206-86ad-fe45006ab436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662522619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.1662522619
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.3915642729
Short name T485
Test name
Test status
Simulation time 55694384 ps
CPU time 2.84 seconds
Started Jul 14 06:52:49 PM PDT 24
Finished Jul 14 06:52:53 PM PDT 24
Peak memory 208580 kb
Host smart-5c2b2df9-e8cb-4879-88a9-da3b15ffc965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915642729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3915642729
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.978296466
Short name T140
Test name
Test status
Simulation time 57203167 ps
CPU time 2.89 seconds
Started Jul 14 06:52:49 PM PDT 24
Finished Jul 14 06:52:53 PM PDT 24
Peak memory 208680 kb
Host smart-fdfda6d7-a3d5-4241-87d4-38d6c983a5b0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978296466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.978296466
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.1179910867
Short name T583
Test name
Test status
Simulation time 40890160 ps
CPU time 2.46 seconds
Started Jul 14 06:52:50 PM PDT 24
Finished Jul 14 06:52:53 PM PDT 24
Peak memory 207280 kb
Host smart-749ffdbf-6bf6-49e0-979f-fce49201e168
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179910867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.1179910867
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.1381697053
Short name T662
Test name
Test status
Simulation time 332384249 ps
CPU time 3.44 seconds
Started Jul 14 06:52:50 PM PDT 24
Finished Jul 14 06:52:55 PM PDT 24
Peak memory 208532 kb
Host smart-cc232652-fe8b-4ea8-ac49-a748f3339cc0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381697053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.1381697053
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.1140364586
Short name T799
Test name
Test status
Simulation time 189608210 ps
CPU time 2.67 seconds
Started Jul 14 06:52:50 PM PDT 24
Finished Jul 14 06:52:54 PM PDT 24
Peak memory 208504 kb
Host smart-e9dc77c5-1935-4636-be88-d9c2b316f30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140364586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.1140364586
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.1807167470
Short name T640
Test name
Test status
Simulation time 167521457 ps
CPU time 4.18 seconds
Started Jul 14 06:52:51 PM PDT 24
Finished Jul 14 06:52:56 PM PDT 24
Peak memory 208932 kb
Host smart-71e16873-d6fc-4334-adbe-73e526f770ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807167470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.1807167470
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.3317239363
Short name T185
Test name
Test status
Simulation time 472423925 ps
CPU time 14.67 seconds
Started Jul 14 06:52:53 PM PDT 24
Finished Jul 14 06:53:08 PM PDT 24
Peak memory 222676 kb
Host smart-a1fecf89-16c9-48c7-b089-3fc1e6b4bb95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317239363 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.3317239363
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.3536023020
Short name T360
Test name
Test status
Simulation time 120719892 ps
CPU time 5.17 seconds
Started Jul 14 06:52:50 PM PDT 24
Finished Jul 14 06:52:56 PM PDT 24
Peak memory 209064 kb
Host smart-f506b90d-5a13-45f5-8815-4645d604f073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536023020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.3536023020
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.3391586432
Short name T206
Test name
Test status
Simulation time 92228822 ps
CPU time 3.56 seconds
Started Jul 14 06:52:49 PM PDT 24
Finished Jul 14 06:52:53 PM PDT 24
Peak memory 209980 kb
Host smart-91be9d61-c3f4-48c0-808f-8d83eb127641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391586432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.3391586432
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.3887943882
Short name T605
Test name
Test status
Simulation time 14380304 ps
CPU time 0.96 seconds
Started Jul 14 06:52:55 PM PDT 24
Finished Jul 14 06:52:57 PM PDT 24
Peak memory 206112 kb
Host smart-1cc62533-36cf-4b68-a7fc-493f41249022
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887943882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.3887943882
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.1728701602
Short name T370
Test name
Test status
Simulation time 2358629528 ps
CPU time 8.31 seconds
Started Jul 14 06:52:55 PM PDT 24
Finished Jul 14 06:53:05 PM PDT 24
Peak memory 215344 kb
Host smart-bde2c51c-3122-4a83-af9c-3af585d1c516
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1728701602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.1728701602
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.2252493740
Short name T342
Test name
Test status
Simulation time 927100497 ps
CPU time 6.26 seconds
Started Jul 14 06:52:56 PM PDT 24
Finished Jul 14 06:53:03 PM PDT 24
Peak memory 209700 kb
Host smart-8667e420-66d6-4f41-a25c-d67f377d701d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252493740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.2252493740
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.2327843073
Short name T107
Test name
Test status
Simulation time 79826275 ps
CPU time 3.74 seconds
Started Jul 14 06:53:00 PM PDT 24
Finished Jul 14 06:53:06 PM PDT 24
Peak memory 222508 kb
Host smart-f8f25b7f-afe4-42ad-94eb-f77d507a9e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327843073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.2327843073
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.4028171431
Short name T694
Test name
Test status
Simulation time 251037350 ps
CPU time 5.59 seconds
Started Jul 14 06:52:55 PM PDT 24
Finished Jul 14 06:53:03 PM PDT 24
Peak memory 209644 kb
Host smart-134476c4-c027-4e7b-a807-4a5b41b66e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028171431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.4028171431
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.2097799056
Short name T600
Test name
Test status
Simulation time 165859969 ps
CPU time 3.2 seconds
Started Jul 14 06:52:54 PM PDT 24
Finished Jul 14 06:52:58 PM PDT 24
Peak memory 214264 kb
Host smart-061f5bb9-1128-4aa8-a7e9-3be63f455e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097799056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.2097799056
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.2369016871
Short name T566
Test name
Test status
Simulation time 24850250 ps
CPU time 2.11 seconds
Started Jul 14 06:52:54 PM PDT 24
Finished Jul 14 06:52:58 PM PDT 24
Peak memory 208868 kb
Host smart-011afa5c-fdcd-43ba-9915-64817ec9110c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369016871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.2369016871
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.4164809634
Short name T780
Test name
Test status
Simulation time 88804972 ps
CPU time 3.76 seconds
Started Jul 14 06:52:54 PM PDT 24
Finished Jul 14 06:52:59 PM PDT 24
Peak memory 209060 kb
Host smart-79747660-e9f5-4dd0-afe3-20452ffebb9b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164809634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.4164809634
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.3203238241
Short name T508
Test name
Test status
Simulation time 52751862 ps
CPU time 2.74 seconds
Started Jul 14 06:52:55 PM PDT 24
Finished Jul 14 06:52:59 PM PDT 24
Peak memory 208068 kb
Host smart-3b55cb99-737e-41d0-8b8b-0457bb46d942
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203238241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.3203238241
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.3039843635
Short name T435
Test name
Test status
Simulation time 735407222 ps
CPU time 3.79 seconds
Started Jul 14 06:52:55 PM PDT 24
Finished Jul 14 06:53:00 PM PDT 24
Peak memory 208516 kb
Host smart-d5c35a64-1626-4272-a280-65561e74f6da
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039843635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.3039843635
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.2783437928
Short name T722
Test name
Test status
Simulation time 358485514 ps
CPU time 4.64 seconds
Started Jul 14 06:52:55 PM PDT 24
Finished Jul 14 06:53:01 PM PDT 24
Peak memory 214404 kb
Host smart-e8851d61-ab7d-49d2-ba61-2f852b9a25fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783437928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2783437928
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.2326384503
Short name T755
Test name
Test status
Simulation time 347720636 ps
CPU time 3.3 seconds
Started Jul 14 06:52:58 PM PDT 24
Finished Jul 14 06:53:03 PM PDT 24
Peak memory 208168 kb
Host smart-15c1a2d7-1293-4b9f-84a1-4fd0a7e77eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326384503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.2326384503
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.1980768864
Short name T256
Test name
Test status
Simulation time 1386731409 ps
CPU time 33.02 seconds
Started Jul 14 06:52:59 PM PDT 24
Finished Jul 14 06:53:34 PM PDT 24
Peak memory 222552 kb
Host smart-1e13f6de-d817-4695-a197-1e19b6b9adb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980768864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.1980768864
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.3526946988
Short name T625
Test name
Test status
Simulation time 259740665 ps
CPU time 3.37 seconds
Started Jul 14 06:52:57 PM PDT 24
Finished Jul 14 06:53:01 PM PDT 24
Peak memory 214436 kb
Host smart-aa8cf5a8-18f5-4c42-99b7-64226a5d5056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526946988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.3526946988
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.2453678134
Short name T865
Test name
Test status
Simulation time 362985702 ps
CPU time 4.5 seconds
Started Jul 14 06:53:01 PM PDT 24
Finished Jul 14 06:53:08 PM PDT 24
Peak memory 210556 kb
Host smart-b1249581-4665-4448-b81f-5bde87d4126d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453678134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2453678134
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.425966976
Short name T792
Test name
Test status
Simulation time 12196546 ps
CPU time 0.79 seconds
Started Jul 14 06:52:58 PM PDT 24
Finished Jul 14 06:53:00 PM PDT 24
Peak memory 206000 kb
Host smart-58e4be20-fbf3-4727-a5c0-9f982f334623
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425966976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.425966976
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.3622301216
Short name T875
Test name
Test status
Simulation time 645862830 ps
CPU time 14.74 seconds
Started Jul 14 06:52:54 PM PDT 24
Finished Jul 14 06:53:10 PM PDT 24
Peak memory 214684 kb
Host smart-0b40aa5b-2bd0-43b0-b7c6-1628bcf3b69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622301216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3622301216
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.3696859474
Short name T460
Test name
Test status
Simulation time 114870869 ps
CPU time 2.37 seconds
Started Jul 14 06:53:01 PM PDT 24
Finished Jul 14 06:53:05 PM PDT 24
Peak memory 218292 kb
Host smart-f65c6ad9-55bb-4c95-8816-e02331f4c51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696859474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.3696859474
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.3248113422
Short name T328
Test name
Test status
Simulation time 73703101 ps
CPU time 3.49 seconds
Started Jul 14 06:52:56 PM PDT 24
Finished Jul 14 06:53:01 PM PDT 24
Peak memory 214332 kb
Host smart-2631779d-5b4c-480f-b931-c182f54c1c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248113422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.3248113422
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.1904171778
Short name T846
Test name
Test status
Simulation time 109676212 ps
CPU time 4.8 seconds
Started Jul 14 06:52:59 PM PDT 24
Finished Jul 14 06:53:05 PM PDT 24
Peak memory 214280 kb
Host smart-2f04ee7a-824f-4b44-bd94-bf2a25f83c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904171778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.1904171778
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.2736991079
Short name T222
Test name
Test status
Simulation time 43763207 ps
CPU time 2.07 seconds
Started Jul 14 06:52:58 PM PDT 24
Finished Jul 14 06:53:02 PM PDT 24
Peak memory 214368 kb
Host smart-5f6e23ae-7da8-4924-9190-50262c499a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736991079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.2736991079
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.3400517213
Short name T377
Test name
Test status
Simulation time 149920594 ps
CPU time 4.13 seconds
Started Jul 14 06:52:54 PM PDT 24
Finished Jul 14 06:52:59 PM PDT 24
Peak memory 214328 kb
Host smart-30b3a75b-5934-4223-aa3f-f7277a58ab85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400517213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3400517213
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.838376876
Short name T507
Test name
Test status
Simulation time 277241487 ps
CPU time 2.81 seconds
Started Jul 14 06:52:56 PM PDT 24
Finished Jul 14 06:53:00 PM PDT 24
Peak memory 206884 kb
Host smart-54c20a30-385f-43b6-aae2-ce0350d901e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838376876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.838376876
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.4011170202
Short name T781
Test name
Test status
Simulation time 1152975323 ps
CPU time 3.38 seconds
Started Jul 14 06:52:59 PM PDT 24
Finished Jul 14 06:53:04 PM PDT 24
Peak memory 208944 kb
Host smart-a857e2cc-cdd6-4ec0-98bc-622893079023
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011170202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.4011170202
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.1065135496
Short name T791
Test name
Test status
Simulation time 6154402656 ps
CPU time 36.2 seconds
Started Jul 14 06:52:52 PM PDT 24
Finished Jul 14 06:53:29 PM PDT 24
Peak memory 208288 kb
Host smart-8e96b517-35f1-4f39-af27-639f736b9d8b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065135496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.1065135496
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.1933542943
Short name T765
Test name
Test status
Simulation time 273910650 ps
CPU time 3.83 seconds
Started Jul 14 06:52:55 PM PDT 24
Finished Jul 14 06:53:00 PM PDT 24
Peak memory 209112 kb
Host smart-96b8bfcf-33fd-4e9b-956b-8bd51c3881cf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933542943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.1933542943
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.1442154129
Short name T703
Test name
Test status
Simulation time 188030865 ps
CPU time 3.43 seconds
Started Jul 14 06:52:55 PM PDT 24
Finished Jul 14 06:53:00 PM PDT 24
Peak memory 214248 kb
Host smart-0caa4fde-872d-48b7-89b3-9b5d2bf0e4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442154129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.1442154129
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.3957549513
Short name T451
Test name
Test status
Simulation time 1530642946 ps
CPU time 36.35 seconds
Started Jul 14 06:52:55 PM PDT 24
Finished Jul 14 06:53:33 PM PDT 24
Peak memory 208528 kb
Host smart-3b98a827-8aa5-47cc-bf59-2f4a7fa79414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957549513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.3957549513
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.808955830
Short name T247
Test name
Test status
Simulation time 1464686997 ps
CPU time 12.48 seconds
Started Jul 14 06:52:58 PM PDT 24
Finished Jul 14 06:53:12 PM PDT 24
Peak memory 214332 kb
Host smart-f00714e4-2805-44e0-9865-13c8d16c87e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808955830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.808955830
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.114920302
Short name T546
Test name
Test status
Simulation time 137682730 ps
CPU time 5.01 seconds
Started Jul 14 06:53:02 PM PDT 24
Finished Jul 14 06:53:09 PM PDT 24
Peak memory 208428 kb
Host smart-9a07873c-1a29-49cb-a021-5003463e577e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114920302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.114920302
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.3540367878
Short name T363
Test name
Test status
Simulation time 108504963 ps
CPU time 1.61 seconds
Started Jul 14 06:52:55 PM PDT 24
Finished Jul 14 06:52:59 PM PDT 24
Peak memory 209988 kb
Host smart-3b83ab33-63b5-4075-8353-d00bae914e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540367878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.3540367878
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.1416786720
Short name T535
Test name
Test status
Simulation time 11943237 ps
CPU time 0.74 seconds
Started Jul 14 06:53:02 PM PDT 24
Finished Jul 14 06:53:05 PM PDT 24
Peak memory 205984 kb
Host smart-562aabf9-7628-4d5b-8359-8e0610097954
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416786720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.1416786720
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.4014553546
Short name T532
Test name
Test status
Simulation time 558215116 ps
CPU time 4.65 seconds
Started Jul 14 06:53:02 PM PDT 24
Finished Jul 14 06:53:08 PM PDT 24
Peak memory 220228 kb
Host smart-83d4b159-436b-4ca2-8ab6-a15800d053d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014553546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.4014553546
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.2848609500
Short name T66
Test name
Test status
Simulation time 124341087 ps
CPU time 3.45 seconds
Started Jul 14 06:53:00 PM PDT 24
Finished Jul 14 06:53:06 PM PDT 24
Peak memory 214312 kb
Host smart-a8e0907d-eb78-4cf2-9d51-dc64ebd62e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848609500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.2848609500
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.948099229
Short name T812
Test name
Test status
Simulation time 260061992 ps
CPU time 2.39 seconds
Started Jul 14 06:53:01 PM PDT 24
Finished Jul 14 06:53:06 PM PDT 24
Peak memory 222340 kb
Host smart-d7e1ccf7-689d-418b-a6d8-47e04cc0dd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948099229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.948099229
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.2310573199
Short name T658
Test name
Test status
Simulation time 44190384 ps
CPU time 2.82 seconds
Started Jul 14 06:52:58 PM PDT 24
Finished Jul 14 06:53:03 PM PDT 24
Peak memory 209528 kb
Host smart-6926f012-b4e5-4a74-9ea5-a6a10da28a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310573199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.2310573199
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.1600223319
Short name T322
Test name
Test status
Simulation time 125129351 ps
CPU time 5.28 seconds
Started Jul 14 06:52:59 PM PDT 24
Finished Jul 14 06:53:07 PM PDT 24
Peak memory 219516 kb
Host smart-0273dd21-9203-49a5-af6e-00cc850c7f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600223319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.1600223319
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.393352288
Short name T406
Test name
Test status
Simulation time 136727723 ps
CPU time 2.28 seconds
Started Jul 14 06:53:02 PM PDT 24
Finished Jul 14 06:53:06 PM PDT 24
Peak memory 206760 kb
Host smart-14058118-09c8-4c26-9338-b0fe148197e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393352288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.393352288
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.3235022724
Short name T538
Test name
Test status
Simulation time 320993731 ps
CPU time 4.35 seconds
Started Jul 14 06:53:00 PM PDT 24
Finished Jul 14 06:53:07 PM PDT 24
Peak memory 206948 kb
Host smart-208b28e3-afd0-4b96-95ea-2b586730e60e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235022724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.3235022724
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.754802327
Short name T251
Test name
Test status
Simulation time 485656907 ps
CPU time 5.46 seconds
Started Jul 14 06:52:57 PM PDT 24
Finished Jul 14 06:53:03 PM PDT 24
Peak memory 206972 kb
Host smart-d1e12471-cee6-4c2f-847c-79058d817463
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754802327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.754802327
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.2941705492
Short name T440
Test name
Test status
Simulation time 56055888 ps
CPU time 2.35 seconds
Started Jul 14 06:53:00 PM PDT 24
Finished Jul 14 06:53:04 PM PDT 24
Peak memory 206736 kb
Host smart-9cae39b0-cc61-428c-bc2a-bf9c6be3c46c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941705492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.2941705492
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.4223034674
Short name T142
Test name
Test status
Simulation time 87170398 ps
CPU time 2.88 seconds
Started Jul 14 06:53:02 PM PDT 24
Finished Jul 14 06:53:07 PM PDT 24
Peak memory 209856 kb
Host smart-8c88b667-c3ee-432c-9ffe-27ccad0cda00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223034674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.4223034674
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.2013751748
Short name T709
Test name
Test status
Simulation time 146827316 ps
CPU time 3.65 seconds
Started Jul 14 06:53:00 PM PDT 24
Finished Jul 14 06:53:07 PM PDT 24
Peak memory 208680 kb
Host smart-9814c9ee-8358-47c9-b9ea-df94a1fa4925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013751748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2013751748
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.1609883126
Short name T285
Test name
Test status
Simulation time 1193554811 ps
CPU time 19.15 seconds
Started Jul 14 06:52:59 PM PDT 24
Finished Jul 14 06:53:20 PM PDT 24
Peak memory 222496 kb
Host smart-25e63cfd-01cb-4bb6-9cab-8e267d5e2600
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609883126 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.1609883126
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.4025772319
Short name T716
Test name
Test status
Simulation time 1175764100 ps
CPU time 5.18 seconds
Started Jul 14 06:52:58 PM PDT 24
Finished Jul 14 06:53:04 PM PDT 24
Peak memory 218048 kb
Host smart-bb0e4192-5be1-490a-b471-49e14c066cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025772319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.4025772319
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.2017116032
Short name T760
Test name
Test status
Simulation time 450056088 ps
CPU time 2.84 seconds
Started Jul 14 06:52:59 PM PDT 24
Finished Jul 14 06:53:04 PM PDT 24
Peak memory 214732 kb
Host smart-abb384bb-c846-4509-a894-109a3c4777ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017116032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.2017116032
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.2839549345
Short name T36
Test name
Test status
Simulation time 270185318 ps
CPU time 1.88 seconds
Started Jul 14 06:52:59 PM PDT 24
Finished Jul 14 06:53:04 PM PDT 24
Peak memory 207120 kb
Host smart-20899d96-48f0-47a9-a191-6e3b6366bacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839549345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.2839549345
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.3448689199
Short name T803
Test name
Test status
Simulation time 11833299876 ps
CPU time 74 seconds
Started Jul 14 06:52:59 PM PDT 24
Finished Jul 14 06:54:15 PM PDT 24
Peak memory 214376 kb
Host smart-c8d19836-3640-4dbf-be43-328914e340fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448689199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.3448689199
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.885104445
Short name T619
Test name
Test status
Simulation time 119173143 ps
CPU time 5.03 seconds
Started Jul 14 06:52:59 PM PDT 24
Finished Jul 14 06:53:05 PM PDT 24
Peak memory 214276 kb
Host smart-c783deaa-b35d-4b6f-8fc4-2c48b77e45cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885104445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.885104445
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.703137932
Short name T596
Test name
Test status
Simulation time 116067979 ps
CPU time 5.51 seconds
Started Jul 14 06:52:58 PM PDT 24
Finished Jul 14 06:53:05 PM PDT 24
Peak memory 218108 kb
Host smart-448d6086-e34b-4f92-af7e-dfd41e64ea1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703137932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.703137932
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.2819019443
Short name T411
Test name
Test status
Simulation time 82387969 ps
CPU time 2.86 seconds
Started Jul 14 06:53:01 PM PDT 24
Finished Jul 14 06:53:06 PM PDT 24
Peak memory 208016 kb
Host smart-86837646-9d29-41b0-8771-293c4a246333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819019443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.2819019443
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.2434929145
Short name T190
Test name
Test status
Simulation time 43883330 ps
CPU time 2.31 seconds
Started Jul 14 06:52:58 PM PDT 24
Finished Jul 14 06:53:01 PM PDT 24
Peak memory 208304 kb
Host smart-e9bc43df-2b7c-44b3-86cc-7ca48e1244d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434929145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2434929145
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.288644661
Short name T772
Test name
Test status
Simulation time 149957295 ps
CPU time 2.78 seconds
Started Jul 14 06:53:00 PM PDT 24
Finished Jul 14 06:53:05 PM PDT 24
Peak memory 208432 kb
Host smart-d876b00c-5e73-406c-a80c-5be8a3ec6f0c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288644661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.288644661
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.3674178876
Short name T412
Test name
Test status
Simulation time 51503374 ps
CPU time 2.88 seconds
Started Jul 14 06:53:00 PM PDT 24
Finished Jul 14 06:53:05 PM PDT 24
Peak memory 207056 kb
Host smart-06c06364-5259-462d-beef-84dc40b692ea
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674178876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3674178876
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.2841210119
Short name T782
Test name
Test status
Simulation time 230632062 ps
CPU time 3.27 seconds
Started Jul 14 06:52:58 PM PDT 24
Finished Jul 14 06:53:02 PM PDT 24
Peak memory 208996 kb
Host smart-4a4867cd-23f7-4c07-a424-310afe98183c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841210119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.2841210119
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.914140233
Short name T660
Test name
Test status
Simulation time 153078490 ps
CPU time 3.05 seconds
Started Jul 14 06:53:00 PM PDT 24
Finished Jul 14 06:53:06 PM PDT 24
Peak memory 218396 kb
Host smart-67a73919-3114-4251-8f0b-6b20f0b57657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914140233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.914140233
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.1361902742
Short name T414
Test name
Test status
Simulation time 82625960 ps
CPU time 2.41 seconds
Started Jul 14 06:53:03 PM PDT 24
Finished Jul 14 06:53:07 PM PDT 24
Peak memory 206936 kb
Host smart-6bbe0811-20e8-4c05-982b-bc9e33786510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361902742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.1361902742
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.3025855983
Short name T771
Test name
Test status
Simulation time 1196726842 ps
CPU time 31.49 seconds
Started Jul 14 06:52:59 PM PDT 24
Finished Jul 14 06:53:33 PM PDT 24
Peak memory 215788 kb
Host smart-fe64b678-52a0-45a1-bd13-f541d5fac662
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025855983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3025855983
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.2672926082
Short name T240
Test name
Test status
Simulation time 173705580 ps
CPU time 10.54 seconds
Started Jul 14 06:53:05 PM PDT 24
Finished Jul 14 06:53:17 PM PDT 24
Peak memory 222636 kb
Host smart-955aecd6-5b24-44b5-a756-c90d71a07e88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672926082 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.2672926082
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.2222237029
Short name T519
Test name
Test status
Simulation time 722516928 ps
CPU time 5.3 seconds
Started Jul 14 06:52:59 PM PDT 24
Finished Jul 14 06:53:07 PM PDT 24
Peak memory 210060 kb
Host smart-fcb4ee3f-3078-4bfb-b801-1a88c8875340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222237029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.2222237029
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.3756802689
Short name T137
Test name
Test status
Simulation time 57178058 ps
CPU time 2.32 seconds
Started Jul 14 06:52:58 PM PDT 24
Finished Jul 14 06:53:01 PM PDT 24
Peak memory 210136 kb
Host smart-280d691e-1d6c-46de-8656-bc6b4f2fcc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756802689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.3756802689
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.3654899749
Short name T673
Test name
Test status
Simulation time 10471203 ps
CPU time 0.71 seconds
Started Jul 14 06:53:09 PM PDT 24
Finished Jul 14 06:53:11 PM PDT 24
Peak memory 205996 kb
Host smart-db1b0d0e-b5ee-4c02-9fac-12c2aa70fbce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654899749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.3654899749
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.2558289578
Short name T31
Test name
Test status
Simulation time 92307657 ps
CPU time 3.8 seconds
Started Jul 14 06:53:08 PM PDT 24
Finished Jul 14 06:53:13 PM PDT 24
Peak memory 209608 kb
Host smart-67bda636-337f-494a-9ca3-e825325449a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558289578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.2558289578
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.3009665973
Short name T341
Test name
Test status
Simulation time 271796150 ps
CPU time 7.48 seconds
Started Jul 14 06:53:06 PM PDT 24
Finished Jul 14 06:53:15 PM PDT 24
Peak memory 214328 kb
Host smart-3c52d914-7086-4e2e-9f33-8993117373a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009665973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3009665973
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.1189358486
Short name T545
Test name
Test status
Simulation time 157500272 ps
CPU time 2.16 seconds
Started Jul 14 06:53:05 PM PDT 24
Finished Jul 14 06:53:08 PM PDT 24
Peak memory 214420 kb
Host smart-463306c5-2e63-4631-8180-ebefaf54c399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189358486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.1189358486
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.1671105944
Short name T63
Test name
Test status
Simulation time 200944602 ps
CPU time 5.71 seconds
Started Jul 14 06:53:06 PM PDT 24
Finished Jul 14 06:53:13 PM PDT 24
Peak memory 221124 kb
Host smart-7c88691b-e120-4603-93d9-6fd433171617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671105944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.1671105944
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.3681009427
Short name T241
Test name
Test status
Simulation time 232841830 ps
CPU time 2.38 seconds
Started Jul 14 06:53:05 PM PDT 24
Finished Jul 14 06:53:09 PM PDT 24
Peak memory 207828 kb
Host smart-07a3a110-f610-4479-9c7c-4a494b092e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681009427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.3681009427
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.2242475279
Short name T565
Test name
Test status
Simulation time 155085612 ps
CPU time 3.84 seconds
Started Jul 14 06:53:06 PM PDT 24
Finished Jul 14 06:53:11 PM PDT 24
Peak memory 209496 kb
Host smart-cbd0e460-d46f-4ff2-894d-137858f32ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242475279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.2242475279
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.1384695173
Short name T428
Test name
Test status
Simulation time 258846319 ps
CPU time 3.54 seconds
Started Jul 14 06:53:05 PM PDT 24
Finished Jul 14 06:53:10 PM PDT 24
Peak memory 208372 kb
Host smart-424f1773-24f1-485c-aa26-89cba399b630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384695173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.1384695173
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.1136542640
Short name T401
Test name
Test status
Simulation time 427842595 ps
CPU time 3.59 seconds
Started Jul 14 06:53:05 PM PDT 24
Finished Jul 14 06:53:11 PM PDT 24
Peak memory 208500 kb
Host smart-f8f08709-e062-458a-8f64-b1dc404794bb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136542640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.1136542640
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.4073659905
Short name T585
Test name
Test status
Simulation time 96808980 ps
CPU time 3.14 seconds
Started Jul 14 06:53:06 PM PDT 24
Finished Jul 14 06:53:11 PM PDT 24
Peak memory 208076 kb
Host smart-dcbe3983-61af-48d0-9cba-4e6b4d7e0d31
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073659905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.4073659905
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.3923740415
Short name T456
Test name
Test status
Simulation time 216646202 ps
CPU time 2.87 seconds
Started Jul 14 06:53:09 PM PDT 24
Finished Jul 14 06:53:13 PM PDT 24
Peak memory 208684 kb
Host smart-2864b002-bec7-4e99-8bc6-4c1bb3099ed8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923740415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.3923740415
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.1160019539
Short name T704
Test name
Test status
Simulation time 36845175 ps
CPU time 1.83 seconds
Started Jul 14 06:53:06 PM PDT 24
Finished Jul 14 06:53:10 PM PDT 24
Peak memory 208032 kb
Host smart-f392dcdb-7dfd-440c-9825-cf69f4a1ebf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160019539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.1160019539
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.1844092104
Short name T894
Test name
Test status
Simulation time 243426645 ps
CPU time 3 seconds
Started Jul 14 06:53:10 PM PDT 24
Finished Jul 14 06:53:15 PM PDT 24
Peak memory 208524 kb
Host smart-4a4fcb05-e08f-42da-878d-2135dd3745c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844092104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.1844092104
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.2045581735
Short name T745
Test name
Test status
Simulation time 2321708686 ps
CPU time 25.97 seconds
Started Jul 14 06:53:07 PM PDT 24
Finished Jul 14 06:53:34 PM PDT 24
Peak memory 221748 kb
Host smart-e3d17314-65bb-4c66-a180-b88aa106ccc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045581735 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.2045581735
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.3430828463
Short name T859
Test name
Test status
Simulation time 399465387 ps
CPU time 6.32 seconds
Started Jul 14 06:53:07 PM PDT 24
Finished Jul 14 06:53:14 PM PDT 24
Peak memory 210252 kb
Host smart-57a54308-4545-4dc7-aa4c-d9af212b5862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430828463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.3430828463
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.2786894779
Short name T579
Test name
Test status
Simulation time 116593878 ps
CPU time 1.8 seconds
Started Jul 14 06:53:09 PM PDT 24
Finished Jul 14 06:53:12 PM PDT 24
Peak memory 209968 kb
Host smart-c9a1aced-770a-48f4-99dc-f583beafc0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786894779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.2786894779
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.4262988641
Short name T478
Test name
Test status
Simulation time 13098977 ps
CPU time 0.89 seconds
Started Jul 14 06:53:13 PM PDT 24
Finished Jul 14 06:53:17 PM PDT 24
Peak memory 205968 kb
Host smart-2bd3e7dc-e891-442a-bacf-fffdd57a4832
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262988641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.4262988641
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.2605520115
Short name T118
Test name
Test status
Simulation time 317660271 ps
CPU time 4.05 seconds
Started Jul 14 06:53:05 PM PDT 24
Finished Jul 14 06:53:10 PM PDT 24
Peak memory 215460 kb
Host smart-aa3946ea-29d8-473b-861e-a472699eecb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2605520115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.2605520115
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.4182954100
Short name T74
Test name
Test status
Simulation time 51927480 ps
CPU time 2.78 seconds
Started Jul 14 06:53:08 PM PDT 24
Finished Jul 14 06:53:12 PM PDT 24
Peak memory 214284 kb
Host smart-f471d096-d6bf-4f0e-831f-d9dae9652317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182954100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.4182954100
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.2705352307
Short name T80
Test name
Test status
Simulation time 123240389 ps
CPU time 2.64 seconds
Started Jul 14 06:53:08 PM PDT 24
Finished Jul 14 06:53:12 PM PDT 24
Peak memory 214340 kb
Host smart-61a2a135-6417-4d71-ad55-51c774c47ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705352307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.2705352307
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.4057919833
Short name T871
Test name
Test status
Simulation time 108972300 ps
CPU time 3.54 seconds
Started Jul 14 06:53:05 PM PDT 24
Finished Jul 14 06:53:10 PM PDT 24
Peak memory 214308 kb
Host smart-6e74f7bc-ce80-461b-8bce-56ccd1291f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057919833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.4057919833
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.3884435553
Short name T475
Test name
Test status
Simulation time 135574814 ps
CPU time 5.59 seconds
Started Jul 14 06:53:07 PM PDT 24
Finished Jul 14 06:53:14 PM PDT 24
Peak memory 210120 kb
Host smart-a8124c60-c118-4128-bda8-9f158695c099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884435553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.3884435553
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.3586986703
Short name T408
Test name
Test status
Simulation time 853505003 ps
CPU time 19.6 seconds
Started Jul 14 06:53:08 PM PDT 24
Finished Jul 14 06:53:29 PM PDT 24
Peak memory 210412 kb
Host smart-848ae470-9cf5-476b-bc7c-39312d560948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586986703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.3586986703
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.2293320327
Short name T298
Test name
Test status
Simulation time 389723575 ps
CPU time 3.73 seconds
Started Jul 14 06:53:08 PM PDT 24
Finished Jul 14 06:53:13 PM PDT 24
Peak memory 208552 kb
Host smart-d6982ab7-9916-4705-8a4d-dfbc937376e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293320327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.2293320327
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.810759178
Short name T616
Test name
Test status
Simulation time 163906300 ps
CPU time 2.45 seconds
Started Jul 14 06:53:07 PM PDT 24
Finished Jul 14 06:53:11 PM PDT 24
Peak memory 206980 kb
Host smart-a3ba6ea7-2bb6-460d-8e37-7235364f5405
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810759178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.810759178
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.4256094993
Short name T338
Test name
Test status
Simulation time 544579130 ps
CPU time 14.31 seconds
Started Jul 14 06:53:09 PM PDT 24
Finished Jul 14 06:53:25 PM PDT 24
Peak memory 208464 kb
Host smart-ecf61646-7aa1-4bee-914f-85bdead4ea29
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256094993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.4256094993
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.1385636241
Short name T870
Test name
Test status
Simulation time 79066030 ps
CPU time 2.78 seconds
Started Jul 14 06:53:07 PM PDT 24
Finished Jul 14 06:53:11 PM PDT 24
Peak memory 206864 kb
Host smart-056a1953-2621-44df-9fa9-e498f8e5652b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385636241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.1385636241
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.4061479594
Short name T422
Test name
Test status
Simulation time 136952113 ps
CPU time 3.36 seconds
Started Jul 14 06:53:08 PM PDT 24
Finished Jul 14 06:53:13 PM PDT 24
Peak memory 208832 kb
Host smart-92b9d8e4-d961-472a-9042-e5748d524dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061479594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.4061479594
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.677955792
Short name T378
Test name
Test status
Simulation time 495381260 ps
CPU time 4.53 seconds
Started Jul 14 06:53:05 PM PDT 24
Finished Jul 14 06:53:10 PM PDT 24
Peak memory 208784 kb
Host smart-0dcb7a6e-fa6d-4462-820d-2a213ff23951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677955792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.677955792
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.3296165590
Short name T249
Test name
Test status
Simulation time 310185925 ps
CPU time 15.27 seconds
Started Jul 14 06:53:11 PM PDT 24
Finished Jul 14 06:53:28 PM PDT 24
Peak memory 216296 kb
Host smart-bffb9b98-81dd-4edb-8df6-174743c587b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296165590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.3296165590
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.1588106491
Short name T438
Test name
Test status
Simulation time 43506853 ps
CPU time 2.96 seconds
Started Jul 14 06:53:08 PM PDT 24
Finished Jul 14 06:53:12 PM PDT 24
Peak memory 207524 kb
Host smart-74e5c05e-d952-42d3-9f8a-c7fd74e1a24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588106491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.1588106491
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.1903477109
Short name T367
Test name
Test status
Simulation time 151192048 ps
CPU time 4.32 seconds
Started Jul 14 06:53:12 PM PDT 24
Finished Jul 14 06:53:19 PM PDT 24
Peak memory 210880 kb
Host smart-4595575a-3685-40b5-95ea-6ffa51719f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903477109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.1903477109
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.1596747894
Short name T830
Test name
Test status
Simulation time 30427808 ps
CPU time 0.76 seconds
Started Jul 14 06:53:16 PM PDT 24
Finished Jul 14 06:53:19 PM PDT 24
Peak memory 205968 kb
Host smart-c96764d6-8ab3-49d5-b45e-b57842a9fd24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596747894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.1596747894
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.175660422
Short name T30
Test name
Test status
Simulation time 182408194 ps
CPU time 2.63 seconds
Started Jul 14 06:53:10 PM PDT 24
Finished Jul 14 06:53:14 PM PDT 24
Peak memory 216180 kb
Host smart-b214cc17-cdd2-4ad9-b31f-cd93bd103686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175660422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.175660422
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.2492063334
Short name T131
Test name
Test status
Simulation time 156183553 ps
CPU time 1.56 seconds
Started Jul 14 06:53:16 PM PDT 24
Finished Jul 14 06:53:19 PM PDT 24
Peak memory 207440 kb
Host smart-ed1f42e2-d0ec-4f0e-b5cc-be56a44c42f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492063334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2492063334
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.2380233753
Short name T505
Test name
Test status
Simulation time 149505232 ps
CPU time 2.97 seconds
Started Jul 14 06:53:12 PM PDT 24
Finished Jul 14 06:53:18 PM PDT 24
Peak memory 217572 kb
Host smart-f96777b2-b23c-4745-9c30-7bafb09dba14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380233753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.2380233753
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.655128649
Short name T291
Test name
Test status
Simulation time 1777513970 ps
CPU time 3.66 seconds
Started Jul 14 06:53:14 PM PDT 24
Finished Jul 14 06:53:20 PM PDT 24
Peak memory 214060 kb
Host smart-a21ef19e-d949-4911-8374-9a867dea5f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655128649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.655128649
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.1895408344
Short name T380
Test name
Test status
Simulation time 223501971 ps
CPU time 4.03 seconds
Started Jul 14 06:53:12 PM PDT 24
Finished Jul 14 06:53:19 PM PDT 24
Peak memory 220528 kb
Host smart-0040fbd3-708d-4225-8ebf-2fccd2572107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895408344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.1895408344
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.3939269575
Short name T898
Test name
Test status
Simulation time 95553606 ps
CPU time 2.46 seconds
Started Jul 14 06:53:16 PM PDT 24
Finished Jul 14 06:53:20 PM PDT 24
Peak memory 207496 kb
Host smart-cadc1998-0af2-4420-90ad-84fb28717cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939269575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.3939269575
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.3412263413
Short name T246
Test name
Test status
Simulation time 257111796 ps
CPU time 4.07 seconds
Started Jul 14 06:53:14 PM PDT 24
Finished Jul 14 06:53:20 PM PDT 24
Peak memory 206760 kb
Host smart-848c1731-aa6e-4242-8217-266fa36fdfe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412263413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.3412263413
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.1801268950
Short name T446
Test name
Test status
Simulation time 649702035 ps
CPU time 9.64 seconds
Started Jul 14 06:53:16 PM PDT 24
Finished Jul 14 06:53:28 PM PDT 24
Peak memory 208264 kb
Host smart-49ff50b2-b443-42f8-9a9e-3a674eb53757
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801268950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.1801268950
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.1644682819
Short name T372
Test name
Test status
Simulation time 124995477 ps
CPU time 3.13 seconds
Started Jul 14 06:53:11 PM PDT 24
Finished Jul 14 06:53:15 PM PDT 24
Peak memory 208596 kb
Host smart-a998526c-48ce-4cd3-91cb-1944dbdff8db
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644682819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.1644682819
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.254248402
Short name T913
Test name
Test status
Simulation time 51176660 ps
CPU time 2.33 seconds
Started Jul 14 06:53:10 PM PDT 24
Finished Jul 14 06:53:14 PM PDT 24
Peak memory 207300 kb
Host smart-2b4dd217-037f-4984-a611-c3aada629123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254248402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.254248402
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.2753743543
Short name T601
Test name
Test status
Simulation time 144633536 ps
CPU time 5.12 seconds
Started Jul 14 06:53:14 PM PDT 24
Finished Jul 14 06:53:21 PM PDT 24
Peak memory 208468 kb
Host smart-4b544ea4-6f04-4aab-92b2-56f2d40406cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753743543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.2753743543
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.61426698
Short name T376
Test name
Test status
Simulation time 260941436 ps
CPU time 5.03 seconds
Started Jul 14 06:53:15 PM PDT 24
Finished Jul 14 06:53:22 PM PDT 24
Peak memory 208868 kb
Host smart-eb52450d-9009-4627-9c3a-249abb59b59e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61426698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.61426698
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.3507524039
Short name T359
Test name
Test status
Simulation time 2231238647 ps
CPU time 26.79 seconds
Started Jul 14 06:53:16 PM PDT 24
Finished Jul 14 06:53:45 PM PDT 24
Peak memory 214160 kb
Host smart-4a69b3ae-8cb2-4adb-904d-6ff5d69c2474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507524039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3507524039
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.864916878
Short name T449
Test name
Test status
Simulation time 61117740 ps
CPU time 3.2 seconds
Started Jul 14 06:53:12 PM PDT 24
Finished Jul 14 06:53:18 PM PDT 24
Peak memory 210268 kb
Host smart-f51577b5-5f1e-4d98-991f-faec93c09447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864916878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.864916878
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.2306896067
Short name T97
Test name
Test status
Simulation time 24670151 ps
CPU time 0.71 seconds
Started Jul 14 06:52:21 PM PDT 24
Finished Jul 14 06:52:23 PM PDT 24
Peak memory 205988 kb
Host smart-f2bc3875-4d7e-4c99-b09d-1907f3cd5338
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306896067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.2306896067
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.745932790
Short name T258
Test name
Test status
Simulation time 1618292864 ps
CPU time 87.56 seconds
Started Jul 14 06:52:18 PM PDT 24
Finished Jul 14 06:53:47 PM PDT 24
Peak memory 214548 kb
Host smart-7d1cf96c-96c6-4ead-81e8-76e650b2f5e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=745932790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.745932790
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.2016079989
Short name T653
Test name
Test status
Simulation time 237018942 ps
CPU time 4.91 seconds
Started Jul 14 06:52:23 PM PDT 24
Finished Jul 14 06:52:30 PM PDT 24
Peak memory 210408 kb
Host smart-d5d5ab45-2f45-477d-980a-446acafd7f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016079989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.2016079989
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.2031435727
Short name T254
Test name
Test status
Simulation time 90993560 ps
CPU time 4.31 seconds
Started Jul 14 06:52:24 PM PDT 24
Finished Jul 14 06:52:29 PM PDT 24
Peak memory 209628 kb
Host smart-ed86d210-46f3-44dd-afda-8eee5f83da50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031435727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.2031435727
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.748871112
Short name T802
Test name
Test status
Simulation time 109067005 ps
CPU time 2.32 seconds
Started Jul 14 06:52:24 PM PDT 24
Finished Jul 14 06:52:28 PM PDT 24
Peak memory 214344 kb
Host smart-6f0b28ea-03f6-438d-8082-b1d70e4cd23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748871112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.748871112
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.2598117029
Short name T652
Test name
Test status
Simulation time 62433041 ps
CPU time 3.06 seconds
Started Jul 14 06:52:21 PM PDT 24
Finished Jul 14 06:52:26 PM PDT 24
Peak memory 209524 kb
Host smart-fa2bdf2f-9672-49d1-844e-52da59351d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598117029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.2598117029
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.936383319
Short name T458
Test name
Test status
Simulation time 379151181 ps
CPU time 5 seconds
Started Jul 14 06:52:21 PM PDT 24
Finished Jul 14 06:52:28 PM PDT 24
Peak memory 209516 kb
Host smart-24b2fad3-0d11-4f3b-99e4-43a897ea5543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936383319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.936383319
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sideload.1456866654
Short name T299
Test name
Test status
Simulation time 2222382057 ps
CPU time 44.74 seconds
Started Jul 14 06:52:23 PM PDT 24
Finished Jul 14 06:53:10 PM PDT 24
Peak memory 208508 kb
Host smart-8d9217fa-a783-4e36-aee3-380a68bb131a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456866654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.1456866654
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.2633985422
Short name T612
Test name
Test status
Simulation time 117429549 ps
CPU time 3.28 seconds
Started Jul 14 06:52:18 PM PDT 24
Finished Jul 14 06:52:23 PM PDT 24
Peak memory 208708 kb
Host smart-ec70d61a-7902-4fe9-9114-4355fff32595
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633985422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.2633985422
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.3719324099
Short name T138
Test name
Test status
Simulation time 1631072486 ps
CPU time 5.79 seconds
Started Jul 14 06:52:24 PM PDT 24
Finished Jul 14 06:52:31 PM PDT 24
Peak memory 208024 kb
Host smart-f89d8ded-e5e5-402f-8fc9-82072b8ff259
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719324099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.3719324099
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.4154077002
Short name T849
Test name
Test status
Simulation time 122373022 ps
CPU time 3.12 seconds
Started Jul 14 06:52:22 PM PDT 24
Finished Jul 14 06:52:27 PM PDT 24
Peak memory 206840 kb
Host smart-e826f392-5bdb-4ca7-b7b7-e8f0c9865617
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154077002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.4154077002
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.5543913
Short name T243
Test name
Test status
Simulation time 97542932 ps
CPU time 3.97 seconds
Started Jul 14 06:52:20 PM PDT 24
Finished Jul 14 06:52:25 PM PDT 24
Peak memory 214296 kb
Host smart-5105cb2e-4b8c-4eb4-82b1-f507120e526e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5543913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.5543913
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.2271706206
Short name T860
Test name
Test status
Simulation time 243313294 ps
CPU time 1.66 seconds
Started Jul 14 06:52:20 PM PDT 24
Finished Jul 14 06:52:23 PM PDT 24
Peak memory 206884 kb
Host smart-b3c6dc53-5cb7-4097-9a8b-776a2409aa26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271706206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.2271706206
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.2550587192
Short name T187
Test name
Test status
Simulation time 271335306 ps
CPU time 10.51 seconds
Started Jul 14 06:52:23 PM PDT 24
Finished Jul 14 06:52:35 PM PDT 24
Peak memory 222632 kb
Host smart-95c49f4e-ad92-41e0-8d5a-0e57988a4c1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550587192 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.2550587192
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.627062111
Short name T670
Test name
Test status
Simulation time 60516689 ps
CPU time 3.25 seconds
Started Jul 14 06:52:23 PM PDT 24
Finished Jul 14 06:52:28 PM PDT 24
Peak memory 208068 kb
Host smart-42b8b6eb-50ab-4df2-945f-791a44f4963a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627062111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.627062111
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.2570852305
Short name T171
Test name
Test status
Simulation time 79957896 ps
CPU time 3.25 seconds
Started Jul 14 06:52:22 PM PDT 24
Finished Jul 14 06:52:27 PM PDT 24
Peak memory 210264 kb
Host smart-1c9f8480-bb4e-412a-840d-f6d478812028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570852305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.2570852305
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.549783337
Short name T490
Test name
Test status
Simulation time 31391009 ps
CPU time 0.71 seconds
Started Jul 14 06:53:12 PM PDT 24
Finished Jul 14 06:53:15 PM PDT 24
Peak memory 206004 kb
Host smart-b7e054aa-af5d-428f-a383-c99c203c6fa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549783337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.549783337
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.588064852
Short name T587
Test name
Test status
Simulation time 1758282274 ps
CPU time 10.72 seconds
Started Jul 14 06:53:13 PM PDT 24
Finished Jul 14 06:53:26 PM PDT 24
Peak memory 207316 kb
Host smart-a4eac05e-7fd2-4c16-9268-dec80c544ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588064852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.588064852
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.1894594568
Short name T100
Test name
Test status
Simulation time 64837554 ps
CPU time 3.18 seconds
Started Jul 14 06:53:14 PM PDT 24
Finished Jul 14 06:53:20 PM PDT 24
Peak memory 214324 kb
Host smart-04ddc6fc-2300-4a4b-93e9-e36fd04ddb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894594568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.1894594568
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2497310404
Short name T102
Test name
Test status
Simulation time 141635206 ps
CPU time 5.77 seconds
Started Jul 14 06:53:12 PM PDT 24
Finished Jul 14 06:53:19 PM PDT 24
Peak memory 214248 kb
Host smart-d9c7a1bb-f5f5-4be4-afa9-8dabb5a3560c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497310404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2497310404
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.3542947036
Short name T808
Test name
Test status
Simulation time 879439412 ps
CPU time 5.7 seconds
Started Jul 14 06:53:15 PM PDT 24
Finished Jul 14 06:53:23 PM PDT 24
Peak memory 214300 kb
Host smart-4a51db36-0b76-4b67-b3a6-a87251792ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542947036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3542947036
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.1081066090
Short name T779
Test name
Test status
Simulation time 621288305 ps
CPU time 2.6 seconds
Started Jul 14 06:53:13 PM PDT 24
Finished Jul 14 06:53:18 PM PDT 24
Peak memory 208832 kb
Host smart-8a80a1d7-2e14-41af-8879-29bc907a3045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081066090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1081066090
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.2394054893
Short name T332
Test name
Test status
Simulation time 3831730169 ps
CPU time 26.31 seconds
Started Jul 14 06:53:15 PM PDT 24
Finished Jul 14 06:53:44 PM PDT 24
Peak memory 208516 kb
Host smart-53350a49-0a62-4809-9606-3ef784f1e64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394054893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.2394054893
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.994160304
Short name T462
Test name
Test status
Simulation time 124277626 ps
CPU time 2.21 seconds
Started Jul 14 06:53:12 PM PDT 24
Finished Jul 14 06:53:16 PM PDT 24
Peak memory 208764 kb
Host smart-4babf9c1-afec-4290-944d-bf735bd604c3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994160304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.994160304
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.2660433090
Short name T278
Test name
Test status
Simulation time 36462657 ps
CPU time 2.22 seconds
Started Jul 14 06:53:13 PM PDT 24
Finished Jul 14 06:53:18 PM PDT 24
Peak memory 207000 kb
Host smart-82ef4ab2-57c6-425b-8de3-269bd4eb6bfb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660433090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.2660433090
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.3842935223
Short name T134
Test name
Test status
Simulation time 403085674 ps
CPU time 2.82 seconds
Started Jul 14 06:53:12 PM PDT 24
Finished Jul 14 06:53:18 PM PDT 24
Peak memory 206748 kb
Host smart-28cfb3a0-2112-4a48-bd47-d038dfd6113c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842935223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.3842935223
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.4168674482
Short name T289
Test name
Test status
Simulation time 230521708 ps
CPU time 3.89 seconds
Started Jul 14 06:53:13 PM PDT 24
Finished Jul 14 06:53:19 PM PDT 24
Peak memory 209792 kb
Host smart-7e5c961b-cc27-4a02-b0fb-9f156dc5cc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168674482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.4168674482
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.1199266780
Short name T549
Test name
Test status
Simulation time 1553346868 ps
CPU time 33.93 seconds
Started Jul 14 06:53:16 PM PDT 24
Finished Jul 14 06:53:52 PM PDT 24
Peak memory 208060 kb
Host smart-ea773543-34d6-4995-ac70-1b876d356c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199266780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.1199266780
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.2002018102
Short name T878
Test name
Test status
Simulation time 533897904 ps
CPU time 21.75 seconds
Started Jul 14 06:53:12 PM PDT 24
Finished Jul 14 06:53:36 PM PDT 24
Peak memory 222204 kb
Host smart-ab9ff858-5b66-45ee-a7c4-b0e74d384723
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002018102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.2002018102
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.1724214368
Short name T632
Test name
Test status
Simulation time 7635561577 ps
CPU time 25.77 seconds
Started Jul 14 06:53:11 PM PDT 24
Finished Jul 14 06:53:38 PM PDT 24
Peak memory 222740 kb
Host smart-183dc44b-e4f1-4770-9eba-8ad0db86fefa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724214368 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.1724214368
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.343035583
Short name T698
Test name
Test status
Simulation time 235564360 ps
CPU time 2.95 seconds
Started Jul 14 06:53:12 PM PDT 24
Finished Jul 14 06:53:18 PM PDT 24
Peak memory 210684 kb
Host smart-caa3948b-afb3-472d-9c61-dd56706fac27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343035583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.343035583
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.120893547
Short name T404
Test name
Test status
Simulation time 20828253 ps
CPU time 0.86 seconds
Started Jul 14 06:53:26 PM PDT 24
Finished Jul 14 06:53:28 PM PDT 24
Peak memory 205976 kb
Host smart-00c21358-c645-4e8a-982c-83c9022298f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120893547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.120893547
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.3869934513
Short name T224
Test name
Test status
Simulation time 79359734 ps
CPU time 2.7 seconds
Started Jul 14 06:53:16 PM PDT 24
Finished Jul 14 06:53:21 PM PDT 24
Peak memory 214288 kb
Host smart-aad4b1a5-5fce-488c-84d7-0b583225e50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869934513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.3869934513
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.3142015647
Short name T194
Test name
Test status
Simulation time 162755870 ps
CPU time 3.74 seconds
Started Jul 14 06:53:13 PM PDT 24
Finished Jul 14 06:53:19 PM PDT 24
Peak memory 210272 kb
Host smart-63d13d61-312a-44e5-a77c-7ee8b562c95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142015647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.3142015647
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2675255507
Short name T18
Test name
Test status
Simulation time 105068214 ps
CPU time 2.08 seconds
Started Jul 14 06:53:14 PM PDT 24
Finished Jul 14 06:53:18 PM PDT 24
Peak memory 214308 kb
Host smart-d7fcdb4d-b92a-4f90-a8ea-2504ed82f4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675255507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2675255507
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.3141131294
Short name T629
Test name
Test status
Simulation time 107623660 ps
CPU time 2.16 seconds
Started Jul 14 06:53:14 PM PDT 24
Finished Jul 14 06:53:22 PM PDT 24
Peak memory 206336 kb
Host smart-644ae880-4ed5-42a2-98bc-1cbd28aa5353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141131294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.3141131294
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.3294029995
Short name T468
Test name
Test status
Simulation time 2923063083 ps
CPU time 24.72 seconds
Started Jul 14 06:53:11 PM PDT 24
Finished Jul 14 06:53:42 PM PDT 24
Peak memory 218536 kb
Host smart-d8648c30-10b6-4284-8871-f9dcd79fe707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294029995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.3294029995
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.1426806539
Short name T419
Test name
Test status
Simulation time 18759251 ps
CPU time 1.85 seconds
Started Jul 14 06:53:14 PM PDT 24
Finished Jul 14 06:53:18 PM PDT 24
Peak memory 207024 kb
Host smart-df228e1d-0222-4557-90fd-01aa1662b3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426806539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.1426806539
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.2619219495
Short name T590
Test name
Test status
Simulation time 133025737 ps
CPU time 2.49 seconds
Started Jul 14 06:53:12 PM PDT 24
Finished Jul 14 06:53:16 PM PDT 24
Peak memory 206800 kb
Host smart-dacc5e8f-0a86-455d-ab20-f249a81c36c1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619219495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.2619219495
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.624358727
Short name T427
Test name
Test status
Simulation time 10202371590 ps
CPU time 49.97 seconds
Started Jul 14 06:53:13 PM PDT 24
Finished Jul 14 06:54:05 PM PDT 24
Peak memory 208104 kb
Host smart-adc83e6f-3f55-44a8-911b-5f3abbffe766
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624358727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.624358727
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.2356536494
Short name T650
Test name
Test status
Simulation time 107775575 ps
CPU time 2.71 seconds
Started Jul 14 06:53:11 PM PDT 24
Finished Jul 14 06:53:15 PM PDT 24
Peak memory 206944 kb
Host smart-0ca5a774-b704-4f6d-ab4e-91ccb7ffb494
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356536494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.2356536494
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.2984443289
Short name T491
Test name
Test status
Simulation time 121078684 ps
CPU time 3.12 seconds
Started Jul 14 06:53:13 PM PDT 24
Finished Jul 14 06:53:19 PM PDT 24
Peak memory 210436 kb
Host smart-92a32944-16ac-4c3c-a559-e987b14801ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984443289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.2984443289
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.1846034834
Short name T75
Test name
Test status
Simulation time 111913381 ps
CPU time 2.13 seconds
Started Jul 14 06:53:11 PM PDT 24
Finished Jul 14 06:53:15 PM PDT 24
Peak memory 206904 kb
Host smart-9c1f5bb3-5d3d-4ca4-bc1c-b301df6bd369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846034834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.1846034834
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.1477541388
Short name T589
Test name
Test status
Simulation time 479080315 ps
CPU time 15.87 seconds
Started Jul 14 06:53:24 PM PDT 24
Finished Jul 14 06:53:41 PM PDT 24
Peak memory 216288 kb
Host smart-229044ca-8adb-4cf8-9dc1-f8a8314b2b9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477541388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.1477541388
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.666521036
Short name T627
Test name
Test status
Simulation time 224454815 ps
CPU time 6.78 seconds
Started Jul 14 06:53:13 PM PDT 24
Finished Jul 14 06:53:22 PM PDT 24
Peak memory 210660 kb
Host smart-77c69656-1630-4498-b5bb-d70b73eb8390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666521036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.666521036
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.3412790258
Short name T861
Test name
Test status
Simulation time 312519762 ps
CPU time 3.39 seconds
Started Jul 14 06:53:24 PM PDT 24
Finished Jul 14 06:53:28 PM PDT 24
Peak memory 210620 kb
Host smart-d3fc847a-1d90-4cb4-a251-ce922c43fd90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412790258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.3412790258
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.2170428930
Short name T497
Test name
Test status
Simulation time 51933440 ps
CPU time 0.9 seconds
Started Jul 14 06:53:26 PM PDT 24
Finished Jul 14 06:53:29 PM PDT 24
Peak memory 206000 kb
Host smart-ce80bdb8-d572-4636-8281-96c69f119d8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170428930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.2170428930
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.442956742
Short name T394
Test name
Test status
Simulation time 236529976 ps
CPU time 3.54 seconds
Started Jul 14 06:53:26 PM PDT 24
Finished Jul 14 06:53:31 PM PDT 24
Peak memory 214312 kb
Host smart-580711d2-fc3a-47c2-a256-a87bdfd74e00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=442956742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.442956742
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.3061604148
Short name T335
Test name
Test status
Simulation time 67455776 ps
CPU time 1.87 seconds
Started Jul 14 06:53:25 PM PDT 24
Finished Jul 14 06:53:27 PM PDT 24
Peak memory 217276 kb
Host smart-61331049-cf5c-4027-a694-47569ea542de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061604148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.3061604148
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.1466175551
Short name T354
Test name
Test status
Simulation time 75488656 ps
CPU time 2.62 seconds
Started Jul 14 06:53:17 PM PDT 24
Finished Jul 14 06:53:21 PM PDT 24
Peak memory 207668 kb
Host smart-515c056c-4b06-411f-8f64-ed042bd608ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466175551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.1466175551
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.1197800667
Short name T82
Test name
Test status
Simulation time 293731621 ps
CPU time 3.05 seconds
Started Jul 14 06:53:26 PM PDT 24
Finished Jul 14 06:53:30 PM PDT 24
Peak memory 214340 kb
Host smart-89b3e15b-2880-48b7-83d6-fbc5f63cbc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197800667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.1197800667
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.3813071711
Short name T280
Test name
Test status
Simulation time 259007544 ps
CPU time 2.58 seconds
Started Jul 14 06:53:27 PM PDT 24
Finished Jul 14 06:53:31 PM PDT 24
Peak memory 214212 kb
Host smart-a0a348dd-1de0-4115-9a19-5339f3ad66e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813071711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.3813071711
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_random.3280880341
Short name T479
Test name
Test status
Simulation time 941789653 ps
CPU time 21.78 seconds
Started Jul 14 06:53:27 PM PDT 24
Finished Jul 14 06:53:51 PM PDT 24
Peak memory 209024 kb
Host smart-14771d53-f674-4180-b595-5b1a8cc46d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280880341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.3280880341
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.312100133
Short name T610
Test name
Test status
Simulation time 50600719 ps
CPU time 2.5 seconds
Started Jul 14 06:53:15 PM PDT 24
Finished Jul 14 06:53:20 PM PDT 24
Peak memory 207164 kb
Host smart-27a66425-7144-42a5-a460-217304eafb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312100133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.312100133
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.567288025
Short name T671
Test name
Test status
Simulation time 139157363 ps
CPU time 2.2 seconds
Started Jul 14 06:53:19 PM PDT 24
Finished Jul 14 06:53:22 PM PDT 24
Peak memory 206928 kb
Host smart-1cb9f178-77c0-4f12-95c3-bc2e91779a50
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567288025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.567288025
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.2202985971
Short name T752
Test name
Test status
Simulation time 923560456 ps
CPU time 5.59 seconds
Started Jul 14 06:53:35 PM PDT 24
Finished Jul 14 06:53:45 PM PDT 24
Peak memory 209084 kb
Host smart-bd31a66a-1371-4da5-ac66-3f9579530f03
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202985971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.2202985971
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.1324901934
Short name T881
Test name
Test status
Simulation time 305663833 ps
CPU time 4.75 seconds
Started Jul 14 06:53:16 PM PDT 24
Finished Jul 14 06:53:23 PM PDT 24
Peak memory 208448 kb
Host smart-df87a3c7-4321-43a7-8abe-923b7c84b435
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324901934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.1324901934
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.1157345225
Short name T477
Test name
Test status
Simulation time 1373687996 ps
CPU time 7.92 seconds
Started Jul 14 06:53:17 PM PDT 24
Finished Jul 14 06:53:27 PM PDT 24
Peak memory 214440 kb
Host smart-403f3a60-2b7d-4a61-b794-95d7f2a5f58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157345225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.1157345225
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.4198456707
Short name T410
Test name
Test status
Simulation time 32822572 ps
CPU time 2.15 seconds
Started Jul 14 06:53:26 PM PDT 24
Finished Jul 14 06:53:30 PM PDT 24
Peak memory 207248 kb
Host smart-a9b97398-4b22-42a9-88b1-31741cae6aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198456707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.4198456707
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.750094883
Short name T61
Test name
Test status
Simulation time 17127121382 ps
CPU time 52.84 seconds
Started Jul 14 06:53:24 PM PDT 24
Finished Jul 14 06:54:18 PM PDT 24
Peak memory 216736 kb
Host smart-829465d5-2c09-448d-b053-20b026e3e6a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750094883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.750094883
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.669731155
Short name T125
Test name
Test status
Simulation time 1592146569 ps
CPU time 18.02 seconds
Started Jul 14 06:53:19 PM PDT 24
Finished Jul 14 06:53:38 PM PDT 24
Peak memory 220956 kb
Host smart-7f97ffd5-aada-41fb-b3ed-bd58addd4a70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669731155 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.669731155
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.2331069956
Short name T644
Test name
Test status
Simulation time 5971364921 ps
CPU time 38.42 seconds
Started Jul 14 06:53:21 PM PDT 24
Finished Jul 14 06:54:00 PM PDT 24
Peak memory 218584 kb
Host smart-439c8dd9-743b-4e75-9346-57a0278462f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331069956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.2331069956
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.1530525409
Short name T733
Test name
Test status
Simulation time 116562066 ps
CPU time 2.41 seconds
Started Jul 14 06:53:16 PM PDT 24
Finished Jul 14 06:53:21 PM PDT 24
Peak memory 210140 kb
Host smart-bff90764-dc51-4adc-8bc1-db44ab32ab52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530525409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.1530525409
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.2771554846
Short name T434
Test name
Test status
Simulation time 54094615 ps
CPU time 0.77 seconds
Started Jul 14 06:53:25 PM PDT 24
Finished Jul 14 06:53:27 PM PDT 24
Peak memory 206056 kb
Host smart-04d96537-35e9-4448-af35-ea45ca2d803d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771554846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.2771554846
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.2391098463
Short name T259
Test name
Test status
Simulation time 139348957 ps
CPU time 7.42 seconds
Started Jul 14 06:53:25 PM PDT 24
Finished Jul 14 06:53:33 PM PDT 24
Peak memory 214404 kb
Host smart-d385a7a1-7c1f-41be-9d35-214a704484d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2391098463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.2391098463
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.2190527020
Short name T437
Test name
Test status
Simulation time 88872144 ps
CPU time 2.48 seconds
Started Jul 14 06:53:26 PM PDT 24
Finished Jul 14 06:53:30 PM PDT 24
Peak memory 208284 kb
Host smart-b618e48e-c426-4039-ad09-9d4d20951b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190527020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2190527020
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.1765835947
Short name T84
Test name
Test status
Simulation time 365767553 ps
CPU time 4.9 seconds
Started Jul 14 06:53:35 PM PDT 24
Finished Jul 14 06:53:43 PM PDT 24
Peak memory 214256 kb
Host smart-d26e33c2-9502-48e9-bdbc-52419a9bb073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765835947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.1765835947
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.2812073881
Short name T873
Test name
Test status
Simulation time 608990257 ps
CPU time 4.27 seconds
Started Jul 14 06:53:25 PM PDT 24
Finished Jul 14 06:53:31 PM PDT 24
Peak memory 212008 kb
Host smart-58002c4e-d252-4b80-971f-0291271eda86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812073881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.2812073881
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.2609390448
Short name T523
Test name
Test status
Simulation time 223703569 ps
CPU time 2.8 seconds
Started Jul 14 06:53:24 PM PDT 24
Finished Jul 14 06:53:28 PM PDT 24
Peak memory 209808 kb
Host smart-c78b0c8d-f9ab-48da-9ed3-f8933db1cb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609390448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.2609390448
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.3541419713
Short name T678
Test name
Test status
Simulation time 285687670 ps
CPU time 7.81 seconds
Started Jul 14 06:53:25 PM PDT 24
Finished Jul 14 06:53:33 PM PDT 24
Peak memory 208100 kb
Host smart-6166023a-e338-4f49-b683-8169628bf9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541419713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.3541419713
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.2784479233
Short name T433
Test name
Test status
Simulation time 380657820 ps
CPU time 9.55 seconds
Started Jul 14 06:53:26 PM PDT 24
Finished Jul 14 06:53:38 PM PDT 24
Peak memory 207920 kb
Host smart-e2d09484-c938-4eaa-ac37-d41a52ffcecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784479233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.2784479233
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1376826190
Short name T770
Test name
Test status
Simulation time 146992506 ps
CPU time 4.19 seconds
Started Jul 14 06:53:24 PM PDT 24
Finished Jul 14 06:53:29 PM PDT 24
Peak memory 208144 kb
Host smart-b46812f3-f125-4c9f-a841-2804203a1971
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376826190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1376826190
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.2923259916
Short name T642
Test name
Test status
Simulation time 108123983 ps
CPU time 3.78 seconds
Started Jul 14 06:53:27 PM PDT 24
Finished Jul 14 06:53:33 PM PDT 24
Peak memory 208912 kb
Host smart-8ca9405f-960f-413f-9e70-478bd33d6863
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923259916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.2923259916
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.1226255758
Short name T634
Test name
Test status
Simulation time 3608528625 ps
CPU time 21.83 seconds
Started Jul 14 06:53:26 PM PDT 24
Finished Jul 14 06:53:50 PM PDT 24
Peak memory 208176 kb
Host smart-901bab3f-6614-481a-a59c-1cbe970b2c8d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226255758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.1226255758
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.1568880076
Short name T284
Test name
Test status
Simulation time 110946879 ps
CPU time 2.81 seconds
Started Jul 14 06:53:25 PM PDT 24
Finished Jul 14 06:53:29 PM PDT 24
Peak memory 209776 kb
Host smart-977a45a0-ced4-4928-a8a0-33aae8f7ab49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568880076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.1568880076
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.3215365611
Short name T576
Test name
Test status
Simulation time 166596955 ps
CPU time 2.55 seconds
Started Jul 14 06:53:15 PM PDT 24
Finished Jul 14 06:53:20 PM PDT 24
Peak memory 206140 kb
Host smart-485d249a-07c8-4624-a491-c289d3817064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215365611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.3215365611
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.2829537526
Short name T480
Test name
Test status
Simulation time 1124470239 ps
CPU time 2.84 seconds
Started Jul 14 06:53:17 PM PDT 24
Finished Jul 14 06:53:22 PM PDT 24
Peak memory 210496 kb
Host smart-eb022de7-352b-4fe1-beb2-d5b2818acd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829537526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.2829537526
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.130009957
Short name T467
Test name
Test status
Simulation time 33055071 ps
CPU time 0.83 seconds
Started Jul 14 06:53:29 PM PDT 24
Finished Jul 14 06:53:31 PM PDT 24
Peak memory 205996 kb
Host smart-07ab2e6a-71be-4d7e-ae14-d8893707f3a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130009957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.130009957
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.341870843
Short name T813
Test name
Test status
Simulation time 201382132 ps
CPU time 2.05 seconds
Started Jul 14 06:53:29 PM PDT 24
Finished Jul 14 06:53:33 PM PDT 24
Peak memory 209136 kb
Host smart-9d9ebc64-2e17-4761-a283-7f0ec255c88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341870843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.341870843
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.3068972229
Short name T828
Test name
Test status
Simulation time 109588485 ps
CPU time 4.21 seconds
Started Jul 14 06:53:32 PM PDT 24
Finished Jul 14 06:53:37 PM PDT 24
Peak memory 209588 kb
Host smart-88d8f748-c5e8-41a5-a9ad-87245d49f637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068972229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.3068972229
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.2056083167
Short name T25
Test name
Test status
Simulation time 1493980476 ps
CPU time 20.08 seconds
Started Jul 14 06:53:31 PM PDT 24
Finished Jul 14 06:53:52 PM PDT 24
Peak memory 214312 kb
Host smart-96ea6eed-4b96-4237-8c25-7cebf2d2530c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056083167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2056083167
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.662230876
Short name T321
Test name
Test status
Simulation time 339885722 ps
CPU time 3.87 seconds
Started Jul 14 06:53:36 PM PDT 24
Finished Jul 14 06:53:44 PM PDT 24
Peak memory 215740 kb
Host smart-30022cc5-eaf2-4ff0-ba8d-cbcc9e4f49dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662230876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.662230876
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.16008239
Short name T351
Test name
Test status
Simulation time 206040452 ps
CPU time 2.49 seconds
Started Jul 14 06:53:27 PM PDT 24
Finished Jul 14 06:53:31 PM PDT 24
Peak memory 208708 kb
Host smart-535fa17a-4f34-4e43-a3cd-72b6b7dcf9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16008239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.16008239
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.3658458240
Short name T504
Test name
Test status
Simulation time 1035340771 ps
CPU time 18.98 seconds
Started Jul 14 06:53:32 PM PDT 24
Finished Jul 14 06:53:54 PM PDT 24
Peak memory 208836 kb
Host smart-171fa449-9e42-46fd-ae7a-94ac7fb6f8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658458240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.3658458240
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.3129119487
Short name T757
Test name
Test status
Simulation time 177539994 ps
CPU time 3.27 seconds
Started Jul 14 06:53:29 PM PDT 24
Finished Jul 14 06:53:33 PM PDT 24
Peak memory 208568 kb
Host smart-ccc00ee1-d0b0-4404-96a9-5051ca7e17e7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129119487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.3129119487
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.2087464203
Short name T482
Test name
Test status
Simulation time 209636956 ps
CPU time 3.16 seconds
Started Jul 14 06:53:27 PM PDT 24
Finished Jul 14 06:53:32 PM PDT 24
Peak memory 207012 kb
Host smart-700e3a0a-3e3d-47c0-a358-80abe7ab432b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087464203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.2087464203
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.2079570224
Short name T471
Test name
Test status
Simulation time 460100805 ps
CPU time 11.3 seconds
Started Jul 14 06:53:31 PM PDT 24
Finished Jul 14 06:53:51 PM PDT 24
Peak memory 208216 kb
Host smart-6311d682-f62b-4b2b-a4a7-7ebb1ad42dd7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079570224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.2079570224
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.3158683223
Short name T611
Test name
Test status
Simulation time 1504048433 ps
CPU time 4.92 seconds
Started Jul 14 06:53:34 PM PDT 24
Finished Jul 14 06:53:43 PM PDT 24
Peak memory 215680 kb
Host smart-45551364-4fec-48c2-9778-026a8985e282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158683223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3158683223
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.3409229921
Short name T132
Test name
Test status
Simulation time 42898787 ps
CPU time 2.28 seconds
Started Jul 14 06:53:33 PM PDT 24
Finished Jul 14 06:53:38 PM PDT 24
Peak memory 208512 kb
Host smart-1d90ef7d-8d6a-4195-a7c9-75d6213c7901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409229921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.3409229921
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.787748086
Short name T548
Test name
Test status
Simulation time 35526466 ps
CPU time 2.46 seconds
Started Jul 14 06:53:33 PM PDT 24
Finished Jul 14 06:53:39 PM PDT 24
Peak memory 207096 kb
Host smart-fa61ddea-83a1-4851-8806-16dc41f31bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787748086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.787748086
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.571831446
Short name T609
Test name
Test status
Simulation time 90309396 ps
CPU time 3.28 seconds
Started Jul 14 06:53:32 PM PDT 24
Finished Jul 14 06:53:36 PM PDT 24
Peak memory 210000 kb
Host smart-4eea5895-4696-486b-b82c-b2c35b7ba03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571831446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.571831446
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.2046245513
Short name T639
Test name
Test status
Simulation time 31040140 ps
CPU time 0.78 seconds
Started Jul 14 06:53:29 PM PDT 24
Finished Jul 14 06:53:31 PM PDT 24
Peak memory 206008 kb
Host smart-dc6eb67b-e1be-49de-a5e3-da9106cfcbcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046245513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.2046245513
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.149093968
Short name T255
Test name
Test status
Simulation time 110083694 ps
CPU time 2.16 seconds
Started Jul 14 06:53:33 PM PDT 24
Finished Jul 14 06:53:37 PM PDT 24
Peak memory 218288 kb
Host smart-b85b89d1-4f66-4a14-a5b0-523c1cb809f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149093968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.149093968
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.2697636568
Short name T867
Test name
Test status
Simulation time 156768103 ps
CPU time 3.97 seconds
Started Jul 14 06:53:29 PM PDT 24
Finished Jul 14 06:53:34 PM PDT 24
Peak memory 214060 kb
Host smart-c49e2006-a173-412d-be3b-7ad50fe96e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697636568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.2697636568
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.756158359
Short name T787
Test name
Test status
Simulation time 49516912 ps
CPU time 2.32 seconds
Started Jul 14 06:53:34 PM PDT 24
Finished Jul 14 06:53:40 PM PDT 24
Peak memory 214280 kb
Host smart-12711112-0e1c-4a4d-9b0f-62122d170c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756158359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.756158359
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.2996669173
Short name T876
Test name
Test status
Simulation time 332609908 ps
CPU time 4.21 seconds
Started Jul 14 06:53:37 PM PDT 24
Finished Jul 14 06:53:46 PM PDT 24
Peak memory 222456 kb
Host smart-c90491c2-403f-4e6c-80ae-39f4ba110311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996669173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.2996669173
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.2729494413
Short name T897
Test name
Test status
Simulation time 292889060 ps
CPU time 8.42 seconds
Started Jul 14 06:53:31 PM PDT 24
Finished Jul 14 06:53:40 PM PDT 24
Peak memory 214280 kb
Host smart-197e65f0-53d2-461d-a6ad-76e39bda5c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729494413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.2729494413
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.3033894447
Short name T785
Test name
Test status
Simulation time 87816380 ps
CPU time 3.84 seconds
Started Jul 14 06:53:31 PM PDT 24
Finished Jul 14 06:53:36 PM PDT 24
Peak memory 208704 kb
Host smart-2246b65e-878e-4743-b6c0-900d179829a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033894447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.3033894447
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.1729258882
Short name T499
Test name
Test status
Simulation time 310438156 ps
CPU time 3.79 seconds
Started Jul 14 06:53:32 PM PDT 24
Finished Jul 14 06:53:36 PM PDT 24
Peak memory 208976 kb
Host smart-54881fb2-de19-4987-bdcd-46cab407535e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729258882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.1729258882
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.355319804
Short name T763
Test name
Test status
Simulation time 622445730 ps
CPU time 4.97 seconds
Started Jul 14 06:53:28 PM PDT 24
Finished Jul 14 06:53:35 PM PDT 24
Peak memory 208016 kb
Host smart-67ee6bad-19d1-456b-b8bf-1ebf3a061078
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355319804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.355319804
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.4191375212
Short name T203
Test name
Test status
Simulation time 152708511 ps
CPU time 4.31 seconds
Started Jul 14 06:53:36 PM PDT 24
Finished Jul 14 06:53:45 PM PDT 24
Peak memory 208724 kb
Host smart-3cafb892-feac-4fce-a565-cba74c873fef
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191375212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.4191375212
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.2470343537
Short name T784
Test name
Test status
Simulation time 24944875 ps
CPU time 1.91 seconds
Started Jul 14 06:53:37 PM PDT 24
Finished Jul 14 06:53:43 PM PDT 24
Peak memory 207716 kb
Host smart-cb5229fa-9d30-4e6a-bc63-fad05caf4ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470343537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.2470343537
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.1147738844
Short name T905
Test name
Test status
Simulation time 203444994 ps
CPU time 4.48 seconds
Started Jul 14 06:53:26 PM PDT 24
Finished Jul 14 06:53:31 PM PDT 24
Peak memory 207968 kb
Host smart-2ce51e43-6a0b-4f5d-be9a-ead3cb24ab68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147738844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.1147738844
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.3405880819
Short name T336
Test name
Test status
Simulation time 966301339 ps
CPU time 10.97 seconds
Started Jul 14 06:53:35 PM PDT 24
Finished Jul 14 06:53:49 PM PDT 24
Peak memory 222372 kb
Host smart-c0cb34a6-119d-4021-b154-4dfad995d325
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405880819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.3405880819
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.1793727794
Short name T116
Test name
Test status
Simulation time 1783681682 ps
CPU time 11.49 seconds
Started Jul 14 06:53:27 PM PDT 24
Finished Jul 14 06:53:41 PM PDT 24
Peak memory 220712 kb
Host smart-558497db-886a-443a-a4a1-b0ae221853a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793727794 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.1793727794
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.1122230883
Short name T553
Test name
Test status
Simulation time 460064320 ps
CPU time 4.49 seconds
Started Jul 14 06:53:36 PM PDT 24
Finished Jul 14 06:53:45 PM PDT 24
Peak memory 207368 kb
Host smart-0209ec5d-7f7e-4aef-8f92-dcf292ad0ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122230883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.1122230883
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.67020711
Short name T711
Test name
Test status
Simulation time 108931800 ps
CPU time 3.16 seconds
Started Jul 14 06:53:37 PM PDT 24
Finished Jul 14 06:53:44 PM PDT 24
Peak memory 210372 kb
Host smart-61f03d95-91f4-457a-b723-96d015f9f338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67020711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.67020711
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.461973495
Short name T741
Test name
Test status
Simulation time 45195674 ps
CPU time 0.88 seconds
Started Jul 14 06:53:28 PM PDT 24
Finished Jul 14 06:53:31 PM PDT 24
Peak memory 205948 kb
Host smart-ce0fa538-bc97-46c5-a8db-f4c523b9edc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461973495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.461973495
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.1219788577
Short name T21
Test name
Test status
Simulation time 208943702 ps
CPU time 8.43 seconds
Started Jul 14 06:53:32 PM PDT 24
Finished Jul 14 06:53:41 PM PDT 24
Peak memory 211168 kb
Host smart-5d718a03-1bf2-4135-9255-c222c6f2e7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219788577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.1219788577
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.2920595257
Short name T500
Test name
Test status
Simulation time 401309880 ps
CPU time 8.25 seconds
Started Jul 14 06:53:37 PM PDT 24
Finished Jul 14 06:53:49 PM PDT 24
Peak memory 214320 kb
Host smart-1ec778c1-d871-4aa6-9ea0-bed475c439c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920595257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2920595257
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.3288368639
Short name T91
Test name
Test status
Simulation time 109509789 ps
CPU time 4.13 seconds
Started Jul 14 06:53:31 PM PDT 24
Finished Jul 14 06:53:36 PM PDT 24
Peak memory 214276 kb
Host smart-ae8a24ba-341c-478c-8286-12edc86f8865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288368639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.3288368639
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.2145253972
Short name T253
Test name
Test status
Simulation time 154485767 ps
CPU time 3.82 seconds
Started Jul 14 06:53:27 PM PDT 24
Finished Jul 14 06:53:32 PM PDT 24
Peak memory 209992 kb
Host smart-f41032bb-b53f-4b1f-89d7-c98ef39ba3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145253972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.2145253972
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.3212102018
Short name T911
Test name
Test status
Simulation time 140379786 ps
CPU time 3.02 seconds
Started Jul 14 06:53:32 PM PDT 24
Finished Jul 14 06:53:36 PM PDT 24
Peak memory 214324 kb
Host smart-c61b3eb6-ca49-430e-bd34-40a8eda1c079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212102018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.3212102018
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1856589736
Short name T139
Test name
Test status
Simulation time 54801758 ps
CPU time 2.87 seconds
Started Jul 14 06:53:29 PM PDT 24
Finished Jul 14 06:53:33 PM PDT 24
Peak memory 206852 kb
Host smart-757202cf-7d1a-4600-a827-a339a21d4bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856589736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1856589736
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.3862377138
Short name T807
Test name
Test status
Simulation time 151451466 ps
CPU time 2.52 seconds
Started Jul 14 06:53:29 PM PDT 24
Finished Jul 14 06:53:33 PM PDT 24
Peak memory 206920 kb
Host smart-17210541-0a33-43ad-a6e7-bef6630de97e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862377138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.3862377138
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.2383299525
Short name T586
Test name
Test status
Simulation time 136144459 ps
CPU time 2.48 seconds
Started Jul 14 06:53:25 PM PDT 24
Finished Jul 14 06:53:29 PM PDT 24
Peak memory 206980 kb
Host smart-68058bc5-a43f-4607-bbad-b3527065feda
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383299525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.2383299525
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.876181008
Short name T646
Test name
Test status
Simulation time 21847302 ps
CPU time 1.76 seconds
Started Jul 14 06:53:29 PM PDT 24
Finished Jul 14 06:53:32 PM PDT 24
Peak memory 206948 kb
Host smart-2fcdf13e-76a9-4714-924a-46f822c8e9e1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876181008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.876181008
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.1166780762
Short name T664
Test name
Test status
Simulation time 84385264 ps
CPU time 2.74 seconds
Started Jul 14 06:53:27 PM PDT 24
Finished Jul 14 06:53:32 PM PDT 24
Peak memory 209488 kb
Host smart-bd9c5c51-9292-431f-90ef-940dd9560438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166780762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1166780762
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.310591122
Short name T528
Test name
Test status
Simulation time 39644186 ps
CPU time 2.49 seconds
Started Jul 14 06:53:33 PM PDT 24
Finished Jul 14 06:53:38 PM PDT 24
Peak memory 208364 kb
Host smart-2f6fe40b-ba49-4045-80dd-50c76da9c545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310591122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.310591122
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.3279480050
Short name T840
Test name
Test status
Simulation time 219132928 ps
CPU time 4.78 seconds
Started Jul 14 06:53:33 PM PDT 24
Finished Jul 14 06:53:40 PM PDT 24
Peak memory 209580 kb
Host smart-9b2b3dc4-d6b2-4c52-86de-f6535f7a7ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279480050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.3279480050
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2862896897
Short name T746
Test name
Test status
Simulation time 446844526 ps
CPU time 2.92 seconds
Started Jul 14 06:53:38 PM PDT 24
Finished Jul 14 06:53:45 PM PDT 24
Peak memory 209872 kb
Host smart-cc58cd2a-8f72-4bba-855d-e332999ed146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862896897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2862896897
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.3838338129
Short name T669
Test name
Test status
Simulation time 41544143 ps
CPU time 0.82 seconds
Started Jul 14 06:53:33 PM PDT 24
Finished Jul 14 06:53:37 PM PDT 24
Peak memory 206012 kb
Host smart-53c538a2-3847-4bd2-88fc-382007e55924
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838338129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3838338129
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.2711996163
Short name T277
Test name
Test status
Simulation time 225761178 ps
CPU time 6.23 seconds
Started Jul 14 06:53:32 PM PDT 24
Finished Jul 14 06:53:40 PM PDT 24
Peak memory 215208 kb
Host smart-8ebcde2b-de51-4b28-b530-59cd9c256c6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2711996163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.2711996163
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.386681886
Short name T40
Test name
Test status
Simulation time 90010501 ps
CPU time 3.33 seconds
Started Jul 14 06:53:37 PM PDT 24
Finished Jul 14 06:53:45 PM PDT 24
Peak memory 209256 kb
Host smart-bfbdd3e5-6c18-47b0-bdba-4bf2341a287e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386681886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.386681886
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.1481088230
Short name T420
Test name
Test status
Simulation time 148557286 ps
CPU time 3.21 seconds
Started Jul 14 06:53:40 PM PDT 24
Finished Jul 14 06:53:47 PM PDT 24
Peak memory 218480 kb
Host smart-ba598ba0-4ad2-44e2-8d4c-163aa3470867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481088230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.1481088230
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.3587757382
Short name T874
Test name
Test status
Simulation time 118141769 ps
CPU time 2.19 seconds
Started Jul 14 06:53:42 PM PDT 24
Finished Jul 14 06:53:47 PM PDT 24
Peak memory 214344 kb
Host smart-7b3a568a-f40a-42e9-bc9b-922a524706c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587757382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.3587757382
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.2947261791
Short name T883
Test name
Test status
Simulation time 95021611 ps
CPU time 3.19 seconds
Started Jul 14 06:53:38 PM PDT 24
Finished Jul 14 06:53:45 PM PDT 24
Peak memory 214292 kb
Host smart-34b4f050-41c8-4683-af47-c8680d6277fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947261791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.2947261791
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.1933907469
Short name T556
Test name
Test status
Simulation time 723513247 ps
CPU time 4.61 seconds
Started Jul 14 06:53:46 PM PDT 24
Finished Jul 14 06:53:54 PM PDT 24
Peak memory 219060 kb
Host smart-87e35c12-287e-4ceb-994e-9a23c3e8e533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933907469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1933907469
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.3136585114
Short name T530
Test name
Test status
Simulation time 2324204466 ps
CPU time 6.68 seconds
Started Jul 14 06:53:44 PM PDT 24
Finished Jul 14 06:53:53 PM PDT 24
Peak memory 218352 kb
Host smart-cfb23689-ec6a-4ed5-b684-f312c5ecf01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136585114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.3136585114
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.2201897334
Short name T262
Test name
Test status
Simulation time 187728988 ps
CPU time 5.32 seconds
Started Jul 14 06:53:39 PM PDT 24
Finished Jul 14 06:53:48 PM PDT 24
Peak memory 208412 kb
Host smart-524ee6ec-f2ad-4180-9932-612da22413bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201897334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.2201897334
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.3927667352
Short name T495
Test name
Test status
Simulation time 4472323498 ps
CPU time 21.78 seconds
Started Jul 14 06:53:34 PM PDT 24
Finished Jul 14 06:54:00 PM PDT 24
Peak memory 208528 kb
Host smart-e29d107a-0b5d-45c1-bb41-5109b76860b7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927667352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.3927667352
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.2901621875
Short name T768
Test name
Test status
Simulation time 179067658 ps
CPU time 4.23 seconds
Started Jul 14 06:53:35 PM PDT 24
Finished Jul 14 06:53:44 PM PDT 24
Peak memory 208748 kb
Host smart-4a59b87e-3c4b-4598-bb94-629c14d7fedd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901621875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.2901621875
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.2824817700
Short name T914
Test name
Test status
Simulation time 508247265 ps
CPU time 6.99 seconds
Started Jul 14 06:53:46 PM PDT 24
Finished Jul 14 06:53:57 PM PDT 24
Peak memory 208440 kb
Host smart-8ea200fb-129f-43bd-a872-674f17c2986b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824817700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.2824817700
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.605926506
Short name T402
Test name
Test status
Simulation time 111148626 ps
CPU time 2.55 seconds
Started Jul 14 06:53:43 PM PDT 24
Finished Jul 14 06:53:49 PM PDT 24
Peak memory 215804 kb
Host smart-2c7c6c83-43b8-4467-ab3c-325caa408a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605926506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.605926506
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.734897585
Short name T450
Test name
Test status
Simulation time 368185481 ps
CPU time 3.09 seconds
Started Jul 14 06:53:28 PM PDT 24
Finished Jul 14 06:53:33 PM PDT 24
Peak memory 208564 kb
Host smart-df6856d1-08b7-45d8-adbd-32dc0f8b873c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734897585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.734897585
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.2191426213
Short name T753
Test name
Test status
Simulation time 160353140 ps
CPU time 1.02 seconds
Started Jul 14 06:53:33 PM PDT 24
Finished Jul 14 06:53:37 PM PDT 24
Peak memory 206144 kb
Host smart-99b4d538-4ff1-4998-96ee-cc03bd984e0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191426213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2191426213
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.22064623
Short name T445
Test name
Test status
Simulation time 57344558 ps
CPU time 3.39 seconds
Started Jul 14 06:53:36 PM PDT 24
Finished Jul 14 06:53:44 PM PDT 24
Peak memory 207484 kb
Host smart-529c5021-2e46-4d3c-ab72-ac620d4635a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22064623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.22064623
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.3605712573
Short name T204
Test name
Test status
Simulation time 41664188 ps
CPU time 1.89 seconds
Started Jul 14 06:53:35 PM PDT 24
Finished Jul 14 06:53:40 PM PDT 24
Peak memory 210072 kb
Host smart-9b67206d-7f1b-4c04-8f76-b3a2b91b7b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605712573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.3605712573
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.529070248
Short name T441
Test name
Test status
Simulation time 26189232 ps
CPU time 0.85 seconds
Started Jul 14 06:53:40 PM PDT 24
Finished Jul 14 06:53:44 PM PDT 24
Peak memory 205948 kb
Host smart-dd3c35b8-c99b-431c-a1b3-2f856d730f8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529070248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.529070248
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.894426613
Short name T148
Test name
Test status
Simulation time 176170420 ps
CPU time 3.5 seconds
Started Jul 14 06:53:36 PM PDT 24
Finished Jul 14 06:53:44 PM PDT 24
Peak memory 214324 kb
Host smart-0b25c895-bb8a-4830-87f6-fd35a76723d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=894426613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.894426613
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.3270913617
Short name T225
Test name
Test status
Simulation time 5126973554 ps
CPU time 23.26 seconds
Started Jul 14 06:53:39 PM PDT 24
Finished Jul 14 06:54:06 PM PDT 24
Peak memory 215540 kb
Host smart-b9a12205-181b-4075-a66e-0f6b1038847f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270913617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.3270913617
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.1404074424
Short name T683
Test name
Test status
Simulation time 31231434 ps
CPU time 2.1 seconds
Started Jul 14 06:53:40 PM PDT 24
Finished Jul 14 06:53:45 PM PDT 24
Peak memory 208168 kb
Host smart-7361a3d9-52ad-4709-8922-c35dee4c757b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404074424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.1404074424
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.1469833901
Short name T880
Test name
Test status
Simulation time 99624915 ps
CPU time 4.37 seconds
Started Jul 14 06:53:35 PM PDT 24
Finished Jul 14 06:53:44 PM PDT 24
Peak memory 214736 kb
Host smart-10b52e85-b6b9-4e9c-b7b1-e9018990263e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469833901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.1469833901
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.49289148
Short name T570
Test name
Test status
Simulation time 1143872319 ps
CPU time 5.69 seconds
Started Jul 14 06:53:34 PM PDT 24
Finished Jul 14 06:53:44 PM PDT 24
Peak memory 214804 kb
Host smart-9690604d-ab03-48e2-a3c6-5ce374b4bd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49289148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.49289148
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.3142403992
Short name T46
Test name
Test status
Simulation time 58074809 ps
CPU time 1.94 seconds
Started Jul 14 06:53:47 PM PDT 24
Finished Jul 14 06:53:54 PM PDT 24
Peak memory 214392 kb
Host smart-9daa745b-0fec-434b-8c78-c98a563d9027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142403992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.3142403992
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.191189332
Short name T843
Test name
Test status
Simulation time 537302113 ps
CPU time 10.57 seconds
Started Jul 14 06:53:32 PM PDT 24
Finished Jul 14 06:53:44 PM PDT 24
Peak memory 218304 kb
Host smart-ab41ab00-980a-475a-a636-3b6b55948b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191189332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.191189332
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.2834857932
Short name T854
Test name
Test status
Simulation time 185241160 ps
CPU time 5.62 seconds
Started Jul 14 06:53:45 PM PDT 24
Finished Jul 14 06:53:54 PM PDT 24
Peak memory 208460 kb
Host smart-22250d45-9c33-46c4-8332-a01b9402c25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834857932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.2834857932
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.815628176
Short name T603
Test name
Test status
Simulation time 358477137 ps
CPU time 3.11 seconds
Started Jul 14 06:53:47 PM PDT 24
Finished Jul 14 06:53:54 PM PDT 24
Peak memory 206956 kb
Host smart-aae129f8-4a2c-49f7-9157-b820f7114aae
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815628176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.815628176
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.3499766293
Short name T143
Test name
Test status
Simulation time 96647192 ps
CPU time 4.02 seconds
Started Jul 14 06:53:42 PM PDT 24
Finished Jul 14 06:53:49 PM PDT 24
Peak memory 209120 kb
Host smart-078e1eae-f39d-4c41-a425-c3331f1b2916
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499766293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.3499766293
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.2732254037
Short name T655
Test name
Test status
Simulation time 1865601626 ps
CPU time 20.99 seconds
Started Jul 14 06:53:34 PM PDT 24
Finished Jul 14 06:53:58 PM PDT 24
Peak memory 208580 kb
Host smart-9a776170-ddcb-4667-bb01-6a9ef568cdb2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732254037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.2732254037
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.106363732
Short name T337
Test name
Test status
Simulation time 58757552 ps
CPU time 2.9 seconds
Started Jul 14 06:53:35 PM PDT 24
Finished Jul 14 06:53:42 PM PDT 24
Peak memory 207568 kb
Host smart-5d2dbca6-c4f9-4b3f-ba55-3943ad718e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106363732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.106363732
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.1531732141
Short name T801
Test name
Test status
Simulation time 322886960 ps
CPU time 3.3 seconds
Started Jul 14 06:53:37 PM PDT 24
Finished Jul 14 06:53:45 PM PDT 24
Peak memory 208408 kb
Host smart-0f23793d-b18d-42c3-82e3-507634bc4f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531732141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.1531732141
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.1709744830
Short name T541
Test name
Test status
Simulation time 180236521 ps
CPU time 11.2 seconds
Started Jul 14 06:53:43 PM PDT 24
Finished Jul 14 06:53:57 PM PDT 24
Peak memory 222532 kb
Host smart-ec847205-d5d2-4a0f-84a5-b388df23da8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709744830 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.1709744830
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.2554849533
Short name T525
Test name
Test status
Simulation time 290870907 ps
CPU time 5.95 seconds
Started Jul 14 06:53:34 PM PDT 24
Finished Jul 14 06:53:43 PM PDT 24
Peak memory 209308 kb
Host smart-fd30fe4f-01cb-46ec-b14f-bb60c304090e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554849533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.2554849533
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.2425332197
Short name T60
Test name
Test status
Simulation time 503294979 ps
CPU time 3.34 seconds
Started Jul 14 06:53:38 PM PDT 24
Finished Jul 14 06:53:45 PM PDT 24
Peak memory 210252 kb
Host smart-00425aa4-3ffa-41f2-be9f-fbb40d4901fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425332197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.2425332197
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.1347036678
Short name T682
Test name
Test status
Simulation time 35990882 ps
CPU time 0.74 seconds
Started Jul 14 06:53:36 PM PDT 24
Finished Jul 14 06:53:41 PM PDT 24
Peak memory 206000 kb
Host smart-c30b6316-4eef-4aba-90e5-12dc98e796e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347036678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1347036678
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.3556844594
Short name T20
Test name
Test status
Simulation time 52048104 ps
CPU time 2.82 seconds
Started Jul 14 06:53:33 PM PDT 24
Finished Jul 14 06:53:39 PM PDT 24
Peak memory 214716 kb
Host smart-f78ca463-f058-431a-9503-e0fb1829171c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556844594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3556844594
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.326315315
Short name T725
Test name
Test status
Simulation time 28220142311 ps
CPU time 46.58 seconds
Started Jul 14 06:53:35 PM PDT 24
Finished Jul 14 06:54:26 PM PDT 24
Peak memory 208672 kb
Host smart-3c729473-d493-4703-98c3-b90159804da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326315315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.326315315
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.2229816654
Short name T732
Test name
Test status
Simulation time 33782812 ps
CPU time 2.27 seconds
Started Jul 14 06:53:42 PM PDT 24
Finished Jul 14 06:53:47 PM PDT 24
Peak memory 222400 kb
Host smart-8767fb27-ad91-4cdf-a2d1-3788373424ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229816654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.2229816654
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_random.1953896067
Short name T891
Test name
Test status
Simulation time 235715819 ps
CPU time 3.78 seconds
Started Jul 14 06:54:03 PM PDT 24
Finished Jul 14 06:54:08 PM PDT 24
Peak memory 207324 kb
Host smart-44b51ce9-32cb-4210-b792-44fe0b547236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953896067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1953896067
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.2045142997
Short name T675
Test name
Test status
Simulation time 389002363 ps
CPU time 3.63 seconds
Started Jul 14 06:53:35 PM PDT 24
Finished Jul 14 06:53:44 PM PDT 24
Peak memory 206860 kb
Host smart-5dd8d276-d925-4148-877d-3123a0b9dfd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045142997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.2045142997
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.2443114476
Short name T557
Test name
Test status
Simulation time 223333683 ps
CPU time 4.81 seconds
Started Jul 14 06:53:48 PM PDT 24
Finished Jul 14 06:53:57 PM PDT 24
Peak memory 208852 kb
Host smart-342c18ef-5685-4822-a106-13c4f4dad5db
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443114476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2443114476
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.422518790
Short name T522
Test name
Test status
Simulation time 316467919 ps
CPU time 2.72 seconds
Started Jul 14 06:53:39 PM PDT 24
Finished Jul 14 06:53:45 PM PDT 24
Peak memory 208568 kb
Host smart-a23f84a1-4873-474c-b35c-7d0326e12022
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422518790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.422518790
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.306128603
Short name T750
Test name
Test status
Simulation time 260819695 ps
CPU time 3.88 seconds
Started Jul 14 06:53:33 PM PDT 24
Finished Jul 14 06:53:40 PM PDT 24
Peak memory 207892 kb
Host smart-4dbe0183-54fd-43ab-baab-1ab3e613d7bd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306128603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.306128603
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.4130965648
Short name T287
Test name
Test status
Simulation time 72816457 ps
CPU time 3.05 seconds
Started Jul 14 06:53:38 PM PDT 24
Finished Jul 14 06:53:45 PM PDT 24
Peak memory 209416 kb
Host smart-4f03256d-7a85-4a0d-bb4a-828a0b4a7943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130965648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.4130965648
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.3490772960
Short name T825
Test name
Test status
Simulation time 5831110078 ps
CPU time 28.82 seconds
Started Jul 14 06:53:39 PM PDT 24
Finished Jul 14 06:54:11 PM PDT 24
Peak memory 207888 kb
Host smart-f51dcd1a-f3a6-4a73-bc0d-75366918a5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490772960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3490772960
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.1573499815
Short name T261
Test name
Test status
Simulation time 365500076 ps
CPU time 19.7 seconds
Started Jul 14 06:53:40 PM PDT 24
Finished Jul 14 06:54:03 PM PDT 24
Peak memory 222560 kb
Host smart-f4a45d20-e9b3-4eb8-ad61-e88c2c685ecc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573499815 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.1573499815
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.653276798
Short name T547
Test name
Test status
Simulation time 1358045995 ps
CPU time 10.87 seconds
Started Jul 14 06:53:33 PM PDT 24
Finished Jul 14 06:53:46 PM PDT 24
Peak memory 209784 kb
Host smart-01fd496f-d687-413a-a028-effb0f11ed68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653276798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.653276798
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.1316076207
Short name T906
Test name
Test status
Simulation time 132314969 ps
CPU time 2.95 seconds
Started Jul 14 06:53:38 PM PDT 24
Finished Jul 14 06:53:45 PM PDT 24
Peak memory 209944 kb
Host smart-d7ed1dc7-a62d-42e4-bf17-d85c4340553f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316076207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.1316076207
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2865921463
Short name T648
Test name
Test status
Simulation time 58343634 ps
CPU time 0.91 seconds
Started Jul 14 06:52:29 PM PDT 24
Finished Jul 14 06:52:31 PM PDT 24
Peak memory 206100 kb
Host smart-061b6ae6-6a6f-42fc-b5a6-d6048a7d5918
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865921463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2865921463
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.1995671110
Short name T37
Test name
Test status
Simulation time 856154990 ps
CPU time 14.64 seconds
Started Jul 14 06:52:30 PM PDT 24
Finished Jul 14 06:52:46 PM PDT 24
Peak memory 214316 kb
Host smart-92a2c929-ddf2-48fd-adf9-c5509057ae6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995671110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.1995671110
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.977103477
Short name T720
Test name
Test status
Simulation time 50220685 ps
CPU time 2.11 seconds
Started Jul 14 06:52:29 PM PDT 24
Finished Jul 14 06:52:32 PM PDT 24
Peak memory 214340 kb
Host smart-9e239aa7-0a45-4f0d-91a5-49598a8c415c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977103477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.977103477
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.2530156738
Short name T374
Test name
Test status
Simulation time 88443236 ps
CPU time 2.91 seconds
Started Jul 14 06:52:26 PM PDT 24
Finished Jul 14 06:52:30 PM PDT 24
Peak memory 208924 kb
Host smart-2b9aa095-7402-4f5e-971e-8c9c63c840db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530156738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2530156738
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.1507707736
Short name T461
Test name
Test status
Simulation time 1403544111 ps
CPU time 32.82 seconds
Started Jul 14 06:52:29 PM PDT 24
Finished Jul 14 06:53:03 PM PDT 24
Peak memory 209260 kb
Host smart-b791ba34-1c22-4b44-8961-307ba8f55509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507707736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.1507707736
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.232637795
Short name T43
Test name
Test status
Simulation time 1308980190 ps
CPU time 8.53 seconds
Started Jul 14 06:52:29 PM PDT 24
Finished Jul 14 06:52:39 PM PDT 24
Peak memory 229400 kb
Host smart-52b4d1c4-89d4-4684-9e82-14c354f02af9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232637795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.232637795
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.2478679063
Short name T263
Test name
Test status
Simulation time 1056351518 ps
CPU time 7.3 seconds
Started Jul 14 06:52:22 PM PDT 24
Finished Jul 14 06:52:31 PM PDT 24
Peak memory 206912 kb
Host smart-8cdc9c16-bb17-4f84-ba02-059e1ae25e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478679063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.2478679063
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.2917585286
Short name T668
Test name
Test status
Simulation time 1993374415 ps
CPU time 31.6 seconds
Started Jul 14 06:52:30 PM PDT 24
Finished Jul 14 06:53:03 PM PDT 24
Peak memory 208448 kb
Host smart-99c6aeaa-3b47-4630-979a-563669bd9a25
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917585286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.2917585286
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.2013137481
Short name T510
Test name
Test status
Simulation time 148162531 ps
CPU time 3.76 seconds
Started Jul 14 06:52:23 PM PDT 24
Finished Jul 14 06:52:29 PM PDT 24
Peak memory 208472 kb
Host smart-09021790-60c9-4eb8-b638-a5b771066939
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013137481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2013137481
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.4064029876
Short name T584
Test name
Test status
Simulation time 714344362 ps
CPU time 3.85 seconds
Started Jul 14 06:52:25 PM PDT 24
Finished Jul 14 06:52:30 PM PDT 24
Peak memory 208992 kb
Host smart-2daa4c9e-6180-4e69-bf5f-8073ba70f5df
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064029876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.4064029876
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.4087303141
Short name T105
Test name
Test status
Simulation time 74928350 ps
CPU time 2.12 seconds
Started Jul 14 06:52:30 PM PDT 24
Finished Jul 14 06:52:34 PM PDT 24
Peak memory 208640 kb
Host smart-c977f965-d8c2-4379-92b2-cd33dd3473bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087303141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.4087303141
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.4153295028
Short name T439
Test name
Test status
Simulation time 675059685 ps
CPU time 6.72 seconds
Started Jul 14 06:52:21 PM PDT 24
Finished Jul 14 06:52:29 PM PDT 24
Peak memory 208840 kb
Host smart-9ebc4fe0-b2ec-47ad-9744-cc7afe47c595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153295028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.4153295028
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.3082855939
Short name T236
Test name
Test status
Simulation time 614459788 ps
CPU time 23.97 seconds
Started Jul 14 06:52:30 PM PDT 24
Finished Jul 14 06:52:55 PM PDT 24
Peak memory 222504 kb
Host smart-67d37863-6a3f-4262-80ee-5d3cbcd4e7a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082855939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.3082855939
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.1796018336
Short name T4
Test name
Test status
Simulation time 117569331 ps
CPU time 3.42 seconds
Started Jul 14 06:52:28 PM PDT 24
Finished Jul 14 06:52:33 PM PDT 24
Peak memory 209828 kb
Host smart-c87c25b0-9968-4565-9500-85397ed003a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796018336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.1796018336
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.867208443
Short name T686
Test name
Test status
Simulation time 189889029 ps
CPU time 1.87 seconds
Started Jul 14 06:52:30 PM PDT 24
Finished Jul 14 06:52:34 PM PDT 24
Peak memory 209872 kb
Host smart-28cf57e2-b992-457f-840a-0231e578b98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867208443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.867208443
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.1914403713
Short name T476
Test name
Test status
Simulation time 59295822 ps
CPU time 0.77 seconds
Started Jul 14 06:53:47 PM PDT 24
Finished Jul 14 06:53:52 PM PDT 24
Peak memory 205988 kb
Host smart-f5d0d215-8055-49b2-9dc1-71c212c88025
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914403713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.1914403713
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.298689331
Short name T213
Test name
Test status
Simulation time 87329709 ps
CPU time 4.91 seconds
Started Jul 14 06:53:47 PM PDT 24
Finished Jul 14 06:53:57 PM PDT 24
Peak memory 215240 kb
Host smart-e992c66c-7f1c-4d5c-90a0-a452e06d07b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=298689331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.298689331
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.1462990511
Short name T23
Test name
Test status
Simulation time 1545103535 ps
CPU time 30.12 seconds
Started Jul 14 06:53:41 PM PDT 24
Finished Jul 14 06:54:14 PM PDT 24
Peak memory 210100 kb
Host smart-e4f6f1ee-44f7-4262-a8f8-e63457a62461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462990511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.1462990511
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.2414982179
Short name T55
Test name
Test status
Simulation time 154695533 ps
CPU time 3.07 seconds
Started Jul 14 06:53:43 PM PDT 24
Finished Jul 14 06:53:49 PM PDT 24
Peak memory 208700 kb
Host smart-86176a29-7bb4-488c-bab9-6c8649371d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414982179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.2414982179
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.2073409283
Short name T81
Test name
Test status
Simulation time 178907360 ps
CPU time 3.97 seconds
Started Jul 14 06:53:44 PM PDT 24
Finished Jul 14 06:53:51 PM PDT 24
Peak memory 214292 kb
Host smart-e85b7405-9a8a-42ee-9d15-73e32c2b1bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073409283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.2073409283
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.2515495002
Short name T910
Test name
Test status
Simulation time 169121935 ps
CPU time 2.03 seconds
Started Jul 14 06:53:51 PM PDT 24
Finished Jul 14 06:53:57 PM PDT 24
Peak memory 214264 kb
Host smart-f37c5ebc-831c-4b6f-baa1-78fd1c2f5e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515495002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.2515495002
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.1361598813
Short name T767
Test name
Test status
Simulation time 73560498 ps
CPU time 2.8 seconds
Started Jul 14 06:53:45 PM PDT 24
Finished Jul 14 06:53:52 PM PDT 24
Peak memory 219744 kb
Host smart-6031e04c-26fa-4a93-a83b-790a2bc37e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361598813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.1361598813
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.2765080462
Short name T726
Test name
Test status
Simulation time 57400879 ps
CPU time 3.48 seconds
Started Jul 14 06:53:45 PM PDT 24
Finished Jul 14 06:53:51 PM PDT 24
Peak memory 214336 kb
Host smart-b0bf043d-2d47-451a-bbe9-f50dfd422b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765080462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.2765080462
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.3461939653
Short name T687
Test name
Test status
Simulation time 134136935 ps
CPU time 2.4 seconds
Started Jul 14 06:53:44 PM PDT 24
Finished Jul 14 06:53:50 PM PDT 24
Peak memory 206092 kb
Host smart-b91f17d2-31b5-4199-a530-5216311fa39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461939653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.3461939653
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.3737423698
Short name T403
Test name
Test status
Simulation time 392129915 ps
CPU time 4.81 seconds
Started Jul 14 06:53:43 PM PDT 24
Finished Jul 14 06:53:51 PM PDT 24
Peak memory 206820 kb
Host smart-882805e0-01db-407f-b54a-52af52b862e1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737423698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3737423698
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.4212970860
Short name T421
Test name
Test status
Simulation time 2115553748 ps
CPU time 19.29 seconds
Started Jul 14 06:53:41 PM PDT 24
Finished Jul 14 06:54:03 PM PDT 24
Peak memory 208908 kb
Host smart-6546779b-3f75-4756-8917-84f46a9baff7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212970860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.4212970860
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2504626680
Short name T509
Test name
Test status
Simulation time 197193671 ps
CPU time 6.84 seconds
Started Jul 14 06:53:47 PM PDT 24
Finished Jul 14 06:54:03 PM PDT 24
Peak memory 208852 kb
Host smart-841510e0-7465-4097-8b91-110de8218ac3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504626680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2504626680
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.1539389313
Short name T692
Test name
Test status
Simulation time 956875266 ps
CPU time 3.39 seconds
Started Jul 14 06:53:48 PM PDT 24
Finished Jul 14 06:53:56 PM PDT 24
Peak memory 218324 kb
Host smart-5b6cfd3b-2251-4698-b8ab-54646439de6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539389313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.1539389313
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.1776589699
Short name T130
Test name
Test status
Simulation time 592681206 ps
CPU time 12.49 seconds
Started Jul 14 06:53:36 PM PDT 24
Finished Jul 14 06:53:53 PM PDT 24
Peak memory 208548 kb
Host smart-1dc6df9a-f364-4717-80a3-fab420a731f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776589699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.1776589699
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.1612850096
Short name T454
Test name
Test status
Simulation time 22401637841 ps
CPU time 79.36 seconds
Started Jul 14 06:53:41 PM PDT 24
Finished Jul 14 06:55:03 PM PDT 24
Peak memory 216620 kb
Host smart-c7288a22-8581-4e96-8630-633e74cf890a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612850096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.1612850096
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.1143501033
Short name T356
Test name
Test status
Simulation time 642203622 ps
CPU time 8.17 seconds
Started Jul 14 06:53:46 PM PDT 24
Finished Jul 14 06:53:59 PM PDT 24
Peak memory 219740 kb
Host smart-44c13102-eb6f-4053-9935-106ffaaf6d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143501033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1143501033
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.4122150490
Short name T850
Test name
Test status
Simulation time 115824812 ps
CPU time 3.48 seconds
Started Jul 14 06:53:47 PM PDT 24
Finished Jul 14 06:53:54 PM PDT 24
Peak memory 210456 kb
Host smart-97dccf6a-e1c1-47f4-a23a-6328a9ba8924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122150490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.4122150490
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.1246395547
Short name T626
Test name
Test status
Simulation time 39399905 ps
CPU time 0.84 seconds
Started Jul 14 06:53:48 PM PDT 24
Finished Jul 14 06:53:53 PM PDT 24
Peak memory 205968 kb
Host smart-2be9a559-f789-4698-bf4d-25a937e193d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246395547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.1246395547
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.2917857587
Short name T695
Test name
Test status
Simulation time 1211945686 ps
CPU time 5.25 seconds
Started Jul 14 06:53:40 PM PDT 24
Finished Jul 14 06:53:49 PM PDT 24
Peak memory 222876 kb
Host smart-e5cfe184-60ae-4035-9d5f-144db4286df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917857587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.2917857587
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.1305684181
Short name T552
Test name
Test status
Simulation time 134964524 ps
CPU time 1.92 seconds
Started Jul 14 06:53:50 PM PDT 24
Finished Jul 14 06:53:56 PM PDT 24
Peak memory 209044 kb
Host smart-adb2285c-6512-4246-b813-8aebb42a1c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305684181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.1305684181
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2166406550
Short name T89
Test name
Test status
Simulation time 725939977 ps
CPU time 7.64 seconds
Started Jul 14 06:53:47 PM PDT 24
Finished Jul 14 06:53:59 PM PDT 24
Peak memory 209380 kb
Host smart-6f58e2f8-a647-4266-a9e6-c8d98f20bb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166406550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2166406550
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.2413848903
Short name T598
Test name
Test status
Simulation time 93971091 ps
CPU time 2.6 seconds
Started Jul 14 06:53:41 PM PDT 24
Finished Jul 14 06:53:46 PM PDT 24
Peak memory 214224 kb
Host smart-dfb4d301-9ff9-4965-809a-ec87d6d23ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413848903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.2413848903
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.3678767055
Short name T855
Test name
Test status
Simulation time 196257272 ps
CPU time 4.87 seconds
Started Jul 14 06:53:51 PM PDT 24
Finished Jul 14 06:54:00 PM PDT 24
Peak memory 222508 kb
Host smart-fe7b369a-b0ed-46a5-82c5-cdf6cbde4ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678767055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.3678767055
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.3157625740
Short name T319
Test name
Test status
Simulation time 848019728 ps
CPU time 4.8 seconds
Started Jul 14 06:53:47 PM PDT 24
Finished Jul 14 06:53:55 PM PDT 24
Peak memory 210180 kb
Host smart-1b23b530-4eb3-4bd8-9399-5b4b95e24f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157625740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.3157625740
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.3072318882
Short name T358
Test name
Test status
Simulation time 103775909 ps
CPU time 3.44 seconds
Started Jul 14 06:53:42 PM PDT 24
Finished Jul 14 06:53:48 PM PDT 24
Peak memory 206888 kb
Host smart-792402dd-0b4c-46a8-af43-0f6fa73dabdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072318882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.3072318882
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.669060796
Short name T560
Test name
Test status
Simulation time 23307164 ps
CPU time 1.93 seconds
Started Jul 14 06:53:38 PM PDT 24
Finished Jul 14 06:53:44 PM PDT 24
Peak memory 208764 kb
Host smart-e4c0366d-9b61-42df-ac51-aeebd274fa75
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669060796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.669060796
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.848618299
Short name T674
Test name
Test status
Simulation time 30156329 ps
CPU time 1.84 seconds
Started Jul 14 06:53:48 PM PDT 24
Finished Jul 14 06:53:54 PM PDT 24
Peak memory 206856 kb
Host smart-6d8c096e-e3fc-4152-aad4-70b8aea5925c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848618299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.848618299
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.1027833944
Short name T888
Test name
Test status
Simulation time 139711067 ps
CPU time 3.65 seconds
Started Jul 14 06:53:48 PM PDT 24
Finished Jul 14 06:53:56 PM PDT 24
Peak memory 207012 kb
Host smart-0baf2e5c-473a-46ee-87ca-a9d680284c11
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027833944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.1027833944
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.4234237921
Short name T654
Test name
Test status
Simulation time 366242350 ps
CPU time 9.82 seconds
Started Jul 14 06:53:45 PM PDT 24
Finished Jul 14 06:53:58 PM PDT 24
Peak memory 214296 kb
Host smart-2d6a533b-690a-4fab-8234-20dae62b9817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234237921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.4234237921
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.770677079
Short name T209
Test name
Test status
Simulation time 459145317 ps
CPU time 2.53 seconds
Started Jul 14 06:53:48 PM PDT 24
Finished Jul 14 06:53:54 PM PDT 24
Peak memory 207000 kb
Host smart-ec61ffeb-3012-4896-8f59-51ee39a02912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770677079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.770677079
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.3549981164
Short name T231
Test name
Test status
Simulation time 2078039579 ps
CPU time 14.8 seconds
Started Jul 14 06:53:48 PM PDT 24
Finished Jul 14 06:54:07 PM PDT 24
Peak memory 215664 kb
Host smart-18a2b937-b241-4d7d-9e51-d64b02de6a98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549981164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.3549981164
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.4218266669
Short name T371
Test name
Test status
Simulation time 938263508 ps
CPU time 6.42 seconds
Started Jul 14 06:53:47 PM PDT 24
Finished Jul 14 06:53:57 PM PDT 24
Peak memory 207728 kb
Host smart-2db5181e-e437-421c-9fee-c6762836e865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218266669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.4218266669
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.779193894
Short name T364
Test name
Test status
Simulation time 818001296 ps
CPU time 1.87 seconds
Started Jul 14 06:53:43 PM PDT 24
Finished Jul 14 06:53:47 PM PDT 24
Peak memory 210776 kb
Host smart-c526e622-fcc4-4ce2-8498-411105287380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779193894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.779193894
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.2271905265
Short name T699
Test name
Test status
Simulation time 40364884 ps
CPU time 0.79 seconds
Started Jul 14 06:53:53 PM PDT 24
Finished Jul 14 06:53:58 PM PDT 24
Peak memory 205972 kb
Host smart-c47428e1-5432-4f84-ad85-60f0a4b6c1ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271905265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2271905265
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.1673723924
Short name T375
Test name
Test status
Simulation time 42772536 ps
CPU time 3.3 seconds
Started Jul 14 06:53:45 PM PDT 24
Finished Jul 14 06:53:52 PM PDT 24
Peak memory 214332 kb
Host smart-0cf93259-f06a-420a-b159-60024268f47d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1673723924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.1673723924
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.431071899
Short name T22
Test name
Test status
Simulation time 247688894 ps
CPU time 6.76 seconds
Started Jul 14 06:53:47 PM PDT 24
Finished Jul 14 06:53:59 PM PDT 24
Peak memory 214608 kb
Host smart-832dac22-c976-4de0-9f0e-b9313025b681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431071899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.431071899
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.3493262112
Short name T71
Test name
Test status
Simulation time 31804797 ps
CPU time 2.23 seconds
Started Jul 14 06:53:49 PM PDT 24
Finished Jul 14 06:53:55 PM PDT 24
Peak memory 208432 kb
Host smart-ab2fa257-ad78-4aaf-ad5d-9021657775a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493262112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.3493262112
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.2888678860
Short name T92
Test name
Test status
Simulation time 98291516 ps
CPU time 4.08 seconds
Started Jul 14 06:53:39 PM PDT 24
Finished Jul 14 06:53:47 PM PDT 24
Peak memory 208744 kb
Host smart-ae7415b1-7d68-4ca7-945f-05cd58a8fdc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888678860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.2888678860
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.3557644198
Short name T688
Test name
Test status
Simulation time 36656701 ps
CPU time 1.74 seconds
Started Jul 14 06:53:44 PM PDT 24
Finished Jul 14 06:53:48 PM PDT 24
Peak memory 214228 kb
Host smart-f000a6f4-0a27-4f79-9644-9deac659d9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557644198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.3557644198
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.335072272
Short name T8
Test name
Test status
Simulation time 164029074 ps
CPU time 2.24 seconds
Started Jul 14 06:53:43 PM PDT 24
Finished Jul 14 06:53:48 PM PDT 24
Peak memory 219660 kb
Host smart-03881e3b-7efc-4134-82da-dfa6c3f4447e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335072272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.335072272
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.3591572222
Short name T805
Test name
Test status
Simulation time 1783691986 ps
CPU time 47.29 seconds
Started Jul 14 06:53:42 PM PDT 24
Finished Jul 14 06:54:32 PM PDT 24
Peak memory 208600 kb
Host smart-5fda00de-1ebc-48aa-8d4c-c1c8e437dd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591572222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.3591572222
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.4212110677
Short name T423
Test name
Test status
Simulation time 166994956 ps
CPU time 2.53 seconds
Started Jul 14 06:53:43 PM PDT 24
Finished Jul 14 06:53:49 PM PDT 24
Peak memory 208340 kb
Host smart-28d59c75-3a23-4d6a-ad03-2f2a027c6b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212110677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.4212110677
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.783373768
Short name T816
Test name
Test status
Simulation time 8091583525 ps
CPU time 48.5 seconds
Started Jul 14 06:53:44 PM PDT 24
Finished Jul 14 06:54:41 PM PDT 24
Peak memory 208820 kb
Host smart-6958fd99-b898-4b3f-a4eb-0a1abf185dd9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783373768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.783373768
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.3833998863
Short name T569
Test name
Test status
Simulation time 762658720 ps
CPU time 14.79 seconds
Started Jul 14 06:53:47 PM PDT 24
Finished Jul 14 06:54:06 PM PDT 24
Peak memory 208688 kb
Host smart-554e9f15-ed0d-4020-a27f-bdc6ff1c4036
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833998863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3833998863
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.2326089623
Short name T823
Test name
Test status
Simulation time 167909260 ps
CPU time 2.76 seconds
Started Jul 14 06:53:42 PM PDT 24
Finished Jul 14 06:53:48 PM PDT 24
Peak memory 206976 kb
Host smart-2d76e10c-4934-4fe5-b1d8-5b8439d0cffb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326089623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.2326089623
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.3348524599
Short name T409
Test name
Test status
Simulation time 92837077 ps
CPU time 1.59 seconds
Started Jul 14 06:53:49 PM PDT 24
Finished Jul 14 06:53:54 PM PDT 24
Peak memory 208964 kb
Host smart-bce03ff5-005a-4b22-ba6b-dabfdd4f6f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348524599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.3348524599
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.3630296066
Short name T426
Test name
Test status
Simulation time 1174849281 ps
CPU time 5.11 seconds
Started Jul 14 06:53:47 PM PDT 24
Finished Jul 14 06:53:57 PM PDT 24
Peak memory 206788 kb
Host smart-71b50018-7f7d-4485-a2ab-85b3c86c588a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630296066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.3630296066
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.3890364304
Short name T110
Test name
Test status
Simulation time 160365863 ps
CPU time 10.62 seconds
Started Jul 14 06:53:53 PM PDT 24
Finished Jul 14 06:54:07 PM PDT 24
Peak memory 219828 kb
Host smart-1a7330d8-9c4e-4a8e-845b-0a2ed13d7453
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890364304 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.3890364304
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.1720395603
Short name T893
Test name
Test status
Simulation time 1591076981 ps
CPU time 5.74 seconds
Started Jul 14 06:53:47 PM PDT 24
Finished Jul 14 06:53:57 PM PDT 24
Peak memory 214372 kb
Host smart-c700c5f5-3947-4ea4-8501-f36e514b77f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720395603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1720395603
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.1520751035
Short name T369
Test name
Test status
Simulation time 42055551 ps
CPU time 1.4 seconds
Started Jul 14 06:53:47 PM PDT 24
Finished Jul 14 06:53:52 PM PDT 24
Peak memory 209852 kb
Host smart-50cc21d1-6d2a-4fc1-be12-5e9a1cbe6895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520751035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.1520751035
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.1203106989
Short name T429
Test name
Test status
Simulation time 58193100 ps
CPU time 0.75 seconds
Started Jul 14 06:53:52 PM PDT 24
Finished Jul 14 06:53:57 PM PDT 24
Peak memory 205896 kb
Host smart-8a24684c-4cef-4efb-ba6f-8b378b237f55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203106989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.1203106989
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.1486284137
Short name T393
Test name
Test status
Simulation time 38872087 ps
CPU time 3.22 seconds
Started Jul 14 06:53:59 PM PDT 24
Finished Jul 14 06:54:04 PM PDT 24
Peak memory 215540 kb
Host smart-32fb89df-834f-4121-bedb-61717b58c2b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1486284137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.1486284137
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.3973323909
Short name T10
Test name
Test status
Simulation time 1155043356 ps
CPU time 6.12 seconds
Started Jul 14 06:53:53 PM PDT 24
Finished Jul 14 06:54:03 PM PDT 24
Peak memory 210308 kb
Host smart-f3712762-2229-4a11-a650-3edd037fe17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973323909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.3973323909
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.1036370002
Short name T72
Test name
Test status
Simulation time 62214128 ps
CPU time 2.73 seconds
Started Jul 14 06:53:54 PM PDT 24
Finished Jul 14 06:54:01 PM PDT 24
Peak memory 209900 kb
Host smart-0540e2bc-7b50-4aa0-9cb3-6075c742ad8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036370002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.1036370002
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.1904715544
Short name T756
Test name
Test status
Simulation time 1455938455 ps
CPU time 5.86 seconds
Started Jul 14 06:53:53 PM PDT 24
Finished Jul 14 06:54:03 PM PDT 24
Peak memory 214756 kb
Host smart-fd1466f9-981c-456a-ab2e-73f2beb8e1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904715544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.1904715544
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.3494111571
Short name T754
Test name
Test status
Simulation time 1084874333 ps
CPU time 3.68 seconds
Started Jul 14 06:53:46 PM PDT 24
Finished Jul 14 06:53:54 PM PDT 24
Peak memory 207264 kb
Host smart-776de5be-66d0-4a41-a787-3d2ab5e0cea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494111571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.3494111571
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.2463488452
Short name T207
Test name
Test status
Simulation time 538349226 ps
CPU time 5.92 seconds
Started Jul 14 06:53:56 PM PDT 24
Finished Jul 14 06:54:04 PM PDT 24
Peak memory 210300 kb
Host smart-baf71c16-4dbd-4c1d-b012-41e9189b5aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463488452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.2463488452
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.2291159845
Short name T622
Test name
Test status
Simulation time 195332029 ps
CPU time 2.74 seconds
Started Jul 14 06:53:47 PM PDT 24
Finished Jul 14 06:53:53 PM PDT 24
Peak memory 206836 kb
Host smart-930ac707-44d6-446a-83f4-ee595a4afb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291159845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.2291159845
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.1504583201
Short name T773
Test name
Test status
Simulation time 32783217 ps
CPU time 2.31 seconds
Started Jul 14 06:53:47 PM PDT 24
Finished Jul 14 06:53:53 PM PDT 24
Peak memory 206980 kb
Host smart-48950bb4-4ca5-4f3e-8704-9ee7c95f8fc9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504583201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.1504583201
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.3040564740
Short name T398
Test name
Test status
Simulation time 117304908 ps
CPU time 3.05 seconds
Started Jul 14 06:53:52 PM PDT 24
Finished Jul 14 06:53:59 PM PDT 24
Peak memory 206856 kb
Host smart-960a9383-0897-470e-8258-cde20c7bff5e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040564740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.3040564740
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.4058222982
Short name T788
Test name
Test status
Simulation time 154356978 ps
CPU time 4.33 seconds
Started Jul 14 06:53:48 PM PDT 24
Finished Jul 14 06:53:57 PM PDT 24
Peak memory 208536 kb
Host smart-6ceb9c18-a8b9-401d-a23d-7fe0f8c49ecb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058222982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.4058222982
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.922413844
Short name T493
Test name
Test status
Simulation time 82242780 ps
CPU time 3.34 seconds
Started Jul 14 06:53:46 PM PDT 24
Finished Jul 14 06:53:53 PM PDT 24
Peak memory 208628 kb
Host smart-f2cddfe8-7931-4642-b946-eb5e051c35af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922413844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.922413844
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.865304265
Short name T594
Test name
Test status
Simulation time 276621528 ps
CPU time 2.82 seconds
Started Jul 14 06:53:52 PM PDT 24
Finished Jul 14 06:53:59 PM PDT 24
Peak memory 206796 kb
Host smart-c756a73f-30b5-4d63-80ad-f0ef8bf10812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865304265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.865304265
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.781594279
Short name T872
Test name
Test status
Simulation time 486466510 ps
CPU time 11.25 seconds
Started Jul 14 06:53:48 PM PDT 24
Finished Jul 14 06:54:04 PM PDT 24
Peak memory 222400 kb
Host smart-ad41f454-35c3-40f7-8e06-5382b6cc0797
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781594279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.781594279
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.1075803065
Short name T845
Test name
Test status
Simulation time 528727894 ps
CPU time 10.6 seconds
Started Jul 14 06:53:47 PM PDT 24
Finished Jul 14 06:54:02 PM PDT 24
Peak memory 222076 kb
Host smart-ee38c0fd-76f8-4765-8ac3-8e361692c1c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075803065 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.1075803065
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.2022204664
Short name T210
Test name
Test status
Simulation time 83572015 ps
CPU time 4.34 seconds
Started Jul 14 06:53:46 PM PDT 24
Finished Jul 14 06:53:54 PM PDT 24
Peak memory 209384 kb
Host smart-02624e28-5e64-47fa-9605-fbebaf756e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022204664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.2022204664
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.138534107
Short name T361
Test name
Test status
Simulation time 121132273 ps
CPU time 2.12 seconds
Started Jul 14 06:53:48 PM PDT 24
Finished Jul 14 06:53:55 PM PDT 24
Peak memory 210172 kb
Host smart-6dfba7ca-3924-4b1b-97e6-70dcb763166f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138534107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.138534107
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.1873175272
Short name T463
Test name
Test status
Simulation time 15634297 ps
CPU time 0.74 seconds
Started Jul 14 06:53:48 PM PDT 24
Finished Jul 14 06:53:53 PM PDT 24
Peak memory 205900 kb
Host smart-75a4bfef-b579-45bd-9e36-4efc1bed26a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873175272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.1873175272
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.3494838024
Short name T727
Test name
Test status
Simulation time 151288699 ps
CPU time 2.88 seconds
Started Jul 14 06:53:52 PM PDT 24
Finished Jul 14 06:54:00 PM PDT 24
Peak memory 215124 kb
Host smart-0e294c68-eba7-42c0-8905-ce347ac72208
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3494838024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3494838024
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.3647868524
Short name T34
Test name
Test status
Simulation time 184510400 ps
CPU time 3.89 seconds
Started Jul 14 06:54:01 PM PDT 24
Finished Jul 14 06:54:05 PM PDT 24
Peak memory 221908 kb
Host smart-fa3079cd-9a3a-4489-a036-248bfedfa6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647868524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.3647868524
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.2769966687
Short name T608
Test name
Test status
Simulation time 91277464 ps
CPU time 2.53 seconds
Started Jul 14 06:53:55 PM PDT 24
Finished Jul 14 06:54:01 PM PDT 24
Peak memory 206904 kb
Host smart-16ad4a05-6a57-4045-b490-c52d9c09ac4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769966687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.2769966687
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.446066579
Short name T311
Test name
Test status
Simulation time 126565867 ps
CPU time 2.88 seconds
Started Jul 14 06:54:07 PM PDT 24
Finished Jul 14 06:54:11 PM PDT 24
Peak memory 214360 kb
Host smart-7aed4f28-bc05-4d34-a902-0f2efdf44929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446066579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.446066579
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.2866902416
Short name T718
Test name
Test status
Simulation time 108772439 ps
CPU time 3.17 seconds
Started Jul 14 06:53:55 PM PDT 24
Finished Jul 14 06:54:01 PM PDT 24
Peak memory 214800 kb
Host smart-e38a26ee-81e2-4f74-8c82-a17074e29d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866902416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.2866902416
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.1570453446
Short name T595
Test name
Test status
Simulation time 1234546140 ps
CPU time 3.77 seconds
Started Jul 14 06:53:48 PM PDT 24
Finished Jul 14 06:54:01 PM PDT 24
Peak memory 222648 kb
Host smart-debf5dcb-9b65-4887-be76-6b17d7b55743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570453446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.1570453446
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.3442996762
Short name T540
Test name
Test status
Simulation time 222238071 ps
CPU time 8.13 seconds
Started Jul 14 06:53:52 PM PDT 24
Finished Jul 14 06:54:05 PM PDT 24
Peak memory 209848 kb
Host smart-b62a7c5e-a954-45b2-abc3-29bcd2772fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442996762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.3442996762
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2314018218
Short name T759
Test name
Test status
Simulation time 233658196 ps
CPU time 3.13 seconds
Started Jul 14 06:53:50 PM PDT 24
Finished Jul 14 06:53:57 PM PDT 24
Peak memory 207028 kb
Host smart-d1ea3376-b0fe-4550-ad16-52ff1b68b616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314018218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2314018218
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.143774302
Short name T769
Test name
Test status
Simulation time 145065677 ps
CPU time 2.27 seconds
Started Jul 14 06:53:47 PM PDT 24
Finished Jul 14 06:53:54 PM PDT 24
Peak memory 207120 kb
Host smart-240b4ebf-47da-4e02-96d2-01ac95c9cccd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143774302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.143774302
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.3524259190
Short name T103
Test name
Test status
Simulation time 747897061 ps
CPU time 6.12 seconds
Started Jul 14 06:53:53 PM PDT 24
Finished Jul 14 06:54:03 PM PDT 24
Peak memory 208148 kb
Host smart-00bd369f-4749-489a-8e3c-58993e04f351
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524259190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.3524259190
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.3293016219
Short name T697
Test name
Test status
Simulation time 65926035 ps
CPU time 3.27 seconds
Started Jul 14 06:53:52 PM PDT 24
Finished Jul 14 06:53:59 PM PDT 24
Peak memory 208824 kb
Host smart-79bb31b7-7395-4140-958d-ea7094755b4a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293016219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3293016219
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.3606855545
Short name T349
Test name
Test status
Simulation time 407092667 ps
CPU time 4.64 seconds
Started Jul 14 06:53:52 PM PDT 24
Finished Jul 14 06:54:01 PM PDT 24
Peak memory 214336 kb
Host smart-9776d425-747c-41b0-902f-4a73dcfb6371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606855545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.3606855545
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.1351005151
Short name T470
Test name
Test status
Simulation time 703901419 ps
CPU time 17.62 seconds
Started Jul 14 06:53:52 PM PDT 24
Finished Jul 14 06:54:14 PM PDT 24
Peak memory 207816 kb
Host smart-e5bea5d0-2c2d-42db-a1e1-bb821c43fbd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351005151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.1351005151
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.1498317144
Short name T848
Test name
Test status
Simulation time 1295767337 ps
CPU time 7.53 seconds
Started Jul 14 06:53:45 PM PDT 24
Finished Jul 14 06:53:56 PM PDT 24
Peak memory 218240 kb
Host smart-c2a7ddb5-19c3-4f78-b05e-373bc786e50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498317144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.1498317144
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.3372142880
Short name T900
Test name
Test status
Simulation time 1203777121 ps
CPU time 10.81 seconds
Started Jul 14 06:53:47 PM PDT 24
Finished Jul 14 06:54:02 PM PDT 24
Peak memory 211180 kb
Host smart-bc7200f8-cc2a-4c6b-b199-72a5ac723bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372142880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.3372142880
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.3314710584
Short name T693
Test name
Test status
Simulation time 37642654 ps
CPU time 0.7 seconds
Started Jul 14 06:53:48 PM PDT 24
Finished Jul 14 06:53:53 PM PDT 24
Peak memory 205892 kb
Host smart-d542e8e6-5661-4442-81cc-7a7427ff269f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314710584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.3314710584
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.820272146
Short name T390
Test name
Test status
Simulation time 1986136888 ps
CPU time 11.6 seconds
Started Jul 14 06:53:54 PM PDT 24
Finished Jul 14 06:54:09 PM PDT 24
Peak memory 214328 kb
Host smart-304c53eb-e4f7-45bf-9164-59dbdbe2902f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=820272146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.820272146
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.677177244
Short name T719
Test name
Test status
Simulation time 272323422 ps
CPU time 2.95 seconds
Started Jul 14 06:54:08 PM PDT 24
Finished Jul 14 06:54:13 PM PDT 24
Peak memory 208836 kb
Host smart-3cf4d346-0f29-437d-b24f-5b59b33be925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677177244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.677177244
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.2139719743
Short name T561
Test name
Test status
Simulation time 185911063 ps
CPU time 2.34 seconds
Started Jul 14 06:53:47 PM PDT 24
Finished Jul 14 06:53:54 PM PDT 24
Peak memory 209648 kb
Host smart-4dc6503d-38aa-43d3-9df8-78d2f994d9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139719743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.2139719743
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.2299671784
Short name T27
Test name
Test status
Simulation time 81339660 ps
CPU time 3.53 seconds
Started Jul 14 06:53:52 PM PDT 24
Finished Jul 14 06:54:00 PM PDT 24
Peak memory 209004 kb
Host smart-f1a46fd0-2278-4fc5-96a4-4f670c0e1555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299671784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.2299671784
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.3534485926
Short name T292
Test name
Test status
Simulation time 38249695 ps
CPU time 2.68 seconds
Started Jul 14 06:53:52 PM PDT 24
Finished Jul 14 06:54:02 PM PDT 24
Peak memory 214296 kb
Host smart-631b77f2-e3a1-4fe7-ac62-2d04bbef0ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534485926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.3534485926
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.3874728248
Short name T48
Test name
Test status
Simulation time 147827665 ps
CPU time 4.02 seconds
Started Jul 14 06:53:51 PM PDT 24
Finished Jul 14 06:54:00 PM PDT 24
Peak memory 219960 kb
Host smart-08da2546-23f3-4921-b658-b282b1af5b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874728248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.3874728248
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.3306572083
Short name T141
Test name
Test status
Simulation time 955645158 ps
CPU time 22.87 seconds
Started Jul 14 06:53:52 PM PDT 24
Finished Jul 14 06:54:19 PM PDT 24
Peak memory 214328 kb
Host smart-82776e19-3dea-4104-b27b-161d27eccc85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306572083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.3306572083
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.2614479403
Short name T128
Test name
Test status
Simulation time 61018961 ps
CPU time 2.76 seconds
Started Jul 14 06:53:47 PM PDT 24
Finished Jul 14 06:53:54 PM PDT 24
Peak memory 206940 kb
Host smart-a5f88edf-7399-4b2d-8d93-2d5ecd1e5495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614479403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2614479403
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.2683468241
Short name T323
Test name
Test status
Simulation time 11040839124 ps
CPU time 21.89 seconds
Started Jul 14 06:53:51 PM PDT 24
Finished Jul 14 06:54:17 PM PDT 24
Peak memory 208904 kb
Host smart-0b0f3080-3740-48df-a83a-903ba3cd390a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683468241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.2683468241
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.637117072
Short name T430
Test name
Test status
Simulation time 315902491 ps
CPU time 3.09 seconds
Started Jul 14 06:53:52 PM PDT 24
Finished Jul 14 06:54:00 PM PDT 24
Peak memory 206928 kb
Host smart-b2712806-f5c0-4a9c-8aef-2cda8386c343
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637117072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.637117072
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.2888756618
Short name T710
Test name
Test status
Simulation time 890348082 ps
CPU time 18.26 seconds
Started Jul 14 06:53:48 PM PDT 24
Finished Jul 14 06:54:16 PM PDT 24
Peak memory 208372 kb
Host smart-86f6b412-729e-460a-a45c-c6628a3a6ffc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888756618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.2888756618
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.2777986629
Short name T296
Test name
Test status
Simulation time 30996641 ps
CPU time 1.52 seconds
Started Jul 14 06:53:47 PM PDT 24
Finished Jul 14 06:53:52 PM PDT 24
Peak memory 207620 kb
Host smart-b66fe837-0974-488a-a3f9-ec9255967690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777986629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.2777986629
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.1063642078
Short name T868
Test name
Test status
Simulation time 2659585657 ps
CPU time 23.69 seconds
Started Jul 14 06:53:49 PM PDT 24
Finished Jul 14 06:54:16 PM PDT 24
Peak memory 207920 kb
Host smart-8d603c8b-b777-4ee8-93eb-3d5d67501c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063642078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1063642078
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.1185224109
Short name T666
Test name
Test status
Simulation time 676635118 ps
CPU time 9.51 seconds
Started Jul 14 06:53:54 PM PDT 24
Finished Jul 14 06:54:07 PM PDT 24
Peak memory 216432 kb
Host smart-b1f9712f-b3ea-48b3-9ab9-59b8a83cd8c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185224109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.1185224109
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.412065084
Short name T233
Test name
Test status
Simulation time 593340785 ps
CPU time 10.38 seconds
Started Jul 14 06:53:53 PM PDT 24
Finished Jul 14 06:54:08 PM PDT 24
Peak memory 222280 kb
Host smart-540b309d-8581-43af-bcc3-2fe4423ba9cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412065084 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.412065084
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.964122410
Short name T496
Test name
Test status
Simulation time 130905460 ps
CPU time 3.76 seconds
Started Jul 14 06:53:52 PM PDT 24
Finished Jul 14 06:54:00 PM PDT 24
Peak memory 214308 kb
Host smart-016682ff-e02a-4a6e-a905-691312c9d1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964122410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.964122410
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.193870307
Short name T57
Test name
Test status
Simulation time 150787578 ps
CPU time 3.21 seconds
Started Jul 14 06:53:45 PM PDT 24
Finished Jul 14 06:53:51 PM PDT 24
Peak memory 210512 kb
Host smart-7080470f-1a33-4de4-80d6-4a6317f359c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193870307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.193870307
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3185697423
Short name T575
Test name
Test status
Simulation time 35362435 ps
CPU time 0.73 seconds
Started Jul 14 06:53:55 PM PDT 24
Finished Jul 14 06:53:59 PM PDT 24
Peak memory 205964 kb
Host smart-764ea664-4c36-4544-9479-dc847224cd19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185697423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3185697423
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.4121091589
Short name T413
Test name
Test status
Simulation time 48012334 ps
CPU time 1.94 seconds
Started Jul 14 06:53:48 PM PDT 24
Finished Jul 14 06:53:54 PM PDT 24
Peak memory 207836 kb
Host smart-29f8002d-7899-4147-9271-6b39413eb3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121091589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.4121091589
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.761655173
Short name T777
Test name
Test status
Simulation time 181182643 ps
CPU time 3.26 seconds
Started Jul 14 06:54:00 PM PDT 24
Finished Jul 14 06:54:04 PM PDT 24
Peak memory 218536 kb
Host smart-38f5ba70-0abb-4a74-8c60-f309410bba5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761655173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.761655173
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.923102515
Short name T656
Test name
Test status
Simulation time 421537448 ps
CPU time 5.17 seconds
Started Jul 14 06:53:58 PM PDT 24
Finished Jul 14 06:54:04 PM PDT 24
Peak memory 209204 kb
Host smart-6775ad35-f9c6-4759-851c-fbba81962cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923102515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.923102515
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.2753308217
Short name T696
Test name
Test status
Simulation time 782880091 ps
CPU time 26.93 seconds
Started Jul 14 06:53:54 PM PDT 24
Finished Jul 14 06:54:25 PM PDT 24
Peak memory 208784 kb
Host smart-3f2d6f2f-4769-43f1-845f-f91acf2d37b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753308217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.2753308217
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.4113732712
Short name T355
Test name
Test status
Simulation time 149145310 ps
CPU time 3.74 seconds
Started Jul 14 06:53:57 PM PDT 24
Finished Jul 14 06:54:03 PM PDT 24
Peak memory 208644 kb
Host smart-b0a284b4-ddb9-4c8b-b075-272124eab52d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113732712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.4113732712
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.833280216
Short name T554
Test name
Test status
Simulation time 173962394 ps
CPU time 2.69 seconds
Started Jul 14 06:53:58 PM PDT 24
Finished Jul 14 06:54:02 PM PDT 24
Peak memory 207052 kb
Host smart-a0ce0716-9037-43b9-88c6-36a346bbebc7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833280216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.833280216
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.1099867147
Short name T599
Test name
Test status
Simulation time 288603861 ps
CPU time 3.02 seconds
Started Jul 14 06:53:55 PM PDT 24
Finished Jul 14 06:54:01 PM PDT 24
Peak memory 208908 kb
Host smart-f5f7cf8f-ba57-40e3-a35b-677b39ec4631
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099867147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.1099867147
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.2346341608
Short name T498
Test name
Test status
Simulation time 95578654 ps
CPU time 2.53 seconds
Started Jul 14 06:54:05 PM PDT 24
Finished Jul 14 06:54:09 PM PDT 24
Peak memory 210152 kb
Host smart-b782c652-14e9-4e3e-be55-17b5042b7ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346341608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.2346341608
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.2419335772
Short name T515
Test name
Test status
Simulation time 31749464 ps
CPU time 2.02 seconds
Started Jul 14 06:53:54 PM PDT 24
Finished Jul 14 06:54:00 PM PDT 24
Peak memory 208484 kb
Host smart-4f6f8861-4288-4afa-9fa9-603c933c7930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419335772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.2419335772
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.79408180
Short name T912
Test name
Test status
Simulation time 838211333 ps
CPU time 9.87 seconds
Started Jul 14 06:54:04 PM PDT 24
Finished Jul 14 06:54:14 PM PDT 24
Peak memory 208812 kb
Host smart-6a434af8-86c8-4a43-8090-47470cf77ab1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79408180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.79408180
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.2254016978
Short name T208
Test name
Test status
Simulation time 11438962393 ps
CPU time 67.56 seconds
Started Jul 14 06:53:45 PM PDT 24
Finished Jul 14 06:54:56 PM PDT 24
Peak memory 214376 kb
Host smart-c327d7ac-dd76-49b2-81e2-307f21ee6096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254016978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.2254016978
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.26208899
Short name T521
Test name
Test status
Simulation time 358206496 ps
CPU time 2.49 seconds
Started Jul 14 06:54:12 PM PDT 24
Finished Jul 14 06:54:17 PM PDT 24
Peak memory 210768 kb
Host smart-42613536-f26d-4d30-82f9-290f3f607b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26208899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.26208899
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.1403457678
Short name T551
Test name
Test status
Simulation time 52678335 ps
CPU time 0.77 seconds
Started Jul 14 06:54:06 PM PDT 24
Finished Jul 14 06:54:08 PM PDT 24
Peak memory 205976 kb
Host smart-f79181eb-2258-4d3c-9b6b-7a2fa0bed1d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403457678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.1403457678
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.3254898551
Short name T739
Test name
Test status
Simulation time 90249031 ps
CPU time 2.03 seconds
Started Jul 14 06:54:08 PM PDT 24
Finished Jul 14 06:54:11 PM PDT 24
Peak memory 206156 kb
Host smart-030f47cf-273c-4b02-aad8-392580e1e2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254898551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.3254898551
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.1444410947
Short name T712
Test name
Test status
Simulation time 415969231 ps
CPU time 2.11 seconds
Started Jul 14 06:54:06 PM PDT 24
Finished Jul 14 06:54:10 PM PDT 24
Peak memory 207576 kb
Host smart-1588fce0-869e-45e1-9bf0-f130cfd86e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444410947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1444410947
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.2055611977
Short name T318
Test name
Test status
Simulation time 50646915 ps
CPU time 2.91 seconds
Started Jul 14 06:53:54 PM PDT 24
Finished Jul 14 06:54:00 PM PDT 24
Peak memory 208824 kb
Host smart-6ffe4603-cf95-4e96-b594-6b161c016c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055611977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.2055611977
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.1111635052
Short name T506
Test name
Test status
Simulation time 191762800 ps
CPU time 3.15 seconds
Started Jul 14 06:54:06 PM PDT 24
Finished Jul 14 06:54:11 PM PDT 24
Peak memory 214336 kb
Host smart-33e8393f-c84c-448d-bb95-59c9c0e61c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111635052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.1111635052
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.1410089193
Short name T889
Test name
Test status
Simulation time 268204104 ps
CPU time 5.75 seconds
Started Jul 14 06:53:59 PM PDT 24
Finished Jul 14 06:54:05 PM PDT 24
Peak memory 209464 kb
Host smart-73521ad0-85d8-4ee9-8f5a-a76d54f9a936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410089193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1410089193
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.1026722560
Short name T274
Test name
Test status
Simulation time 133286490 ps
CPU time 2.53 seconds
Started Jul 14 06:54:09 PM PDT 24
Finished Jul 14 06:54:13 PM PDT 24
Peak memory 208752 kb
Host smart-9cf67ad0-df85-4dc3-98ad-8df5ca910b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026722560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.1026722560
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.921958447
Short name T537
Test name
Test status
Simulation time 6941566553 ps
CPU time 27.03 seconds
Started Jul 14 06:54:03 PM PDT 24
Finished Jul 14 06:54:31 PM PDT 24
Peak memory 208304 kb
Host smart-ed9bc2f8-67f4-4532-879d-9ffe3d6e03a9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921958447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.921958447
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.992851930
Short name T676
Test name
Test status
Simulation time 153169632 ps
CPU time 3.03 seconds
Started Jul 14 06:54:09 PM PDT 24
Finished Jul 14 06:54:13 PM PDT 24
Peak memory 206828 kb
Host smart-8adc1ede-54f0-4c85-b6f1-d485f64ca714
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992851930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.992851930
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.4224893002
Short name T592
Test name
Test status
Simulation time 33202921 ps
CPU time 2.3 seconds
Started Jul 14 06:54:11 PM PDT 24
Finished Jul 14 06:54:16 PM PDT 24
Peak memory 207108 kb
Host smart-d91a75e8-1e34-4c30-b929-0ca602136162
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224893002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.4224893002
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.371110922
Short name T774
Test name
Test status
Simulation time 258802807 ps
CPU time 3.54 seconds
Started Jul 14 06:54:06 PM PDT 24
Finished Jul 14 06:54:10 PM PDT 24
Peak memory 214384 kb
Host smart-8007427b-f8e9-4466-ad1b-53268862744b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371110922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.371110922
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.3388730200
Short name T877
Test name
Test status
Simulation time 463966882 ps
CPU time 2.61 seconds
Started Jul 14 06:54:13 PM PDT 24
Finished Jul 14 06:54:18 PM PDT 24
Peak memory 208464 kb
Host smart-795d395f-c99f-42b8-9d29-0140f78af6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388730200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.3388730200
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.2251202421
Short name T734
Test name
Test status
Simulation time 583852253 ps
CPU time 4.11 seconds
Started Jul 14 06:53:59 PM PDT 24
Finished Jul 14 06:54:04 PM PDT 24
Peak memory 207508 kb
Host smart-9504a67b-dabf-435a-bfa7-0535ecd0cdde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251202421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.2251202421
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.666120056
Short name T892
Test name
Test status
Simulation time 622421129 ps
CPU time 3.77 seconds
Started Jul 14 06:53:53 PM PDT 24
Finished Jul 14 06:54:01 PM PDT 24
Peak memory 210416 kb
Host smart-da695bde-015d-4512-b7ae-4c62398bdb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666120056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.666120056
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.2753073092
Short name T751
Test name
Test status
Simulation time 35029710 ps
CPU time 0.72 seconds
Started Jul 14 06:54:12 PM PDT 24
Finished Jul 14 06:54:16 PM PDT 24
Peak memory 205872 kb
Host smart-70dcaf17-b512-4c39-a767-b7880dac0180
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753073092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.2753073092
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.1260929608
Short name T387
Test name
Test status
Simulation time 36911571 ps
CPU time 2.7 seconds
Started Jul 14 06:54:09 PM PDT 24
Finished Jul 14 06:54:13 PM PDT 24
Peak memory 214328 kb
Host smart-16e3738e-c191-4e01-acae-8ab07cd1e6e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1260929608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.1260929608
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.2203557625
Short name T672
Test name
Test status
Simulation time 118102584 ps
CPU time 2.75 seconds
Started Jul 14 06:54:20 PM PDT 24
Finished Jul 14 06:54:26 PM PDT 24
Peak memory 207376 kb
Host smart-2485bc98-93e2-4852-9ea3-38621741e684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203557625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.2203557625
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.2882670892
Short name T308
Test name
Test status
Simulation time 122125644 ps
CPU time 2.86 seconds
Started Jul 14 06:54:11 PM PDT 24
Finished Jul 14 06:54:16 PM PDT 24
Peak memory 214308 kb
Host smart-a3636be8-c56a-4efa-8956-77d5a2eac757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882670892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.2882670892
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.4171560487
Short name T329
Test name
Test status
Simulation time 77014100 ps
CPU time 2.81 seconds
Started Jul 14 06:54:08 PM PDT 24
Finished Jul 14 06:54:12 PM PDT 24
Peak memory 214340 kb
Host smart-20e837d5-18b2-4386-8c9b-0967e87f8496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171560487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.4171560487
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.820141357
Short name T819
Test name
Test status
Simulation time 34026947 ps
CPU time 2.23 seconds
Started Jul 14 06:54:20 PM PDT 24
Finished Jul 14 06:54:26 PM PDT 24
Peak memory 215388 kb
Host smart-cec4ba11-8da6-4e25-a0a7-dbe71bd13c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820141357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.820141357
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.1624691143
Short name T620
Test name
Test status
Simulation time 543546451 ps
CPU time 7.13 seconds
Started Jul 14 06:54:07 PM PDT 24
Finished Jul 14 06:54:16 PM PDT 24
Peak memory 214296 kb
Host smart-9d2d13af-bf71-4999-9eb4-544eead868ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624691143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.1624691143
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.2581795393
Short name T714
Test name
Test status
Simulation time 247705981 ps
CPU time 2.85 seconds
Started Jul 14 06:54:06 PM PDT 24
Finished Jul 14 06:54:10 PM PDT 24
Peak memory 206820 kb
Host smart-3763d857-0ecf-4c61-a3a3-bb02599f9fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581795393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.2581795393
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.502891154
Short name T737
Test name
Test status
Simulation time 614488785 ps
CPU time 4.96 seconds
Started Jul 14 06:53:53 PM PDT 24
Finished Jul 14 06:54:02 PM PDT 24
Peak memory 207880 kb
Host smart-54d3f93d-e72d-4394-8420-ef32b4638ede
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502891154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.502891154
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.1637875377
Short name T706
Test name
Test status
Simulation time 160019871 ps
CPU time 2.61 seconds
Started Jul 14 06:53:51 PM PDT 24
Finished Jul 14 06:53:59 PM PDT 24
Peak memory 207012 kb
Host smart-016b8fe1-771a-42fb-9842-55bc9bd3c4fe
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637875377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.1637875377
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.1935897379
Short name T833
Test name
Test status
Simulation time 392401081 ps
CPU time 14.33 seconds
Started Jul 14 06:53:55 PM PDT 24
Finished Jul 14 06:54:12 PM PDT 24
Peak memory 208084 kb
Host smart-573b812e-ca13-4b5c-8557-09f1d4be632d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935897379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.1935897379
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.1632738491
Short name T257
Test name
Test status
Simulation time 92572393 ps
CPU time 4.24 seconds
Started Jul 14 06:54:10 PM PDT 24
Finished Jul 14 06:54:16 PM PDT 24
Peak memory 218224 kb
Host smart-97f384f6-0637-4359-8b2b-5cfba020677e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632738491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.1632738491
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.2851740217
Short name T399
Test name
Test status
Simulation time 249325909 ps
CPU time 2.92 seconds
Started Jul 14 06:54:09 PM PDT 24
Finished Jul 14 06:54:14 PM PDT 24
Peak memory 208516 kb
Host smart-3f01ae7b-a4be-47b8-b44e-3edef1b28ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851740217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.2851740217
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.3264915609
Short name T28
Test name
Test status
Simulation time 125272543 ps
CPU time 4.5 seconds
Started Jul 14 06:54:09 PM PDT 24
Finished Jul 14 06:54:15 PM PDT 24
Peak memory 209000 kb
Host smart-a674c928-55b7-46b8-9111-a9ea8a795fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264915609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.3264915609
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.399387396
Short name T536
Test name
Test status
Simulation time 340346064 ps
CPU time 3.63 seconds
Started Jul 14 06:54:04 PM PDT 24
Finished Jul 14 06:54:09 PM PDT 24
Peak memory 210404 kb
Host smart-05917105-8559-47d4-99f8-ece2da78158e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399387396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.399387396
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.3778858893
Short name T818
Test name
Test status
Simulation time 36415134 ps
CPU time 0.93 seconds
Started Jul 14 06:54:09 PM PDT 24
Finished Jul 14 06:54:12 PM PDT 24
Peak memory 205980 kb
Host smart-6f3d4471-7bf7-4c52-843c-756a3236106b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778858893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.3778858893
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.4084098440
Short name T146
Test name
Test status
Simulation time 125774548 ps
CPU time 2.47 seconds
Started Jul 14 06:54:07 PM PDT 24
Finished Jul 14 06:54:11 PM PDT 24
Peak memory 214304 kb
Host smart-9bdeddeb-bc37-477a-995c-8c86c076e81f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4084098440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.4084098440
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.4206674363
Short name T65
Test name
Test status
Simulation time 318236604 ps
CPU time 2.95 seconds
Started Jul 14 06:54:16 PM PDT 24
Finished Jul 14 06:54:22 PM PDT 24
Peak memory 221528 kb
Host smart-8ac2685d-a743-4cb1-8b99-0132232d9549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206674363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.4206674363
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.1891559176
Short name T838
Test name
Test status
Simulation time 354696879 ps
CPU time 3.19 seconds
Started Jul 14 06:54:11 PM PDT 24
Finished Jul 14 06:54:17 PM PDT 24
Peak memory 210100 kb
Host smart-2c07e3b7-06b2-4fbc-9340-036b0ff78fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891559176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.1891559176
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.2885974266
Short name T447
Test name
Test status
Simulation time 59189792 ps
CPU time 2.9 seconds
Started Jul 14 06:54:06 PM PDT 24
Finished Jul 14 06:54:10 PM PDT 24
Peak memory 214364 kb
Host smart-6ad559a9-ae78-41bc-ab9c-3350e6c54f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885974266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2885974266
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.3497092277
Short name T790
Test name
Test status
Simulation time 362605995 ps
CPU time 2.76 seconds
Started Jul 14 06:54:07 PM PDT 24
Finished Jul 14 06:54:12 PM PDT 24
Peak memory 209816 kb
Host smart-20bdaf44-0c60-41f7-9cc3-8109a9e69a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497092277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.3497092277
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.243764429
Short name T617
Test name
Test status
Simulation time 234306507 ps
CPU time 8.47 seconds
Started Jul 14 06:54:05 PM PDT 24
Finished Jul 14 06:54:15 PM PDT 24
Peak memory 214316 kb
Host smart-e4af971d-3253-47de-9060-54f5b0ec81c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243764429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.243764429
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.1672132660
Short name T518
Test name
Test status
Simulation time 541986789 ps
CPU time 3.45 seconds
Started Jul 14 06:54:08 PM PDT 24
Finished Jul 14 06:54:13 PM PDT 24
Peak memory 208612 kb
Host smart-01d3888e-c556-4024-a166-82d4411be464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672132660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.1672132660
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.1838010692
Short name T533
Test name
Test status
Simulation time 372435895 ps
CPU time 4.19 seconds
Started Jul 14 06:54:10 PM PDT 24
Finished Jul 14 06:54:16 PM PDT 24
Peak memory 208956 kb
Host smart-354636a2-082a-41cb-89e6-754a3ee8bb07
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838010692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.1838010692
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.2996347643
Short name T264
Test name
Test status
Simulation time 156468366 ps
CPU time 2.9 seconds
Started Jul 14 06:54:17 PM PDT 24
Finished Jul 14 06:54:24 PM PDT 24
Peak memory 206940 kb
Host smart-a7d23f63-2e47-4172-a41d-6cf847783be6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996347643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2996347643
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.3532541934
Short name T904
Test name
Test status
Simulation time 89970601 ps
CPU time 3.98 seconds
Started Jul 14 06:54:12 PM PDT 24
Finished Jul 14 06:54:19 PM PDT 24
Peak memory 208860 kb
Host smart-338d0704-662c-4aee-94e3-8dd074ab7448
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532541934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.3532541934
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.3953725762
Short name T762
Test name
Test status
Simulation time 611268268 ps
CPU time 14.12 seconds
Started Jul 14 06:54:11 PM PDT 24
Finished Jul 14 06:54:28 PM PDT 24
Peak memory 208040 kb
Host smart-ee406d53-56a8-4f6b-8749-163f3bf8d8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953725762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.3953725762
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.4278371749
Short name T559
Test name
Test status
Simulation time 1654755845 ps
CPU time 10.61 seconds
Started Jul 14 06:54:06 PM PDT 24
Finished Jul 14 06:54:19 PM PDT 24
Peak memory 208108 kb
Host smart-f8e90fb6-fe5e-4124-92d0-426595d27df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278371749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.4278371749
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.3332783652
Short name T907
Test name
Test status
Simulation time 2023098019 ps
CPU time 19.99 seconds
Started Jul 14 06:54:24 PM PDT 24
Finished Jul 14 06:54:46 PM PDT 24
Peak memory 222616 kb
Host smart-47c416ed-8c0e-4c59-a333-d08b1824dd59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332783652 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.3332783652
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.297727314
Short name T631
Test name
Test status
Simulation time 1389220179 ps
CPU time 7.03 seconds
Started Jul 14 06:54:25 PM PDT 24
Finished Jul 14 06:54:33 PM PDT 24
Peak memory 208008 kb
Host smart-0e5db007-caa9-44dc-b118-1422a97dd048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297727314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.297727314
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.842634056
Short name T604
Test name
Test status
Simulation time 165374581 ps
CPU time 2.55 seconds
Started Jul 14 06:54:16 PM PDT 24
Finished Jul 14 06:54:21 PM PDT 24
Peak memory 210644 kb
Host smart-3dc30999-a7ea-4bab-8a4c-778e5aeae465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842634056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.842634056
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.1904675112
Short name T637
Test name
Test status
Simulation time 63255463 ps
CPU time 0.87 seconds
Started Jul 14 06:52:34 PM PDT 24
Finished Jul 14 06:52:37 PM PDT 24
Peak memory 205936 kb
Host smart-9f15cb90-4bcd-4156-bb79-67ead7d2c7c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904675112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1904675112
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.2257015269
Short name T778
Test name
Test status
Simulation time 32139255 ps
CPU time 2.42 seconds
Started Jul 14 06:52:28 PM PDT 24
Finished Jul 14 06:52:32 PM PDT 24
Peak memory 214348 kb
Host smart-219882a8-61c9-450e-ad96-a3ed6755c9de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2257015269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.2257015269
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.3601081936
Short name T568
Test name
Test status
Simulation time 65729272 ps
CPU time 1.74 seconds
Started Jul 14 06:52:29 PM PDT 24
Finished Jul 14 06:52:32 PM PDT 24
Peak memory 208196 kb
Host smart-9ffc5f47-1dac-49a5-8c64-ab998ba88478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601081936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.3601081936
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.3120639062
Short name T486
Test name
Test status
Simulation time 275847563 ps
CPU time 3.2 seconds
Started Jul 14 06:52:31 PM PDT 24
Finished Jul 14 06:52:36 PM PDT 24
Peak memory 214304 kb
Host smart-9028152b-78aa-4e9c-9e58-79f3fe7f8d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120639062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.3120639062
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.3806627063
Short name T52
Test name
Test status
Simulation time 211818889 ps
CPU time 4.38 seconds
Started Jul 14 06:52:28 PM PDT 24
Finished Jul 14 06:52:33 PM PDT 24
Peak memory 214400 kb
Host smart-cd891f3d-ccaa-40bd-9399-9d9856372ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806627063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.3806627063
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.674939095
Short name T230
Test name
Test status
Simulation time 56141526 ps
CPU time 2.55 seconds
Started Jul 14 06:52:31 PM PDT 24
Finished Jul 14 06:52:35 PM PDT 24
Peak memory 208468 kb
Host smart-6e580156-4278-4397-ba0b-bc982e93dc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674939095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.674939095
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.2295574624
Short name T834
Test name
Test status
Simulation time 342079569 ps
CPU time 4.62 seconds
Started Jul 14 06:52:28 PM PDT 24
Finished Jul 14 06:52:34 PM PDT 24
Peak memory 207400 kb
Host smart-7770b1fb-23aa-4466-aeee-286d23ee4baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295574624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2295574624
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.2177126327
Short name T12
Test name
Test status
Simulation time 719745374 ps
CPU time 5.2 seconds
Started Jul 14 06:52:28 PM PDT 24
Finished Jul 14 06:52:34 PM PDT 24
Peak memory 237276 kb
Host smart-5ea23b41-9fad-425c-8559-18531e30f72d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177126327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.2177126327
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.1508291462
Short name T316
Test name
Test status
Simulation time 264650933 ps
CPU time 3.68 seconds
Started Jul 14 06:52:25 PM PDT 24
Finished Jul 14 06:52:30 PM PDT 24
Peak memory 208616 kb
Host smart-236391e5-4724-4c7d-9bdd-46a264a3c145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508291462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1508291462
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.3280316480
Short name T744
Test name
Test status
Simulation time 892016334 ps
CPU time 6.47 seconds
Started Jul 14 06:52:29 PM PDT 24
Finished Jul 14 06:52:36 PM PDT 24
Peak memory 207972 kb
Host smart-d4323c2d-737d-45f8-9aa7-bfe574b8eeb1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280316480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.3280316480
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.2459282715
Short name T761
Test name
Test status
Simulation time 133099940 ps
CPU time 2.67 seconds
Started Jul 14 06:52:29 PM PDT 24
Finished Jul 14 06:52:33 PM PDT 24
Peak memory 208828 kb
Host smart-e6ff009f-4dd5-4852-8137-9f63a3179641
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459282715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.2459282715
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.2246311288
Short name T320
Test name
Test status
Simulation time 1792225488 ps
CPU time 10.17 seconds
Started Jul 14 06:52:27 PM PDT 24
Finished Jul 14 06:52:38 PM PDT 24
Peak memory 209108 kb
Host smart-47f7a90c-f23c-4633-a96d-d88130af1bb0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246311288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.2246311288
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.928393749
Short name T582
Test name
Test status
Simulation time 67759314 ps
CPU time 2.62 seconds
Started Jul 14 06:52:29 PM PDT 24
Finished Jul 14 06:52:33 PM PDT 24
Peak memory 214332 kb
Host smart-08cd654f-38ec-4e86-ad8b-864677f5c388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928393749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.928393749
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.2915392852
Short name T832
Test name
Test status
Simulation time 1432496772 ps
CPU time 25.27 seconds
Started Jul 14 06:52:26 PM PDT 24
Finished Jul 14 06:52:52 PM PDT 24
Peak memory 208008 kb
Host smart-98fd06ec-b36c-4ec1-83a3-2303c15375a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915392852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.2915392852
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.74302970
Short name T198
Test name
Test status
Simulation time 12809832601 ps
CPU time 269.99 seconds
Started Jul 14 06:52:26 PM PDT 24
Finished Jul 14 06:56:57 PM PDT 24
Peak memory 218780 kb
Host smart-a2405a83-2e43-4b08-bd17-00977e667f16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74302970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.74302970
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.266126204
Short name T312
Test name
Test status
Simulation time 238997876 ps
CPU time 4.42 seconds
Started Jul 14 06:52:28 PM PDT 24
Finished Jul 14 06:52:34 PM PDT 24
Peak memory 218208 kb
Host smart-5d9acb18-3b55-43ba-ad42-4e64df38774f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266126204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.266126204
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.2375146497
Short name T362
Test name
Test status
Simulation time 242288434 ps
CPU time 2.63 seconds
Started Jul 14 06:52:26 PM PDT 24
Finished Jul 14 06:52:29 PM PDT 24
Peak memory 210496 kb
Host smart-706aa567-ec82-4a23-b0a5-71d3e372e743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375146497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2375146497
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.2198321270
Short name T835
Test name
Test status
Simulation time 116574190 ps
CPU time 0.79 seconds
Started Jul 14 06:54:14 PM PDT 24
Finished Jul 14 06:54:17 PM PDT 24
Peak memory 205988 kb
Host smart-e1e1c39c-4b43-4f56-84ba-953c9160ea39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198321270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.2198321270
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.1221755446
Short name T32
Test name
Test status
Simulation time 86775502 ps
CPU time 2.97 seconds
Started Jul 14 06:54:07 PM PDT 24
Finished Jul 14 06:54:12 PM PDT 24
Peak memory 214316 kb
Host smart-a543543d-1203-48bb-aadf-a6b584eed27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221755446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.1221755446
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.1206585979
Short name T866
Test name
Test status
Simulation time 176088840 ps
CPU time 4.7 seconds
Started Jul 14 06:54:10 PM PDT 24
Finished Jul 14 06:54:17 PM PDT 24
Peak memory 208984 kb
Host smart-6af54443-08fa-401d-9cd0-203a46efeb31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206585979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.1206585979
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.869476613
Short name T677
Test name
Test status
Simulation time 30642507 ps
CPU time 2.03 seconds
Started Jul 14 06:54:16 PM PDT 24
Finished Jul 14 06:54:22 PM PDT 24
Peak memory 214356 kb
Host smart-0a4e679b-372d-4b95-b86b-2e7bfaa21f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869476613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.869476613
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.3905188078
Short name T98
Test name
Test status
Simulation time 44577495 ps
CPU time 2.98 seconds
Started Jul 14 06:54:18 PM PDT 24
Finished Jul 14 06:54:24 PM PDT 24
Peak memory 214276 kb
Host smart-a4a12560-c77f-440c-ac63-4deb63433c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905188078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3905188078
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.200573766
Short name T302
Test name
Test status
Simulation time 84929171 ps
CPU time 3.38 seconds
Started Jul 14 06:54:04 PM PDT 24
Finished Jul 14 06:54:09 PM PDT 24
Peak memory 209832 kb
Host smart-c7589e08-70f7-4e53-a9b2-d2319c207f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200573766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.200573766
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.3746380345
Short name T217
Test name
Test status
Simulation time 387122048 ps
CPU time 4.45 seconds
Started Jul 14 06:54:08 PM PDT 24
Finished Jul 14 06:54:14 PM PDT 24
Peak memory 208728 kb
Host smart-5b390107-caa7-4027-a61d-e2c0dfdec938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746380345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.3746380345
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.219307618
Short name T465
Test name
Test status
Simulation time 614489096 ps
CPU time 21.04 seconds
Started Jul 14 06:54:23 PM PDT 24
Finished Jul 14 06:54:46 PM PDT 24
Peak memory 208752 kb
Host smart-ad682f2a-329c-4163-a2f3-41a52d8f9362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219307618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.219307618
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.2529757882
Short name T661
Test name
Test status
Simulation time 134509961 ps
CPU time 4.72 seconds
Started Jul 14 06:54:13 PM PDT 24
Finished Jul 14 06:54:21 PM PDT 24
Peak memory 208064 kb
Host smart-b91c2723-a607-4c9d-99c9-6247b973306b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529757882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2529757882
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.1595314344
Short name T250
Test name
Test status
Simulation time 5683524900 ps
CPU time 54.19 seconds
Started Jul 14 06:54:10 PM PDT 24
Finished Jul 14 06:55:07 PM PDT 24
Peak memory 209240 kb
Host smart-bda1d912-64aa-4a30-b550-13824fece824
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595314344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.1595314344
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.2377654696
Short name T503
Test name
Test status
Simulation time 6875630655 ps
CPU time 39.73 seconds
Started Jul 14 06:54:10 PM PDT 24
Finished Jul 14 06:54:51 PM PDT 24
Peak memory 208976 kb
Host smart-dd92e4ee-b120-47d5-935e-e562365c9106
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377654696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.2377654696
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.1725889715
Short name T817
Test name
Test status
Simulation time 29862175 ps
CPU time 1.33 seconds
Started Jul 14 06:54:07 PM PDT 24
Finished Jul 14 06:54:11 PM PDT 24
Peak memory 208124 kb
Host smart-59476c2c-b317-4d7b-9613-84dc31126629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725889715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1725889715
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.3874706908
Short name T613
Test name
Test status
Simulation time 124222166 ps
CPU time 2.55 seconds
Started Jul 14 06:54:10 PM PDT 24
Finished Jul 14 06:54:14 PM PDT 24
Peak memory 206848 kb
Host smart-e70b238e-aac7-40a0-88fd-34e316ad28bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874706908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.3874706908
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.1820674309
Short name T352
Test name
Test status
Simulation time 1508386293 ps
CPU time 5.27 seconds
Started Jul 14 06:54:06 PM PDT 24
Finished Jul 14 06:54:12 PM PDT 24
Peak memory 208020 kb
Host smart-7f22dea1-9e65-49bb-bce2-f5c2b9ee8af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820674309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1820674309
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.1785364249
Short name T895
Test name
Test status
Simulation time 53179773 ps
CPU time 1.99 seconds
Started Jul 14 06:54:22 PM PDT 24
Finished Jul 14 06:54:27 PM PDT 24
Peak memory 210088 kb
Host smart-4c167cd0-e893-4680-87a4-74cc977a7e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785364249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.1785364249
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.3011002863
Short name T191
Test name
Test status
Simulation time 38454226 ps
CPU time 0.74 seconds
Started Jul 14 06:54:19 PM PDT 24
Finished Jul 14 06:54:23 PM PDT 24
Peak memory 205992 kb
Host smart-3405c369-ab9c-40e6-9dc9-671e6beb6100
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011002863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.3011002863
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.1101100826
Short name T317
Test name
Test status
Simulation time 52993756 ps
CPU time 2.27 seconds
Started Jul 14 06:54:12 PM PDT 24
Finished Jul 14 06:54:17 PM PDT 24
Peak memory 214192 kb
Host smart-2ffff8f6-d270-4678-a95e-06b8bd03a46f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1101100826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.1101100826
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.424422107
Short name T220
Test name
Test status
Simulation time 154539370 ps
CPU time 3.44 seconds
Started Jul 14 06:54:24 PM PDT 24
Finished Jul 14 06:54:29 PM PDT 24
Peak memory 221340 kb
Host smart-2b9a1156-a0b9-49fd-a740-60eabf0f9594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424422107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.424422107
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.3574832068
Short name T350
Test name
Test status
Simulation time 197182607 ps
CPU time 3.26 seconds
Started Jul 14 06:54:05 PM PDT 24
Finished Jul 14 06:54:09 PM PDT 24
Peak memory 209660 kb
Host smart-2e1d62b1-0a14-42fd-915d-7dbed39771fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574832068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3574832068
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.284618082
Short name T252
Test name
Test status
Simulation time 41995094 ps
CPU time 2.08 seconds
Started Jul 14 06:54:20 PM PDT 24
Finished Jul 14 06:54:26 PM PDT 24
Peak memory 214648 kb
Host smart-cd6212ea-2170-4615-a070-a9332a38db43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284618082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.284618082
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.312830823
Short name T16
Test name
Test status
Simulation time 887423101 ps
CPU time 8.15 seconds
Started Jul 14 06:54:07 PM PDT 24
Finished Jul 14 06:54:17 PM PDT 24
Peak memory 214276 kb
Host smart-3f191ef7-0084-4faa-998e-8f0591d8f7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312830823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.312830823
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.1631027103
Short name T193
Test name
Test status
Simulation time 557776105 ps
CPU time 3.91 seconds
Started Jul 14 06:54:10 PM PDT 24
Finished Jul 14 06:54:17 PM PDT 24
Peak memory 214340 kb
Host smart-e2600d9d-9e36-4abb-b579-856fc4d746c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631027103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.1631027103
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.2185836945
Short name T425
Test name
Test status
Simulation time 958766035 ps
CPU time 5.09 seconds
Started Jul 14 06:54:23 PM PDT 24
Finished Jul 14 06:54:30 PM PDT 24
Peak memory 208020 kb
Host smart-28772fcc-4878-4a6d-ad73-d78775b0e935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185836945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.2185836945
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.3324062073
Short name T882
Test name
Test status
Simulation time 63923282 ps
CPU time 3.01 seconds
Started Jul 14 06:54:20 PM PDT 24
Finished Jul 14 06:54:27 PM PDT 24
Peak memory 207024 kb
Host smart-13b25be3-2a0d-45d2-bb81-98839af82842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324062073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.3324062073
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.908671971
Short name T691
Test name
Test status
Simulation time 288565570 ps
CPU time 3.53 seconds
Started Jul 14 06:54:11 PM PDT 24
Finished Jul 14 06:54:17 PM PDT 24
Peak memory 208280 kb
Host smart-3083fa20-3747-48bd-ba04-cd63b1647598
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908671971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.908671971
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.22303278
Short name T728
Test name
Test status
Simulation time 589596210 ps
CPU time 15.35 seconds
Started Jul 14 06:54:15 PM PDT 24
Finished Jul 14 06:54:33 PM PDT 24
Peak memory 207952 kb
Host smart-7c2ef1c3-fdda-4e54-98bd-66fc476b8fbf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22303278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.22303278
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.3830326250
Short name T899
Test name
Test status
Simulation time 328962161 ps
CPU time 2.43 seconds
Started Jul 14 06:54:12 PM PDT 24
Finished Jul 14 06:54:17 PM PDT 24
Peak memory 206664 kb
Host smart-7c58f199-3c5d-420e-a6d6-41d4639db489
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830326250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3830326250
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.2094254283
Short name T862
Test name
Test status
Simulation time 1261639549 ps
CPU time 11.56 seconds
Started Jul 14 06:54:19 PM PDT 24
Finished Jul 14 06:54:34 PM PDT 24
Peak memory 208940 kb
Host smart-644170eb-7f5e-4ee5-b043-c628e44d1112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094254283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.2094254283
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.3240808657
Short name T108
Test name
Test status
Simulation time 846230310 ps
CPU time 5.9 seconds
Started Jul 14 06:54:13 PM PDT 24
Finished Jul 14 06:54:22 PM PDT 24
Peak memory 208152 kb
Host smart-e4636272-b1e8-4709-a12d-a8f715bbf1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240808657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.3240808657
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.4101024355
Short name T514
Test name
Test status
Simulation time 140264076 ps
CPU time 5.4 seconds
Started Jul 14 06:54:25 PM PDT 24
Finished Jul 14 06:54:32 PM PDT 24
Peak memory 220608 kb
Host smart-f1262270-358a-4dfc-b42c-4d3369e48cc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101024355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.4101024355
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.1756716668
Short name T492
Test name
Test status
Simulation time 102969593 ps
CPU time 7.42 seconds
Started Jul 14 06:54:10 PM PDT 24
Finished Jul 14 06:54:19 PM PDT 24
Peak memory 220084 kb
Host smart-118681be-8218-4ccf-af1b-ff684a89edcd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756716668 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.1756716668
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.2899493504
Short name T721
Test name
Test status
Simulation time 302451505 ps
CPU time 8.12 seconds
Started Jul 14 06:54:10 PM PDT 24
Finished Jul 14 06:54:20 PM PDT 24
Peak memory 209016 kb
Host smart-851523ba-9b34-4757-a13d-c264c606725a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899493504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.2899493504
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.4217555217
Short name T707
Test name
Test status
Simulation time 47416567 ps
CPU time 2.26 seconds
Started Jul 14 06:54:14 PM PDT 24
Finished Jul 14 06:54:19 PM PDT 24
Peak memory 210188 kb
Host smart-21b84e90-2253-43ba-a9b6-bfe5cc613050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217555217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.4217555217
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.3712823234
Short name T841
Test name
Test status
Simulation time 18473769 ps
CPU time 0.96 seconds
Started Jul 14 06:54:18 PM PDT 24
Finished Jul 14 06:54:22 PM PDT 24
Peak memory 206088 kb
Host smart-f7117054-670d-4a99-a18b-5903d94e18eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712823234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.3712823234
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.3310206090
Short name T41
Test name
Test status
Simulation time 98360960 ps
CPU time 1.9 seconds
Started Jul 14 06:54:18 PM PDT 24
Finished Jul 14 06:54:24 PM PDT 24
Peak memory 209328 kb
Host smart-4ad142fa-a118-4eb2-b92a-e55ed821f532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310206090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3310206090
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.1285585942
Short name T689
Test name
Test status
Simulation time 3108857073 ps
CPU time 16.2 seconds
Started Jul 14 06:54:06 PM PDT 24
Finished Jul 14 06:54:23 PM PDT 24
Peak memory 214472 kb
Host smart-79927d4c-a437-4c43-8fa1-0d959b0e9f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285585942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.1285585942
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.1210205775
Short name T908
Test name
Test status
Simulation time 147231880 ps
CPU time 2.48 seconds
Started Jul 14 06:54:21 PM PDT 24
Finished Jul 14 06:54:27 PM PDT 24
Peak memory 222508 kb
Host smart-2a32ef58-8e38-4457-994b-64c78aa5a617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210205775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.1210205775
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.4256481985
Short name T306
Test name
Test status
Simulation time 332818570 ps
CPU time 2.19 seconds
Started Jul 14 06:54:12 PM PDT 24
Finished Jul 14 06:54:17 PM PDT 24
Peak memory 214172 kb
Host smart-3cfb459d-bd1c-4dc5-a0ab-b09c2d91d72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256481985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.4256481985
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.411463688
Short name T511
Test name
Test status
Simulation time 1348646990 ps
CPU time 4.48 seconds
Started Jul 14 06:54:12 PM PDT 24
Finished Jul 14 06:54:20 PM PDT 24
Peak memory 215900 kb
Host smart-2c801048-f6a9-4332-b459-b5343d31a8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411463688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.411463688
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2934131418
Short name T339
Test name
Test status
Simulation time 789987819 ps
CPU time 4.24 seconds
Started Jul 14 06:54:10 PM PDT 24
Finished Jul 14 06:54:17 PM PDT 24
Peak memory 208308 kb
Host smart-ee97d577-c62f-4d10-bfc8-f3593a066278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934131418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2934131418
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.3218580480
Short name T783
Test name
Test status
Simulation time 624552903 ps
CPU time 2.62 seconds
Started Jul 14 06:54:12 PM PDT 24
Finished Jul 14 06:54:18 PM PDT 24
Peak memory 206748 kb
Host smart-5095a01f-2a24-4877-8cd5-e72d7767e833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218580480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.3218580480
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3678610161
Short name T44
Test name
Test status
Simulation time 324373783 ps
CPU time 11.31 seconds
Started Jul 14 06:54:20 PM PDT 24
Finished Jul 14 06:54:35 PM PDT 24
Peak memory 206936 kb
Host smart-1675578a-c724-4b24-859e-5c42c7d9c11d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678610161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3678610161
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.165148575
Short name T593
Test name
Test status
Simulation time 347547512 ps
CPU time 7.17 seconds
Started Jul 14 06:54:19 PM PDT 24
Finished Jul 14 06:54:30 PM PDT 24
Peak memory 208468 kb
Host smart-76de19f9-4a23-4387-a31a-ff97a0b07c1d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165148575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.165148575
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.623024993
Short name T581
Test name
Test status
Simulation time 34062323 ps
CPU time 1.91 seconds
Started Jul 14 06:54:12 PM PDT 24
Finished Jul 14 06:54:17 PM PDT 24
Peak memory 207312 kb
Host smart-149105f4-7ec7-444c-9bfe-24b3bbbcf2c1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623024993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.623024993
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.566224845
Short name T649
Test name
Test status
Simulation time 462045055 ps
CPU time 3.21 seconds
Started Jul 14 06:54:25 PM PDT 24
Finished Jul 14 06:54:30 PM PDT 24
Peak memory 208804 kb
Host smart-e027650f-cff4-4072-8582-e42f596b936b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566224845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.566224845
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.2878062385
Short name T133
Test name
Test status
Simulation time 1402722413 ps
CPU time 13.3 seconds
Started Jul 14 06:54:28 PM PDT 24
Finished Jul 14 06:54:43 PM PDT 24
Peak memory 208112 kb
Host smart-a67f947e-a31b-4c03-806a-cc5321b62c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878062385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2878062385
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.2740583211
Short name T869
Test name
Test status
Simulation time 1127228668 ps
CPU time 7.78 seconds
Started Jul 14 06:54:12 PM PDT 24
Finished Jul 14 06:54:22 PM PDT 24
Peak memory 215044 kb
Host smart-3654c653-51ad-4950-915f-0f6171e780bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740583211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.2740583211
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.3407987847
Short name T815
Test name
Test status
Simulation time 397814233 ps
CPU time 5.46 seconds
Started Jul 14 06:54:17 PM PDT 24
Finished Jul 14 06:54:25 PM PDT 24
Peak memory 214336 kb
Host smart-86afefae-53ee-48a4-aa86-43b1e32e90c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407987847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.3407987847
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.2116382999
Short name T42
Test name
Test status
Simulation time 312470172 ps
CPU time 2.47 seconds
Started Jul 14 06:54:25 PM PDT 24
Finished Jul 14 06:54:29 PM PDT 24
Peak memory 210316 kb
Host smart-fdb6b95c-aab4-4a89-a0cf-2a0e1b65c7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116382999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.2116382999
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.935339937
Short name T513
Test name
Test status
Simulation time 60548885 ps
CPU time 0.81 seconds
Started Jul 14 06:54:30 PM PDT 24
Finished Jul 14 06:54:34 PM PDT 24
Peak memory 206016 kb
Host smart-f7ab3b8d-9c19-464f-b6a3-83ae8c830306
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935339937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.935339937
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.2171247145
Short name T391
Test name
Test status
Simulation time 434119362 ps
CPU time 2.25 seconds
Started Jul 14 06:54:26 PM PDT 24
Finished Jul 14 06:54:30 PM PDT 24
Peak memory 214340 kb
Host smart-6dfedaa1-d488-470a-8af2-5233ebcf472f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2171247145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.2171247145
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.973436280
Short name T315
Test name
Test status
Simulation time 137972173 ps
CPU time 1.59 seconds
Started Jul 14 06:54:33 PM PDT 24
Finished Jul 14 06:54:38 PM PDT 24
Peak memory 214316 kb
Host smart-f8779ac2-dbae-47fa-ad17-56d5d6d1380e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973436280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.973436280
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.3466202897
Short name T93
Test name
Test status
Simulation time 1816003363 ps
CPU time 9.09 seconds
Started Jul 14 06:54:29 PM PDT 24
Finished Jul 14 06:54:41 PM PDT 24
Peak memory 214304 kb
Host smart-130a30ba-95d4-4e3c-9b15-7c677dc55c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466202897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.3466202897
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.2484703679
Short name T270
Test name
Test status
Simulation time 156274485 ps
CPU time 2.97 seconds
Started Jul 14 06:54:15 PM PDT 24
Finished Jul 14 06:54:21 PM PDT 24
Peak memory 214324 kb
Host smart-1879e6e1-4106-4cc7-9a9d-304de3b8fdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484703679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.2484703679
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.581217109
Short name T842
Test name
Test status
Simulation time 119750205 ps
CPU time 2.14 seconds
Started Jul 14 06:54:12 PM PDT 24
Finished Jul 14 06:54:17 PM PDT 24
Peak memory 219732 kb
Host smart-fefb3515-ab92-419e-a831-e112932f8717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581217109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.581217109
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.3668517030
Short name T607
Test name
Test status
Simulation time 48339715 ps
CPU time 3.1 seconds
Started Jul 14 06:54:12 PM PDT 24
Finished Jul 14 06:54:18 PM PDT 24
Peak memory 209828 kb
Host smart-c1dbc4fa-1377-45c7-8856-464703fa12be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668517030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.3668517030
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.3690684615
Short name T502
Test name
Test status
Simulation time 47703593 ps
CPU time 2.56 seconds
Started Jul 14 06:54:27 PM PDT 24
Finished Jul 14 06:54:32 PM PDT 24
Peak memory 206992 kb
Host smart-12fc0034-34d5-4963-8aaf-a5e5b36138ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690684615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.3690684615
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.300342449
Short name T275
Test name
Test status
Simulation time 598758536 ps
CPU time 3.68 seconds
Started Jul 14 06:54:11 PM PDT 24
Finished Jul 14 06:54:17 PM PDT 24
Peak memory 208600 kb
Host smart-b164dff7-527e-4d21-b0db-da772d37a0f0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300342449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.300342449
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.2877041985
Short name T457
Test name
Test status
Simulation time 69481454 ps
CPU time 2.86 seconds
Started Jul 14 06:54:19 PM PDT 24
Finished Jul 14 06:54:25 PM PDT 24
Peak memory 207528 kb
Host smart-64f70210-144c-44ce-9adc-47e492abcf5c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877041985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.2877041985
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.2068587099
Short name T839
Test name
Test status
Simulation time 361971741 ps
CPU time 4.28 seconds
Started Jul 14 06:54:06 PM PDT 24
Finished Jul 14 06:54:12 PM PDT 24
Peak memory 208788 kb
Host smart-3a3af0ae-a7c3-48f4-81ff-4ec358fd0cf2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068587099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2068587099
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.3451728087
Short name T472
Test name
Test status
Simulation time 17786152 ps
CPU time 1.33 seconds
Started Jul 14 06:54:16 PM PDT 24
Finished Jul 14 06:54:20 PM PDT 24
Peak memory 207348 kb
Host smart-21629eb2-56ee-46f8-860a-2c6cb083bad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451728087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.3451728087
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.97206128
Short name T796
Test name
Test status
Simulation time 1398033140 ps
CPU time 4.93 seconds
Started Jul 14 06:54:30 PM PDT 24
Finished Jul 14 06:54:38 PM PDT 24
Peak memory 207920 kb
Host smart-72b38ac1-8213-4a52-9cc2-92392cf1e788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97206128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.97206128
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.70916681
Short name T638
Test name
Test status
Simulation time 360755346 ps
CPU time 5.3 seconds
Started Jul 14 06:54:17 PM PDT 24
Finished Jul 14 06:54:26 PM PDT 24
Peak memory 215800 kb
Host smart-c48b4515-d561-4ff1-9872-084dacae4736
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70916681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.70916681
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.333796433
Short name T775
Test name
Test status
Simulation time 215213734 ps
CPU time 4.74 seconds
Started Jul 14 06:54:13 PM PDT 24
Finished Jul 14 06:54:20 PM PDT 24
Peak memory 207552 kb
Host smart-873e80b6-0e27-4c8e-98aa-a2181125f386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333796433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.333796433
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.1544029760
Short name T591
Test name
Test status
Simulation time 15209303 ps
CPU time 0.79 seconds
Started Jul 14 06:54:21 PM PDT 24
Finished Jul 14 06:54:25 PM PDT 24
Peak memory 206024 kb
Host smart-47946fa2-6fe0-440a-85fa-dd47e3c68c29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544029760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.1544029760
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.4126605240
Short name T145
Test name
Test status
Simulation time 431213434 ps
CPU time 2.99 seconds
Started Jul 14 06:54:22 PM PDT 24
Finished Jul 14 06:54:27 PM PDT 24
Peak memory 214328 kb
Host smart-6e4264b9-cc33-4c13-8e29-37ed420aa871
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4126605240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.4126605240
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.3544846975
Short name T550
Test name
Test status
Simulation time 86801597 ps
CPU time 2.73 seconds
Started Jul 14 06:54:19 PM PDT 24
Finished Jul 14 06:54:25 PM PDT 24
Peak memory 222388 kb
Host smart-4262f6b4-6df6-4302-bc62-9fcfb05532e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544846975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3544846975
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.1502120306
Short name T494
Test name
Test status
Simulation time 117780473 ps
CPU time 2.6 seconds
Started Jul 14 06:54:28 PM PDT 24
Finished Jul 14 06:54:34 PM PDT 24
Peak memory 214320 kb
Host smart-40f4c77b-3188-47b6-8091-a29863b46256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502120306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.1502120306
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.1859853825
Short name T636
Test name
Test status
Simulation time 515048859 ps
CPU time 3.14 seconds
Started Jul 14 06:54:25 PM PDT 24
Finished Jul 14 06:54:30 PM PDT 24
Peak memory 214288 kb
Host smart-dd00660b-7d01-4312-9421-f37f8eaa5f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859853825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.1859853825
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.3219226904
Short name T330
Test name
Test status
Simulation time 719525271 ps
CPU time 3.69 seconds
Started Jul 14 06:54:14 PM PDT 24
Finished Jul 14 06:54:20 PM PDT 24
Peak memory 222472 kb
Host smart-6f8074f6-7035-463a-8b99-a6e932079857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219226904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.3219226904
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.4170771196
Short name T417
Test name
Test status
Simulation time 1396345538 ps
CPU time 4.01 seconds
Started Jul 14 06:54:16 PM PDT 24
Finished Jul 14 06:54:23 PM PDT 24
Peak memory 215480 kb
Host smart-f7d98548-782a-4255-9fa9-1d8dfe865e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170771196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.4170771196
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.2053152125
Short name T679
Test name
Test status
Simulation time 104197443 ps
CPU time 5 seconds
Started Jul 14 06:54:14 PM PDT 24
Finished Jul 14 06:54:22 PM PDT 24
Peak memory 207404 kb
Host smart-3c78dc16-a37b-4619-8d19-954728951a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053152125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.2053152125
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.2320759971
Short name T300
Test name
Test status
Simulation time 226761724 ps
CPU time 6.49 seconds
Started Jul 14 06:54:27 PM PDT 24
Finished Jul 14 06:54:35 PM PDT 24
Peak memory 208080 kb
Host smart-4da22303-e0fc-425e-a97c-d8571dcaf1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320759971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2320759971
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.4098230631
Short name T464
Test name
Test status
Simulation time 168075748 ps
CPU time 2.58 seconds
Started Jul 14 06:54:12 PM PDT 24
Finished Jul 14 06:54:17 PM PDT 24
Peak memory 207044 kb
Host smart-561314f4-96e6-47a2-9949-d96a1bf96c02
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098230631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.4098230631
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.2209504718
Short name T539
Test name
Test status
Simulation time 234444655 ps
CPU time 2.92 seconds
Started Jul 14 06:54:19 PM PDT 24
Finished Jul 14 06:54:25 PM PDT 24
Peak memory 206884 kb
Host smart-96182581-8d08-4c73-acb3-48ff71de6f93
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209504718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.2209504718
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.641722832
Short name T265
Test name
Test status
Simulation time 1508317895 ps
CPU time 45.81 seconds
Started Jul 14 06:54:13 PM PDT 24
Finished Jul 14 06:55:02 PM PDT 24
Peak memory 208624 kb
Host smart-d8d65a85-d320-403b-bef2-de431e735a24
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641722832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.641722832
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.3190907391
Short name T415
Test name
Test status
Simulation time 78111143 ps
CPU time 2.95 seconds
Started Jul 14 06:54:28 PM PDT 24
Finished Jul 14 06:54:34 PM PDT 24
Peak memory 218528 kb
Host smart-b9384cbd-3c0a-47fa-a272-69f1851c4a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190907391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.3190907391
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3251786909
Short name T844
Test name
Test status
Simulation time 1187744334 ps
CPU time 4.4 seconds
Started Jul 14 06:54:29 PM PDT 24
Finished Jul 14 06:54:36 PM PDT 24
Peak memory 206812 kb
Host smart-9e46fe7e-5114-4dd7-9233-054bb46793ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251786909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3251786909
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.1533803712
Short name T748
Test name
Test status
Simulation time 270664387 ps
CPU time 4.53 seconds
Started Jul 14 06:54:11 PM PDT 24
Finished Jul 14 06:54:19 PM PDT 24
Peak memory 207592 kb
Host smart-dd809a70-f4e0-40ec-9eb5-13400231bd19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533803712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.1533803712
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.3470169137
Short name T863
Test name
Test status
Simulation time 95725568 ps
CPU time 1.68 seconds
Started Jul 14 06:54:27 PM PDT 24
Finished Jul 14 06:54:31 PM PDT 24
Peak memory 210028 kb
Host smart-17f74217-18a9-404b-81e4-32dcd4045b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470169137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.3470169137
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.1595298377
Short name T858
Test name
Test status
Simulation time 22305797 ps
CPU time 0.84 seconds
Started Jul 14 06:54:31 PM PDT 24
Finished Jul 14 06:54:35 PM PDT 24
Peak memory 205972 kb
Host smart-c3ee91d0-5175-4f47-8655-1f6272ed86b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595298377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.1595298377
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.2609136858
Short name T156
Test name
Test status
Simulation time 301737982 ps
CPU time 4.73 seconds
Started Jul 14 06:54:16 PM PDT 24
Finished Jul 14 06:54:23 PM PDT 24
Peak memory 214312 kb
Host smart-032ca778-55a1-4d68-ab6b-1f8a2da7eed0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2609136858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.2609136858
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.1810323241
Short name T520
Test name
Test status
Simulation time 198434414 ps
CPU time 3.53 seconds
Started Jul 14 06:54:15 PM PDT 24
Finished Jul 14 06:54:21 PM PDT 24
Peak memory 218348 kb
Host smart-913ab588-7b7e-49e0-80bc-2a7f609dc792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810323241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.1810323241
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.1936210828
Short name T749
Test name
Test status
Simulation time 2947511950 ps
CPU time 18.67 seconds
Started Jul 14 06:54:27 PM PDT 24
Finished Jul 14 06:54:49 PM PDT 24
Peak memory 214384 kb
Host smart-1d36a7d6-9bd3-4e8e-9d84-24c0d3eb34d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936210828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.1936210828
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.3570678152
Short name T764
Test name
Test status
Simulation time 272328627 ps
CPU time 2.4 seconds
Started Jul 14 06:54:19 PM PDT 24
Finished Jul 14 06:54:25 PM PDT 24
Peak memory 214272 kb
Host smart-5c0f9f12-971f-472b-99fc-e38e51720ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570678152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.3570678152
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1996000788
Short name T45
Test name
Test status
Simulation time 55820234 ps
CPU time 2.31 seconds
Started Jul 14 06:54:27 PM PDT 24
Finished Jul 14 06:54:32 PM PDT 24
Peak memory 219668 kb
Host smart-474be594-821e-4728-949a-aca208e3b04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996000788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1996000788
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.1355135047
Short name T474
Test name
Test status
Simulation time 308539547 ps
CPU time 8.49 seconds
Started Jul 14 06:54:17 PM PDT 24
Finished Jul 14 06:54:29 PM PDT 24
Peak memory 214340 kb
Host smart-6b477ebd-82e3-4e7c-8b70-c805b1b4188f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355135047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.1355135047
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.2998725802
Short name T501
Test name
Test status
Simulation time 2191101819 ps
CPU time 14.78 seconds
Started Jul 14 06:54:37 PM PDT 24
Finished Jul 14 06:54:55 PM PDT 24
Peak memory 208580 kb
Host smart-41715c15-c5fe-4d14-869d-e32bb30373a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998725802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.2998725802
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.3931935318
Short name T747
Test name
Test status
Simulation time 7617584981 ps
CPU time 45.59 seconds
Started Jul 14 06:54:21 PM PDT 24
Finished Jul 14 06:55:10 PM PDT 24
Peak memory 208160 kb
Host smart-45c06b80-c910-4c5c-be86-2570ccdf8444
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931935318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.3931935318
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.3758078567
Short name T303
Test name
Test status
Simulation time 4460358234 ps
CPU time 7.28 seconds
Started Jul 14 06:54:19 PM PDT 24
Finished Jul 14 06:54:30 PM PDT 24
Peak memory 207048 kb
Host smart-48607100-c3f4-4049-a191-b8aa333aaeee
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758078567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.3758078567
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.41553850
Short name T129
Test name
Test status
Simulation time 764758046 ps
CPU time 8.52 seconds
Started Jul 14 06:54:21 PM PDT 24
Finished Jul 14 06:54:33 PM PDT 24
Peak memory 206944 kb
Host smart-24d471d1-4490-4810-96e6-aac654dc85a7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41553850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.41553850
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.3640975354
Short name T211
Test name
Test status
Simulation time 187871255 ps
CPU time 1.69 seconds
Started Jul 14 06:54:36 PM PDT 24
Finished Jul 14 06:54:41 PM PDT 24
Peak memory 207528 kb
Host smart-ae1334fd-5fd1-412d-99d5-e0608df3dc90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640975354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.3640975354
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.860514437
Short name T684
Test name
Test status
Simulation time 241390499 ps
CPU time 4.98 seconds
Started Jul 14 06:54:16 PM PDT 24
Finished Jul 14 06:54:23 PM PDT 24
Peak memory 208784 kb
Host smart-044c422b-e92c-4802-974d-d3319738c587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860514437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.860514437
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.4209044713
Short name T333
Test name
Test status
Simulation time 8393982639 ps
CPU time 42 seconds
Started Jul 14 06:54:17 PM PDT 24
Finished Jul 14 06:55:03 PM PDT 24
Peak memory 222624 kb
Host smart-73f23360-6800-46a1-b02a-0a78c92a69d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209044713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.4209044713
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.452773359
Short name T186
Test name
Test status
Simulation time 5340875017 ps
CPU time 26.92 seconds
Started Jul 14 06:54:20 PM PDT 24
Finished Jul 14 06:54:50 PM PDT 24
Peak memory 223892 kb
Host smart-d016b47f-e647-43d9-85df-b528398ffe01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452773359 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.452773359
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.2221504350
Short name T681
Test name
Test status
Simulation time 141964556 ps
CPU time 4.13 seconds
Started Jul 14 06:54:27 PM PDT 24
Finished Jul 14 06:54:34 PM PDT 24
Peak memory 209916 kb
Host smart-8cf3e5fe-6685-442f-afdc-ef53b29d5180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221504350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.2221504350
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.3338379184
Short name T685
Test name
Test status
Simulation time 38895859 ps
CPU time 2.31 seconds
Started Jul 14 06:54:17 PM PDT 24
Finished Jul 14 06:54:22 PM PDT 24
Peak memory 209880 kb
Host smart-99a352d0-31e9-461f-a493-f0c3017c9042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338379184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.3338379184
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.2790560522
Short name T563
Test name
Test status
Simulation time 45210737 ps
CPU time 0.76 seconds
Started Jul 14 06:54:27 PM PDT 24
Finished Jul 14 06:54:29 PM PDT 24
Peak memory 206012 kb
Host smart-7b5a742d-ed7b-46c2-86fe-5f442952b220
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790560522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.2790560522
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.1040402396
Short name T273
Test name
Test status
Simulation time 144867699 ps
CPU time 4.36 seconds
Started Jul 14 06:54:33 PM PDT 24
Finished Jul 14 06:54:41 PM PDT 24
Peak memory 222436 kb
Host smart-391c5518-8812-414b-91d0-a6330e1db9f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1040402396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.1040402396
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.1860883550
Short name T487
Test name
Test status
Simulation time 679404438 ps
CPU time 3.28 seconds
Started Jul 14 06:54:31 PM PDT 24
Finished Jul 14 06:54:38 PM PDT 24
Peak memory 222416 kb
Host smart-3552c9b8-7dd7-4dc0-9341-c1af636cf8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860883550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.1860883550
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.688316825
Short name T314
Test name
Test status
Simulation time 308807282 ps
CPU time 4.68 seconds
Started Jul 14 06:54:31 PM PDT 24
Finished Jul 14 06:54:40 PM PDT 24
Peak memory 222436 kb
Host smart-f2b8dc7a-9f24-4107-8a59-bd41252c0609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688316825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.688316825
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.2797817238
Short name T99
Test name
Test status
Simulation time 514640134 ps
CPU time 3.73 seconds
Started Jul 14 06:54:18 PM PDT 24
Finished Jul 14 06:54:25 PM PDT 24
Peak memory 214260 kb
Host smart-e4b9445b-d229-4ae4-b413-24d4d2e0d6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797817238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.2797817238
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.2969675671
Short name T228
Test name
Test status
Simulation time 847842484 ps
CPU time 12.4 seconds
Started Jul 14 06:54:27 PM PDT 24
Finished Jul 14 06:54:41 PM PDT 24
Peak memory 217820 kb
Host smart-7ca8a584-345b-4ac6-b380-d0498a63801a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969675671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.2969675671
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.2286206732
Short name T588
Test name
Test status
Simulation time 73210710 ps
CPU time 3.6 seconds
Started Jul 14 06:54:16 PM PDT 24
Finished Jul 14 06:54:23 PM PDT 24
Peak memory 208896 kb
Host smart-316f58b7-f255-4268-bdb0-325b61c2d9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286206732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.2286206732
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.2986358186
Short name T738
Test name
Test status
Simulation time 36796859 ps
CPU time 2.4 seconds
Started Jul 14 06:54:23 PM PDT 24
Finished Jul 14 06:54:28 PM PDT 24
Peak memory 208512 kb
Host smart-7c518e42-a4f6-43cc-a743-576323860f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986358186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.2986358186
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.3118308142
Short name T192
Test name
Test status
Simulation time 81140383 ps
CPU time 3.8 seconds
Started Jul 14 06:54:27 PM PDT 24
Finished Jul 14 06:54:33 PM PDT 24
Peak memory 208852 kb
Host smart-cf8c124a-caca-40ea-bc77-8391805002d8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118308142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.3118308142
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1276436300
Short name T201
Test name
Test status
Simulation time 683476099 ps
CPU time 5.64 seconds
Started Jul 14 06:54:19 PM PDT 24
Finished Jul 14 06:54:28 PM PDT 24
Peak memory 209040 kb
Host smart-739c67ce-9ce1-48d4-9db7-113566f14486
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276436300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1276436300
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.3980961216
Short name T562
Test name
Test status
Simulation time 1497241949 ps
CPU time 25.89 seconds
Started Jul 14 06:54:17 PM PDT 24
Finished Jul 14 06:54:46 PM PDT 24
Peak memory 208680 kb
Host smart-e5ab3804-4a19-4f4a-be81-1164d79983c7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980961216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.3980961216
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2344495666
Short name T212
Test name
Test status
Simulation time 67582177 ps
CPU time 1.95 seconds
Started Jul 14 06:54:16 PM PDT 24
Finished Jul 14 06:54:21 PM PDT 24
Peak memory 209652 kb
Host smart-9187059f-0cfe-4e84-81a1-bd087b8f5efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344495666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2344495666
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.4172151986
Short name T715
Test name
Test status
Simulation time 39960856 ps
CPU time 1.74 seconds
Started Jul 14 06:54:27 PM PDT 24
Finished Jul 14 06:54:31 PM PDT 24
Peak memory 206788 kb
Host smart-2a725801-1a0a-4dc7-b2ad-b0ec26f36d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172151986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.4172151986
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.121697865
Short name T70
Test name
Test status
Simulation time 833097837 ps
CPU time 28.06 seconds
Started Jul 14 06:54:21 PM PDT 24
Finished Jul 14 06:54:52 PM PDT 24
Peak memory 222524 kb
Host smart-dd215817-4109-4568-b061-8aadbf056beb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121697865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.121697865
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.1925023566
Short name T624
Test name
Test status
Simulation time 234971622 ps
CPU time 3.31 seconds
Started Jul 14 06:54:27 PM PDT 24
Finished Jul 14 06:54:33 PM PDT 24
Peak memory 207360 kb
Host smart-28c0d3e8-d89c-4ab3-937d-1bde95b3b881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925023566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.1925023566
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.1958375886
Short name T38
Test name
Test status
Simulation time 138646966 ps
CPU time 2.79 seconds
Started Jul 14 06:54:17 PM PDT 24
Finished Jul 14 06:54:23 PM PDT 24
Peak memory 210044 kb
Host smart-c68f173c-6610-4832-afb2-7b31668f7025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958375886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1958375886
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.1753652554
Short name T886
Test name
Test status
Simulation time 38433347 ps
CPU time 0.83 seconds
Started Jul 14 06:54:30 PM PDT 24
Finished Jul 14 06:54:34 PM PDT 24
Peak memory 205972 kb
Host smart-24b30e4d-4f4b-4e1c-8675-78798426776f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753652554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.1753652554
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.1114900635
Short name T104
Test name
Test status
Simulation time 567537990 ps
CPU time 9.29 seconds
Started Jul 14 06:54:17 PM PDT 24
Finished Jul 14 06:54:30 PM PDT 24
Peak memory 222420 kb
Host smart-f7a8df25-8492-48fd-85a0-64c9b49fd121
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1114900635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.1114900635
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.4074245416
Short name T516
Test name
Test status
Simulation time 113828564 ps
CPU time 3 seconds
Started Jul 14 06:54:32 PM PDT 24
Finished Jul 14 06:54:39 PM PDT 24
Peak memory 222844 kb
Host smart-2dd019d4-d8b9-40fb-b916-41ad807b463d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074245416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.4074245416
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.3156270878
Short name T304
Test name
Test status
Simulation time 735236013 ps
CPU time 2.79 seconds
Started Jul 14 06:54:28 PM PDT 24
Finished Jul 14 06:54:34 PM PDT 24
Peak memory 210108 kb
Host smart-19934989-8f0a-4f4d-9649-5b86587a1d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156270878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3156270878
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.306010653
Short name T628
Test name
Test status
Simulation time 80878778 ps
CPU time 4.22 seconds
Started Jul 14 06:54:30 PM PDT 24
Finished Jul 14 06:54:38 PM PDT 24
Peak memory 209608 kb
Host smart-d68331b9-59cc-4eee-b049-48a04ec57086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306010653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.306010653
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.3805959379
Short name T293
Test name
Test status
Simulation time 108650085 ps
CPU time 4.74 seconds
Started Jul 14 06:54:28 PM PDT 24
Finished Jul 14 06:54:37 PM PDT 24
Peak memory 214220 kb
Host smart-da5b89f8-faaf-4317-a0bd-93afd53c2466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805959379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.3805959379
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.2714307966
Short name T574
Test name
Test status
Simulation time 106012586 ps
CPU time 2.24 seconds
Started Jul 14 06:54:22 PM PDT 24
Finished Jul 14 06:54:27 PM PDT 24
Peak memory 219828 kb
Host smart-a558f3f1-c9a3-4b9e-9c8c-6598b6920a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714307966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.2714307966
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.1600751594
Short name T452
Test name
Test status
Simulation time 55492861 ps
CPU time 3.05 seconds
Started Jul 14 06:54:30 PM PDT 24
Finished Jul 14 06:54:36 PM PDT 24
Peak memory 208284 kb
Host smart-084ff3c0-449e-491c-931c-abafbb3f018d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600751594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1600751594
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.851037436
Short name T708
Test name
Test status
Simulation time 362029241 ps
CPU time 3.2 seconds
Started Jul 14 06:54:17 PM PDT 24
Finished Jul 14 06:54:24 PM PDT 24
Peak memory 208636 kb
Host smart-e42532ba-4538-402c-832e-37997c07f110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851037436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.851037436
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.3201002883
Short name T340
Test name
Test status
Simulation time 234786444 ps
CPU time 5.8 seconds
Started Jul 14 06:54:30 PM PDT 24
Finished Jul 14 06:54:39 PM PDT 24
Peak memory 207772 kb
Host smart-4189bea6-c472-4ca4-8ac1-e7b0235c8915
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201002883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.3201002883
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.1232604755
Short name T573
Test name
Test status
Simulation time 300099537 ps
CPU time 6.27 seconds
Started Jul 14 06:54:28 PM PDT 24
Finished Jul 14 06:54:37 PM PDT 24
Peak memory 208100 kb
Host smart-18b2ee5b-662c-4df6-a9b2-16802a5faad9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232604755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.1232604755
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.3591800016
Short name T700
Test name
Test status
Simulation time 4010025660 ps
CPU time 24.44 seconds
Started Jul 14 06:54:29 PM PDT 24
Finished Jul 14 06:54:57 PM PDT 24
Peak memory 208940 kb
Host smart-0d456930-728e-46b5-bcd2-314361f67987
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591800016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.3591800016
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.401662560
Short name T331
Test name
Test status
Simulation time 155014714 ps
CPU time 3.51 seconds
Started Jul 14 06:54:28 PM PDT 24
Finished Jul 14 06:54:35 PM PDT 24
Peak memory 214344 kb
Host smart-a9d29dab-a2be-4f0d-888e-3ae4fafcdb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401662560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.401662560
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.1154976213
Short name T484
Test name
Test status
Simulation time 257823713 ps
CPU time 3.16 seconds
Started Jul 14 06:54:28 PM PDT 24
Finished Jul 14 06:54:39 PM PDT 24
Peak memory 208972 kb
Host smart-8793ba15-02bd-4428-8348-ed546d741b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154976213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.1154976213
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.64944645
Short name T245
Test name
Test status
Simulation time 3751989350 ps
CPU time 15.79 seconds
Started Jul 14 06:54:18 PM PDT 24
Finished Jul 14 06:54:37 PM PDT 24
Peak memory 210644 kb
Host smart-806c27ee-e202-44a8-8c45-d3d3016f4f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64944645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.64944645
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.1923267567
Short name T794
Test name
Test status
Simulation time 17417060 ps
CPU time 0.77 seconds
Started Jul 14 06:54:44 PM PDT 24
Finished Jul 14 06:54:52 PM PDT 24
Peak memory 206060 kb
Host smart-97809683-e6c5-41a3-9515-b537b563b417
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923267567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.1923267567
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.3387198090
Short name T301
Test name
Test status
Simulation time 69912238 ps
CPU time 3.88 seconds
Started Jul 14 06:54:29 PM PDT 24
Finished Jul 14 06:54:36 PM PDT 24
Peak memory 208816 kb
Host smart-b6b4c2b4-1955-400f-bc08-4caafb03c406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387198090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3387198090
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.25078093
Short name T665
Test name
Test status
Simulation time 81996964 ps
CPU time 3.43 seconds
Started Jul 14 06:54:33 PM PDT 24
Finished Jul 14 06:54:40 PM PDT 24
Peak memory 214324 kb
Host smart-a79aae4c-334f-4525-b921-d1816650a6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25078093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.25078093
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.1735655314
Short name T481
Test name
Test status
Simulation time 57579089 ps
CPU time 2.96 seconds
Started Jul 14 06:54:33 PM PDT 24
Finished Jul 14 06:54:40 PM PDT 24
Peak memory 214364 kb
Host smart-1b139640-a87a-4a62-9d55-ed782f114744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735655314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.1735655314
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.2398637850
Short name T789
Test name
Test status
Simulation time 1432903842 ps
CPU time 3.44 seconds
Started Jul 14 06:54:33 PM PDT 24
Finished Jul 14 06:54:41 PM PDT 24
Peak memory 214264 kb
Host smart-10816c39-486e-4920-b040-395b9f8614bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398637850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.2398637850
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.1110491348
Short name T238
Test name
Test status
Simulation time 318056369 ps
CPU time 3.74 seconds
Started Jul 14 06:54:27 PM PDT 24
Finished Jul 14 06:54:33 PM PDT 24
Peak memory 214284 kb
Host smart-13f97982-2342-4d76-86a6-1ee322b598be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110491348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.1110491348
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.1965240218
Short name T793
Test name
Test status
Simulation time 94568958 ps
CPU time 3.47 seconds
Started Jul 14 06:54:34 PM PDT 24
Finished Jul 14 06:54:41 PM PDT 24
Peak memory 207276 kb
Host smart-49374e3f-74d9-4106-bd51-c7e18af16923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965240218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.1965240218
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.4090481430
Short name T853
Test name
Test status
Simulation time 150008177 ps
CPU time 2.48 seconds
Started Jul 14 06:54:33 PM PDT 24
Finished Jul 14 06:54:39 PM PDT 24
Peak memory 206884 kb
Host smart-a5baaca1-c441-4aa4-bf69-2d18bedc9ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090481430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.4090481430
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.2887706802
Short name T821
Test name
Test status
Simulation time 4330810399 ps
CPU time 52.8 seconds
Started Jul 14 06:54:29 PM PDT 24
Finished Jul 14 06:55:25 PM PDT 24
Peak memory 209272 kb
Host smart-798ade55-534d-4b6b-b7e8-d97426aa4396
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887706802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.2887706802
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.3281394267
Short name T623
Test name
Test status
Simulation time 65993885 ps
CPU time 1.69 seconds
Started Jul 14 06:54:34 PM PDT 24
Finished Jul 14 06:54:39 PM PDT 24
Peak memory 206972 kb
Host smart-3fde7b2d-220c-477f-8110-4475ffcd2f45
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281394267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3281394267
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.308667646
Short name T1
Test name
Test status
Simulation time 114169034 ps
CPU time 2.77 seconds
Started Jul 14 06:54:29 PM PDT 24
Finished Jul 14 06:54:35 PM PDT 24
Peak memory 206880 kb
Host smart-1bf1e0f5-74f8-480d-992f-1ef1c689522c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308667646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.308667646
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.1305855866
Short name T742
Test name
Test status
Simulation time 964254284 ps
CPU time 5.98 seconds
Started Jul 14 06:54:35 PM PDT 24
Finished Jul 14 06:54:44 PM PDT 24
Peak memory 210196 kb
Host smart-27eb4683-7770-4592-ad70-febb68e94531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305855866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1305855866
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.2771242074
Short name T488
Test name
Test status
Simulation time 204535099 ps
CPU time 5.44 seconds
Started Jul 14 06:54:22 PM PDT 24
Finished Jul 14 06:54:30 PM PDT 24
Peak memory 207956 kb
Host smart-753203a2-729d-42ac-a68a-6ebc501004f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771242074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.2771242074
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.2371299274
Short name T197
Test name
Test status
Simulation time 790430693 ps
CPU time 7.52 seconds
Started Jul 14 06:54:43 PM PDT 24
Finished Jul 14 06:54:53 PM PDT 24
Peak memory 215212 kb
Host smart-f46c3196-fe7c-46f5-9e11-08d6446880b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371299274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.2371299274
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.1306483055
Short name T184
Test name
Test status
Simulation time 1318503100 ps
CPU time 13.41 seconds
Started Jul 14 06:54:26 PM PDT 24
Finished Jul 14 06:54:40 PM PDT 24
Peak memory 222568 kb
Host smart-d91dfba7-ae65-410d-8aff-199dd545f051
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306483055 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.1306483055
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.1157548873
Short name T580
Test name
Test status
Simulation time 285930022 ps
CPU time 7.13 seconds
Started Jul 14 06:54:35 PM PDT 24
Finished Jul 14 06:54:50 PM PDT 24
Peak memory 218340 kb
Host smart-6f89d03a-6212-4a40-ac42-c23e30189aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157548873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.1157548873
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.2595631849
Short name T432
Test name
Test status
Simulation time 38492330 ps
CPU time 1.49 seconds
Started Jul 14 06:54:46 PM PDT 24
Finished Jul 14 06:54:50 PM PDT 24
Peak memory 209708 kb
Host smart-1482a0de-3be3-4106-9b8e-46bab28a65c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595631849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.2595631849
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.1987887691
Short name T786
Test name
Test status
Simulation time 42084053 ps
CPU time 0.86 seconds
Started Jul 14 06:54:33 PM PDT 24
Finished Jul 14 06:54:38 PM PDT 24
Peak memory 205936 kb
Host smart-28912073-89b0-46cc-8665-7217030b8833
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987887691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.1987887691
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.2442475265
Short name T680
Test name
Test status
Simulation time 225357258 ps
CPU time 4.8 seconds
Started Jul 14 06:54:39 PM PDT 24
Finished Jul 14 06:54:46 PM PDT 24
Peak memory 222808 kb
Host smart-da583d8b-a09f-499a-a74a-7b45fcb14649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442475265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.2442475265
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.218510452
Short name T577
Test name
Test status
Simulation time 66708409 ps
CPU time 1.79 seconds
Started Jul 14 06:54:23 PM PDT 24
Finished Jul 14 06:54:27 PM PDT 24
Peak memory 208492 kb
Host smart-98a42426-551a-45e5-a54b-ddf3851d6872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218510452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.218510452
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.351562115
Short name T346
Test name
Test status
Simulation time 645223388 ps
CPU time 4.23 seconds
Started Jul 14 06:54:47 PM PDT 24
Finished Jul 14 06:54:54 PM PDT 24
Peak memory 209236 kb
Host smart-0d19f979-17b7-4816-8f88-c5f35509c6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351562115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.351562115
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.3252189411
Short name T51
Test name
Test status
Simulation time 49073200 ps
CPU time 3.51 seconds
Started Jul 14 06:54:34 PM PDT 24
Finished Jul 14 06:54:41 PM PDT 24
Peak memory 214812 kb
Host smart-73024a01-9f31-4f39-81f1-1c15eff7002a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252189411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.3252189411
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.3220882042
Short name T542
Test name
Test status
Simulation time 365963613 ps
CPU time 3.92 seconds
Started Jul 14 06:54:27 PM PDT 24
Finished Jul 14 06:54:32 PM PDT 24
Peak memory 208904 kb
Host smart-f3f20687-a214-4c28-9290-a9a2b9227078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220882042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.3220882042
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.1919290545
Short name T543
Test name
Test status
Simulation time 243521750 ps
CPU time 7.41 seconds
Started Jul 14 06:54:45 PM PDT 24
Finished Jul 14 06:54:56 PM PDT 24
Peak memory 218496 kb
Host smart-b488cc66-1975-496f-902e-86e4fbd74481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919290545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.1919290545
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.614662650
Short name T455
Test name
Test status
Simulation time 243759947 ps
CPU time 2.62 seconds
Started Jul 14 06:54:27 PM PDT 24
Finished Jul 14 06:54:31 PM PDT 24
Peak memory 207408 kb
Host smart-d8bf109e-224e-4daa-aab0-6fef11fbb030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614662650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.614662650
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.2748830190
Short name T327
Test name
Test status
Simulation time 1008243914 ps
CPU time 11.42 seconds
Started Jul 14 06:54:38 PM PDT 24
Finished Jul 14 06:54:52 PM PDT 24
Peak memory 208668 kb
Host smart-13eba9e2-f819-4234-9d2c-f36992c60733
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748830190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.2748830190
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.330878943
Short name T663
Test name
Test status
Simulation time 2814168386 ps
CPU time 30.25 seconds
Started Jul 14 06:54:33 PM PDT 24
Finished Jul 14 06:55:07 PM PDT 24
Peak memory 208656 kb
Host smart-2ff832b4-b65b-4058-acb0-a160200f4038
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330878943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.330878943
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.2389830280
Short name T837
Test name
Test status
Simulation time 859448800 ps
CPU time 22.09 seconds
Started Jul 14 06:54:29 PM PDT 24
Finished Jul 14 06:54:55 PM PDT 24
Peak memory 208536 kb
Host smart-226fab4b-aab5-4094-8b3e-3fc0ba487137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389830280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.2389830280
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.400435955
Short name T444
Test name
Test status
Simulation time 723824340 ps
CPU time 3.89 seconds
Started Jul 14 06:54:33 PM PDT 24
Finished Jul 14 06:54:40 PM PDT 24
Peak memory 208440 kb
Host smart-0eb1d396-10a7-43ac-92e3-c65d6f70644e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400435955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.400435955
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.3736657543
Short name T558
Test name
Test status
Simulation time 328110424 ps
CPU time 4.21 seconds
Started Jul 14 06:54:30 PM PDT 24
Finished Jul 14 06:54:38 PM PDT 24
Peak memory 208444 kb
Host smart-e6245a34-067d-4771-a998-ba2704e5a197
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736657543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.3736657543
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.3584478434
Short name T630
Test name
Test status
Simulation time 996954492 ps
CPU time 13.19 seconds
Started Jul 14 06:54:22 PM PDT 24
Finished Jul 14 06:54:38 PM PDT 24
Peak memory 222548 kb
Host smart-8e089f5a-022b-41b2-9a34-f65891bd52af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584478434 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.3584478434
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.2845900939
Short name T29
Test name
Test status
Simulation time 48586777 ps
CPU time 3.32 seconds
Started Jul 14 06:54:41 PM PDT 24
Finished Jul 14 06:54:46 PM PDT 24
Peak memory 209836 kb
Host smart-4633f8f0-f434-43f5-8340-e7187ba10691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845900939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.2845900939
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.415591111
Short name T365
Test name
Test status
Simulation time 228942888 ps
CPU time 1.67 seconds
Started Jul 14 06:54:37 PM PDT 24
Finished Jul 14 06:54:42 PM PDT 24
Peak memory 209932 kb
Host smart-d2aa6e1b-d45c-45cd-be53-ebea0d0890f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415591111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.415591111
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.3217805096
Short name T400
Test name
Test status
Simulation time 14985573 ps
CPU time 0.79 seconds
Started Jul 14 06:52:35 PM PDT 24
Finished Jul 14 06:52:37 PM PDT 24
Peak memory 206008 kb
Host smart-440a4f8a-6335-47f1-a4fb-d9d8b93d8760
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217805096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.3217805096
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.357955546
Short name T389
Test name
Test status
Simulation time 140503376 ps
CPU time 8.24 seconds
Started Jul 14 06:52:33 PM PDT 24
Finished Jul 14 06:52:43 PM PDT 24
Peak memory 214304 kb
Host smart-64ff1643-e8b0-4468-b621-429aecbfbb23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=357955546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.357955546
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.2041645166
Short name T531
Test name
Test status
Simulation time 576078205 ps
CPU time 4.99 seconds
Started Jul 14 06:52:31 PM PDT 24
Finished Jul 14 06:52:38 PM PDT 24
Peak memory 222856 kb
Host smart-5cb24ecb-c4e7-4d45-bc07-3823d190c062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041645166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.2041645166
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.2748974794
Short name T448
Test name
Test status
Simulation time 48716661 ps
CPU time 1.88 seconds
Started Jul 14 06:52:34 PM PDT 24
Finished Jul 14 06:52:38 PM PDT 24
Peak memory 207848 kb
Host smart-daa67195-6b2e-489c-ab0f-cb59ad76320c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748974794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.2748974794
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.1962198513
Short name T88
Test name
Test status
Simulation time 1382252222 ps
CPU time 10.61 seconds
Started Jul 14 06:52:32 PM PDT 24
Finished Jul 14 06:52:44 PM PDT 24
Peak memory 214340 kb
Host smart-9607f760-80d1-406e-b2cf-ff3dbcac753b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962198513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.1962198513
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.441447096
Short name T343
Test name
Test status
Simulation time 128158808 ps
CPU time 4.77 seconds
Started Jul 14 06:52:31 PM PDT 24
Finished Jul 14 06:52:38 PM PDT 24
Peak memory 207356 kb
Host smart-ffbfa4ed-9740-49cc-ae73-0f175c0ae583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441447096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.441447096
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.3435793913
Short name T56
Test name
Test status
Simulation time 176737151 ps
CPU time 3.76 seconds
Started Jul 14 06:52:34 PM PDT 24
Finished Jul 14 06:52:40 PM PDT 24
Peak memory 209472 kb
Host smart-0de3b92c-e1e3-4449-8996-56093e823a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435793913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.3435793913
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.1973162477
Short name T657
Test name
Test status
Simulation time 748130519 ps
CPU time 5.26 seconds
Started Jul 14 06:52:31 PM PDT 24
Finished Jul 14 06:52:38 PM PDT 24
Peak memory 207760 kb
Host smart-59a09377-815e-4315-bab7-7b5bf5903cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973162477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.1973162477
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.734280751
Short name T822
Test name
Test status
Simulation time 591772357 ps
CPU time 20.8 seconds
Started Jul 14 06:52:32 PM PDT 24
Finished Jul 14 06:52:55 PM PDT 24
Peak memory 208148 kb
Host smart-795b4f40-8a68-4c74-b2f2-ea1ba46b3d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734280751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.734280751
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.3515926154
Short name T740
Test name
Test status
Simulation time 4992500813 ps
CPU time 29.75 seconds
Started Jul 14 06:52:34 PM PDT 24
Finished Jul 14 06:53:06 PM PDT 24
Peak memory 208412 kb
Host smart-f5509a82-3eb2-4379-9c52-abb1247d6f5f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515926154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.3515926154
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.2066906462
Short name T578
Test name
Test status
Simulation time 119133103 ps
CPU time 2.3 seconds
Started Jul 14 06:52:31 PM PDT 24
Finished Jul 14 06:52:35 PM PDT 24
Peak memory 206984 kb
Host smart-2e4413f7-1107-4306-88ff-91b368f2758e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066906462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2066906462
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.3183756893
Short name T896
Test name
Test status
Simulation time 415395420 ps
CPU time 13.88 seconds
Started Jul 14 06:52:33 PM PDT 24
Finished Jul 14 06:52:50 PM PDT 24
Peak memory 207008 kb
Host smart-2b8524ed-55d1-4299-a3fe-22ab7cb326b7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183756893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.3183756893
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.1262753188
Short name T313
Test name
Test status
Simulation time 102580775 ps
CPU time 3.2 seconds
Started Jul 14 06:52:31 PM PDT 24
Finished Jul 14 06:52:36 PM PDT 24
Peak memory 209788 kb
Host smart-bab4abb8-632b-487c-b203-16a6d0d9375a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262753188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1262753188
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.2903334350
Short name T459
Test name
Test status
Simulation time 52247246 ps
CPU time 2.47 seconds
Started Jul 14 06:52:36 PM PDT 24
Finished Jul 14 06:52:40 PM PDT 24
Peak memory 207856 kb
Host smart-1802fb5e-8358-4b63-b614-396ff8639d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903334350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.2903334350
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.3591136935
Short name T124
Test name
Test status
Simulation time 182128259 ps
CPU time 9.33 seconds
Started Jul 14 06:52:33 PM PDT 24
Finished Jul 14 06:52:44 PM PDT 24
Peak memory 219972 kb
Host smart-96f7a533-1f87-4dba-9511-0254d72c0dad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591136935 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.3591136935
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.2241382100
Short name T705
Test name
Test status
Simulation time 859085703 ps
CPU time 17.46 seconds
Started Jul 14 06:52:34 PM PDT 24
Finished Jul 14 06:52:54 PM PDT 24
Peak memory 209064 kb
Host smart-82fddccb-e7d7-4e4c-acae-55ab6fa72711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241382100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.2241382100
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.1540587715
Short name T135
Test name
Test status
Simulation time 49956436 ps
CPU time 1.88 seconds
Started Jul 14 06:52:32 PM PDT 24
Finished Jul 14 06:52:37 PM PDT 24
Peak memory 210104 kb
Host smart-5005dc0a-e35d-4a15-84c7-6b93c7a54066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540587715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.1540587715
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.1504124948
Short name T798
Test name
Test status
Simulation time 15135164 ps
CPU time 0.89 seconds
Started Jul 14 06:52:32 PM PDT 24
Finished Jul 14 06:52:35 PM PDT 24
Peak memory 206132 kb
Host smart-1aa4dfb5-f486-4aad-b487-c8db90d74ae7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504124948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.1504124948
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.4254803569
Short name T119
Test name
Test status
Simulation time 218121279 ps
CPU time 3.95 seconds
Started Jul 14 06:52:32 PM PDT 24
Finished Jul 14 06:52:38 PM PDT 24
Peak memory 215468 kb
Host smart-bd840d05-a101-4b3c-adf7-c066faa1759d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4254803569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.4254803569
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2161565867
Short name T884
Test name
Test status
Simulation time 121365426 ps
CPU time 2.55 seconds
Started Jul 14 06:52:37 PM PDT 24
Finished Jul 14 06:52:42 PM PDT 24
Peak memory 221976 kb
Host smart-59163a47-ded3-4271-a137-a835d8325631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161565867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2161565867
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.3197817
Short name T295
Test name
Test status
Simulation time 300697417 ps
CPU time 4.11 seconds
Started Jul 14 06:52:33 PM PDT 24
Finished Jul 14 06:52:40 PM PDT 24
Peak memory 222492 kb
Host smart-1d8642a3-4125-4959-bcf3-62ec114dc9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.3197817
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.2437566599
Short name T736
Test name
Test status
Simulation time 136440534 ps
CPU time 3.84 seconds
Started Jul 14 06:52:31 PM PDT 24
Finished Jul 14 06:52:37 PM PDT 24
Peak memory 222540 kb
Host smart-5f264df2-84a7-4654-a436-3642d22b9e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437566599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2437566599
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.2703525886
Short name T269
Test name
Test status
Simulation time 175477601 ps
CPU time 2.29 seconds
Started Jul 14 06:52:30 PM PDT 24
Finished Jul 14 06:52:34 PM PDT 24
Peak memory 222524 kb
Host smart-a6d04fef-95fb-4d66-a9d8-8d3a24682389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703525886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.2703525886
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.1372639650
Short name T234
Test name
Test status
Simulation time 430411857 ps
CPU time 4.09 seconds
Started Jul 14 06:52:34 PM PDT 24
Finished Jul 14 06:52:40 PM PDT 24
Peak memory 209860 kb
Host smart-c8f675ef-79f6-4968-b3d0-e427ef4202cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372639650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.1372639650
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.3907251397
Short name T702
Test name
Test status
Simulation time 2216813566 ps
CPU time 11.02 seconds
Started Jul 14 06:52:33 PM PDT 24
Finished Jul 14 06:52:46 PM PDT 24
Peak memory 208640 kb
Host smart-ce8c62ad-b9be-461e-83b9-abf38e5b04e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907251397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.3907251397
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.3239124739
Short name T290
Test name
Test status
Simulation time 637787437 ps
CPU time 6.06 seconds
Started Jul 14 06:52:34 PM PDT 24
Finished Jul 14 06:52:42 PM PDT 24
Peak memory 206972 kb
Host smart-278e34db-1bfe-489b-b607-d8c44ccaf82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239124739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.3239124739
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.1944856010
Short name T887
Test name
Test status
Simulation time 185290940 ps
CPU time 4.86 seconds
Started Jul 14 06:52:32 PM PDT 24
Finished Jul 14 06:52:40 PM PDT 24
Peak memory 208128 kb
Host smart-b09c6566-dcc9-4bcd-adcf-4fce4d771322
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944856010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.1944856010
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.2754805417
Short name T216
Test name
Test status
Simulation time 139444626 ps
CPU time 3.28 seconds
Started Jul 14 06:52:35 PM PDT 24
Finished Jul 14 06:52:40 PM PDT 24
Peak memory 208888 kb
Host smart-bbd9d846-b0b2-43e9-a15d-7182846fffe7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754805417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2754805417
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.2942587059
Short name T811
Test name
Test status
Simulation time 60167734 ps
CPU time 3.03 seconds
Started Jul 14 06:52:32 PM PDT 24
Finished Jul 14 06:52:37 PM PDT 24
Peak memory 206800 kb
Host smart-71187fbf-c3c7-4345-b559-216b6167402f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942587059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.2942587059
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.3375851800
Short name T396
Test name
Test status
Simulation time 39340546 ps
CPU time 2.1 seconds
Started Jul 14 06:52:32 PM PDT 24
Finished Jul 14 06:52:35 PM PDT 24
Peak memory 207068 kb
Host smart-22d2dd54-cb3e-4e2f-9e4b-354b525f1988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375851800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.3375851800
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.1613084844
Short name T909
Test name
Test status
Simulation time 460800645 ps
CPU time 3.08 seconds
Started Jul 14 06:52:38 PM PDT 24
Finished Jul 14 06:52:43 PM PDT 24
Peak memory 207052 kb
Host smart-6f6ee047-f694-4869-8915-d17d2fdfc2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613084844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.1613084844
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.265087427
Short name T743
Test name
Test status
Simulation time 4755301434 ps
CPU time 47.36 seconds
Started Jul 14 06:52:35 PM PDT 24
Finished Jul 14 06:53:24 PM PDT 24
Peak memory 222556 kb
Host smart-1d222a52-d41b-4e21-8d1e-67432132b081
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265087427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.265087427
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.78141237
Short name T856
Test name
Test status
Simulation time 1412890098 ps
CPU time 10.63 seconds
Started Jul 14 06:52:34 PM PDT 24
Finished Jul 14 06:52:47 PM PDT 24
Peak memory 222600 kb
Host smart-a0e48fdb-a243-4e1a-9e74-7135332bd84a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78141237 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.78141237
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2890886213
Short name T215
Test name
Test status
Simulation time 143929577 ps
CPU time 4.85 seconds
Started Jul 14 06:52:38 PM PDT 24
Finished Jul 14 06:52:45 PM PDT 24
Peak memory 214392 kb
Host smart-d11c8d22-c0e4-448e-8a23-e3efc5330fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890886213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2890886213
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.4060373181
Short name T172
Test name
Test status
Simulation time 55317054 ps
CPU time 1.72 seconds
Started Jul 14 06:52:31 PM PDT 24
Finished Jul 14 06:52:34 PM PDT 24
Peak memory 210104 kb
Host smart-b3094be9-a76f-40e5-baf1-c4be794437b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060373181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.4060373181
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.919819038
Short name T820
Test name
Test status
Simulation time 67307247 ps
CPU time 0.81 seconds
Started Jul 14 06:52:37 PM PDT 24
Finished Jul 14 06:52:40 PM PDT 24
Peak memory 206064 kb
Host smart-3b5bf1c5-fbbf-40fd-b455-adc162c3639b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919819038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.919819038
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.1346237657
Short name T325
Test name
Test status
Simulation time 432527264 ps
CPU time 6.53 seconds
Started Jul 14 06:52:33 PM PDT 24
Finished Jul 14 06:52:42 PM PDT 24
Peak memory 214512 kb
Host smart-0f8e8637-a5bf-4730-832b-de30802a83a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1346237657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.1346237657
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.3636441512
Short name T690
Test name
Test status
Simulation time 3752261177 ps
CPU time 17 seconds
Started Jul 14 06:52:45 PM PDT 24
Finished Jul 14 06:53:03 PM PDT 24
Peak memory 214356 kb
Host smart-75ca506a-b50a-4beb-9e10-8268144a880b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636441512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.3636441512
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.169268702
Short name T26
Test name
Test status
Simulation time 12828995628 ps
CPU time 75.57 seconds
Started Jul 14 06:52:38 PM PDT 24
Finished Jul 14 06:53:55 PM PDT 24
Peak memory 214384 kb
Host smart-34fdc8e7-0a0c-4d08-8f12-5f1b4443f80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169268702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.169268702
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.3002597391
Short name T109
Test name
Test status
Simulation time 43333831 ps
CPU time 2.05 seconds
Started Jul 14 06:52:38 PM PDT 24
Finished Jul 14 06:52:43 PM PDT 24
Peak memory 214276 kb
Host smart-bfd47087-2efa-4ab0-ae8c-8f12d0d0effe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002597391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.3002597391
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.533058151
Short name T831
Test name
Test status
Simulation time 219887517 ps
CPU time 3.56 seconds
Started Jul 14 06:52:41 PM PDT 24
Finished Jul 14 06:52:46 PM PDT 24
Peak memory 214308 kb
Host smart-79a12b8f-5b1c-4c6b-b095-6e7791dd90da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533058151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.533058151
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.1961928841
Short name T852
Test name
Test status
Simulation time 20426594881 ps
CPU time 80.27 seconds
Started Jul 14 06:52:31 PM PDT 24
Finished Jul 14 06:53:53 PM PDT 24
Peak memory 222556 kb
Host smart-ff0f41e4-e6e5-4589-902e-16d249fb7b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961928841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1961928841
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.4178203034
Short name T379
Test name
Test status
Simulation time 73633706 ps
CPU time 3.43 seconds
Started Jul 14 06:52:32 PM PDT 24
Finished Jul 14 06:52:38 PM PDT 24
Peak memory 208716 kb
Host smart-0ca16eba-d3d1-4374-bd7f-a646f66497b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178203034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.4178203034
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.364859700
Short name T614
Test name
Test status
Simulation time 899674876 ps
CPU time 5.34 seconds
Started Jul 14 06:52:34 PM PDT 24
Finished Jul 14 06:52:41 PM PDT 24
Peak memory 208904 kb
Host smart-da3c2518-5430-449d-a428-a15c54c844b7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364859700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.364859700
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.3902827859
Short name T529
Test name
Test status
Simulation time 37089910 ps
CPU time 2.41 seconds
Started Jul 14 06:52:32 PM PDT 24
Finished Jul 14 06:52:37 PM PDT 24
Peak memory 207336 kb
Host smart-9d6c0da6-5b54-46b3-ae9f-b5eba1a7bcd8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902827859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.3902827859
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.216250855
Short name T618
Test name
Test status
Simulation time 301131471 ps
CPU time 3.37 seconds
Started Jul 14 06:52:32 PM PDT 24
Finished Jul 14 06:52:38 PM PDT 24
Peak memory 206932 kb
Host smart-565b8920-ce08-43ce-b6ad-f6789647b88a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216250855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.216250855
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.3986027789
Short name T635
Test name
Test status
Simulation time 247370745 ps
CPU time 2.73 seconds
Started Jul 14 06:52:38 PM PDT 24
Finished Jul 14 06:52:44 PM PDT 24
Peak memory 210128 kb
Host smart-d4c5a954-3411-4d42-ae10-d37cc39dd6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986027789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3986027789
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.2928173573
Short name T597
Test name
Test status
Simulation time 706702603 ps
CPU time 6.28 seconds
Started Jul 14 06:52:37 PM PDT 24
Finished Jul 14 06:52:46 PM PDT 24
Peak memory 206856 kb
Host smart-1f663aa5-0d78-4c5d-a8d3-661270c77b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928173573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.2928173573
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.3167144188
Short name T544
Test name
Test status
Simulation time 8427535581 ps
CPU time 48.05 seconds
Started Jul 14 06:52:38 PM PDT 24
Finished Jul 14 06:53:28 PM PDT 24
Peak memory 216508 kb
Host smart-5c931b44-ac30-4d2e-b1d1-32824b234db7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167144188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.3167144188
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2966469957
Short name T729
Test name
Test status
Simulation time 81076805 ps
CPU time 4.04 seconds
Started Jul 14 06:52:38 PM PDT 24
Finished Jul 14 06:52:44 PM PDT 24
Peak memory 209488 kb
Host smart-3fd9f27e-b49b-45ab-aa18-6c216f4c8695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966469957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2966469957
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3993218173
Short name T851
Test name
Test status
Simulation time 132187316 ps
CPU time 2.56 seconds
Started Jul 14 06:52:40 PM PDT 24
Finished Jul 14 06:52:44 PM PDT 24
Peak memory 210032 kb
Host smart-bf856589-6ee6-4351-b4a1-de5b7e2af941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993218173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3993218173
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.4089583444
Short name T95
Test name
Test status
Simulation time 151350053 ps
CPU time 0.74 seconds
Started Jul 14 06:52:38 PM PDT 24
Finished Jul 14 06:52:40 PM PDT 24
Peak memory 205892 kb
Host smart-d44c73e1-2c11-412a-b19e-69d6bebaa85f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089583444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.4089583444
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.3169559312
Short name T386
Test name
Test status
Simulation time 2819388987 ps
CPU time 13.29 seconds
Started Jul 14 06:52:39 PM PDT 24
Finished Jul 14 06:52:55 PM PDT 24
Peak memory 214408 kb
Host smart-c87f34c9-4170-4018-8ab4-2ab333d6b541
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3169559312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.3169559312
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.2893954889
Short name T621
Test name
Test status
Simulation time 74026980 ps
CPU time 2.83 seconds
Started Jul 14 06:52:38 PM PDT 24
Finished Jul 14 06:52:44 PM PDT 24
Peak memory 208196 kb
Host smart-d4e58be8-81f6-4ec1-ab6b-eb97f059d98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893954889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.2893954889
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.3937335502
Short name T266
Test name
Test status
Simulation time 88775263 ps
CPU time 2.14 seconds
Started Jul 14 06:52:39 PM PDT 24
Finished Jul 14 06:52:44 PM PDT 24
Peak memory 214224 kb
Host smart-2e52be84-82a7-4405-8564-5c94769858c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937335502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.3937335502
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.2943944113
Short name T795
Test name
Test status
Simulation time 1177080500 ps
CPU time 8.89 seconds
Started Jul 14 06:52:36 PM PDT 24
Finished Jul 14 06:52:46 PM PDT 24
Peak memory 214292 kb
Host smart-552e2266-38f5-4d4b-a762-14b4ee0f1685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943944113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.2943944113
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.1097360293
Short name T473
Test name
Test status
Simulation time 148262489 ps
CPU time 2.36 seconds
Started Jul 14 06:52:37 PM PDT 24
Finished Jul 14 06:52:41 PM PDT 24
Peak memory 214296 kb
Host smart-cb2b330f-8ae8-4c7b-ae0e-53e36f3ba8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097360293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.1097360293
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.80336084
Short name T667
Test name
Test status
Simulation time 320940296 ps
CPU time 2.64 seconds
Started Jul 14 06:52:40 PM PDT 24
Finished Jul 14 06:52:44 PM PDT 24
Peak memory 222488 kb
Host smart-fe6f2aec-5aaf-4dcb-90d0-d52a5754bf2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80336084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.80336084
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.3175989413
Short name T567
Test name
Test status
Simulation time 969766731 ps
CPU time 6.74 seconds
Started Jul 14 06:52:40 PM PDT 24
Finished Jul 14 06:52:48 PM PDT 24
Peak memory 209680 kb
Host smart-73e034b0-5930-412f-92a7-b74452dd31ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175989413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.3175989413
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.719942183
Short name T512
Test name
Test status
Simulation time 643992375 ps
CPU time 8.78 seconds
Started Jul 14 06:52:38 PM PDT 24
Finished Jul 14 06:52:49 PM PDT 24
Peak memory 208160 kb
Host smart-64988bdb-ce39-46f5-84d8-0617398822db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719942183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.719942183
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.3873763638
Short name T489
Test name
Test status
Simulation time 56066133 ps
CPU time 2.89 seconds
Started Jul 14 06:52:37 PM PDT 24
Finished Jul 14 06:52:42 PM PDT 24
Peak memory 207036 kb
Host smart-21e287b7-b4bd-4176-9780-36c89692c89c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873763638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.3873763638
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.2608512708
Short name T517
Test name
Test status
Simulation time 392244065 ps
CPU time 2.67 seconds
Started Jul 14 06:52:37 PM PDT 24
Finished Jul 14 06:52:40 PM PDT 24
Peak memory 206880 kb
Host smart-95fc0ced-fb4d-443f-beb7-552ff99c6471
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608512708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2608512708
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.3793479947
Short name T564
Test name
Test status
Simulation time 49496929 ps
CPU time 1.77 seconds
Started Jul 14 06:52:39 PM PDT 24
Finished Jul 14 06:52:43 PM PDT 24
Peak memory 206912 kb
Host smart-bb83657e-e701-458d-a973-f024412f08b2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793479947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.3793479947
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.2602633431
Short name T348
Test name
Test status
Simulation time 95126708 ps
CPU time 3.06 seconds
Started Jul 14 06:52:40 PM PDT 24
Finished Jul 14 06:52:45 PM PDT 24
Peak memory 209288 kb
Host smart-1edbe948-d1ef-4ea9-8e46-48d305d2a136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602633431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.2602633431
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.1313427770
Short name T534
Test name
Test status
Simulation time 25857526 ps
CPU time 1.82 seconds
Started Jul 14 06:52:37 PM PDT 24
Finished Jul 14 06:52:41 PM PDT 24
Peak memory 208472 kb
Host smart-9836a917-0f61-4ebc-bf89-efeb9b6fcca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313427770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.1313427770
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.2118147964
Short name T232
Test name
Test status
Simulation time 3301140246 ps
CPU time 23.43 seconds
Started Jul 14 06:52:38 PM PDT 24
Finished Jul 14 06:53:04 PM PDT 24
Peak memory 215868 kb
Host smart-56e79c27-772d-4e73-b1b0-94c28ad25fbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118147964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.2118147964
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.3867896226
Short name T806
Test name
Test status
Simulation time 758777536 ps
CPU time 7.28 seconds
Started Jul 14 06:52:39 PM PDT 24
Finished Jul 14 06:52:49 PM PDT 24
Peak memory 222612 kb
Host smart-e5ecf827-3c77-49aa-9e45-cb423f4c9dda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867896226 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.3867896226
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.2387510045
Short name T890
Test name
Test status
Simulation time 1478195569 ps
CPU time 8.72 seconds
Started Jul 14 06:52:38 PM PDT 24
Finished Jul 14 06:52:49 PM PDT 24
Peak memory 210280 kb
Host smart-f1861941-0631-4dcb-9959-094b635b0e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387510045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.2387510045
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.544272348
Short name T766
Test name
Test status
Simulation time 193837652 ps
CPU time 2.52 seconds
Started Jul 14 06:52:38 PM PDT 24
Finished Jul 14 06:52:43 PM PDT 24
Peak memory 210508 kb
Host smart-d72c2895-2686-4d51-af47-2af34e8eb407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544272348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.544272348
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.1660362019
Short name T96
Test name
Test status
Simulation time 68553769 ps
CPU time 0.85 seconds
Started Jul 14 06:52:45 PM PDT 24
Finished Jul 14 06:52:47 PM PDT 24
Peak memory 205996 kb
Host smart-64865325-5d46-4a07-9ff6-b794c8bc683b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660362019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.1660362019
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.3245686207
Short name T903
Test name
Test status
Simulation time 250155088 ps
CPU time 4.14 seconds
Started Jul 14 06:52:37 PM PDT 24
Finished Jul 14 06:52:43 PM PDT 24
Peak memory 215384 kb
Host smart-bc047d07-4102-4bd7-8e01-cdf671b5a209
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3245686207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3245686207
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.28233646
Short name T879
Test name
Test status
Simulation time 2213534061 ps
CPU time 19.1 seconds
Started Jul 14 06:52:42 PM PDT 24
Finished Jul 14 06:53:02 PM PDT 24
Peak memory 214728 kb
Host smart-c481b1a0-4cbd-4d9e-95c6-8ca16af993fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28233646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.28233646
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.3740000737
Short name T814
Test name
Test status
Simulation time 394672142 ps
CPU time 4.14 seconds
Started Jul 14 06:52:39 PM PDT 24
Finished Jul 14 06:52:45 PM PDT 24
Peak memory 210204 kb
Host smart-6dedea47-b728-4a98-9905-53e9afd7faab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740000737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.3740000737
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.2589222328
Short name T200
Test name
Test status
Simulation time 1334426601 ps
CPU time 3.21 seconds
Started Jul 14 06:52:45 PM PDT 24
Finished Jul 14 06:52:50 PM PDT 24
Peak memory 214356 kb
Host smart-99d8ed26-2b1f-42ca-a84c-ef9c7e6ea8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589222328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.2589222328
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.3526965576
Short name T237
Test name
Test status
Simulation time 106213223 ps
CPU time 4.24 seconds
Started Jul 14 06:52:40 PM PDT 24
Finished Jul 14 06:52:46 PM PDT 24
Peak memory 209312 kb
Host smart-779066c4-740b-479f-9c7d-12ed0ef2fbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526965576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.3526965576
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.3665367284
Short name T615
Test name
Test status
Simulation time 1520021438 ps
CPU time 10.61 seconds
Started Jul 14 06:52:38 PM PDT 24
Finished Jul 14 06:52:51 PM PDT 24
Peak memory 218440 kb
Host smart-ae6c99a8-1cd1-4d24-aef9-06f1120b29ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665367284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.3665367284
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.2504308290
Short name T713
Test name
Test status
Simulation time 1736712077 ps
CPU time 14.53 seconds
Started Jul 14 06:52:38 PM PDT 24
Finished Jul 14 06:52:55 PM PDT 24
Peak memory 208304 kb
Host smart-a8d51e6d-6b0c-4e0d-8573-b96b74af0738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504308290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.2504308290
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.544365827
Short name T776
Test name
Test status
Simulation time 10462501351 ps
CPU time 47.47 seconds
Started Jul 14 06:52:42 PM PDT 24
Finished Jul 14 06:53:31 PM PDT 24
Peak memory 208104 kb
Host smart-19cb3ae7-cd90-4d99-a1b1-c6f9ab23e2be
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544365827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.544365827
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.3789016359
Short name T443
Test name
Test status
Simulation time 90853533 ps
CPU time 1.91 seconds
Started Jul 14 06:52:43 PM PDT 24
Finished Jul 14 06:52:46 PM PDT 24
Peak memory 206988 kb
Host smart-b83a0600-7b30-4e0f-884c-f8195a4f834c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789016359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.3789016359
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.1762405388
Short name T397
Test name
Test status
Simulation time 34820057 ps
CPU time 2.25 seconds
Started Jul 14 06:52:40 PM PDT 24
Finished Jul 14 06:52:44 PM PDT 24
Peak memory 206972 kb
Host smart-da966a3c-6376-43a2-bae5-81c44ea63ae3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762405388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.1762405388
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.2557403388
Short name T901
Test name
Test status
Simulation time 296077390 ps
CPU time 4.07 seconds
Started Jul 14 06:52:40 PM PDT 24
Finished Jul 14 06:52:46 PM PDT 24
Peak memory 214304 kb
Host smart-947df0cb-1fea-406f-9ff6-13ede84d2a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557403388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.2557403388
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.1551861885
Short name T466
Test name
Test status
Simulation time 34721822 ps
CPU time 2.15 seconds
Started Jul 14 06:52:43 PM PDT 24
Finished Jul 14 06:52:46 PM PDT 24
Peak memory 206864 kb
Host smart-6e2b758e-8719-4bf6-8f64-105942db49cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551861885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1551861885
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.3225219818
Short name T572
Test name
Test status
Simulation time 2947128277 ps
CPU time 30.05 seconds
Started Jul 14 06:52:39 PM PDT 24
Finished Jul 14 06:53:11 PM PDT 24
Peak memory 218372 kb
Host smart-20b8ea56-94e6-4a40-81aa-121e910dbbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225219818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.3225219818
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.1300264316
Short name T136
Test name
Test status
Simulation time 183110115 ps
CPU time 5.22 seconds
Started Jul 14 06:52:47 PM PDT 24
Finished Jul 14 06:52:53 PM PDT 24
Peak memory 210420 kb
Host smart-24c77713-0d93-42de-bb06-d44966c50fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300264316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1300264316
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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