Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
68.25	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	19	30	61.22

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	2	12	85.71	100	1	1	0
state_x_op_cross	35	17	18	51.43	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	40	1			T12	1		T41	1		T42	1
auto[OpGenId]	13	1			T211	1		T212	1		T59	1
auto[OpGenSwOut]	21	1			T98	1		T193	1		T213	1
auto[OpGenHwOut]	13	1			T5	1		T6	1		T7	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1656	1			T12	1		T42	4		T104	4
auto[StInit]	92	1			T12	1		T27	1		T33	1
auto[StCreatorRootKey]	65	1			T2	1		T13	2		T104	1
auto[StOwnerIntKey]	51	1			T42	1		T53	1		T54	1
auto[StOwnerKey]	36	1			T13	1		T17	1		T49	1
auto[StDisabled]	457	1			T12	3		T13	2		T31	1
auto[StInvalid]	50	1			T14	1		T32	1		T46	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3411

1

T1

1

T2

2

T3

1

auto[1]

87

1

T12

1

T41

1

T42

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	2	12	85.71	2

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[1]]	0	1	1
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1656	1			T12	1		T42	4		T104	4
auto[StInit]	auto[0]	51	1			T27	1		T33	1		T18	1
auto[StInit]	auto[1]	41	1			T12	1		T6	1		T98	1
auto[StCreatorRootKey]	auto[0]	45	1			T2	1		T13	2		T104	1
auto[StCreatorRootKey]	auto[1]	20	1			T5	1		T212	1		T214	1
auto[StOwnerIntKey]	auto[0]	44	1			T53	1		T54	1		T38	1
auto[StOwnerIntKey]	auto[1]	7	1			T42	1		T215	1		T34	1
auto[StOwnerKey]	auto[0]	29	1			T13	1		T17	1		T49	1
auto[StOwnerKey]	auto[1]	7	1			T7	1		T59	1		T72	2
auto[StDisabled]	auto[0]	445	1			T12	3		T13	2		T31	1
auto[StDisabled]	auto[1]	12	1			T41	1		T62	1		T211	1
auto[StInvalid]	auto[0]	50	1			T14	1		T32	1		T46	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	17	18	51.43	17

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	*	--	--	5
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInit] , auto[StCreatorRootKey]]	[auto[OpDisable]]	--	--	2
[auto[StOwnerIntKey]]	[auto[OpGenHwOut] , auto[OpDisable]]	--	--	2
[auto[StOwnerKey]]	[auto[OpAdvance]]	0	1	1
[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[StDisabled]]	[auto[OpDisable]]	0	1	1

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StInit]	auto[OpAdvance]	20	1			T12	1		T49	3		T216	1
auto[StInit]	auto[OpGenId]	5	1			T217	1		T218	1		T219	1
auto[StInit]	auto[OpGenSwOut]	10	1			T98	1		T193	1		T70	1
auto[StInit]	auto[OpGenHwOut]	6	1			T6	1		T220	1		T36	1
auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T214	1		T35	1		T221	1
auto[StCreatorRootKey]	auto[OpGenId]	2	1			T212	1		T222	1		-	-
auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T213	1		T223	1		T224	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	4	1			T5	1		T225	1		T226	1
auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T42	1		T215	1		T34	1
auto[StOwnerIntKey]	auto[OpGenId]	1	1			T124	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpGenSwOut]	1	1			T227	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenId]	3	1			T59	1		T72	1		T228	1
auto[StOwnerKey]	auto[OpGenSwOut]	2	1			T72	1		T229	1		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	2	1			T7	1		T230	1		-	-
auto[StDisabled]	auto[OpAdvance]	6	1			T41	1		T62	1		T72	1
auto[StDisabled]	auto[OpGenId]	2	1			T211	1		T231	1		-	-
auto[StDisabled]	auto[OpGenSwOut]	3	1			T70	1		T232	1		T233	1
auto[StDisabled]	auto[OpGenHwOut]	1	1			T234	1		-	-		-	-