Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
81.10	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	72	258	78.18

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	53	227	81.07	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4875

1

T1

12

T2

5

T3

7

auto[1]

573

1

T4

1

T16

2

T40

4

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4875

1

T1

12

T2

5

T3

7

auto[1]

573

1

T4

1

T16

2

T40

4

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4875

1

T1

9

T2

5

T3

7

auto[1]

573

1

T1

3

T12

1

T15

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4875

1

T1

9

T2

5

T3

7

auto[1]

573

1

T1

3

T12

1

T15

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	428	1			T3	3		T4	2		T13	2
auto[OpGenId]	1144	1			T2	2		T3	2		T12	2
auto[OpGenSwOut]	1189	1			T3	1		T4	1		T12	2
auto[OpGenHwOut]	2603	1			T1	12		T2	3		T3	1
auto[OpDisable]	84	1			T42	2		T44	1		T55	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	428	1			T3	3		T4	2		T13	2
auto[OpGenId]	1144	1			T2	2		T3	2		T12	2
auto[OpGenSwOut]	1189	1			T3	1		T4	1		T12	2
auto[OpGenHwOut]	2603	1			T1	12		T2	3		T3	1
auto[OpDisable]	84	1			T42	2		T44	1		T55	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4908

1

T1

12

T2

5

T3

7

auto[1]

540

1

T4

1

T12

3

T16

2

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4908

1

T1

12

T2

5

T3

7

auto[1]

540

1

T4

1

T12

3

T16

2

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5171

1

T1

12

T2

5

T3

7

auto[1]

277

1

T131

2

T146

13

T132

2

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1883	1			T1	3		T2	2		T3	2
auto[1]	666	1			T1	2		T3	1		T12	1
auto[2]	714	1			T1	3		T12	1		T13	3
auto[3]	744	1			T1	1		T3	1		T12	3
auto[4]	351	1			T1	2		T15	1		T16	1
auto[5]	385	1			T1	1		T2	1		T3	2
auto[6]	353	1			T2	2		T4	1		T13	2
auto[7]	352	1			T3	1		T4	1		T13	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1441	1			T1	3		T2	3		T3	3
clear_one[1]	666	1			T1	2		T3	1		T12	1
clear_one[2]	714	1			T1	3		T12	1		T13	3
clear_one[3]	744	1			T1	1		T3	1		T12	3
clear_none	1883	1			T1	3		T2	2		T3	2

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1026	1			T1	4		T2	4		T3	2
auto[StInit]	680	1			T1	1		T2	1		T3	1
auto[StCreatorRootKey]	613	1			T1	1		T3	1		T13	4
auto[StOwnerIntKey]	517	1			T1	1		T12	2		T13	1
auto[StOwnerKey]	474	1			T1	1		T3	1		T13	1
auto[StDisabled]	1877	1			T1	4		T3	2		T4	3
auto[StInvalid]	261	1			T14	2		T32	6		T45	6

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1026	1			T1	4		T2	4		T3	2
auto[StInit]	680	1			T1	1		T2	1		T3	1
auto[StCreatorRootKey]	613	1			T1	1		T3	1		T13	4
auto[StOwnerIntKey]	517	1			T1	1		T12	2		T13	1
auto[StOwnerKey]	474	1			T1	1		T3	1		T13	1
auto[StDisabled]	1877	1			T1	4		T3	2		T4	3
auto[StInvalid]	261	1			T14	2		T32	6		T45	6

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	53	227	81.07	53

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[2]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	15
[auto[0] - auto[2]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3
[auto[3] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	5
[auto[3] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	5
[auto[3] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	20
[auto[3] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	5

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	2	1			T235	1		T236	1		-	-
auto[0]	auto[StReset]	auto[OpGenId]	158	1			T31	1		T42	1		T55	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	174	1			T12	1		T13	1		T32	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	288	1			T1	1		T2	2		T3	1
auto[0]	auto[StInit]	auto[OpAdvance]	42	1			T16	1		T84	1		T146	1
auto[0]	auto[StInit]	auto[OpGenId]	101	1			T13	1		T15	1		T21	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	101	1			T13	1		T42	3		T18	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	190	1			T1	1		T13	1		T40	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	15	1			T49	1		T54	1		T192	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	50	1			T41	1		T88	1		T146	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	51	1			T43	1		T112	1		T146	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	83	1			T42	1		T203	1		T237	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	11	1			T238	1		T239	1		T240	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	31	1			T31	1		T84	1		T146	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	32	1			T62	1		T23	1		T54	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	44	1			T12	1		T126	1		T146	2
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	15	1			T23	1		T241	1		T193	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	18	1			T19	1		T242	1		T69	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	26	1			T42	1		T61	1		T62	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	48	1			T1	1		T243	1		T49	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	28	1			T3	1		T4	1		T13	1
auto[0]	auto[StDisabled]	auto[OpGenId]	59	1			T88	1		T22	1		T49	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	63	1			T42	1		T22	1		T242	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	168	1			T16	1		T206	1		T146	1
auto[0]	auto[StDisabled]	auto[OpDisable]	20	1			T42	1		T55	1		T50	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	7	1			T244	1		T245	1		T246	1
auto[0]	auto[StInvalid]	auto[OpGenId]	21	1			T45	1		T46	1		T247	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	16	1			T14	1		T89	1		T248	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	21	1			T32	1		T99	1		T249	1
auto[1]	auto[StReset]	auto[OpAdvance]	1	1			T250	1		-	-		-	-
auto[1]	auto[StReset]	auto[OpGenId]	21	1			T129	1		T251	1		T85	2
auto[1]	auto[StReset]	auto[OpGenSwOut]	12	1			T55	1		T98	1		T20	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	34	1			T1	1		T203	1		T237	1
auto[1]	auto[StInit]	auto[OpAdvance]	8	1			T137	2		T252	1		T96	1
auto[1]	auto[StInit]	auto[OpGenId]	10	1			T133	1		T253	1		T254	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	12	1			T20	1		T91	2		T69	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	15	1			T208	1		T255	1		T256	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T53	1		T135	1		T20	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T49	1		T137	1		T257	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	18	1			T13	1		T258	2		T259	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	58	1			T1	1		T129	1		T42	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	9	1			T49	1		T70	1		T260	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T94	1		T261	1		T192	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T122	1		T158	1		T262	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	42	1			T203	1		T263	1		T264	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T265	1		T266	1		T267	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	11	1			T84	1		T200	1		T268	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T41	1		T269	1		T270	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	38	1			T13	1		T206	1		T203	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	23	1			T49	1		T62	1		T265	1
auto[1]	auto[StDisabled]	auto[OpGenId]	43	1			T3	1		T12	1		T112	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	58	1			T84	1		T42	1		T61	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	153	1			T42	1		T208	1		T206	1
auto[1]	auto[StDisabled]	auto[OpDisable]	9	1			T271	1		T272	1		T193	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	5	1			T273	1		T274	1		T275	1
auto[1]	auto[StInvalid]	auto[OpGenId]	9	1			T45	1		T276	1		T86	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	16	1			T32	1		T45	1		T89	2
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T32	2		T248	1		T246	1
auto[2]	auto[StReset]	auto[OpAdvance]	2	1			T277	2		-	-		-	-
auto[2]	auto[StReset]	auto[OpGenId]	14	1			T32	1		T42	1		T78	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	22	1			T42	1		T62	1		T211	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	44	1			T1	1		T32	1		T60	1
auto[2]	auto[StInit]	auto[OpAdvance]	9	1			T216	1		T34	1		T124	1
auto[2]	auto[StInit]	auto[OpGenId]	9	1			T200	1		T211	1		T26	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	5	1			T93	1		T278	1		T219	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	22	1			T13	1		T21	1		T279	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T13	1		T258	1		T265	2
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	15	1			T133	2		T280	1		T168	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T110	1		T205	1		T168	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	41	1			T40	1		T281	1		T282	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	9	1			T42	1		T90	1		T110	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	14	1			T22	1		T59	1		T283	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	18	1			T43	1		T258	2		T265	3
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	41	1			T206	1		T49	1		T82	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T129	1		T49	1		T284	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	12	1			T265	1		T285	1		T192	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T265	1		T280	1		T286	2
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	44	1			T40	1		T133	1		T211	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	25	1			T131	1		T49	1		T111	1
auto[2]	auto[StDisabled]	auto[OpGenId]	77	1			T13	1		T16	1		T41	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	59	1			T12	1		T129	1		T42	2
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	136	1			T1	2		T40	1		T42	1
auto[2]	auto[StDisabled]	auto[OpDisable]	14	1			T42	1		T62	1		T193	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	5	1			T46	1		T287	1		T288	1
auto[2]	auto[StInvalid]	auto[OpGenId]	11	1			T45	1		T273	1		T245	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	17	1			T249	1		T80	1		T289	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T14	1		T89	1		T247	1
auto[3]	auto[StReset]	auto[OpGenId]	16	1			T42	1		T112	1		T123	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	23	1			T47	1		T202	1		T108	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	40	1			T208	1		T98	1		T243	1
auto[3]	auto[StInit]	auto[OpAdvance]	6	1			T42	1		T290	1		T291	1
auto[3]	auto[StInit]	auto[OpGenId]	12	1			T44	1		T108	1		T286	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	8	1			T3	1		T23	1		T258	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	30	1			T55	1		T243	1		T203	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T21	1		T65	1		T254	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	15	1			T251	1		T205	1		T123	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	15	1			T13	1		T42	2		T55	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	39	1			T208	1		T255	1		T292	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T131	1		T146	1		T91	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	17	1			T205	1		T65	2		T63	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T15	1		T293	1		T268	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	43	1			T1	1		T12	1		T41	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T137	2		T194	1		T254	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	19	1			T31	1		T55	1		T146	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T294	1		T69	1		T254	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	39	1			T53	1		T24	1		T204	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	33	1			T109	1		T110	1		T111	1
auto[3]	auto[StDisabled]	auto[OpGenId]	65	1			T12	1		T42	4		T112	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	62	1			T13	1		T16	1		T42	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	166	1			T12	1		T15	1		T40	1
auto[3]	auto[StDisabled]	auto[OpDisable]	16	1			T253	1		T217	1		T295	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	9	1			T80	1		T245	1		T288	1
auto[3]	auto[StInvalid]	auto[OpGenId]	16	1			T45	1		T249	1		T289	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T89	1		T85	1		T296	2
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T248	1		T85	1		T274	1
auto[4]	auto[StReset]	auto[OpGenId]	10	1			T44	1		T205	1		T297	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	8	1			T205	1		T294	1		T123	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	24	1			T1	1		T83	2		T298	1
auto[4]	auto[StInit]	auto[OpAdvance]	2	1			T299	1		T300	1		-	-
auto[4]	auto[StInit]	auto[OpGenId]	7	1			T49	1		T301	1		T302	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	5	1			T205	1		T103	1		T303	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	12	1			T31	1		T304	1		T305	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T306	1		T307	1		-	-
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	14	1			T16	1		T122	1		T306	2
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T308	1		T253	1		T309	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	15	1			T243	1		T108	1		T310	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T266	1		T71	1		T311	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T69	1		T312	1		T185	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T65	1		T313	1		T168	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	13	1			T314	1		T315	1		T316	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	1	1			T196	1		-	-		-	-
auto[4]	auto[StOwnerKey]	auto[OpGenId]	8	1			T205	1		T317	1		T318	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T319	1		T65	1		T59	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	33	1			T42	1		T208	1		T112	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	6	1			T108	1		T65	1		T320	1
auto[4]	auto[StDisabled]	auto[OpGenId]	23	1			T15	1		T49	2		T321	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	28	1			T126	1		T44	1		T49	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	80	1			T1	1		T40	1		T206	1
auto[4]	auto[StDisabled]	auto[OpDisable]	6	1			T44	1		T60	1		T193	2
auto[4]	auto[StInvalid]	auto[OpAdvance]	2	1			T207	1		T322	1		-	-
auto[4]	auto[StInvalid]	auto[OpGenId]	6	1			T276	1		T323	1		T324	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T287	1		T207	1		T325	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T326	1		T327	1		T245	1
auto[5]	auto[StReset]	auto[OpGenId]	12	1			T2	1		T3	1		T90	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	7	1			T216	1		T328	1		T329	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	23	1			T112	1		T133	1		T292	1
auto[5]	auto[StInit]	auto[OpAdvance]	5	1			T209	1		T314	1		T330	3
auto[5]	auto[StInit]	auto[OpGenId]	4	1			T77	1		T92	1		T331	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	7	1			T132	1		T78	1		T192	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	8	1			T332	1		T194	1		T333	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T3	1		T269	1		T270	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T217	1		T334	1		T335	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	14	1			T132	2		T56	1		T293	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	19	1			T205	1		T216	1		T34	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T205	1		T124	1		T307	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T42	1		T205	1		T319	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	18	1			T235	1		T270	1		T336	3
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	20	1			T204	1		T332	1		T337	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T320	1		T219	1		T307	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	10	1			T126	1		T79	1		T205	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T21	1		T90	1		T111	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	19	1			T15	1		T49	1		T337	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	11	1			T42	1		T338	1		T339	1
auto[5]	auto[StDisabled]	auto[OpGenId]	23	1			T126	1		T205	1		T216	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	24	1			T53	1		T235	2		T340	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	89	1			T1	1		T40	1		T42	1
auto[5]	auto[StDisabled]	auto[OpDisable]	8	1			T293	1		T341	1		T254	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	6	1			T32	1		T86	1		T342	1
auto[5]	auto[StInvalid]	auto[OpGenId]	8	1			T244	2		T328	1		T343	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T276	1		T296	1		T344	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T32	1		T289	1		T345	1
auto[6]	auto[StReset]	auto[OpGenId]	8	1			T216	1		T346	1		T347	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	12	1			T326	1		T65	1		T348	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	26	1			T2	1		T255	1		T279	1
auto[6]	auto[StInit]	auto[OpAdvance]	3	1			T349	1		T350	1		T351	1
auto[6]	auto[StInit]	auto[OpGenId]	6	1			T2	1		T280	1		T209	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	5	1			T205	1		T352	1		T353	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	14	1			T111	1		T354	1		T337	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T131	1		T252	2		T192	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T355	1		T196	1		T71	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T195	1		T184	1		T196	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	16	1			T42	1		T90	1		T356	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T21	1		T241	1		T357	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	13	1			T252	1		T358	1		T195	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T7	1		T192	1		T168	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	18	1			T13	1		T135	1		T359	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T349	1		T360	1		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenId]	7	1			T42	1		T235	1		T336	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T125	1		T361	1		T362	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	27	1			T42	1		T237	1		T107	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	15	1			T4	1		T90	1		T146	2
auto[6]	auto[StDisabled]	auto[OpGenId]	31	1			T42	1		T146	3		T205	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	25	1			T13	1		T308	1		T193	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	70	1			T129	1		T206	1		T146	3
auto[6]	auto[StDisabled]	auto[OpDisable]	3	1			T67	1		T72	1		T363	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	3	1			T364	1		T365	1		T366	1
auto[6]	auto[StInvalid]	auto[OpGenId]	2	1			T367	1		T324	1		-	-
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T99	1		T244	1		T85	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T368	1		T369	1		T370	1
auto[7]	auto[StReset]	auto[OpGenId]	3	1			T32	1		T70	1		T371	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	18	1			T42	1		T91	1		T34	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	24	1			T208	1		T62	1		T332	2
auto[7]	auto[StInit]	auto[OpAdvance]	1	1			T311	1		-	-		-	-
auto[7]	auto[StInit]	auto[OpGenId]	9	1			T22	1		T372	1		T123	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	3	1			T297	1		T221	1		T229	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	9	1			T373	1		T374	1		T375	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T133	1		T62	1		T269	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T13	1		T265	1		T372	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T376	1		T193	1		T260	3
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	22	1			T206	1		T107	1		T204	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T158	1		T71	1		-	-
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T109	1		T70	1		T260	3
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T42	1		T267	1		T377	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	27	1			T40	1		T42	1		T133	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	1	1			T3	1		-	-		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenId]	3	1			T112	1		T378	2		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T62	1		T378	1		T379	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	9	1			T380	1		T375	1		T381	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	12	1			T90	1		T132	1		T192	1
auto[7]	auto[StDisabled]	auto[OpGenId]	22	1			T16	1		T112	1		T109	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	43	1			T4	1		T49	1		T205	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	73	1			T84	1		T237	1		T107	2
auto[7]	auto[StDisabled]	auto[OpDisable]	8	1			T205	1		T68	1		T158	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	5	1			T45	1		T327	1		T296	1
auto[7]	auto[StInvalid]	auto[OpGenId]	3	1			T382	1		T383	1		T384	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	2	1			T80	1		T246	1		-	-
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T80	1		T325	1		T85	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1441

1

T1

3

T2

3

T3

3

clear_one[1]

auto[0]

auto[0]

auto[0]

367

1

T1

1

T3

1

T13

2

clear_one[1]

auto[0]

auto[0]

auto[1]

132

1

T12

1

T42

2

T208

1

clear_one[1]

auto[0]

auto[1]

auto[0]

131

1

T1

1

T84

1

T41

1

clear_one[1]

auto[0]

auto[1]

auto[1]

36

1

T61

1

T135

1

T265

1

clear_one[2]

auto[0]

auto[0]

auto[0]

427

1

T1

3

T13

3

T14

1

clear_one[2]

auto[0]

auto[0]

auto[1]

113

1

T12

1

T208

1

T237

1

clear_one[2]

auto[1]

auto[0]

auto[0]

136

1

T40

3

T129

2

T42

1

clear_one[2]

auto[1]

auto[0]

auto[1]

38

1

T16

1

T42

1

T54

1

clear_one[3]

auto[0]

auto[0]

auto[0]

431

1

T3

1

T12

2

T13

2

clear_one[3]

auto[0]

auto[1]

auto[0]

133

1

T1

1

T12

1

T15

1

clear_one[3]

auto[1]

auto[0]

auto[0]

127

1

T16

1

T40

1

T42

2

clear_one[3]

auto[1]

auto[1]

auto[0]

53

1

T55

1

T49

1

T251

1

clear_none

auto[0]

auto[0]

auto[0]

1361

1

T1

2

T2

2

T3

2

clear_none

auto[0]

auto[0]

auto[1]

136

1

T12

1

T16

1

T146

3

clear_none

auto[0]

auto[1]

auto[0]

123

1

T1

1

T43

1

T206

1

clear_none

auto[0]

auto[1]

auto[1]

44

1

T61

1

T22

2

T49

1

clear_none

auto[1]

auto[0]

auto[0]

138

1

T88

1

T146

1

T203

3

clear_none

auto[1]

auto[0]

auto[1]

28

1

T4

1

T19

1

T146

1

clear_none

auto[1]

auto[1]

auto[0]

40

1

T55

1

T53

1

T136

5

clear_none

auto[1]

auto[1]

auto[1]

13

1

T59

1

T69

1

T253

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1344	1			T1	3		T2	3		T3	3
clear_all	auto[1]	97	1			T146	8		T132	1		T133	1
clear_one[1]	auto[0]	640	1			T1	2		T3	1		T12	1
clear_one[1]	auto[1]	26	1			T133	1		T137	2		T258	1
clear_one[2]	auto[0]	669	1			T1	3		T12	1		T13	3
clear_one[2]	auto[1]	45	1			T131	1		T132	1		T133	1
clear_one[3]	auto[0]	700	1			T1	1		T3	1		T12	3
clear_one[3]	auto[1]	44	1			T131	1		T146	1		T133	2
clear_none	auto[0]	1818	1			T1	3		T2	2		T3	2
clear_none	auto[1]	65	1			T146	4		T235	2		T136	9