Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11430

1

T1

13

T2

14

T3

11

auto[Attestation]

7735

1

T1

5

T2

1

T3

3

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2834	1			T2	1		T3	2		T4	4
auto[Aes]	3345	1			T2	1		T3	2		T4	4
auto[Kmac]	3480	1			T1	18		T2	2		T3	2
auto[Otbn]	3456	1			T2	3		T3	2		T4	3

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7676	1			T1	8		T2	2		T3	8
auto[OpGenId]	6050	1			T2	8		T3	6		T4	1
auto[OpGenSwOut]	5892	1			T2	3		T3	5		T4	8
auto[OpGenHwOut]	7223	1			T1	18		T2	4		T3	3
auto[OpDisable]	154	1			T43	1		T42	2		T44	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10861

1

T1

8

T2

2

T3

7

auto[OpDoneFail]

16134

1

T1

18

T2

15

T3

15

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6705	1			T1	11		T2	14		T3	5
auto[StInit]	3788	1			T1	2		T2	3		T3	5
auto[StCreatorRootKey]	3338	1			T1	2		T3	1		T4	6
auto[StOwnerIntKey]	2773	1			T1	2		T3	3		T4	3
auto[StOwnerKey]	2485	1			T1	2		T3	1		T4	1
auto[StDisabled]	7906	1			T1	7		T3	7		T4	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	336	1			T2	1		T32	1		T84	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	117	1			T12	1		T13	1		T129	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	87	1			T13	1		T43	1		T130	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	80	1			T3	1		T17	1		T42	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	51	1			T88	1		T42	1		T49	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	216	1			T3	1		T4	2		T13	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	333	1			T2	1		T32	3		T88	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	100	1			T3	1		T4	1		T129	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	95	1			T4	1		T13	1		T42	4
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	71	1			T13	1		T16	1		T31	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	55	1			T41	1		T90	1		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	188	1			T3	1		T12	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	332	1			T2	1		T12	1		T13	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	113	1			T129	1		T21	2		T41	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	94	1			T13	1		T42	1		T49	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	75	1			T13	1		T31	1		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	56	1			T13	1		T17	1		T31	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	185	1			T84	1		T129	1		T42	4
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	305	1			T12	2		T129	1		T33	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	109	1			T4	1		T129	1		T33	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	88	1			T13	1		T90	1		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	59	1			T42	1		T111	1		T200	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	58	1			T146	1		T108	1		T54	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	236	1			T13	2		T84	1		T128	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	88	1			T12	2		T42	2		T49	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	116	1			T4	1		T126	1		T42	4
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	84	1			T12	1		T126	1		T42	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	65	1			T4	1		T49	1		T111	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	68	1			T21	1		T42	2		T61	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	233	1			T16	1		T129	1		T88	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	81	1			T13	2		T32	1		T42	6
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	83	1			T13	1		T17	1		T21	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	74	1			T42	1		T19	1		T112	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	69	1			T16	1		T42	1		T49	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	66	1			T12	2		T21	2		T41	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	221	1			T13	1		T42	6		T201	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	80	1			T12	3		T13	1		T32	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	99	1			T3	1		T44	1		T55	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	87	1			T4	1		T12	2		T13	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	85	1			T12	1		T13	1		T202	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	53	1			T12	1		T13	1		T42	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	217	1			T12	1		T84	1		T42	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	62	1			T13	1		T32	1		T42	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	86	1			T13	1		T104	1		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	86	1			T13	2		T42	1		T62	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	75	1			T15	1		T16	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	67	1			T31	1		T42	1		T146	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	208	1			T84	2		T126	1		T42	4
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	276	1			T126	1		T129	1		T33	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	86	1			T12	2		T32	1		T43	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	97	1			T42	4		T90	1		T49	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	59	1			T126	1		T41	1		T88	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	37	1			T88	1		T42	2		T90	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	202	1			T13	1		T129	2		T88	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	504	1			T31	1		T32	2		T84	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	121	1			T4	1		T55	1		T131	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	103	1			T4	1		T40	1		T130	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	93	1			T129	1		T146	1		T203	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	100	1			T88	1		T49	1		T204	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	264	1			T16	1		T40	1		T43	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	537	1			T1	10		T2	1		T32	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	141	1			T1	1		T12	1		T31	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	136	1			T43	1		T130	1		T42	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	91	1			T1	1		T3	1		T13	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	80	1			T1	1		T41	1		T112	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	255	1			T4	1		T84	1		T88	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	529	1			T2	3		T3	1		T42	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	116	1			T13	1		T43	1		T130	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	119	1			T4	1		T42	3		T49	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	97	1			T12	1		T13	1		T42	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	91	1			T13	1		T42	1		T55	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	304	1			T12	1		T15	1		T16	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	70	1			T12	1		T32	2		T42	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	91	1			T88	1		T42	2		T131	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	78	1			T129	1		T88	1		T42	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	58	1			T22	1		T49	1		T53	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	66	1			T13	1		T42	2		T49	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	173	1			T13	1		T129	1		T42	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	60	1			T13	1		T32	1		T49	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	96	1			T13	1		T40	1		T131	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	114	1			T13	1		T42	2		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	80	1			T40	1		T49	1		T108	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	82	1			T40	1		T88	1		T42	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	292	1			T16	1		T40	3		T129	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	57	1			T12	2		T42	2		T205	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	115	1			T32	1		T43	1		T21	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	121	1			T1	1		T15	1		T130	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	101	1			T49	2		T107	1		T108	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	97	1			T13	1		T15	1		T206	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	273	1			T1	4		T4	1		T12	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	63	1			T49	2		T205	2		T207	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	111	1			T12	1		T13	1		T43	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	126	1			T130	3		T42	1		T90	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	89	1			T4	1		T12	1		T42	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	90	1			T42	1		T208	1		T108	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	282	1			T3	1		T12	1		T42	2

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	202	1			T3	1		T13	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	685	1			T2	1		T3	1		T4	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	204	1			T4	1		T13	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	638	1			T2	1		T3	2		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	209	1			T13	3		T17	1		T31	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	646	1			T2	1		T12	1		T13	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	197	1			T13	1		T90	1		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	658	1			T4	1		T12	2		T13	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	200	1			T4	1		T12	1		T126	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	454	1			T4	1		T12	2		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	197	1			T12	2		T16	1		T21	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	397	1			T13	4		T17	1		T32	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	212	1			T4	1		T12	4		T13	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	409	1			T3	1		T12	4		T13	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	212	1			T13	1		T15	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	372	1			T13	3		T32	1		T84	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	181	1			T126	1		T41	1		T88	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	576	1			T12	2		T13	1		T32	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	273	1			T4	1		T40	1		T129	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	912	1			T4	1		T16	1		T31	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	295	1			T1	2		T3	1		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	945	1			T1	11		T2	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	286	1			T4	1		T12	1		T42	7
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	970	1			T2	3		T3	1		T12	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	187	1			T13	1		T129	1		T88	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	349	1			T12	1		T13	1		T32	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	265	1			T13	1		T40	2		T88	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	459	1			T13	2		T16	1		T32	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	299	1			T1	1		T13	1		T15	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	465	1			T1	4		T4	1		T12	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	290	1			T4	1		T12	1		T130	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	471	1			T3	1		T12	2		T13	1