Unified Coverage Report :: Group Instance : attest_sw_binding_2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32886

1

T1

31

T2

18

T3

27

auto[1]

276

1

T131

1

T146

3

T132

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	32898	1			T1	31		T2	18		T3	27
auto[134217728:268435455]	11	1			T146	1		T132	1		T235	2
auto[268435456:402653183]	12	1			T132	1		T133	1		T137	2
auto[402653184:536870911]	7	1			T146	1		T133	1		T378	1
auto[536870912:671088639]	7	1			T133	1		T252	1		T415	1
auto[671088640:805306367]	7	1			T133	1		T306	1		T340	1
auto[805306368:939524095]	11	1			T136	1		T137	1		T336	1
auto[939524096:1073741823]	12	1			T235	1		T306	1		T349	1
auto[1073741824:1207959551]	7	1			T132	1		T238	1		T260	1
auto[1207959552:1342177279]	8	1			T131	1		T266	1		T306	1
auto[1342177280:1476395007]	11	1			T137	3		T239	1		T349	1
auto[1476395008:1610612735]	10	1			T133	1		T235	1		T258	1
auto[1610612736:1744830463]	7	1			T137	1		T266	1		T239	1
auto[1744830464:1879048191]	7	1			T336	1		T266	1		T239	1
auto[1879048192:2013265919]	4	1			T378	1		T277	1		T250	1
auto[2013265920:2147483647]	11	1			T137	1		T252	1		T286	1
auto[2147483648:2281701375]	6	1			T133	2		T235	2		T320	1
auto[2281701376:2415919103]	11	1			T252	2		T285	1		T306	2
auto[2415919104:2550136831]	11	1			T133	1		T136	1		T258	1
auto[2550136832:2684354559]	6	1			T133	2		T286	1		T416	1
auto[2684354560:2818572287]	6	1			T133	1		T137	2		T349	1
auto[2818572288:2952790015]	9	1			T133	2		T235	1		T336	1
auto[2952790016:3087007743]	14	1			T133	2		T137	2		T252	2
auto[3087007744:3221225471]	11	1			T252	1		T266	1		T340	1
auto[3221225472:3355443199]	6	1			T349	1		T417	1		T418	1
auto[3355443200:3489660927]	8	1			T252	1		T286	1		T306	1
auto[3489660928:3623878655]	10	1			T137	1		T252	1		T286	1
auto[3623878656:3758096383]	5	1			T137	1		T252	1		T285	1
auto[3758096384:3892314111]	8	1			T135	1		T136	1		T306	1
auto[3892314112:4026531839]	7	1			T320	1		T378	1		T291	1
auto[4026531840:4160749567]	3	1			T252	1		T419	2		-	-
auto[4160749568:4294967295]	11	1			T133	1		T136	1		T266	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	32886	1			T1	31		T2	18		T3	27
auto[0:134217727]	auto[1]	12	1			T146	1		T286	1		T241	1
auto[134217728:268435455]	auto[1]	11	1			T146	1		T132	1		T235	2
auto[268435456:402653183]	auto[1]	12	1			T132	1		T133	1		T137	2
auto[402653184:536870911]	auto[1]	7	1			T146	1		T133	1		T378	1
auto[536870912:671088639]	auto[1]	7	1			T133	1		T252	1		T415	1
auto[671088640:805306367]	auto[1]	7	1			T133	1		T306	1		T340	1
auto[805306368:939524095]	auto[1]	11	1			T136	1		T137	1		T336	1
auto[939524096:1073741823]	auto[1]	12	1			T235	1		T306	1		T349	1
auto[1073741824:1207959551]	auto[1]	7	1			T132	1		T238	1		T260	1
auto[1207959552:1342177279]	auto[1]	8	1			T131	1		T266	1		T306	1
auto[1342177280:1476395007]	auto[1]	11	1			T137	3		T239	1		T349	1
auto[1476395008:1610612735]	auto[1]	10	1			T133	1		T235	1		T258	1
auto[1610612736:1744830463]	auto[1]	7	1			T137	1		T266	1		T239	1
auto[1744830464:1879048191]	auto[1]	7	1			T336	1		T266	1		T239	1
auto[1879048192:2013265919]	auto[1]	4	1			T378	1		T277	1		T250	1
auto[2013265920:2147483647]	auto[1]	11	1			T137	1		T252	1		T286	1
auto[2147483648:2281701375]	auto[1]	6	1			T133	2		T235	2		T320	1
auto[2281701376:2415919103]	auto[1]	11	1			T252	2		T285	1		T306	2
auto[2415919104:2550136831]	auto[1]	11	1			T133	1		T136	1		T258	1
auto[2550136832:2684354559]	auto[1]	6	1			T133	2		T286	1		T416	1
auto[2684354560:2818572287]	auto[1]	6	1			T133	1		T137	2		T349	1
auto[2818572288:2952790015]	auto[1]	9	1			T133	2		T235	1		T336	1
auto[2952790016:3087007743]	auto[1]	14	1			T133	2		T137	2		T252	2
auto[3087007744:3221225471]	auto[1]	11	1			T252	1		T266	1		T340	1
auto[3221225472:3355443199]	auto[1]	6	1			T349	1		T417	1		T418	1
auto[3355443200:3489660927]	auto[1]	8	1			T252	1		T286	1		T306	1
auto[3489660928:3623878655]	auto[1]	10	1			T137	1		T252	1		T286	1
auto[3623878656:3758096383]	auto[1]	5	1			T137	1		T252	1		T285	1
auto[3758096384:3892314111]	auto[1]	8	1			T135	1		T136	1		T306	1
auto[3892314112:4026531839]	auto[1]	7	1			T320	1		T378	1		T291	1
auto[4026531840:4160749567]	auto[1]	3	1			T252	1		T419	2		-	-
auto[4160749568:4294967295]	auto[1]	11	1			T133	1		T136	1		T266	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3005

1

T2

2

T3

4

T4

4

auto[1]

274

1

T131

2

T146

11

T132

7

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	96	1			T3	1		T32	1		T42	1
auto[134217728:268435455]	100	1			T43	1		T42	1		T98	1
auto[268435456:402653183]	100	1			T32	1		T43	1		T88	1
auto[402653184:536870911]	103	1			T3	1		T42	2		T104	1
auto[536870912:671088639]	94	1			T13	2		T84	1		T43	1
auto[671088640:805306367]	90	1			T14	1		T16	1		T32	1
auto[805306368:939524095]	88	1			T12	1		T84	2		T88	1
auto[939524096:1073741823]	113	1			T13	1		T42	3		T19	1
auto[1073741824:1207959551]	103	1			T2	1		T13	1		T42	2
auto[1207959552:1342177279]	98	1			T13	1		T31	1		T130	1
auto[1342177280:1476395007]	102	1			T14	1		T18	1		T55	1
auto[1476395008:1610612735]	91	1			T13	1		T42	1		T99	1
auto[1610612736:1744830463]	92	1			T31	1		T84	1		T41	1
auto[1744830464:1879048191]	95	1			T2	1		T88	1		T61	1
auto[1879048192:2013265919]	90	1			T4	1		T32	1		T47	1
auto[2013265920:2147483647]	93	1			T14	1		T21	1		T131	1
auto[2147483648:2281701375]	106	1			T42	1		T55	1		T112	1
auto[2281701376:2415919103]	105	1			T4	1		T42	1		T90	1
auto[2415919104:2550136831]	123	1			T32	1		T129	1		T90	1
auto[2550136832:2684354559]	120	1			T84	1		T129	1		T21	1
auto[2684354560:2818572287]	111	1			T4	1		T13	1		T16	1
auto[2818572288:2952790015]	104	1			T16	1		T31	1		T32	1
auto[2952790016:3087007743]	98	1			T13	1		T42	1		T98	1
auto[3087007744:3221225471]	101	1			T21	1		T45	1		T46	1
auto[3221225472:3355443199]	112	1			T4	1		T16	1		T84	1
auto[3355443200:3489660927]	107	1			T12	1		T13	1		T130	1
auto[3489660928:3623878655]	102	1			T3	1		T31	1		T90	1
auto[3623878656:3758096383]	101	1			T3	1		T16	1		T84	1
auto[3758096384:3892314111]	93	1			T129	1		T61	1		T146	2
auto[3892314112:4026531839]	118	1			T88	1		T42	2		T131	1
auto[4026531840:4160749567]	108	1			T13	1		T42	2		T45	1
auto[4160749568:4294967295]	122	1			T32	2		T84	1		T42	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	1	63	98.44	1

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[671088640:805306367]]	[auto[1]]	0	1	1

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	88	1			T3	1		T32	1		T42	1
auto[0:134217727]	auto[1]	8	1			T131	1		T146	1		T133	1
auto[134217728:268435455]	auto[0]	89	1			T43	1		T42	1		T98	1
auto[134217728:268435455]	auto[1]	11	1			T420	2		T417	1		T291	1
auto[268435456:402653183]	auto[0]	88	1			T32	1		T43	1		T88	1
auto[268435456:402653183]	auto[1]	12	1			T132	1		T235	2		T265	1
auto[402653184:536870911]	auto[0]	86	1			T3	1		T42	2		T104	1
auto[402653184:536870911]	auto[1]	17	1			T146	2		T132	1		T133	1
auto[536870912:671088639]	auto[0]	85	1			T13	2		T84	1		T43	1
auto[536870912:671088639]	auto[1]	9	1			T133	1		T306	1		T260	1
auto[671088640:805306367]	auto[0]	90	1			T14	1		T16	1		T32	1
auto[805306368:939524095]	auto[0]	86	1			T12	1		T84	2		T88	1
auto[805306368:939524095]	auto[1]	2	1			T311	1		T307	1		-	-
auto[939524096:1073741823]	auto[0]	103	1			T13	1		T42	3		T19	1
auto[939524096:1073741823]	auto[1]	10	1			T133	1		T266	1		T239	1
auto[1073741824:1207959551]	auto[0]	96	1			T2	1		T13	1		T42	2
auto[1073741824:1207959551]	auto[1]	7	1			T146	1		T136	1		T239	1
auto[1207959552:1342177279]	auto[0]	86	1			T13	1		T31	1		T130	1
auto[1207959552:1342177279]	auto[1]	12	1			T336	1		T266	1		T306	1
auto[1342177280:1476395007]	auto[0]	89	1			T14	1		T18	1		T55	1
auto[1342177280:1476395007]	auto[1]	13	1			T146	1		T137	1		T286	1
auto[1476395008:1610612735]	auto[0]	83	1			T13	1		T42	1		T99	1
auto[1476395008:1610612735]	auto[1]	8	1			T133	1		T136	1		T265	1
auto[1610612736:1744830463]	auto[0]	82	1			T31	1		T84	1		T41	1
auto[1610612736:1744830463]	auto[1]	10	1			T146	1		T136	1		T286	1
auto[1744830464:1879048191]	auto[0]	89	1			T2	1		T88	1		T61	1
auto[1744830464:1879048191]	auto[1]	6	1			T286	1		T241	1		T306	1
auto[1879048192:2013265919]	auto[0]	80	1			T4	1		T32	1		T47	1
auto[1879048192:2013265919]	auto[1]	10	1			T137	1		T286	2		T241	1
auto[2013265920:2147483647]	auto[0]	87	1			T14	1		T21	1		T99	1
auto[2013265920:2147483647]	auto[1]	6	1			T131	1		T146	1		T137	1
auto[2147483648:2281701375]	auto[0]	97	1			T42	1		T55	1		T112	1
auto[2147483648:2281701375]	auto[1]	9	1			T133	1		T239	2		T415	1
auto[2281701376:2415919103]	auto[0]	94	1			T4	1		T42	1		T90	1
auto[2281701376:2415919103]	auto[1]	11	1			T241	1		T336	1		T320	1
auto[2415919104:2550136831]	auto[0]	117	1			T32	1		T129	1		T90	1
auto[2415919104:2550136831]	auto[1]	6	1			T378	1		T260	1		T277	1
auto[2550136832:2684354559]	auto[0]	116	1			T84	1		T129	1		T21	1
auto[2550136832:2684354559]	auto[1]	4	1			T378	2		T307	1		T421	1
auto[2684354560:2818572287]	auto[0]	103	1			T4	1		T13	1		T16	1
auto[2684354560:2818572287]	auto[1]	8	1			T136	1		T137	1		T286	1
auto[2818572288:2952790015]	auto[0]	94	1			T16	1		T31	1		T32	1
auto[2818572288:2952790015]	auto[1]	10	1			T146	1		T132	1		T137	1
auto[2952790016:3087007743]	auto[0]	86	1			T13	1		T42	1		T98	1
auto[2952790016:3087007743]	auto[1]	12	1			T132	1		T241	1		T336	1
auto[3087007744:3221225471]	auto[0]	94	1			T21	1		T45	1		T46	1
auto[3087007744:3221225471]	auto[1]	7	1			T146	1		T265	1		T252	1
auto[3221225472:3355443199]	auto[0]	105	1			T4	1		T16	1		T84	1
auto[3221225472:3355443199]	auto[1]	7	1			T136	2		T137	3		T286	1
auto[3355443200:3489660927]	auto[0]	101	1			T12	1		T13	1		T130	1
auto[3355443200:3489660927]	auto[1]	6	1			T286	1		T241	1		T422	1
auto[3489660928:3623878655]	auto[0]	95	1			T3	1		T31	1		T90	1
auto[3489660928:3623878655]	auto[1]	7	1			T306	1		T320	1		T378	2
auto[3623878656:3758096383]	auto[0]	89	1			T3	1		T16	1		T84	1
auto[3623878656:3758096383]	auto[1]	12	1			T135	1		T137	1		T265	2
auto[3758096384:3892314111]	auto[0]	85	1			T129	1		T61	1		T146	1
auto[3758096384:3892314111]	auto[1]	8	1			T146	1		T132	1		T320	1
auto[3892314112:4026531839]	auto[0]	110	1			T88	1		T42	2		T131	1
auto[3892314112:4026531839]	auto[1]	8	1			T132	1		T133	1		T265	1
auto[4026531840:4160749567]	auto[0]	101	1			T13	1		T42	2		T45	1
auto[4026531840:4160749567]	auto[1]	7	1			T146	1		T132	1		T349	1
auto[4160749568:4294967295]	auto[0]	111	1			T32	2		T84	1		T42	1
auto[4160749568:4294967295]	auto[1]	11	1			T136	1		T306	2		T238	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1617

1

T2

3

T3

1

T4

2

auto[1]

1798

1

T2

4

T3

3

T4

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	114	1			T4	1		T13	1		T42	2
auto[134217728:268435455]	90	1			T27	1		T42	1		T6	1
auto[268435456:402653183]	121	1			T2	1		T12	1		T42	1
auto[402653184:536870911]	100	1			T3	1		T42	1		T5	1
auto[536870912:671088639]	96	1			T31	1		T21	1		T55	1
auto[671088640:805306367]	103	1			T2	1		T43	1		T18	1
auto[805306368:939524095]	101	1			T42	2		T131	1		T133	1
auto[939524096:1073741823]	105	1			T88	1		T46	1		T24	1
auto[1073741824:1207959551]	116	1			T3	1		T32	1		T84	1
auto[1207959552:1342177279]	103	1			T13	1		T31	1		T84	1
auto[1342177280:1476395007]	112	1			T2	1		T4	1		T32	1
auto[1476395008:1610612735]	104	1			T32	1		T42	1		T131	1
auto[1610612736:1744830463]	114	1			T3	1		T13	1		T42	1
auto[1744830464:1879048191]	98	1			T2	1		T12	1		T31	1
auto[1879048192:2013265919]	93	1			T16	1		T21	1		T90	1
auto[2013265920:2147483647]	109	1			T3	1		T13	1		T14	2
auto[2147483648:2281701375]	111	1			T14	1		T32	1		T129	1
auto[2281701376:2415919103]	112	1			T104	1		T49	4		T108	1
auto[2415919104:2550136831]	136	1			T12	1		T88	1		T42	1
auto[2550136832:2684354559]	102	1			T2	1		T13	1		T21	1
auto[2684354560:2818572287]	126	1			T4	1		T32	1		T84	1
auto[2818572288:2952790015]	109	1			T16	1		T31	1		T41	1
auto[2952790016:3087007743]	118	1			T16	1		T84	1		T130	1
auto[3087007744:3221225471]	91	1			T12	2		T13	1		T31	1
auto[3221225472:3355443199]	111	1			T129	1		T42	1		T22	1
auto[3355443200:3489660927]	102	1			T42	2		T6	1		T61	1
auto[3489660928:3623878655]	98	1			T13	1		T84	1		T42	1
auto[3623878656:3758096383]	121	1			T2	1		T13	2		T32	1
auto[3758096384:3892314111]	98	1			T2	1		T19	1		T61	2
auto[3892314112:4026531839]	118	1			T31	1		T32	1		T88	2
auto[4026531840:4160749567]	91	1			T4	1		T31	1		T32	1
auto[4160749568:4294967295]	92	1			T13	1		T16	1		T88	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	58	1			T4	1		T42	1		T46	1
auto[0:134217727]	auto[1]	56	1			T13	1		T42	1		T19	1
auto[134217728:268435455]	auto[0]	44	1			T42	1		T61	1		T49	1
auto[134217728:268435455]	auto[1]	46	1			T27	1		T6	1		T22	1
auto[268435456:402653183]	auto[0]	62	1			T12	1		T90	1		T47	1
auto[268435456:402653183]	auto[1]	59	1			T2	1		T42	1		T22	1
auto[402653184:536870911]	auto[0]	45	1			T46	1		T112	1		T98	1
auto[402653184:536870911]	auto[1]	55	1			T3	1		T42	1		T5	1
auto[536870912:671088639]	auto[0]	47	1			T31	1		T55	1		T99	1
auto[536870912:671088639]	auto[1]	49	1			T21	1		T108	1		T110	1
auto[671088640:805306367]	auto[0]	56	1			T43	1		T132	1		T49	1
auto[671088640:805306367]	auto[1]	47	1			T2	1		T18	1		T49	2
auto[805306368:939524095]	auto[0]	42	1			T131	1		T62	2		T216	1
auto[805306368:939524095]	auto[1]	59	1			T42	2		T133	1		T62	1
auto[939524096:1073741823]	auto[0]	35	1			T46	1		T24	1		T54	1
auto[939524096:1073741823]	auto[1]	70	1			T88	1		T298	1		T258	1
auto[1073741824:1207959551]	auto[0]	49	1			T42	1		T98	1		T49	1
auto[1073741824:1207959551]	auto[1]	67	1			T3	1		T32	1		T84	1
auto[1207959552:1342177279]	auto[0]	49	1			T13	1		T84	1		T41	1
auto[1207959552:1342177279]	auto[1]	54	1			T31	1		T132	3		T49	1
auto[1342177280:1476395007]	auto[0]	62	1			T2	1		T32	1		T49	1
auto[1342177280:1476395007]	auto[1]	50	1			T4	1		T84	1		T44	1
auto[1476395008:1610612735]	auto[0]	55	1			T32	1		T42	1		T62	3
auto[1476395008:1610612735]	auto[1]	49	1			T131	1		T49	2		T111	1
auto[1610612736:1744830463]	auto[0]	56	1			T13	1		T46	1		T99	1
auto[1610612736:1744830463]	auto[1]	58	1			T3	1		T42	1		T104	1
auto[1744830464:1879048191]	auto[0]	47	1			T2	1		T31	1		T84	1
auto[1744830464:1879048191]	auto[1]	51	1			T12	1		T104	1		T22	1
auto[1879048192:2013265919]	auto[0]	45	1			T21	1		T5	1		T46	1
auto[1879048192:2013265919]	auto[1]	48	1			T16	1		T90	1		T44	1
auto[2013265920:2147483647]	auto[0]	46	1			T3	1		T14	1		T43	1
auto[2013265920:2147483647]	auto[1]	63	1			T13	1		T14	1		T16	1
auto[2147483648:2281701375]	auto[0]	54	1			T14	1		T32	1		T47	1
auto[2147483648:2281701375]	auto[1]	57	1			T129	1		T205	1		T137	1
auto[2281701376:2415919103]	auto[0]	44	1			T49	1		T89	1		T205	1
auto[2281701376:2415919103]	auto[1]	68	1			T104	1		T49	3		T108	1
auto[2415919104:2550136831]	auto[0]	69	1			T88	1		T45	2		T47	1
auto[2415919104:2550136831]	auto[1]	67	1			T12	1		T42	1		T109	1
auto[2550136832:2684354559]	auto[0]	46	1			T21	1		T41	1		T45	1
auto[2550136832:2684354559]	auto[1]	56	1			T2	1		T13	1		T42	1
auto[2684354560:2818572287]	auto[0]	58	1			T84	1		T49	1		T23	1
auto[2684354560:2818572287]	auto[1]	68	1			T4	1		T32	1		T90	1
auto[2818572288:2952790015]	auto[0]	55	1			T90	1		T104	1		T5	1
auto[2818572288:2952790015]	auto[1]	54	1			T16	1		T31	1		T41	1
auto[2952790016:3087007743]	auto[0]	50	1			T84	1		T90	1		T62	1
auto[2952790016:3087007743]	auto[1]	68	1			T16	1		T130	1		T42	1
auto[3087007744:3221225471]	auto[0]	43	1			T12	1		T31	1		T49	1
auto[3087007744:3221225471]	auto[1]	48	1			T12	1		T13	1		T88	1
auto[3221225472:3355443199]	auto[0]	60	1			T49	1		T62	2		T24	1
auto[3221225472:3355443199]	auto[1]	51	1			T129	1		T42	1		T22	1
auto[3355443200:3489660927]	auto[0]	47	1			T42	1		T6	1		T61	1
auto[3355443200:3489660927]	auto[1]	55	1			T42	1		T49	2		T108	1
auto[3489660928:3623878655]	auto[0]	49	1			T147	1		T62	1		T423	1
auto[3489660928:3623878655]	auto[1]	49	1			T13	1		T84	1		T42	1
auto[3623878656:3758096383]	auto[0]	51	1			T2	1		T13	1		T32	1
auto[3623878656:3758096383]	auto[1]	70	1			T13	1		T129	1		T21	1
auto[3758096384:3892314111]	auto[0]	50	1			T19	1		T61	1		T62	1
auto[3758096384:3892314111]	auto[1]	48	1			T2	1		T61	1		T147	1
auto[3892314112:4026531839]	auto[0]	57	1			T32	1		T88	1		T42	1
auto[3892314112:4026531839]	auto[1]	61	1			T31	1		T88	1		T42	3
auto[4026531840:4160749567]	auto[0]	42	1			T4	1		T31	1		T42	1
auto[4026531840:4160749567]	auto[1]	49	1			T32	1		T42	1		T146	1
auto[4160749568:4294967295]	auto[0]	44	1			T13	1		T16	1		T61	1
auto[4160749568:4294967295]	auto[1]	48	1			T88	1		T42	1		T61	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1599

1

T2

3

T3

2

T4

2

auto[1]

1816

1

T2

4

T3

2

T4

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	95	1			T16	1		T31	1		T84	1
auto[134217728:268435455]	93	1			T2	1		T13	1		T84	1
auto[268435456:402653183]	120	1			T42	1		T108	1		T60	1
auto[402653184:536870911]	90	1			T4	1		T32	1		T21	1
auto[536870912:671088639]	110	1			T12	1		T13	1		T32	1
auto[671088640:805306367]	105	1			T4	1		T16	1		T42	3
auto[805306368:939524095]	100	1			T16	1		T88	2		T42	3
auto[939524096:1073741823]	111	1			T12	1		T13	1		T31	1
auto[1073741824:1207959551]	99	1			T13	1		T31	1		T32	1
auto[1207959552:1342177279]	102	1			T12	1		T43	1		T21	1
auto[1342177280:1476395007]	114	1			T3	1		T4	1		T42	2
auto[1476395008:1610612735]	123	1			T129	1		T88	1		T42	1
auto[1610612736:1744830463]	109	1			T12	1		T84	2		T88	1
auto[1744830464:1879048191]	101	1			T4	1		T13	1		T32	2
auto[1879048192:2013265919]	109	1			T2	1		T146	1		T49	3
auto[2013265920:2147483647]	113	1			T2	1		T13	1		T16	1
auto[2147483648:2281701375]	94	1			T2	1		T88	1		T147	1
auto[2281701376:2415919103]	120	1			T14	1		T32	1		T42	2
auto[2415919104:2550136831]	86	1			T31	1		T129	1		T21	1
auto[2550136832:2684354559]	103	1			T2	1		T31	1		T41	1
auto[2684354560:2818572287]	102	1			T41	1		T88	1		T45	1
auto[2818572288:2952790015]	129	1			T45	1		T146	1		T132	1
auto[2952790016:3087007743]	108	1			T2	1		T13	2		T32	1
auto[3087007744:3221225471]	107	1			T2	1		T3	1		T32	1
auto[3221225472:3355443199]	100	1			T14	2		T88	1		T55	1
auto[3355443200:3489660927]	107	1			T41	1		T44	1		T19	1
auto[3489660928:3623878655]	107	1			T13	1		T84	1		T42	1
auto[3623878656:3758096383]	105	1			T3	1		T43	1		T61	2
auto[3758096384:3892314111]	120	1			T16	1		T31	1		T42	1
auto[3892314112:4026531839]	116	1			T3	1		T13	1		T31	1
auto[4026531840:4160749567]	105	1			T42	1		T132	1		T111	1
auto[4160749568:4294967295]	112	1			T12	1		T42	3		T44	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	43	1			T31	1		T84	1		T41	1
auto[0:134217727]	auto[1]	52	1			T16	1		T42	1		T132	1
auto[134217728:268435455]	auto[0]	49	1			T98	1		T99	1		T89	1
auto[134217728:268435455]	auto[1]	44	1			T2	1		T13	1		T84	1
auto[268435456:402653183]	auto[0]	55	1			T60	1		T205	1		T397	1
auto[268435456:402653183]	auto[1]	65	1			T42	1		T108	1		T67	1
auto[402653184:536870911]	auto[0]	39	1			T32	1		T21	1		T104	1
auto[402653184:536870911]	auto[1]	51	1			T4	1		T6	1		T131	1
auto[536870912:671088639]	auto[0]	51	1			T13	1		T32	1		T46	1
auto[536870912:671088639]	auto[1]	59	1			T12	1		T129	1		T90	1
auto[671088640:805306367]	auto[0]	48	1			T4	1		T42	1		T90	1
auto[671088640:805306367]	auto[1]	57	1			T16	1		T42	2		T6	1
auto[805306368:939524095]	auto[0]	55	1			T88	2		T42	1		T90	1
auto[805306368:939524095]	auto[1]	45	1			T16	1		T42	2		T249	1
auto[939524096:1073741823]	auto[0]	46	1			T12	1		T13	1		T47	1
auto[939524096:1073741823]	auto[1]	65	1			T31	1		T129	1		T18	1
auto[1073741824:1207959551]	auto[0]	52	1			T13	1		T32	1		T99	1
auto[1073741824:1207959551]	auto[1]	47	1			T31	1		T49	1		T110	1
auto[1207959552:1342177279]	auto[0]	50	1			T12	1		T43	1		T62	1
auto[1207959552:1342177279]	auto[1]	52	1			T21	1		T42	1		T112	1
auto[1342177280:1476395007]	auto[0]	61	1			T3	1		T46	1		T47	1
auto[1342177280:1476395007]	auto[1]	53	1			T4	1		T42	2		T146	1
auto[1476395008:1610612735]	auto[0]	54	1			T88	1		T42	1		T46	1
auto[1476395008:1610612735]	auto[1]	69	1			T129	1		T5	1		T19	1
auto[1610612736:1744830463]	auto[0]	60	1			T84	2		T42	1		T22	1
auto[1610612736:1744830463]	auto[1]	49	1			T12	1		T88	1		T104	1
auto[1744830464:1879048191]	auto[0]	41	1			T4	1		T32	1		T46	1
auto[1744830464:1879048191]	auto[1]	60	1			T13	1		T32	1		T84	1
auto[1879048192:2013265919]	auto[0]	47	1			T49	1		T77	1		T54	1
auto[1879048192:2013265919]	auto[1]	62	1			T2	1		T146	1		T49	2
auto[2013265920:2147483647]	auto[0]	57	1			T2	1		T16	1		T84	1
auto[2013265920:2147483647]	auto[1]	56	1			T13	1		T130	1		T49	1
auto[2147483648:2281701375]	auto[0]	35	1			T49	3		T110	1		T62	2
auto[2147483648:2281701375]	auto[1]	59	1			T2	1		T88	1		T147	1
auto[2281701376:2415919103]	auto[0]	48	1			T14	1		T99	1		T53	1
auto[2281701376:2415919103]	auto[1]	72	1			T32	1		T42	2		T104	1
auto[2415919104:2550136831]	auto[0]	45	1			T31	1		T21	1		T19	1
auto[2415919104:2550136831]	auto[1]	41	1			T129	1		T42	1		T90	1
auto[2550136832:2684354559]	auto[0]	43	1			T2	1		T31	1		T131	1
auto[2550136832:2684354559]	auto[1]	60	1			T41	1		T49	2		T53	1
auto[2684354560:2818572287]	auto[0]	48	1			T88	1		T45	1		T6	1
auto[2684354560:2818572287]	auto[1]	54	1			T41	1		T49	2		T62	1
auto[2818572288:2952790015]	auto[0]	63	1			T45	1		T132	1		T235	1
auto[2818572288:2952790015]	auto[1]	66	1			T146	1		T109	1		T424	1
auto[2952790016:3087007743]	auto[0]	62	1			T2	1		T13	1		T32	1
auto[2952790016:3087007743]	auto[1]	46	1			T13	1		T42	1		T49	1
auto[3087007744:3221225471]	auto[0]	43	1			T3	1		T32	1		T42	1
auto[3087007744:3221225471]	auto[1]	64	1			T2	1		T43	1		T104	1
auto[3221225472:3355443199]	auto[0]	48	1			T14	1		T47	1		T98	1
auto[3221225472:3355443199]	auto[1]	52	1			T14	1		T88	1		T55	1
auto[3355443200:3489660927]	auto[0]	53	1			T41	1		T98	2		T22	1
auto[3355443200:3489660927]	auto[1]	54	1			T44	1		T19	1		T49	2
auto[3489660928:3623878655]	auto[0]	54	1			T13	1		T47	1		T61	1
auto[3489660928:3623878655]	auto[1]	53	1			T84	1		T42	1		T55	1
auto[3623878656:3758096383]	auto[0]	47	1			T43	1		T61	1		T135	1
auto[3623878656:3758096383]	auto[1]	58	1			T3	1		T61	1		T146	1
auto[3758096384:3892314111]	auto[0]	51	1			T146	1		T132	1		T60	1
auto[3758096384:3892314111]	auto[1]	69	1			T16	1		T31	1		T42	1
auto[3892314112:4026531839]	auto[0]	52	1			T13	1		T31	1		T84	1
auto[3892314112:4026531839]	auto[1]	64	1			T3	1		T21	1		T90	1
auto[4026531840:4160749567]	auto[0]	45	1			T42	1		T111	1		T62	2
auto[4026531840:4160749567]	auto[1]	60	1			T132	1		T50	1		T205	1
auto[4160749568:4294967295]	auto[0]	54	1			T12	1		T49	2		T62	1
auto[4160749568:4294967295]	auto[1]	58	1			T42	3		T44	1		T112	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1593

1

T2

2

T3

3

T4

2

auto[1]

1822

1

T2

5

T3

1

T4

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	110	1			T31	2		T42	2		T45	1
auto[134217728:268435455]	113	1			T12	1		T16	1		T31	1
auto[268435456:402653183]	98	1			T88	1		T46	1		T49	1
auto[402653184:536870911]	116	1			T31	1		T42	2		T90	1
auto[536870912:671088639]	84	1			T90	2		T46	1		T49	1
auto[671088640:805306367]	123	1			T3	1		T32	3		T129	2
auto[805306368:939524095]	92	1			T2	1		T61	1		T49	1
auto[939524096:1073741823]	109	1			T12	1		T13	1		T14	2
auto[1073741824:1207959551]	122	1			T2	1		T42	2		T19	1
auto[1207959552:1342177279]	105	1			T3	1		T55	1		T46	1
auto[1342177280:1476395007]	105	1			T2	1		T13	1		T31	1
auto[1476395008:1610612735]	93	1			T3	1		T16	1		T32	1
auto[1610612736:1744830463]	103	1			T16	1		T32	1		T84	1
auto[1744830464:1879048191]	100	1			T13	2		T31	1		T90	1
auto[1879048192:2013265919]	93	1			T16	1		T32	1		T84	1
auto[2013265920:2147483647]	91	1			T12	1		T14	1		T42	1
auto[2147483648:2281701375]	127	1			T2	1		T13	1		T84	1
auto[2281701376:2415919103]	109	1			T2	1		T13	1		T84	1
auto[2415919104:2550136831]	101	1			T3	1		T27	1		T21	1
auto[2550136832:2684354559]	118	1			T4	1		T42	3		T104	1
auto[2684354560:2818572287]	108	1			T43	2		T42	2		T6	1
auto[2818572288:2952790015]	109	1			T4	1		T12	1		T16	1
auto[2952790016:3087007743]	115	1			T129	1		T21	2		T19	1
auto[3087007744:3221225471]	104	1			T31	1		T32	1		T42	3
auto[3221225472:3355443199]	105	1			T4	2		T13	1		T32	1
auto[3355443200:3489660927]	103	1			T2	1		T84	1		T88	1
auto[3489660928:3623878655]	93	1			T13	1		T43	1		T130	1
auto[3623878656:3758096383]	122	1			T12	1		T84	1		T42	2
auto[3758096384:3892314111]	111	1			T13	2		T84	2		T42	1
auto[3892314112:4026531839]	107	1			T146	1		T22	1		T109	1
auto[4026531840:4160749567]	108	1			T2	1		T42	2		T46	1
auto[4160749568:4294967295]	118	1			T21	1		T41	1		T18	1