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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3007 1 T2 2 T3 4 T4 4
auto[1] 285 1 T131 2 T146 5 T132 5


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 106 1 T14 1 T21 1 T90 1
auto[134217728:268435455] 101 1 T4 1 T13 1 T32 1
auto[268435456:402653183] 113 1 T13 2 T46 1 T49 1
auto[402653184:536870911] 103 1 T2 1 T4 1 T42 2
auto[536870912:671088639] 105 1 T130 1 T42 2 T49 3
auto[671088640:805306367] 113 1 T84 1 T42 1 T46 1
auto[805306368:939524095] 103 1 T129 1 T21 2 T104 1
auto[939524096:1073741823] 100 1 T14 1 T42 2 T62 1
auto[1073741824:1207959551] 112 1 T31 1 T130 1 T42 2
auto[1207959552:1342177279] 88 1 T21 1 T146 1 T49 1
auto[1342177280:1476395007] 104 1 T13 1 T41 1 T88 1
auto[1476395008:1610612735] 108 1 T13 1 T32 1 T129 1
auto[1610612736:1744830463] 100 1 T13 1 T84 1 T42 1
auto[1744830464:1879048191] 97 1 T3 1 T84 1 T43 1
auto[1879048192:2013265919] 100 1 T84 1 T42 2 T61 1
auto[2013265920:2147483647] 97 1 T12 1 T129 1 T88 1
auto[2147483648:2281701375] 94 1 T13 1 T31 1 T44 1
auto[2281701376:2415919103] 107 1 T13 1 T43 1 T61 2
auto[2415919104:2550136831] 92 1 T84 1 T6 1 T99 1
auto[2550136832:2684354559] 108 1 T13 1 T22 1 T49 2
auto[2684354560:2818572287] 97 1 T12 1 T16 2 T84 1
auto[2818572288:2952790015] 113 1 T3 1 T88 1 T42 2
auto[2952790016:3087007743] 99 1 T14 1 T21 1 T104 1
auto[3087007744:3221225471] 106 1 T3 1 T4 1 T32 1
auto[3221225472:3355443199] 93 1 T3 1 T16 1 T31 1
auto[3355443200:3489660927] 107 1 T2 1 T4 1 T16 1
auto[3489660928:3623878655] 97 1 T31 1 T32 1 T62 2
auto[3623878656:3758096383] 104 1 T32 1 T84 1 T88 1
auto[3758096384:3892314111] 97 1 T88 2 T44 1 T55 1
auto[3892314112:4026531839] 125 1 T32 2 T129 1 T90 1
auto[4026531840:4160749567] 102 1 T31 1 T32 1 T84 1
auto[4160749568:4294967295] 101 1 T13 1 T16 1 T43 1


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 96 1 T14 1 T21 1 T90 1
auto[0:134217727] auto[1] 10 1 T265 1 T252 1 T286 1
auto[134217728:268435455] auto[0] 93 1 T4 1 T13 1 T32 1
auto[134217728:268435455] auto[1] 8 1 T132 1 T133 1 T415 1
auto[268435456:402653183] auto[0] 104 1 T13 2 T46 1 T49 1
auto[268435456:402653183] auto[1] 9 1 T235 1 T286 1 T260 1
auto[402653184:536870911] auto[0] 98 1 T2 1 T4 1 T42 2
auto[402653184:536870911] auto[1] 5 1 T136 1 T336 1 T425 1
auto[536870912:671088639] auto[0] 95 1 T130 1 T42 2 T49 3
auto[536870912:671088639] auto[1] 10 1 T137 1 T252 1 T306 1
auto[671088640:805306367] auto[0] 97 1 T84 1 T42 1 T46 1
auto[671088640:805306367] auto[1] 16 1 T132 1 T135 1 T137 2
auto[805306368:939524095] auto[0] 91 1 T129 1 T21 2 T104 1
auto[805306368:939524095] auto[1] 12 1 T336 1 T306 1 T238 1
auto[939524096:1073741823] auto[0] 92 1 T14 1 T42 2 T62 1
auto[939524096:1073741823] auto[1] 8 1 T137 1 T286 1 T340 1
auto[1073741824:1207959551] auto[0] 107 1 T31 1 T130 1 T42 2
auto[1073741824:1207959551] auto[1] 5 1 T146 1 T137 1 T417 1
auto[1207959552:1342177279] auto[0] 77 1 T21 1 T49 1 T110 1
auto[1207959552:1342177279] auto[1] 11 1 T146 1 T239 2 T415 1
auto[1342177280:1476395007] auto[0] 98 1 T13 1 T41 1 T88 1
auto[1342177280:1476395007] auto[1] 6 1 T258 1 T252 1 T239 1
auto[1476395008:1610612735] auto[0] 103 1 T13 1 T32 1 T129 1
auto[1476395008:1610612735] auto[1] 5 1 T252 1 T286 1 T241 1
auto[1610612736:1744830463] auto[0] 91 1 T13 1 T84 1 T42 1
auto[1610612736:1744830463] auto[1] 9 1 T132 1 T241 1 T336 1
auto[1744830464:1879048191] auto[0] 89 1 T3 1 T84 1 T43 1
auto[1744830464:1879048191] auto[1] 8 1 T286 1 T266 1 T306 1
auto[1879048192:2013265919] auto[0] 95 1 T84 1 T42 2 T61 1
auto[1879048192:2013265919] auto[1] 5 1 T306 1 T394 1 T378 1
auto[2013265920:2147483647] auto[0] 92 1 T12 1 T129 1 T88 1
auto[2013265920:2147483647] auto[1] 5 1 T137 1 T265 1 T330 1
auto[2147483648:2281701375] auto[0] 83 1 T13 1 T31 1 T44 1
auto[2147483648:2281701375] auto[1] 11 1 T132 1 T266 1 T306 1
auto[2281701376:2415919103] auto[0] 93 1 T13 1 T43 1 T61 2
auto[2281701376:2415919103] auto[1] 14 1 T136 1 T137 1 T252 1
auto[2415919104:2550136831] auto[0] 83 1 T84 1 T6 1 T99 1
auto[2415919104:2550136831] auto[1] 9 1 T133 1 T137 1 T269 1
auto[2550136832:2684354559] auto[0] 100 1 T13 1 T22 1 T49 2
auto[2550136832:2684354559] auto[1] 8 1 T137 1 T266 1 T425 1
auto[2684354560:2818572287] auto[0] 88 1 T12 1 T16 2 T84 1
auto[2684354560:2818572287] auto[1] 9 1 T137 1 T285 1 T336 1
auto[2818572288:2952790015] auto[0] 103 1 T3 1 T88 1 T42 2
auto[2818572288:2952790015] auto[1] 10 1 T131 1 T146 1 T133 1
auto[2952790016:3087007743] auto[0] 90 1 T14 1 T21 1 T104 1
auto[2952790016:3087007743] auto[1] 9 1 T265 1 T252 1 T286 2
auto[3087007744:3221225471] auto[0] 98 1 T3 1 T4 1 T32 1
auto[3087007744:3221225471] auto[1] 8 1 T131 1 T132 1 T137 1
auto[3221225472:3355443199] auto[0] 88 1 T3 1 T16 1 T31 1
auto[3221225472:3355443199] auto[1] 5 1 T415 1 T311 1 T429 1
auto[3355443200:3489660927] auto[0] 93 1 T2 1 T4 1 T16 1
auto[3355443200:3489660927] auto[1] 14 1 T252 1 T266 1 T238 1
auto[3489660928:3623878655] auto[0] 90 1 T31 1 T32 1 T62 2
auto[3489660928:3623878655] auto[1] 7 1 T266 1 T260 1 T236 1
auto[3623878656:3758096383] auto[0] 95 1 T32 1 T84 1 T88 1
auto[3623878656:3758096383] auto[1] 9 1 T146 1 T336 1 T306 1
auto[3758096384:3892314111] auto[0] 89 1 T88 2 T44 1 T55 1
auto[3758096384:3892314111] auto[1] 8 1 T133 1 T266 1 T306 1
auto[3892314112:4026531839] auto[0] 110 1 T32 2 T129 1 T90 1
auto[3892314112:4026531839] auto[1] 15 1 T235 1 T137 1 T336 1
auto[4026531840:4160749567] auto[0] 91 1 T31 1 T32 1 T84 1
auto[4026531840:4160749567] auto[1] 11 1 T146 1 T133 1 T135 1
auto[4160749568:4294967295] auto[0] 95 1 T13 1 T16 1 T43 1
auto[4160749568:4294967295] auto[1] 6 1 T137 2 T320 1 T415 1

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