Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6991

1

T2

3

T3

11

T4

6

auto[1]

280

1

T131

1

T146

7

T132

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	2955	1			T2	1		T3	4		T4	2
auto[134217728:268435455]	168	1			T4	1		T13	1		T42	1
auto[268435456:402653183]	162	1			T16	1		T42	3		T90	1
auto[402653184:536870911]	143	1			T84	1		T88	1		T42	1
auto[536870912:671088639]	163	1			T13	2		T84	1		T88	2
auto[671088640:805306367]	134	1			T3	1		T13	2		T31	1
auto[805306368:939524095]	155	1			T3	1		T31	1		T129	1
auto[939524096:1073741823]	133	1			T13	1		T31	1		T18	1
auto[1073741824:1207959551]	143	1			T3	1		T31	1		T84	1
auto[1207959552:1342177279]	138	1			T13	1		T90	1		T45	1
auto[1342177280:1476395007]	155	1			T4	1		T13	2		T90	1
auto[1476395008:1610612735]	126	1			T2	1		T3	1		T12	1
auto[1610612736:1744830463]	129	1			T32	2		T130	1		T88	1
auto[1744830464:1879048191]	135	1			T16	1		T32	1		T42	1
auto[1879048192:2013265919]	132	1			T3	2		T13	1		T19	1
auto[2013265920:2147483647]	130	1			T14	1		T32	1		T43	1
auto[2147483648:2281701375]	124	1			T3	1		T32	2		T84	1
auto[2281701376:2415919103]	113	1			T42	1		T22	1		T132	1
auto[2415919104:2550136831]	125	1			T14	1		T31	1		T43	1
auto[2550136832:2684354559]	128	1			T16	1		T21	1		T41	1
auto[2684354560:2818572287]	136	1			T12	1		T42	2		T46	1
auto[2818572288:2952790015]	128	1			T42	1		T132	1		T99	1
auto[2952790016:3087007743]	134	1			T4	1		T13	1		T84	1
auto[3087007744:3221225471]	122	1			T4	1		T21	2		T88	2
auto[3221225472:3355443199]	141	1			T13	1		T14	1		T16	1
auto[3355443200:3489660927]	139	1			T32	2		T84	1		T88	1
auto[3489660928:3623878655]	163	1			T16	1		T84	1		T130	1
auto[3623878656:3758096383]	125	1			T13	1		T32	2		T84	1
auto[3758096384:3892314111]	132	1			T13	1		T84	1		T21	1
auto[3892314112:4026531839]	141	1			T129	1		T130	1		T42	2
auto[4026531840:4160749567]	168	1			T2	1		T13	2		T16	1
auto[4160749568:4294967295]	151	1			T13	5		T42	2		T45	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2946	1			T2	1		T3	4		T4	2
auto[0:134217727]	auto[1]	9	1			T146	1		T135	1		T137	1
auto[134217728:268435455]	auto[0]	158	1			T4	1		T13	1		T42	1
auto[134217728:268435455]	auto[1]	10	1			T133	2		T235	1		T306	1
auto[268435456:402653183]	auto[0]	153	1			T16	1		T42	3		T90	1
auto[268435456:402653183]	auto[1]	9	1			T132	1		T136	1		T336	1
auto[402653184:536870911]	auto[0]	136	1			T84	1		T88	1		T42	1
auto[402653184:536870911]	auto[1]	7	1			T136	1		T425	1		T417	2
auto[536870912:671088639]	auto[0]	153	1			T13	2		T84	1		T88	2
auto[536870912:671088639]	auto[1]	10	1			T136	1		T265	1		T336	1
auto[671088640:805306367]	auto[0]	128	1			T3	1		T13	2		T31	1
auto[671088640:805306367]	auto[1]	6	1			T137	1		T286	1		T238	1
auto[805306368:939524095]	auto[0]	146	1			T3	1		T31	1		T129	1
auto[805306368:939524095]	auto[1]	9	1			T133	3		T392	1		T260	1
auto[939524096:1073741823]	auto[0]	123	1			T13	1		T31	1		T18	1
auto[939524096:1073741823]	auto[1]	10	1			T132	1		T137	1		T378	1
auto[1073741824:1207959551]	auto[0]	129	1			T3	1		T31	1		T84	1
auto[1073741824:1207959551]	auto[1]	14	1			T235	1		T285	1		T394	1
auto[1207959552:1342177279]	auto[0]	129	1			T13	1		T90	1		T45	1
auto[1207959552:1342177279]	auto[1]	9	1			T136	1		T306	1		T238	1
auto[1342177280:1476395007]	auto[0]	145	1			T4	1		T13	2		T90	1
auto[1342177280:1476395007]	auto[1]	10	1			T146	1		T286	2		T266	1
auto[1476395008:1610612735]	auto[0]	120	1			T2	1		T3	1		T12	1
auto[1476395008:1610612735]	auto[1]	6	1			T258	1		T265	1		T306	1
auto[1610612736:1744830463]	auto[0]	122	1			T32	2		T130	1		T88	1
auto[1610612736:1744830463]	auto[1]	7	1			T133	1		T239	1		T260	1
auto[1744830464:1879048191]	auto[0]	123	1			T16	1		T32	1		T42	1
auto[1744830464:1879048191]	auto[1]	12	1			T146	2		T336	1		T266	1
auto[1879048192:2013265919]	auto[0]	123	1			T3	2		T13	1		T19	1
auto[1879048192:2013265919]	auto[1]	9	1			T146	1		T137	1		T265	1
auto[2013265920:2147483647]	auto[0]	121	1			T14	1		T32	1		T43	1
auto[2013265920:2147483647]	auto[1]	9	1			T137	1		T286	1		T320	1
auto[2147483648:2281701375]	auto[0]	116	1			T3	1		T32	2		T84	1
auto[2147483648:2281701375]	auto[1]	8	1			T146	1		T136	2		T286	1
auto[2281701376:2415919103]	auto[0]	107	1			T42	1		T22	1		T132	1
auto[2281701376:2415919103]	auto[1]	6	1			T133	1		T286	1		T241	1
auto[2415919104:2550136831]	auto[0]	113	1			T14	1		T31	1		T43	1
auto[2415919104:2550136831]	auto[1]	12	1			T286	2		T266	1		T238	1
auto[2550136832:2684354559]	auto[0]	119	1			T16	1		T21	1		T41	1
auto[2550136832:2684354559]	auto[1]	9	1			T252	1		T286	1		T241	1
auto[2684354560:2818572287]	auto[0]	126	1			T12	1		T42	2		T46	1
auto[2684354560:2818572287]	auto[1]	10	1			T135	1		T378	1		T260	1
auto[2818572288:2952790015]	auto[0]	120	1			T42	1		T132	1		T99	1
auto[2818572288:2952790015]	auto[1]	8	1			T136	1		T269	1		T306	1
auto[2952790016:3087007743]	auto[0]	127	1			T4	1		T13	1		T84	1
auto[2952790016:3087007743]	auto[1]	7	1			T239	1		T349	1		T291	2
auto[3087007744:3221225471]	auto[0]	111	1			T4	1		T21	2		T88	2
auto[3087007744:3221225471]	auto[1]	11	1			T137	1		T258	1		T286	1
auto[3221225472:3355443199]	auto[0]	136	1			T13	1		T14	1		T16	1
auto[3221225472:3355443199]	auto[1]	5	1			T415	1		T425	2		T419	1
auto[3355443200:3489660927]	auto[0]	131	1			T32	2		T84	1		T88	1
auto[3355443200:3489660927]	auto[1]	8	1			T266	2		T306	1		T307	2
auto[3489660928:3623878655]	auto[0]	149	1			T16	1		T84	1		T130	1
auto[3489660928:3623878655]	auto[1]	14	1			T131	1		T146	1		T306	3
auto[3623878656:3758096383]	auto[0]	116	1			T13	1		T32	2		T84	1
auto[3623878656:3758096383]	auto[1]	9	1			T132	1		T378	2		T417	1
auto[3758096384:3892314111]	auto[0]	128	1			T13	1		T84	1		T21	1
auto[3758096384:3892314111]	auto[1]	4	1			T137	1		T286	1		T425	1
auto[3892314112:4026531839]	auto[0]	137	1			T129	1		T130	1		T42	2
auto[3892314112:4026531839]	auto[1]	4	1			T306	1		T291	1		T330	1
auto[4026531840:4160749567]	auto[0]	160	1			T2	1		T13	2		T16	1
auto[4026531840:4160749567]	auto[1]	8	1			T132	1		T258	1		T266	3
auto[4160749568:4294967295]	auto[0]	140	1			T13	5		T42	2		T45	1
auto[4160749568:4294967295]	auto[1]	11	1			T136	2		T285	1		T340	1