Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.71 99.04 97.95 98.48 100.00 99.02 98.41 91.09


Total test records in report: 1091
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1008 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.4293580218 Jul 15 07:11:58 PM PDT 24 Jul 15 07:12:11 PM PDT 24 752281836 ps
T1009 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3940373676 Jul 15 07:11:53 PM PDT 24 Jul 15 07:12:02 PM PDT 24 17103364 ps
T1010 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3964131505 Jul 15 07:12:07 PM PDT 24 Jul 15 07:12:20 PM PDT 24 516080351 ps
T163 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3935689112 Jul 15 07:11:58 PM PDT 24 Jul 15 07:12:10 PM PDT 24 219825311 ps
T1011 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.339846437 Jul 15 07:12:00 PM PDT 24 Jul 15 07:12:09 PM PDT 24 10187182 ps
T1012 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.1285159000 Jul 15 07:12:02 PM PDT 24 Jul 15 07:12:22 PM PDT 24 3477970128 ps
T1013 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.588320140 Jul 15 07:11:58 PM PDT 24 Jul 15 07:12:08 PM PDT 24 62255207 ps
T1014 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2752743364 Jul 15 07:12:06 PM PDT 24 Jul 15 07:12:14 PM PDT 24 38322767 ps
T1015 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.4046274814 Jul 15 07:12:05 PM PDT 24 Jul 15 07:12:16 PM PDT 24 342715564 ps
T1016 /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3515271482 Jul 15 07:12:20 PM PDT 24 Jul 15 07:12:25 PM PDT 24 14752376 ps
T1017 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3808867629 Jul 15 07:12:34 PM PDT 24 Jul 15 07:12:53 PM PDT 24 10973594 ps
T1018 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.889006706 Jul 15 07:12:07 PM PDT 24 Jul 15 07:12:15 PM PDT 24 194040916 ps
T1019 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3437699580 Jul 15 07:12:27 PM PDT 24 Jul 15 07:12:36 PM PDT 24 35841921 ps
T173 /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2460995516 Jul 15 07:12:01 PM PDT 24 Jul 15 07:12:17 PM PDT 24 1080763273 ps
T1020 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3588687401 Jul 15 07:12:00 PM PDT 24 Jul 15 07:12:10 PM PDT 24 52496646 ps
T1021 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2503451665 Jul 15 07:12:30 PM PDT 24 Jul 15 07:12:47 PM PDT 24 175202019 ps
T386 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3983778174 Jul 15 07:12:02 PM PDT 24 Jul 15 07:12:15 PM PDT 24 148902911 ps
T1022 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1784880621 Jul 15 07:12:16 PM PDT 24 Jul 15 07:12:19 PM PDT 24 19264304 ps
T1023 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.809186821 Jul 15 07:12:03 PM PDT 24 Jul 15 07:12:12 PM PDT 24 41104843 ps
T1024 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1787594505 Jul 15 07:12:06 PM PDT 24 Jul 15 07:12:15 PM PDT 24 210372553 ps
T1025 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.2692534857 Jul 15 07:12:03 PM PDT 24 Jul 15 07:12:14 PM PDT 24 553092904 ps
T1026 /workspace/coverage/cover_reg_top/42.keymgr_intr_test.59270910 Jul 15 07:12:33 PM PDT 24 Jul 15 07:12:52 PM PDT 24 13869168 ps
T1027 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.4054178440 Jul 15 07:12:00 PM PDT 24 Jul 15 07:12:39 PM PDT 24 2844887928 ps
T1028 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2694953631 Jul 15 07:11:52 PM PDT 24 Jul 15 07:12:01 PM PDT 24 175274366 ps
T1029 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.1490332295 Jul 15 07:12:07 PM PDT 24 Jul 15 07:12:13 PM PDT 24 42480137 ps
T1030 /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3779359849 Jul 15 07:12:01 PM PDT 24 Jul 15 07:12:12 PM PDT 24 206350974 ps
T1031 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.120697758 Jul 15 07:11:58 PM PDT 24 Jul 15 07:12:07 PM PDT 24 212324365 ps
T1032 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1731098248 Jul 15 07:11:59 PM PDT 24 Jul 15 07:12:15 PM PDT 24 1311701747 ps
T1033 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.1316460883 Jul 15 07:12:00 PM PDT 24 Jul 15 07:12:10 PM PDT 24 46415294 ps
T1034 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2624370036 Jul 15 07:12:31 PM PDT 24 Jul 15 07:12:45 PM PDT 24 29311587 ps
T1035 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.1533620165 Jul 15 07:11:56 PM PDT 24 Jul 15 07:12:09 PM PDT 24 779689296 ps
T1036 /workspace/coverage/cover_reg_top/7.keymgr_intr_test.4219796616 Jul 15 07:12:01 PM PDT 24 Jul 15 07:12:10 PM PDT 24 45590053 ps
T1037 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1250901723 Jul 15 07:12:07 PM PDT 24 Jul 15 07:12:16 PM PDT 24 99638588 ps
T1038 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2570028704 Jul 15 07:12:25 PM PDT 24 Jul 15 07:12:33 PM PDT 24 201861461 ps
T176 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.2278218401 Jul 15 07:12:04 PM PDT 24 Jul 15 07:12:16 PM PDT 24 139084476 ps
T1039 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3706495733 Jul 15 07:12:20 PM PDT 24 Jul 15 07:12:26 PM PDT 24 104973304 ps
T1040 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2461221065 Jul 15 07:12:05 PM PDT 24 Jul 15 07:12:12 PM PDT 24 16670824 ps
T1041 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1313657994 Jul 15 07:12:28 PM PDT 24 Jul 15 07:12:49 PM PDT 24 4780170494 ps
T1042 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.826765887 Jul 15 07:12:00 PM PDT 24 Jul 15 07:12:10 PM PDT 24 96095674 ps
T1043 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2784722285 Jul 15 07:12:28 PM PDT 24 Jul 15 07:12:39 PM PDT 24 54066653 ps
T1044 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1638901835 Jul 15 07:11:56 PM PDT 24 Jul 15 07:12:30 PM PDT 24 12295968700 ps
T1045 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2019619404 Jul 15 07:12:03 PM PDT 24 Jul 15 07:12:13 PM PDT 24 86817418 ps
T1046 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.4016050730 Jul 15 07:11:56 PM PDT 24 Jul 15 07:12:08 PM PDT 24 153301284 ps
T1047 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3168346578 Jul 15 07:11:59 PM PDT 24 Jul 15 07:12:16 PM PDT 24 509474331 ps
T1048 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1295578893 Jul 15 07:11:57 PM PDT 24 Jul 15 07:12:07 PM PDT 24 45496614 ps
T1049 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3660712 Jul 15 07:12:01 PM PDT 24 Jul 15 07:12:12 PM PDT 24 48225707 ps
T161 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2096366803 Jul 15 07:11:59 PM PDT 24 Jul 15 07:12:11 PM PDT 24 551074594 ps
T1050 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1444087012 Jul 15 07:12:31 PM PDT 24 Jul 15 07:12:44 PM PDT 24 39374870 ps
T1051 /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.2880814471 Jul 15 07:12:28 PM PDT 24 Jul 15 07:12:39 PM PDT 24 22622937 ps
T1052 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.2762587106 Jul 15 07:11:50 PM PDT 24 Jul 15 07:12:00 PM PDT 24 89817659 ps
T1053 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.2421525787 Jul 15 07:12:07 PM PDT 24 Jul 15 07:12:17 PM PDT 24 812903303 ps
T1054 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.4156998160 Jul 15 07:11:58 PM PDT 24 Jul 15 07:12:15 PM PDT 24 1459364516 ps
T1055 /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.604079222 Jul 15 07:12:05 PM PDT 24 Jul 15 07:12:15 PM PDT 24 82393027 ps
T178 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.2647756929 Jul 15 07:12:10 PM PDT 24 Jul 15 07:12:17 PM PDT 24 348822454 ps
T1056 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3471304678 Jul 15 07:12:07 PM PDT 24 Jul 15 07:12:13 PM PDT 24 57102108 ps
T1057 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3557785331 Jul 15 07:11:58 PM PDT 24 Jul 15 07:12:07 PM PDT 24 65857493 ps
T1058 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.3235778592 Jul 15 07:11:59 PM PDT 24 Jul 15 07:12:07 PM PDT 24 13851321 ps
T1059 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.4187255815 Jul 15 07:12:32 PM PDT 24 Jul 15 07:12:50 PM PDT 24 57320816 ps
T1060 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.565113155 Jul 15 07:12:27 PM PDT 24 Jul 15 07:12:36 PM PDT 24 27757715 ps
T1061 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2292911644 Jul 15 07:11:55 PM PDT 24 Jul 15 07:12:05 PM PDT 24 169005415 ps
T1062 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1851696257 Jul 15 07:12:27 PM PDT 24 Jul 15 07:12:38 PM PDT 24 1030097006 ps
T1063 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1422644396 Jul 15 07:12:24 PM PDT 24 Jul 15 07:12:31 PM PDT 24 92415525 ps
T1064 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.3535148140 Jul 15 07:12:33 PM PDT 24 Jul 15 07:12:52 PM PDT 24 13378377 ps
T1065 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3678599817 Jul 15 07:12:32 PM PDT 24 Jul 15 07:12:49 PM PDT 24 37794406 ps
T1066 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3740250923 Jul 15 07:12:19 PM PDT 24 Jul 15 07:12:23 PM PDT 24 62368756 ps
T1067 /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.248807375 Jul 15 07:11:53 PM PDT 24 Jul 15 07:12:06 PM PDT 24 539932352 ps
T1068 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.612120671 Jul 15 07:12:00 PM PDT 24 Jul 15 07:12:10 PM PDT 24 102556996 ps
T1069 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.462885577 Jul 15 07:12:01 PM PDT 24 Jul 15 07:12:12 PM PDT 24 58039790 ps
T1070 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1016392528 Jul 15 07:12:31 PM PDT 24 Jul 15 07:12:45 PM PDT 24 19611926 ps
T1071 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.260584115 Jul 15 07:11:56 PM PDT 24 Jul 15 07:12:20 PM PDT 24 450122608 ps
T1072 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.2128222010 Jul 15 07:12:01 PM PDT 24 Jul 15 07:12:12 PM PDT 24 318536839 ps
T1073 /workspace/coverage/cover_reg_top/18.keymgr_intr_test.23469409 Jul 15 07:12:25 PM PDT 24 Jul 15 07:12:32 PM PDT 24 102028947 ps
T1074 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.53572900 Jul 15 07:12:03 PM PDT 24 Jul 15 07:12:12 PM PDT 24 209756529 ps
T1075 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.3132462266 Jul 15 07:12:03 PM PDT 24 Jul 15 07:12:12 PM PDT 24 106891040 ps
T1076 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1359363962 Jul 15 07:12:10 PM PDT 24 Jul 15 07:12:15 PM PDT 24 63784595 ps
T1077 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3774943324 Jul 15 07:11:56 PM PDT 24 Jul 15 07:12:08 PM PDT 24 48288443 ps
T1078 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1053259827 Jul 15 07:12:03 PM PDT 24 Jul 15 07:12:13 PM PDT 24 101055391 ps
T1079 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2857900111 Jul 15 07:11:56 PM PDT 24 Jul 15 07:12:06 PM PDT 24 285626101 ps
T1080 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1193170387 Jul 15 07:12:31 PM PDT 24 Jul 15 07:12:45 PM PDT 24 35998634 ps
T1081 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1656199802 Jul 15 07:12:05 PM PDT 24 Jul 15 07:12:13 PM PDT 24 162709030 ps
T1082 /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3486257529 Jul 15 07:12:32 PM PDT 24 Jul 15 07:12:50 PM PDT 24 42923773 ps
T174 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2689295275 Jul 15 07:12:00 PM PDT 24 Jul 15 07:12:11 PM PDT 24 55761581 ps
T1083 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.1948044316 Jul 15 07:12:28 PM PDT 24 Jul 15 07:12:38 PM PDT 24 27717063 ps
T1084 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2537134014 Jul 15 07:11:58 PM PDT 24 Jul 15 07:12:10 PM PDT 24 154728340 ps
T1085 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2477398053 Jul 15 07:11:54 PM PDT 24 Jul 15 07:12:03 PM PDT 24 93450681 ps
T1086 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2458825038 Jul 15 07:11:59 PM PDT 24 Jul 15 07:12:07 PM PDT 24 9859076 ps
T1087 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1396833730 Jul 15 07:11:59 PM PDT 24 Jul 15 07:12:08 PM PDT 24 80110584 ps
T1088 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.450870336 Jul 15 07:11:56 PM PDT 24 Jul 15 07:12:14 PM PDT 24 1357019740 ps
T1089 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1665318002 Jul 15 07:12:27 PM PDT 24 Jul 15 07:12:36 PM PDT 24 10583127 ps
T1090 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1889230444 Jul 15 07:11:57 PM PDT 24 Jul 15 07:12:08 PM PDT 24 300572212 ps
T1091 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3540883535 Jul 15 07:12:27 PM PDT 24 Jul 15 07:12:39 PM PDT 24 88664613 ps

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.3608418919
Short name T12
Test name
Test status
Simulation time 677151438 ps
CPU time 12.37 seconds
Started Jul 15 07:20:40 PM PDT 24
Finished Jul 15 07:21:29 PM PDT 24
Peak memory 218432 kb
Host smart-d90751e1-37d1-40ab-9e4e-af5200fd1e03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608418919 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.3608418919
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.1580713703
Short name T49
Test name
Test status
Simulation time 4130972414 ps
CPU time 79.6 seconds
Started Jul 15 07:21:27 PM PDT 24
Finished Jul 15 07:23:39 PM PDT 24
Peak memory 216804 kb
Host smart-a2530816-f098-4b3a-9100-d625fbe47b14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580713703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.1580713703
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.1845886424
Short name T42
Test name
Test status
Simulation time 4263307530 ps
CPU time 41.94 seconds
Started Jul 15 07:22:54 PM PDT 24
Finished Jul 15 07:24:44 PM PDT 24
Peak memory 215220 kb
Host smart-ef42e62d-571c-403f-afb4-54436c57aa33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845886424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1845886424
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.3921374759
Short name T9
Test name
Test status
Simulation time 605755812 ps
CPU time 6.67 seconds
Started Jul 15 07:19:30 PM PDT 24
Finished Jul 15 07:20:35 PM PDT 24
Peak memory 233980 kb
Host smart-446aebff-077b-4a91-baec-2f9a78911151
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921374759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.3921374759
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.3309841025
Short name T62
Test name
Test status
Simulation time 786764267 ps
CPU time 23.21 seconds
Started Jul 15 07:21:17 PM PDT 24
Finished Jul 15 07:22:28 PM PDT 24
Peak memory 222544 kb
Host smart-759ca861-5ebb-469a-b4b7-b0579c11028b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309841025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.3309841025
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.938973051
Short name T14
Test name
Test status
Simulation time 414674248 ps
CPU time 3.22 seconds
Started Jul 15 07:20:14 PM PDT 24
Finished Jul 15 07:20:56 PM PDT 24
Peak memory 214280 kb
Host smart-cdd57e26-1f5a-4628-bc07-155c2bfde361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938973051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.938973051
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.603897781
Short name T133
Test name
Test status
Simulation time 91241602 ps
CPU time 5.58 seconds
Started Jul 15 07:22:24 PM PDT 24
Finished Jul 15 07:23:36 PM PDT 24
Peak memory 222400 kb
Host smart-92484b98-2ab4-41e9-9116-c12fc6a5fee6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=603897781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.603897781
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.1152170497
Short name T69
Test name
Test status
Simulation time 59967127877 ps
CPU time 193.19 seconds
Started Jul 15 07:20:08 PM PDT 24
Finished Jul 15 07:23:59 PM PDT 24
Peak memory 222488 kb
Host smart-36dd057f-97cd-48a9-a20c-4c28f36be8df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152170497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1152170497
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.1037448799
Short name T307
Test name
Test status
Simulation time 1798423997 ps
CPU time 48.23 seconds
Started Jul 15 07:21:51 PM PDT 24
Finished Jul 15 07:23:38 PM PDT 24
Peak memory 222384 kb
Host smart-37aa0c36-69d8-4414-97f8-0bad38b8fdde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1037448799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.1037448799
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.4194693419
Short name T8
Test name
Test status
Simulation time 134263795 ps
CPU time 2.88 seconds
Started Jul 15 07:22:53 PM PDT 24
Finished Jul 15 07:24:05 PM PDT 24
Peak memory 217884 kb
Host smart-1d8ecb45-ef7e-4216-9357-5392d9410d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194693419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.4194693419
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.874865371
Short name T123
Test name
Test status
Simulation time 306971277 ps
CPU time 18.84 seconds
Started Jul 15 07:19:07 PM PDT 24
Finished Jul 15 07:20:37 PM PDT 24
Peak memory 222664 kb
Host smart-6b6356f5-390b-4615-a57e-f647ceb356e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874865371 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.874865371
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3368411638
Short name T114
Test name
Test status
Simulation time 498364683 ps
CPU time 7.77 seconds
Started Jul 15 07:12:05 PM PDT 24
Finished Jul 15 07:12:19 PM PDT 24
Peak memory 213972 kb
Host smart-6ed695de-c512-479f-abb1-f4d097e57f54
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368411638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.3368411638
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.20067974
Short name T205
Test name
Test status
Simulation time 11386315009 ps
CPU time 291.04 seconds
Started Jul 15 07:22:58 PM PDT 24
Finished Jul 15 07:28:59 PM PDT 24
Peak memory 223212 kb
Host smart-a5c695f0-4d44-4124-920c-b506337069d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20067974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.20067974
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.3842841901
Short name T20
Test name
Test status
Simulation time 269566713 ps
CPU time 2.88 seconds
Started Jul 15 07:20:52 PM PDT 24
Finished Jul 15 07:21:37 PM PDT 24
Peak memory 221816 kb
Host smart-4b09842f-7cb8-41c7-89f3-5e3c55afc99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842841901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.3842841901
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.2012233694
Short name T32
Test name
Test status
Simulation time 138788956 ps
CPU time 2.91 seconds
Started Jul 15 07:20:34 PM PDT 24
Finished Jul 15 07:21:14 PM PDT 24
Peak memory 222440 kb
Host smart-105eb393-d58f-4f67-9c5c-8ced86b5977b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012233694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.2012233694
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.4157196138
Short name T260
Test name
Test status
Simulation time 9354925262 ps
CPU time 130.66 seconds
Started Jul 15 07:21:05 PM PDT 24
Finished Jul 15 07:24:01 PM PDT 24
Peak memory 220068 kb
Host smart-bb4c68ac-046e-4b30-8a8d-85aeb4d26db5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4157196138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.4157196138
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.3434347665
Short name T23
Test name
Test status
Simulation time 312289133 ps
CPU time 7.05 seconds
Started Jul 15 07:19:19 PM PDT 24
Finished Jul 15 07:20:30 PM PDT 24
Peak memory 222476 kb
Host smart-dbc6d592-e712-47bb-bcfe-014603268c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434347665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.3434347665
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.2083155787
Short name T157
Test name
Test status
Simulation time 185722095 ps
CPU time 2.16 seconds
Started Jul 15 07:12:07 PM PDT 24
Finished Jul 15 07:12:14 PM PDT 24
Peak memory 213812 kb
Host smart-9bf92955-811b-48f2-be98-8dc9987c8f42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083155787 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.2083155787
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.2041609081
Short name T252
Test name
Test status
Simulation time 71035200 ps
CPU time 4.12 seconds
Started Jul 15 07:22:53 PM PDT 24
Finished Jul 15 07:24:07 PM PDT 24
Peak memory 215328 kb
Host smart-2f245845-60e3-4bba-a94c-bf11cdbc30a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2041609081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.2041609081
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_random.3931581055
Short name T84
Test name
Test status
Simulation time 630421380 ps
CPU time 4.95 seconds
Started Jul 15 07:22:18 PM PDT 24
Finished Jul 15 07:23:28 PM PDT 24
Peak memory 219784 kb
Host smart-f994dd65-1eab-4741-a839-a4c1442b8196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931581055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.3931581055
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.653355533
Short name T146
Test name
Test status
Simulation time 803140178 ps
CPU time 38.69 seconds
Started Jul 15 07:21:06 PM PDT 24
Finished Jul 15 07:22:29 PM PDT 24
Peak memory 222432 kb
Host smart-644cf619-f4d6-4adb-92cd-d283589d4e3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=653355533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.653355533
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.592909266
Short name T59
Test name
Test status
Simulation time 3865349660 ps
CPU time 25.86 seconds
Started Jul 15 07:22:42 PM PDT 24
Finished Jul 15 07:24:16 PM PDT 24
Peak memory 216224 kb
Host smart-ae478fca-6328-4576-8344-f838ccd539f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592909266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.592909266
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.947018114
Short name T115
Test name
Test status
Simulation time 99531755 ps
CPU time 2.34 seconds
Started Jul 15 07:12:03 PM PDT 24
Finished Jul 15 07:12:13 PM PDT 24
Peak memory 214072 kb
Host smart-d75bb5f2-441c-466d-914b-43bb6e712b53
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947018114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow
_reg_errors.947018114
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.2236159688
Short name T61
Test name
Test status
Simulation time 68403984 ps
CPU time 4.38 seconds
Started Jul 15 07:21:38 PM PDT 24
Finished Jul 15 07:22:36 PM PDT 24
Peak memory 218488 kb
Host smart-bc63814a-0ccd-4ccf-9892-62851887b550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236159688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.2236159688
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.1509542043
Short name T250
Test name
Test status
Simulation time 129172031 ps
CPU time 7.12 seconds
Started Jul 15 07:21:15 PM PDT 24
Finished Jul 15 07:22:09 PM PDT 24
Peak memory 214776 kb
Host smart-9b3fb471-5865-4ac8-8542-952eb6923e77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1509542043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.1509542043
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.2665830330
Short name T221
Test name
Test status
Simulation time 1872221448 ps
CPU time 4.53 seconds
Started Jul 15 07:19:08 PM PDT 24
Finished Jul 15 07:20:23 PM PDT 24
Peak memory 218600 kb
Host smart-e11561e0-60b5-4f3d-a63a-73a3dedc8779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665830330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2665830330
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.2870553512
Short name T286
Test name
Test status
Simulation time 888684074 ps
CPU time 49.79 seconds
Started Jul 15 07:22:30 PM PDT 24
Finished Jul 15 07:24:27 PM PDT 24
Peak memory 215520 kb
Host smart-fccc397c-78d6-45aa-a540-f7033730f909
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2870553512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.2870553512
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.1893505538
Short name T92
Test name
Test status
Simulation time 198656638 ps
CPU time 4.74 seconds
Started Jul 15 07:21:41 PM PDT 24
Finished Jul 15 07:22:38 PM PDT 24
Peak memory 214548 kb
Host smart-6af2f8e8-2147-44e4-ba00-796d9fa63557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893505538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.1893505538
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.4271463028
Short name T70
Test name
Test status
Simulation time 94691907633 ps
CPU time 585.43 seconds
Started Jul 15 07:20:57 PM PDT 24
Finished Jul 15 07:31:27 PM PDT 24
Peak memory 222580 kb
Host smart-1700ca07-f060-40fd-9af8-02c1a706f4bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271463028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.4271463028
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.4282797418
Short name T433
Test name
Test status
Simulation time 60563070 ps
CPU time 0.93 seconds
Started Jul 15 07:19:11 PM PDT 24
Finished Jul 15 07:20:21 PM PDT 24
Peak memory 206056 kb
Host smart-d82a2164-2fbe-4e8e-af14-468d5fc43554
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282797418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.4282797418
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.41933352
Short name T46
Test name
Test status
Simulation time 133430223 ps
CPU time 2.24 seconds
Started Jul 15 07:22:39 PM PDT 24
Finished Jul 15 07:23:47 PM PDT 24
Peak memory 214724 kb
Host smart-02b62703-3785-41be-893e-0b023d847409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41933352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.41933352
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.1042808959
Short name T29
Test name
Test status
Simulation time 61800092 ps
CPU time 2.94 seconds
Started Jul 15 07:20:59 PM PDT 24
Finished Jul 15 07:21:45 PM PDT 24
Peak memory 214320 kb
Host smart-6dcfded5-5776-4db4-b773-b8a96fb319c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042808959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1042808959
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.2119552643
Short name T277
Test name
Test status
Simulation time 81643509 ps
CPU time 4.43 seconds
Started Jul 15 07:22:40 PM PDT 24
Finished Jul 15 07:23:50 PM PDT 24
Peak memory 215212 kb
Host smart-01304d18-5fd1-4d1c-aea3-10fe7f1a12e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2119552643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.2119552643
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.3123272973
Short name T159
Test name
Test status
Simulation time 182703156 ps
CPU time 4.35 seconds
Started Jul 15 07:12:02 PM PDT 24
Finished Jul 15 07:12:15 PM PDT 24
Peak memory 213728 kb
Host smart-de5c29b7-5a2a-4956-bd7d-d8fda0b40123
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123272973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.3123272973
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.469378658
Short name T58
Test name
Test status
Simulation time 1008910323 ps
CPU time 3.48 seconds
Started Jul 15 07:20:59 PM PDT 24
Finished Jul 15 07:21:46 PM PDT 24
Peak memory 209984 kb
Host smart-5cf00527-24d4-4d53-b803-65010ee62261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469378658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.469378658
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.3974587494
Short name T77
Test name
Test status
Simulation time 1083278873 ps
CPU time 11.45 seconds
Started Jul 15 07:20:59 PM PDT 24
Finished Jul 15 07:21:54 PM PDT 24
Peak memory 219100 kb
Host smart-baf6033a-c1cb-4c1a-a6f1-697abe63ce77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974587494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.3974587494
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.2194038773
Short name T13
Test name
Test status
Simulation time 1148439750 ps
CPU time 9.77 seconds
Started Jul 15 07:22:35 PM PDT 24
Finished Jul 15 07:23:51 PM PDT 24
Peak memory 222688 kb
Host smart-45daeb30-2e2f-4374-b125-76e3b69a1c8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194038773 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.2194038773
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.468085426
Short name T419
Test name
Test status
Simulation time 2231465864 ps
CPU time 108.58 seconds
Started Jul 15 07:20:21 PM PDT 24
Finished Jul 15 07:22:45 PM PDT 24
Peak memory 214440 kb
Host smart-fed14159-e3b7-4d8a-92af-12f654de31ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=468085426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.468085426
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.3750771217
Short name T71
Test name
Test status
Simulation time 12018932471 ps
CPU time 60.71 seconds
Started Jul 15 07:20:26 PM PDT 24
Finished Jul 15 07:22:03 PM PDT 24
Peak memory 217212 kb
Host smart-6cde665d-16a7-4caa-8a91-cfc3e7ad91f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750771217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3750771217
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.2679978517
Short name T19
Test name
Test status
Simulation time 63698738 ps
CPU time 4.29 seconds
Started Jul 15 07:22:25 PM PDT 24
Finished Jul 15 07:23:35 PM PDT 24
Peak memory 210572 kb
Host smart-9cfd8c17-c44f-4767-b9fc-9959cfe80199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679978517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.2679978517
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.1796403243
Short name T192
Test name
Test status
Simulation time 1897614422 ps
CPU time 21.79 seconds
Started Jul 15 07:19:06 PM PDT 24
Finished Jul 15 07:20:45 PM PDT 24
Peak memory 222476 kb
Host smart-f0c36c11-1ead-42c0-9f10-c898cdb8a470
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796403243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.1796403243
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.2917943572
Short name T85
Test name
Test status
Simulation time 779827472 ps
CPU time 6.08 seconds
Started Jul 15 07:20:08 PM PDT 24
Finished Jul 15 07:20:52 PM PDT 24
Peak memory 222428 kb
Host smart-d8a5942d-2db8-42bb-8c5c-b847db7c1c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917943572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.2917943572
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.2713402724
Short name T326
Test name
Test status
Simulation time 165004455 ps
CPU time 3.09 seconds
Started Jul 15 07:21:31 PM PDT 24
Finished Jul 15 07:22:25 PM PDT 24
Peak memory 214404 kb
Host smart-64689853-d57e-4811-9feb-8bfdbec36d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713402724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.2713402724
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.2233919861
Short name T148
Test name
Test status
Simulation time 135382099 ps
CPU time 5.24 seconds
Started Jul 15 07:20:59 PM PDT 24
Finished Jul 15 07:21:48 PM PDT 24
Peak memory 218264 kb
Host smart-86333b3c-72f6-4c88-ab73-5b7da8f5f07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233919861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2233919861
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.3888812600
Short name T137
Test name
Test status
Simulation time 633163857 ps
CPU time 9.08 seconds
Started Jul 15 07:21:24 PM PDT 24
Finished Jul 15 07:22:23 PM PDT 24
Peak memory 216072 kb
Host smart-2c8d2e06-b585-493f-9413-2dc93cf7f366
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3888812600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.3888812600
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.4082317425
Short name T244
Test name
Test status
Simulation time 117674665 ps
CPU time 2.43 seconds
Started Jul 15 07:22:15 PM PDT 24
Finished Jul 15 07:23:22 PM PDT 24
Peak memory 221544 kb
Host smart-1875d5bf-2199-4d3e-91ef-e64e5abc401a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082317425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.4082317425
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.794054582
Short name T21
Test name
Test status
Simulation time 111334585 ps
CPU time 3.59 seconds
Started Jul 15 07:21:06 PM PDT 24
Finished Jul 15 07:21:54 PM PDT 24
Peak memory 209152 kb
Host smart-bcb484cd-4273-4611-8824-c435084594a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794054582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.794054582
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.67987244
Short name T764
Test name
Test status
Simulation time 3076015346 ps
CPU time 39.93 seconds
Started Jul 15 07:22:31 PM PDT 24
Finished Jul 15 07:24:17 PM PDT 24
Peak memory 222564 kb
Host smart-7d41a5ee-3fc9-4ddf-b7a3-7971995cf51b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67987244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.67987244
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.1984665817
Short name T162
Test name
Test status
Simulation time 222170072 ps
CPU time 3.16 seconds
Started Jul 15 07:11:51 PM PDT 24
Finished Jul 15 07:12:01 PM PDT 24
Peak memory 213672 kb
Host smart-e8d106f7-264c-4b97-810d-4931cb32ca1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984665817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.1984665817
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2460995516
Short name T173
Test name
Test status
Simulation time 1080763273 ps
CPU time 7.37 seconds
Started Jul 15 07:12:01 PM PDT 24
Finished Jul 15 07:12:17 PM PDT 24
Peak memory 216168 kb
Host smart-0fda24d4-2edd-4c89-8330-cb81cdbb7c52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460995516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.2460995516
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.2031293416
Short name T311
Test name
Test status
Simulation time 235948740 ps
CPU time 4.45 seconds
Started Jul 15 07:19:09 PM PDT 24
Finished Jul 15 07:20:23 PM PDT 24
Peak memory 215468 kb
Host smart-f73f0d29-2c92-42da-abb1-7adbf15c9078
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2031293416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.2031293416
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.546053738
Short name T229
Test name
Test status
Simulation time 5989335993 ps
CPU time 143.71 seconds
Started Jul 15 07:20:41 PM PDT 24
Finished Jul 15 07:23:43 PM PDT 24
Peak memory 222544 kb
Host smart-436cae96-8b10-4d0b-afa0-c82532202e33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546053738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.546053738
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.2428000923
Short name T883
Test name
Test status
Simulation time 372815482 ps
CPU time 3.08 seconds
Started Jul 15 07:21:38 PM PDT 24
Finished Jul 15 07:22:35 PM PDT 24
Peak memory 214252 kb
Host smart-acc4102d-5921-4dc3-ab09-1e49e3a66f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428000923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.2428000923
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.626684432
Short name T378
Test name
Test status
Simulation time 104114610 ps
CPU time 5.7 seconds
Started Jul 15 07:19:31 PM PDT 24
Finished Jul 15 07:20:34 PM PDT 24
Peak memory 215320 kb
Host smart-c6d50817-507e-46c6-a604-a1dac15ce39a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=626684432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.626684432
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1932270720
Short name T967
Test name
Test status
Simulation time 420071138 ps
CPU time 11 seconds
Started Jul 15 07:11:57 PM PDT 24
Finished Jul 15 07:12:16 PM PDT 24
Peak memory 214000 kb
Host smart-b04788a4-a688-47ab-bbff-a21b7a2baaf3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932270720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.1932270720
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.3712763077
Short name T154
Test name
Test status
Simulation time 50671594 ps
CPU time 2.15 seconds
Started Jul 15 07:20:06 PM PDT 24
Finished Jul 15 07:20:46 PM PDT 24
Peak memory 222708 kb
Host smart-5a6de483-6cbb-409a-afb5-887e952c4a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712763077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.3712763077
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.3921429854
Short name T196
Test name
Test status
Simulation time 3516117948 ps
CPU time 28.25 seconds
Started Jul 15 07:20:13 PM PDT 24
Finished Jul 15 07:21:20 PM PDT 24
Peak memory 217460 kb
Host smart-424f2c80-fa17-4009-a02f-b5b28ec64aa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921429854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3921429854
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.3817326958
Short name T387
Test name
Test status
Simulation time 492029308 ps
CPU time 2.39 seconds
Started Jul 15 07:21:02 PM PDT 24
Finished Jul 15 07:21:48 PM PDT 24
Peak memory 210256 kb
Host smart-35a4a8b6-86a6-4767-a3b3-b6e2be7cb1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817326958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.3817326958
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.2590310328
Short name T124
Test name
Test status
Simulation time 1222259976 ps
CPU time 17.43 seconds
Started Jul 15 07:21:20 PM PDT 24
Finished Jul 15 07:22:27 PM PDT 24
Peak memory 222728 kb
Host smart-90ad97c2-afb1-4e78-86b5-3e1a5e5f35a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590310328 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.2590310328
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.2701197320
Short name T276
Test name
Test status
Simulation time 52410977 ps
CPU time 2.3 seconds
Started Jul 15 07:22:39 PM PDT 24
Finished Jul 15 07:23:47 PM PDT 24
Peak memory 220144 kb
Host smart-667c3d29-b1eb-431d-9c2f-12c00d113cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701197320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.2701197320
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.605842210
Short name T255
Test name
Test status
Simulation time 6644307982 ps
CPU time 42.3 seconds
Started Jul 15 07:22:46 PM PDT 24
Finished Jul 15 07:24:38 PM PDT 24
Peak memory 209232 kb
Host smart-8eeb459d-bda0-40c0-ab1e-6472e7e5d560
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605842210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.605842210
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2689295275
Short name T174
Test name
Test status
Simulation time 55761581 ps
CPU time 3.03 seconds
Started Jul 15 07:12:00 PM PDT 24
Finished Jul 15 07:12:11 PM PDT 24
Peak memory 213676 kb
Host smart-b8dd188e-09d8-4b5d-9739-ef50c13213ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689295275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.2689295275
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.3045366653
Short name T152
Test name
Test status
Simulation time 72309561 ps
CPU time 2.42 seconds
Started Jul 15 07:22:56 PM PDT 24
Finished Jul 15 07:24:08 PM PDT 24
Peak memory 218012 kb
Host smart-b7c3424d-8408-4bfb-958a-e9d7a417b70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045366653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3045366653
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1990443554
Short name T153
Test name
Test status
Simulation time 83103233 ps
CPU time 2.96 seconds
Started Jul 15 07:19:21 PM PDT 24
Finished Jul 15 07:20:26 PM PDT 24
Peak memory 218460 kb
Host smart-518480af-33cd-48cf-a2b7-87b01d7eab54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990443554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1990443554
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.3967956468
Short name T149
Test name
Test status
Simulation time 416774973 ps
CPU time 3.84 seconds
Started Jul 15 07:22:31 PM PDT 24
Finished Jul 15 07:23:41 PM PDT 24
Peak memory 217980 kb
Host smart-bc54e1cb-b890-4863-b0f2-b6543af13ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967956468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.3967956468
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.2824761985
Short name T151
Test name
Test status
Simulation time 588729516 ps
CPU time 5.95 seconds
Started Jul 15 07:22:49 PM PDT 24
Finished Jul 15 07:24:04 PM PDT 24
Peak memory 218252 kb
Host smart-4e98b86f-7716-4a41-b22d-5d6eb70125c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824761985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2824761985
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.1300123220
Short name T375
Test name
Test status
Simulation time 92473693 ps
CPU time 2.05 seconds
Started Jul 15 07:19:08 PM PDT 24
Finished Jul 15 07:20:25 PM PDT 24
Peak memory 208892 kb
Host smart-8d59d159-0624-48d2-bb52-85ea8f9b018f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300123220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.1300123220
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.3991381866
Short name T72
Test name
Test status
Simulation time 11444395089 ps
CPU time 27.85 seconds
Started Jul 15 07:20:52 PM PDT 24
Finished Jul 15 07:22:02 PM PDT 24
Peak memory 216096 kb
Host smart-1296dbfa-25be-4995-ae4c-b5a3b4c4ad46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991381866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3991381866
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.1998733700
Short name T269
Test name
Test status
Simulation time 289463503 ps
CPU time 3.13 seconds
Started Jul 15 07:21:04 PM PDT 24
Finished Jul 15 07:21:53 PM PDT 24
Peak memory 215424 kb
Host smart-84739319-c1dd-47a1-bcf4-b90e638a3931
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1998733700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1998733700
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.1536309597
Short name T282
Test name
Test status
Simulation time 157679870 ps
CPU time 5.53 seconds
Started Jul 15 07:21:04 PM PDT 24
Finished Jul 15 07:21:56 PM PDT 24
Peak memory 206984 kb
Host smart-4895c687-41ca-45f0-b07d-672f23cc4067
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536309597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.1536309597
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.935433725
Short name T93
Test name
Test status
Simulation time 132995177 ps
CPU time 3.88 seconds
Started Jul 15 07:21:31 PM PDT 24
Finished Jul 15 07:22:27 PM PDT 24
Peak memory 214512 kb
Host smart-bc85717b-43c2-4721-83f3-360087299c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935433725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.935433725
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.3440116667
Short name T207
Test name
Test status
Simulation time 76591620 ps
CPU time 2.85 seconds
Started Jul 15 07:21:56 PM PDT 24
Finished Jul 15 07:22:58 PM PDT 24
Peak memory 222348 kb
Host smart-9b51b9ab-4bf5-492e-843a-f1af000785a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440116667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.3440116667
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.2114981130
Short name T349
Test name
Test status
Simulation time 266424850 ps
CPU time 4.44 seconds
Started Jul 15 07:22:16 PM PDT 24
Finished Jul 15 07:23:24 PM PDT 24
Peak memory 222356 kb
Host smart-109d8c58-204d-4f9b-a3f5-e3df348d7ed3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2114981130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2114981130
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.763492659
Short name T383
Test name
Test status
Simulation time 56877393 ps
CPU time 1.64 seconds
Started Jul 15 07:22:49 PM PDT 24
Finished Jul 15 07:24:00 PM PDT 24
Peak memory 214244 kb
Host smart-c4b082cf-d0a3-4c86-811e-5c49e3d073ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763492659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.763492659
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.3060367362
Short name T7
Test name
Test status
Simulation time 59456517 ps
CPU time 3.96 seconds
Started Jul 15 07:19:25 PM PDT 24
Finished Jul 15 07:20:29 PM PDT 24
Peak memory 210604 kb
Host smart-efb8d691-5289-418f-bef2-af4bd2230973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060367362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.3060367362
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3935689112
Short name T163
Test name
Test status
Simulation time 219825311 ps
CPU time 3.12 seconds
Started Jul 15 07:11:58 PM PDT 24
Finished Jul 15 07:12:10 PM PDT 24
Peak memory 213756 kb
Host smart-f2eedb3f-f05a-42d2-b5ff-59cfdc171ef5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935689112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.3935689112
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.1896778720
Short name T172
Test name
Test status
Simulation time 1078996253 ps
CPU time 9.69 seconds
Started Jul 15 07:12:02 PM PDT 24
Finished Jul 15 07:12:20 PM PDT 24
Peak memory 213724 kb
Host smart-370ec761-aaea-468f-bb53-d220bd46a696
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896778720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.1896778720
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.2278218401
Short name T176
Test name
Test status
Simulation time 139084476 ps
CPU time 4.53 seconds
Started Jul 15 07:12:04 PM PDT 24
Finished Jul 15 07:12:16 PM PDT 24
Peak memory 205528 kb
Host smart-3276e32d-0557-4223-9c99-fe738d34aa41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278218401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.2278218401
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.2647756929
Short name T178
Test name
Test status
Simulation time 348822454 ps
CPU time 3.81 seconds
Started Jul 15 07:12:10 PM PDT 24
Finished Jul 15 07:12:17 PM PDT 24
Peak memory 213740 kb
Host smart-e14ae487-25da-459c-883a-81a8f01e04c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647756929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.2647756929
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1172293134
Short name T169
Test name
Test status
Simulation time 312353594 ps
CPU time 8.17 seconds
Started Jul 15 07:12:18 PM PDT 24
Finished Jul 15 07:12:27 PM PDT 24
Peak memory 213692 kb
Host smart-ec9849f9-cdf5-49d0-b14f-6ad8380cf197
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172293134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.1172293134
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1064927780
Short name T160
Test name
Test status
Simulation time 52331001 ps
CPU time 2.99 seconds
Started Jul 15 07:11:59 PM PDT 24
Finished Jul 15 07:12:10 PM PDT 24
Peak memory 213744 kb
Host smart-71f82a2e-9a80-452d-b323-b90c6b1605a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064927780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.1064927780
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.751168623
Short name T225
Test name
Test status
Simulation time 178016620 ps
CPU time 3.56 seconds
Started Jul 15 07:20:57 PM PDT 24
Finished Jul 15 07:21:44 PM PDT 24
Peak memory 217624 kb
Host smart-c8731d73-8e18-439a-8c7e-1eef95cc0dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751168623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.751168623
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.3257312009
Short name T150
Test name
Test status
Simulation time 157365738 ps
CPU time 2.28 seconds
Started Jul 15 07:22:33 PM PDT 24
Finished Jul 15 07:23:43 PM PDT 24
Peak memory 222612 kb
Host smart-d8a7635e-87ad-4856-a0ec-15cc17cee970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257312009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3257312009
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.3026775677
Short name T234
Test name
Test status
Simulation time 109769296 ps
CPU time 4.1 seconds
Started Jul 15 07:18:59 PM PDT 24
Finished Jul 15 07:20:18 PM PDT 24
Peak memory 214356 kb
Host smart-0d6b94f1-68b1-4b2e-867f-3a6820d063ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026775677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.3026775677
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.4191620623
Short name T291
Test name
Test status
Simulation time 1568960261 ps
CPU time 22.53 seconds
Started Jul 15 07:20:08 PM PDT 24
Finished Jul 15 07:21:08 PM PDT 24
Peak memory 215564 kb
Host smart-976bdbfe-a8f4-49e7-9b17-b6f32d83800e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4191620623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.4191620623
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.3431406184
Short name T365
Test name
Test status
Simulation time 89861298 ps
CPU time 2.68 seconds
Started Jul 15 07:20:27 PM PDT 24
Finished Jul 15 07:21:07 PM PDT 24
Peak memory 214312 kb
Host smart-ffbfe8fb-83e2-48c4-83c8-41d3c593cb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431406184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.3431406184
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.689012249
Short name T299
Test name
Test status
Simulation time 1184717076 ps
CPU time 12.93 seconds
Started Jul 15 07:20:26 PM PDT 24
Finished Jul 15 07:21:15 PM PDT 24
Peak memory 222640 kb
Host smart-84656135-e1ed-4a5b-b030-a54c9b7ba4d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689012249 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.689012249
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.848760097
Short name T314
Test name
Test status
Simulation time 1799038526 ps
CPU time 17.36 seconds
Started Jul 15 07:20:46 PM PDT 24
Finished Jul 15 07:21:44 PM PDT 24
Peak memory 222636 kb
Host smart-d7259ac5-2482-4a39-ad7e-54c370b29184
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848760097 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.848760097
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.2190921258
Short name T52
Test name
Test status
Simulation time 385692471 ps
CPU time 2.39 seconds
Started Jul 15 07:20:41 PM PDT 24
Finished Jul 15 07:21:22 PM PDT 24
Peak memory 209896 kb
Host smart-5b6bfe06-4498-4215-ad5d-bb1fc1217a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190921258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2190921258
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.1244293645
Short name T871
Test name
Test status
Simulation time 98007433 ps
CPU time 2.63 seconds
Started Jul 15 07:20:38 PM PDT 24
Finished Jul 15 07:21:17 PM PDT 24
Peak memory 209436 kb
Host smart-39963ae9-48e8-4171-b29f-5676da84e927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244293645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.1244293645
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.4150313356
Short name T324
Test name
Test status
Simulation time 46419331 ps
CPU time 1.63 seconds
Started Jul 15 07:20:44 PM PDT 24
Finished Jul 15 07:21:25 PM PDT 24
Peak memory 214248 kb
Host smart-4b04b788-7562-4e89-bf91-8e503607b192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150313356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.4150313356
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.148317256
Short name T271
Test name
Test status
Simulation time 533524906 ps
CPU time 3.81 seconds
Started Jul 15 07:20:48 PM PDT 24
Finished Jul 15 07:21:31 PM PDT 24
Peak memory 207256 kb
Host smart-f4e8eaee-675c-4f1e-8564-c4e587b7cee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148317256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.148317256
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.142914592
Short name T758
Test name
Test status
Simulation time 4418986965 ps
CPU time 27.89 seconds
Started Jul 15 07:21:03 PM PDT 24
Finished Jul 15 07:22:15 PM PDT 24
Peak memory 222592 kb
Host smart-d57575eb-0161-401e-bae6-8bc8434a29aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142914592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.142914592
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.852938243
Short name T236
Test name
Test status
Simulation time 925467422 ps
CPU time 13.1 seconds
Started Jul 15 07:20:52 PM PDT 24
Finished Jul 15 07:21:48 PM PDT 24
Peak memory 214340 kb
Host smart-e606da76-d59e-4db6-b88c-2ac3edcedd64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=852938243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.852938243
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.3070374643
Short name T258
Test name
Test status
Simulation time 37182606 ps
CPU time 2.35 seconds
Started Jul 15 07:20:58 PM PDT 24
Finished Jul 15 07:21:44 PM PDT 24
Peak memory 214460 kb
Host smart-3549a00a-b362-4972-81bb-d9807be127d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3070374643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.3070374643
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.2446528645
Short name T211
Test name
Test status
Simulation time 259277322 ps
CPU time 3.8 seconds
Started Jul 15 07:21:03 PM PDT 24
Finished Jul 15 07:21:50 PM PDT 24
Peak memory 220588 kb
Host smart-3ae5c123-1b3a-42f6-8e97-32fbd75afe73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446528645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.2446528645
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.3524047697
Short name T750
Test name
Test status
Simulation time 58581625 ps
CPU time 3.26 seconds
Started Jul 15 07:21:12 PM PDT 24
Finished Jul 15 07:22:02 PM PDT 24
Peak memory 209796 kb
Host smart-f2e4f779-9fd4-4622-bb4f-b3e47d2ecfe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524047697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.3524047697
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.99797675
Short name T222
Test name
Test status
Simulation time 278689057 ps
CPU time 3.45 seconds
Started Jul 15 07:21:25 PM PDT 24
Finished Jul 15 07:22:20 PM PDT 24
Peak memory 222680 kb
Host smart-d9a8dd10-9f87-4995-9f52-54a9bbad665a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99797675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.99797675
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.466194857
Short name T3
Test name
Test status
Simulation time 49116329 ps
CPU time 2.7 seconds
Started Jul 15 07:21:31 PM PDT 24
Finished Jul 15 07:22:25 PM PDT 24
Peak memory 222520 kb
Host smart-8530efbd-3dc5-4695-94da-713c97ad4e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466194857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.466194857
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.1882434169
Short name T246
Test name
Test status
Simulation time 73247338 ps
CPU time 3.91 seconds
Started Jul 15 07:22:05 PM PDT 24
Finished Jul 15 07:23:10 PM PDT 24
Peak memory 214312 kb
Host smart-21bef5b4-3ed9-4ff4-8009-2e4c68e5ba4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882434169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.1882434169
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.3951678044
Short name T227
Test name
Test status
Simulation time 111489009 ps
CPU time 3.13 seconds
Started Jul 15 07:22:55 PM PDT 24
Finished Jul 15 07:24:09 PM PDT 24
Peak memory 216236 kb
Host smart-79ee0c0d-5408-4546-bf84-065e65d6e114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951678044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.3951678044
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.2806742493
Short name T145
Test name
Test status
Simulation time 265246354 ps
CPU time 7.8 seconds
Started Jul 15 07:11:55 PM PDT 24
Finished Jul 15 07:12:11 PM PDT 24
Peak memory 205540 kb
Host smart-71ffae06-455e-4515-aaee-0dd469a0a008
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806742493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.2
806742493
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1638901835
Short name T1044
Test name
Test status
Simulation time 12295968700 ps
CPU time 25.51 seconds
Started Jul 15 07:11:56 PM PDT 24
Finished Jul 15 07:12:30 PM PDT 24
Peak memory 205456 kb
Host smart-205662ec-1044-45dc-b8fa-690d86129873
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638901835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.1
638901835
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3751715852
Short name T936
Test name
Test status
Simulation time 27311766 ps
CPU time 1.13 seconds
Started Jul 15 07:11:54 PM PDT 24
Finished Jul 15 07:12:04 PM PDT 24
Peak memory 205424 kb
Host smart-e20616ab-d8b9-4486-9d84-97e27253a347
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751715852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.3
751715852
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.588320140
Short name T1013
Test name
Test status
Simulation time 62255207 ps
CPU time 2.26 seconds
Started Jul 15 07:11:58 PM PDT 24
Finished Jul 15 07:12:08 PM PDT 24
Peak memory 213716 kb
Host smart-f76386ad-0e0f-4551-9771-8aca89c9439f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588320140 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.588320140
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3940373676
Short name T1009
Test name
Test status
Simulation time 17103364 ps
CPU time 1.12 seconds
Started Jul 15 07:11:53 PM PDT 24
Finished Jul 15 07:12:02 PM PDT 24
Peak memory 205496 kb
Host smart-df1ca48a-bfa1-4b9c-bf0b-29f5bded9f72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940373676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.3940373676
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2477398053
Short name T1085
Test name
Test status
Simulation time 93450681 ps
CPU time 0.74 seconds
Started Jul 15 07:11:54 PM PDT 24
Finished Jul 15 07:12:03 PM PDT 24
Peak memory 205296 kb
Host smart-f46893df-2978-4178-bf61-cec62a1a931e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477398053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.2477398053
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3893934371
Short name T142
Test name
Test status
Simulation time 80265124 ps
CPU time 1.34 seconds
Started Jul 15 07:11:55 PM PDT 24
Finished Jul 15 07:12:05 PM PDT 24
Peak memory 205516 kb
Host smart-c521d69f-7529-4ad4-8a5d-e71f8eec22b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893934371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.3893934371
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1889230444
Short name T1090
Test name
Test status
Simulation time 300572212 ps
CPU time 2.4 seconds
Started Jul 15 07:11:57 PM PDT 24
Finished Jul 15 07:12:08 PM PDT 24
Peak memory 214004 kb
Host smart-9a4eef56-612c-41a2-9db2-4ea94337c596
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889230444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.1889230444
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.3508335937
Short name T938
Test name
Test status
Simulation time 184223344 ps
CPU time 3.25 seconds
Started Jul 15 07:11:57 PM PDT 24
Finished Jul 15 07:12:09 PM PDT 24
Peak memory 213712 kb
Host smart-596b071a-6cd5-4e78-b234-977063c408c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508335937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.3508335937
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.4016050730
Short name T1046
Test name
Test status
Simulation time 153301284 ps
CPU time 2.94 seconds
Started Jul 15 07:11:56 PM PDT 24
Finished Jul 15 07:12:08 PM PDT 24
Peak memory 205416 kb
Host smart-86c3c1ca-2fd8-4ab8-bcf4-7863f11dcead
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016050730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.4016050730
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3201141465
Short name T954
Test name
Test status
Simulation time 373680710 ps
CPU time 10.64 seconds
Started Jul 15 07:11:53 PM PDT 24
Finished Jul 15 07:12:12 PM PDT 24
Peak memory 205340 kb
Host smart-5e8e6d36-fcbd-4922-9777-3c3938863172
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201141465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.3
201141465
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3514046353
Short name T948
Test name
Test status
Simulation time 251045495 ps
CPU time 11.76 seconds
Started Jul 15 07:11:57 PM PDT 24
Finished Jul 15 07:12:17 PM PDT 24
Peak memory 205524 kb
Host smart-d5fa41d0-7183-4189-881f-e1027d31fd3f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514046353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.3
514046353
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3188024640
Short name T1007
Test name
Test status
Simulation time 68958928 ps
CPU time 0.92 seconds
Started Jul 15 07:11:54 PM PDT 24
Finished Jul 15 07:12:04 PM PDT 24
Peak memory 205372 kb
Host smart-437db94f-b790-4d36-8cf2-f6d7f67fdd3f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188024640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.3
188024640
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.383053812
Short name T393
Test name
Test status
Simulation time 42737942 ps
CPU time 1.19 seconds
Started Jul 15 07:11:57 PM PDT 24
Finished Jul 15 07:12:06 PM PDT 24
Peak memory 213772 kb
Host smart-e4d1a292-30bf-404b-bb54-745dd0b37cd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383053812 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.383053812
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2136571507
Short name T998
Test name
Test status
Simulation time 154411635 ps
CPU time 0.92 seconds
Started Jul 15 07:11:55 PM PDT 24
Finished Jul 15 07:12:05 PM PDT 24
Peak memory 205356 kb
Host smart-46edfef1-479c-485c-89c1-5129758187ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136571507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.2136571507
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1756066948
Short name T930
Test name
Test status
Simulation time 14295109 ps
CPU time 0.75 seconds
Started Jul 15 07:11:55 PM PDT 24
Finished Jul 15 07:12:04 PM PDT 24
Peak memory 205332 kb
Host smart-e4739222-dc85-4450-a8b8-8406f5cabb96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756066948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1756066948
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2857900111
Short name T1079
Test name
Test status
Simulation time 285626101 ps
CPU time 1.37 seconds
Started Jul 15 07:11:56 PM PDT 24
Finished Jul 15 07:12:06 PM PDT 24
Peak memory 205452 kb
Host smart-b8f807d6-a9c4-4f8a-b6cc-3f47f3d5e1c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857900111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.2857900111
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3033707889
Short name T116
Test name
Test status
Simulation time 283511933 ps
CPU time 1.86 seconds
Started Jul 15 07:11:57 PM PDT 24
Finished Jul 15 07:12:07 PM PDT 24
Peak memory 214112 kb
Host smart-3658b0ee-2891-47c2-8612-670c9e5f5b2a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033707889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.3033707889
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.450870336
Short name T1088
Test name
Test status
Simulation time 1357019740 ps
CPU time 8.99 seconds
Started Jul 15 07:11:56 PM PDT 24
Finished Jul 15 07:12:14 PM PDT 24
Peak memory 214024 kb
Host smart-22ab763b-1a12-4b44-ba25-23baa415ab96
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450870336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_shadow_reg_errors_with_csr_rw.450870336
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1082656405
Short name T990
Test name
Test status
Simulation time 300738769 ps
CPU time 2.42 seconds
Started Jul 15 07:11:54 PM PDT 24
Finished Jul 15 07:12:05 PM PDT 24
Peak memory 216020 kb
Host smart-7a4c10da-caef-4aef-82c0-368c6069d2a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082656405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1082656405
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1588813495
Short name T190
Test name
Test status
Simulation time 106992773 ps
CPU time 1.61 seconds
Started Jul 15 07:12:07 PM PDT 24
Finished Jul 15 07:12:14 PM PDT 24
Peak memory 213696 kb
Host smart-ebbb3510-4d69-434c-9589-15755df7c2eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588813495 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1588813495
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2432528129
Short name T955
Test name
Test status
Simulation time 17080302 ps
CPU time 0.96 seconds
Started Jul 15 07:11:59 PM PDT 24
Finished Jul 15 07:12:08 PM PDT 24
Peak memory 205448 kb
Host smart-1050b60c-7d5d-47da-a925-5ad5b65d73c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432528129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.2432528129
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.339846437
Short name T1011
Test name
Test status
Simulation time 10187182 ps
CPU time 0.72 seconds
Started Jul 15 07:12:00 PM PDT 24
Finished Jul 15 07:12:09 PM PDT 24
Peak memory 205228 kb
Host smart-0a9d4aea-f3f4-4007-a69f-79af899fb68e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339846437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.339846437
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.462885577
Short name T1069
Test name
Test status
Simulation time 58039790 ps
CPU time 2.35 seconds
Started Jul 15 07:12:01 PM PDT 24
Finished Jul 15 07:12:12 PM PDT 24
Peak memory 205508 kb
Host smart-81cc65e7-dd50-4e81-a9d1-a8b8b336cf36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462885577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_sa
me_csr_outstanding.462885577
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.72239618
Short name T988
Test name
Test status
Simulation time 1707973667 ps
CPU time 4.75 seconds
Started Jul 15 07:11:59 PM PDT 24
Finished Jul 15 07:12:12 PM PDT 24
Peak memory 214028 kb
Host smart-615bcc5f-1cc7-40c0-9880-b25e5fd5fe21
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72239618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shadow
_reg_errors.72239618
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.2421525787
Short name T1053
Test name
Test status
Simulation time 812903303 ps
CPU time 4.64 seconds
Started Jul 15 07:12:07 PM PDT 24
Finished Jul 15 07:12:17 PM PDT 24
Peak memory 214004 kb
Host smart-4b0479f7-27d2-48cf-afed-bd607b6e93f3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421525787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.2421525787
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1250901723
Short name T1037
Test name
Test status
Simulation time 99638588 ps
CPU time 3.36 seconds
Started Jul 15 07:12:07 PM PDT 24
Finished Jul 15 07:12:16 PM PDT 24
Peak memory 213716 kb
Host smart-6132af3c-9ce6-413c-8729-17fabbc8d2fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250901723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.1250901723
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.942427415
Short name T935
Test name
Test status
Simulation time 185311203 ps
CPU time 2.25 seconds
Started Jul 15 07:11:57 PM PDT 24
Finished Jul 15 07:12:08 PM PDT 24
Peak memory 213728 kb
Host smart-9be3e745-b984-4d3a-b85e-0b0acc401f89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942427415 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.942427415
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.1756570599
Short name T946
Test name
Test status
Simulation time 66752235 ps
CPU time 0.9 seconds
Started Jul 15 07:12:00 PM PDT 24
Finished Jul 15 07:12:09 PM PDT 24
Peak memory 205360 kb
Host smart-531ed1a9-d918-49db-a60b-42dd2f43c542
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756570599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.1756570599
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2118805136
Short name T947
Test name
Test status
Simulation time 15422718 ps
CPU time 0.78 seconds
Started Jul 15 07:12:01 PM PDT 24
Finished Jul 15 07:12:10 PM PDT 24
Peak memory 205336 kb
Host smart-38461a57-0983-41f7-b4ef-1dcbc56ed406
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118805136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.2118805136
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3782111515
Short name T140
Test name
Test status
Simulation time 354699882 ps
CPU time 2.75 seconds
Started Jul 15 07:12:00 PM PDT 24
Finished Jul 15 07:12:11 PM PDT 24
Peak memory 205512 kb
Host smart-b7e6f20e-d099-459b-8fe8-31f7732f7a58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782111515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.3782111515
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2537134014
Short name T1084
Test name
Test status
Simulation time 154728340 ps
CPU time 4.65 seconds
Started Jul 15 07:11:58 PM PDT 24
Finished Jul 15 07:12:10 PM PDT 24
Peak memory 222180 kb
Host smart-4ac968d6-1906-4b7b-a128-2c061b1429a6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537134014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.2537134014
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3964131505
Short name T1010
Test name
Test status
Simulation time 516080351 ps
CPU time 8.01 seconds
Started Jul 15 07:12:07 PM PDT 24
Finished Jul 15 07:12:20 PM PDT 24
Peak memory 213972 kb
Host smart-cb6ad99a-68e7-482e-ade8-e33b129540e0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964131505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.3964131505
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1787594505
Short name T1024
Test name
Test status
Simulation time 210372553 ps
CPU time 2.21 seconds
Started Jul 15 07:12:06 PM PDT 24
Finished Jul 15 07:12:15 PM PDT 24
Peak memory 213820 kb
Host smart-50adb52f-701d-41ac-a63b-4fa9a7a002fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787594505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1787594505
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1857710541
Short name T389
Test name
Test status
Simulation time 229948710 ps
CPU time 4.81 seconds
Started Jul 15 07:12:00 PM PDT 24
Finished Jul 15 07:12:13 PM PDT 24
Peak memory 205644 kb
Host smart-d7064812-b19b-4454-86ff-3cd8274f2c66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857710541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.1857710541
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.120697758
Short name T1031
Test name
Test status
Simulation time 212324365 ps
CPU time 1.07 seconds
Started Jul 15 07:11:58 PM PDT 24
Finished Jul 15 07:12:07 PM PDT 24
Peak memory 205580 kb
Host smart-01a75378-3f4b-41a1-9367-9c2f6a155374
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120697758 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.120697758
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2459928283
Short name T138
Test name
Test status
Simulation time 40259032 ps
CPU time 1.09 seconds
Started Jul 15 07:11:56 PM PDT 24
Finished Jul 15 07:12:06 PM PDT 24
Peak memory 205468 kb
Host smart-6c4694d0-e011-42f6-86f3-88a6304b2bea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459928283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.2459928283
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3510907155
Short name T984
Test name
Test status
Simulation time 28646172 ps
CPU time 0.71 seconds
Started Jul 15 07:11:59 PM PDT 24
Finished Jul 15 07:12:08 PM PDT 24
Peak memory 205316 kb
Host smart-0afc4151-4986-4453-943c-37f22211a7d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510907155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3510907155
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.325411862
Short name T139
Test name
Test status
Simulation time 34123030 ps
CPU time 2.39 seconds
Started Jul 15 07:12:02 PM PDT 24
Finished Jul 15 07:12:13 PM PDT 24
Peak memory 205548 kb
Host smart-1db39f3d-b4b1-48e7-a955-0d2d2bbdd310
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325411862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_sa
me_csr_outstanding.325411862
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2292911644
Short name T1061
Test name
Test status
Simulation time 169005415 ps
CPU time 1.4 seconds
Started Jul 15 07:11:55 PM PDT 24
Finished Jul 15 07:12:05 PM PDT 24
Peak memory 214032 kb
Host smart-635a57fb-d73d-44e2-820d-7c9af0dec5c3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292911644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.2292911644
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.260584115
Short name T1071
Test name
Test status
Simulation time 450122608 ps
CPU time 15.14 seconds
Started Jul 15 07:11:56 PM PDT 24
Finished Jul 15 07:12:20 PM PDT 24
Peak memory 220664 kb
Host smart-d0a4d5dc-c089-484a-8eb4-c7c57493d4a9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260584115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_shadow_reg_errors_with_csr_rw.260584115
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2503153329
Short name T960
Test name
Test status
Simulation time 171753309 ps
CPU time 3.61 seconds
Started Jul 15 07:12:01 PM PDT 24
Finished Jul 15 07:12:13 PM PDT 24
Peak memory 216892 kb
Host smart-b6c19411-7130-423c-ae41-8ccc50613588
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503153329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.2503153329
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3660712
Short name T1049
Test name
Test status
Simulation time 48225707 ps
CPU time 2.25 seconds
Started Jul 15 07:12:01 PM PDT 24
Finished Jul 15 07:12:12 PM PDT 24
Peak memory 214024 kb
Host smart-9a51f6d6-5a75-48e1-8cee-53f4900b22a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660712 -assert nopostproc +UVM_TESTNAME=ke
ymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.3660712
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.3126148759
Short name T956
Test name
Test status
Simulation time 39656802 ps
CPU time 1.23 seconds
Started Jul 15 07:12:04 PM PDT 24
Finished Jul 15 07:12:12 PM PDT 24
Peak memory 205536 kb
Host smart-bc1467b1-dba2-4a75-80e4-2e7267df5483
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126148759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.3126148759
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.1490332295
Short name T1029
Test name
Test status
Simulation time 42480137 ps
CPU time 0.78 seconds
Started Jul 15 07:12:07 PM PDT 24
Finished Jul 15 07:12:13 PM PDT 24
Peak memory 205232 kb
Host smart-bec916d5-5c9f-4809-bde6-a167c34ed93e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490332295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.1490332295
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2752743364
Short name T1014
Test name
Test status
Simulation time 38322767 ps
CPU time 2.03 seconds
Started Jul 15 07:12:06 PM PDT 24
Finished Jul 15 07:12:14 PM PDT 24
Peak memory 205620 kb
Host smart-bb8997af-a3f9-4039-be43-eddb1f011602
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752743364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2752743364
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1295578893
Short name T1048
Test name
Test status
Simulation time 45496614 ps
CPU time 1.83 seconds
Started Jul 15 07:11:57 PM PDT 24
Finished Jul 15 07:12:07 PM PDT 24
Peak memory 213976 kb
Host smart-6b1206ae-d090-4e5a-bd51-7b6866dd6a44
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295578893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.1295578893
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.4293580218
Short name T1008
Test name
Test status
Simulation time 752281836 ps
CPU time 5.56 seconds
Started Jul 15 07:11:58 PM PDT 24
Finished Jul 15 07:12:11 PM PDT 24
Peak memory 213892 kb
Host smart-49a3d96b-ec67-4ba8-9ed9-151ac2b0efe3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293580218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.4293580218
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3802067977
Short name T971
Test name
Test status
Simulation time 470002510 ps
CPU time 3.66 seconds
Started Jul 15 07:12:02 PM PDT 24
Finished Jul 15 07:12:14 PM PDT 24
Peak memory 213652 kb
Host smart-c92d9148-2620-4c92-b541-957c2bc5d72a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802067977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.3802067977
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.943337760
Short name T155
Test name
Test status
Simulation time 53033155 ps
CPU time 2.1 seconds
Started Jul 15 07:12:13 PM PDT 24
Finished Jul 15 07:12:17 PM PDT 24
Peak memory 213792 kb
Host smart-de8b1717-08e6-4eae-9cbe-04125bd793be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943337760 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.943337760
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.506169135
Short name T164
Test name
Test status
Simulation time 15687583 ps
CPU time 0.93 seconds
Started Jul 15 07:12:12 PM PDT 24
Finished Jul 15 07:12:15 PM PDT 24
Peak memory 205416 kb
Host smart-9265afaa-16a4-4278-9ee5-c4581d135db2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506169135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.506169135
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3072448768
Short name T945
Test name
Test status
Simulation time 14934580 ps
CPU time 0.75 seconds
Started Jul 15 07:12:07 PM PDT 24
Finished Jul 15 07:12:13 PM PDT 24
Peak memory 205228 kb
Host smart-48ab4654-0625-48a2-a548-e702d66c3d98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072448768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.3072448768
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.889006706
Short name T1018
Test name
Test status
Simulation time 194040916 ps
CPU time 2.22 seconds
Started Jul 15 07:12:07 PM PDT 24
Finished Jul 15 07:12:15 PM PDT 24
Peak memory 205340 kb
Host smart-49c7ac40-4163-46bf-a9d0-2255e0d30011
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889006706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_sa
me_csr_outstanding.889006706
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.2692534857
Short name T1025
Test name
Test status
Simulation time 553092904 ps
CPU time 3.88 seconds
Started Jul 15 07:12:03 PM PDT 24
Finished Jul 15 07:12:14 PM PDT 24
Peak memory 214004 kb
Host smart-5a3febd2-09f2-4d8d-a09e-d743c69d6832
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692534857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.2692534857
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.4046274814
Short name T1015
Test name
Test status
Simulation time 342715564 ps
CPU time 4.44 seconds
Started Jul 15 07:12:05 PM PDT 24
Finished Jul 15 07:12:16 PM PDT 24
Peak memory 214120 kb
Host smart-e9d3e16d-1407-48d0-89a7-fa8ee67cd206
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046274814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.4046274814
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.967174704
Short name T191
Test name
Test status
Simulation time 264326283 ps
CPU time 2.8 seconds
Started Jul 15 07:12:03 PM PDT 24
Finished Jul 15 07:12:14 PM PDT 24
Peak memory 215020 kb
Host smart-82e8c424-69dc-4125-a12f-cdfc278c2a81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967174704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.967174704
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2570028704
Short name T1038
Test name
Test status
Simulation time 201861461 ps
CPU time 2.09 seconds
Started Jul 15 07:12:25 PM PDT 24
Finished Jul 15 07:12:33 PM PDT 24
Peak memory 205508 kb
Host smart-cf5841ce-df59-423b-bdeb-08618ab43273
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570028704 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.2570028704
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2646190474
Short name T980
Test name
Test status
Simulation time 29566431 ps
CPU time 1.1 seconds
Started Jul 15 07:12:08 PM PDT 24
Finished Jul 15 07:12:14 PM PDT 24
Peak memory 205360 kb
Host smart-51ce4c99-2fab-467e-b7b7-5faa943da625
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646190474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.2646190474
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.3315061980
Short name T952
Test name
Test status
Simulation time 15901860 ps
CPU time 0.78 seconds
Started Jul 15 07:12:12 PM PDT 24
Finished Jul 15 07:12:15 PM PDT 24
Peak memory 205244 kb
Host smart-4805c64e-1e5e-47d6-8768-77296aea2051
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315061980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.3315061980
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1359363962
Short name T1076
Test name
Test status
Simulation time 63784595 ps
CPU time 1.5 seconds
Started Jul 15 07:12:10 PM PDT 24
Finished Jul 15 07:12:15 PM PDT 24
Peak memory 205676 kb
Host smart-5b44d277-12e4-471a-86d2-ca8ad27bedc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359363962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.1359363962
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.290314507
Short name T982
Test name
Test status
Simulation time 147365239 ps
CPU time 3.19 seconds
Started Jul 15 07:12:08 PM PDT 24
Finished Jul 15 07:12:16 PM PDT 24
Peak memory 213956 kb
Host smart-217ddf80-a6bc-4e4e-813b-4cbeb0e43507
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290314507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shado
w_reg_errors.290314507
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.4003414399
Short name T113
Test name
Test status
Simulation time 220592539 ps
CPU time 5.33 seconds
Started Jul 15 07:12:10 PM PDT 24
Finished Jul 15 07:12:19 PM PDT 24
Peak memory 219936 kb
Host smart-a4cea5ef-8e63-4889-a366-1b4df4ea2f09
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003414399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.4003414399
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.3929960083
Short name T991
Test name
Test status
Simulation time 226823790 ps
CPU time 1.91 seconds
Started Jul 15 07:12:12 PM PDT 24
Finished Jul 15 07:12:17 PM PDT 24
Peak memory 205552 kb
Host smart-ab68521c-c287-4110-b4a2-3455c64d8679
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929960083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.3929960083
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1784880621
Short name T1022
Test name
Test status
Simulation time 19264304 ps
CPU time 1.35 seconds
Started Jul 15 07:12:16 PM PDT 24
Finished Jul 15 07:12:19 PM PDT 24
Peak memory 213828 kb
Host smart-ced9a543-8a30-4f51-baa7-d8f9e9c940fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784880621 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.1784880621
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.2880814471
Short name T1051
Test name
Test status
Simulation time 22622937 ps
CPU time 1.27 seconds
Started Jul 15 07:12:28 PM PDT 24
Finished Jul 15 07:12:39 PM PDT 24
Peak memory 205528 kb
Host smart-56e65477-694f-4731-a071-0646f2a690c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880814471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.2880814471
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3322717600
Short name T931
Test name
Test status
Simulation time 17133255 ps
CPU time 0.94 seconds
Started Jul 15 07:12:22 PM PDT 24
Finished Jul 15 07:12:28 PM PDT 24
Peak memory 205324 kb
Host smart-77e2ed12-bf98-45ae-ad0a-ede40eafc1db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322717600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3322717600
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1070014871
Short name T976
Test name
Test status
Simulation time 335175121 ps
CPU time 3.36 seconds
Started Jul 15 07:12:20 PM PDT 24
Finished Jul 15 07:12:26 PM PDT 24
Peak memory 205432 kb
Host smart-6dc59bbb-38a4-4a1d-9047-16f3bb56de35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070014871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.1070014871
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2584947487
Short name T978
Test name
Test status
Simulation time 459714924 ps
CPU time 1.86 seconds
Started Jul 15 07:12:15 PM PDT 24
Finished Jul 15 07:12:18 PM PDT 24
Peak memory 214024 kb
Host smart-4d74922e-a9d1-4f59-8d0d-a267253898f3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584947487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.2584947487
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.233391325
Short name T119
Test name
Test status
Simulation time 204805161 ps
CPU time 7.34 seconds
Started Jul 15 07:12:16 PM PDT 24
Finished Jul 15 07:12:25 PM PDT 24
Peak memory 220660 kb
Host smart-8a0ccc80-9251-4b2f-86c8-05b979dc5bb9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233391325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
keymgr_shadow_reg_errors_with_csr_rw.233391325
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.3864728832
Short name T1003
Test name
Test status
Simulation time 229591286 ps
CPU time 3.91 seconds
Started Jul 15 07:12:24 PM PDT 24
Finished Jul 15 07:12:34 PM PDT 24
Peak memory 213720 kb
Host smart-bca860a4-71cc-40c8-ac7e-a82997d4d27d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864728832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.3864728832
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2374082413
Short name T175
Test name
Test status
Simulation time 799077050 ps
CPU time 5.81 seconds
Started Jul 15 07:12:20 PM PDT 24
Finished Jul 15 07:12:29 PM PDT 24
Peak memory 205436 kb
Host smart-aa525bab-db62-482e-8038-e790dc959589
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374082413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.2374082413
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2067411693
Short name T941
Test name
Test status
Simulation time 15240722 ps
CPU time 1.11 seconds
Started Jul 15 07:12:27 PM PDT 24
Finished Jul 15 07:12:36 PM PDT 24
Peak memory 213772 kb
Host smart-2423bbb8-d2cc-4658-b87e-f43eb075e14b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067411693 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.2067411693
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.3460391945
Short name T1001
Test name
Test status
Simulation time 13968319 ps
CPU time 1.13 seconds
Started Jul 15 07:12:15 PM PDT 24
Finished Jul 15 07:12:17 PM PDT 24
Peak memory 205500 kb
Host smart-d091bcdf-b970-4b44-b75c-f91c118a3bb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460391945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.3460391945
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3515271482
Short name T1016
Test name
Test status
Simulation time 14752376 ps
CPU time 0.83 seconds
Started Jul 15 07:12:20 PM PDT 24
Finished Jul 15 07:12:25 PM PDT 24
Peak memory 205228 kb
Host smart-0abbeab0-ee49-4d50-8c5b-703e2e646e2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515271482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.3515271482
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.2610617237
Short name T970
Test name
Test status
Simulation time 229355929 ps
CPU time 2.01 seconds
Started Jul 15 07:12:24 PM PDT 24
Finished Jul 15 07:12:31 PM PDT 24
Peak memory 205572 kb
Host smart-afb6fcab-bc11-479b-b79e-e5031274d703
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610617237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.2610617237
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2429839364
Short name T121
Test name
Test status
Simulation time 496467027 ps
CPU time 2.36 seconds
Started Jul 15 07:12:26 PM PDT 24
Finished Jul 15 07:12:36 PM PDT 24
Peak memory 214032 kb
Host smart-36705a7f-ff87-4395-ab6e-714ed4e70546
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429839364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.2429839364
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.907781864
Short name T995
Test name
Test status
Simulation time 354217083 ps
CPU time 12.42 seconds
Started Jul 15 07:12:22 PM PDT 24
Finished Jul 15 07:12:39 PM PDT 24
Peak memory 213920 kb
Host smart-2c69d095-0b9d-4628-a067-234c744bcdfb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907781864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_shadow_reg_errors_with_csr_rw.907781864
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3740250923
Short name T1066
Test name
Test status
Simulation time 62368756 ps
CPU time 2.63 seconds
Started Jul 15 07:12:19 PM PDT 24
Finished Jul 15 07:12:23 PM PDT 24
Peak memory 214772 kb
Host smart-6e42c29c-2ab8-4776-8597-f28bf6e1935d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740250923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.3740250923
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2503451665
Short name T1021
Test name
Test status
Simulation time 175202019 ps
CPU time 3.73 seconds
Started Jul 15 07:12:30 PM PDT 24
Finished Jul 15 07:12:47 PM PDT 24
Peak memory 205700 kb
Host smart-962d007e-23c6-43c3-81a5-a6c8bdf43fca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503451665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.2503451665
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2254301569
Short name T940
Test name
Test status
Simulation time 66860868 ps
CPU time 2.07 seconds
Started Jul 15 07:12:27 PM PDT 24
Finished Jul 15 07:12:37 PM PDT 24
Peak memory 216884 kb
Host smart-c9b8d1d1-4ebc-4928-8a0f-7530d1fda4e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254301569 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.2254301569
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3925603804
Short name T141
Test name
Test status
Simulation time 14319382 ps
CPU time 1.08 seconds
Started Jul 15 07:12:15 PM PDT 24
Finished Jul 15 07:12:17 PM PDT 24
Peak memory 205460 kb
Host smart-6d016ba5-7b1f-4abc-94c4-75c94e20f76e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925603804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.3925603804
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.23469409
Short name T1073
Test name
Test status
Simulation time 102028947 ps
CPU time 0.73 seconds
Started Jul 15 07:12:25 PM PDT 24
Finished Jul 15 07:12:32 PM PDT 24
Peak memory 205328 kb
Host smart-eec4ccc6-14af-4a9c-9a79-aa890c25bed3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23469409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.23469409
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3540883535
Short name T1091
Test name
Test status
Simulation time 88664613 ps
CPU time 2.64 seconds
Started Jul 15 07:12:27 PM PDT 24
Finished Jul 15 07:12:39 PM PDT 24
Peak memory 205532 kb
Host smart-9974f168-05d0-4b95-9bb7-09db1f927c7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540883535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.3540883535
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2093527964
Short name T1004
Test name
Test status
Simulation time 214993610 ps
CPU time 5.93 seconds
Started Jul 15 07:12:22 PM PDT 24
Finished Jul 15 07:12:33 PM PDT 24
Peak memory 213984 kb
Host smart-fbd461d3-6d0f-42fc-96ab-341e77fc7157
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093527964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.2093527964
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.4061349549
Short name T1006
Test name
Test status
Simulation time 354681109 ps
CPU time 13.04 seconds
Started Jul 15 07:12:21 PM PDT 24
Finished Jul 15 07:12:39 PM PDT 24
Peak memory 214076 kb
Host smart-430f6e79-11d6-46e7-8846-ed62c68eff44
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061349549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.4061349549
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3706495733
Short name T1039
Test name
Test status
Simulation time 104973304 ps
CPU time 2.01 seconds
Started Jul 15 07:12:20 PM PDT 24
Finished Jul 15 07:12:26 PM PDT 24
Peak memory 213720 kb
Host smart-9419ad59-c4a4-4cd3-a536-ee3fb8da0d7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706495733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3706495733
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.2531142984
Short name T949
Test name
Test status
Simulation time 61525750 ps
CPU time 1.04 seconds
Started Jul 15 07:12:16 PM PDT 24
Finished Jul 15 07:12:18 PM PDT 24
Peak memory 205520 kb
Host smart-c9db090d-d3ad-41f8-abb4-c2771cfcf808
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531142984 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.2531142984
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1422644396
Short name T1063
Test name
Test status
Simulation time 92415525 ps
CPU time 1.52 seconds
Started Jul 15 07:12:24 PM PDT 24
Finished Jul 15 07:12:31 PM PDT 24
Peak memory 205440 kb
Host smart-f2f98f26-73ef-42fd-8f59-6768336f8943
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422644396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.1422644396
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.30977056
Short name T951
Test name
Test status
Simulation time 10597870 ps
CPU time 0.81 seconds
Started Jul 15 07:12:25 PM PDT 24
Finished Jul 15 07:12:32 PM PDT 24
Peak memory 205328 kb
Host smart-40eb063b-faf1-4763-9575-327c28f6b33f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30977056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.30977056
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1851696257
Short name T1062
Test name
Test status
Simulation time 1030097006 ps
CPU time 3.27 seconds
Started Jul 15 07:12:27 PM PDT 24
Finished Jul 15 07:12:38 PM PDT 24
Peak memory 205508 kb
Host smart-47dd5983-e4d0-4732-b4fc-d7d44f4840be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851696257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.1851696257
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1968512856
Short name T958
Test name
Test status
Simulation time 233738027 ps
CPU time 1.9 seconds
Started Jul 15 07:12:23 PM PDT 24
Finished Jul 15 07:12:30 PM PDT 24
Peak memory 214024 kb
Host smart-aeb82bc5-1a44-46a2-a680-3b7cc8875d36
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968512856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.1968512856
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1313657994
Short name T1041
Test name
Test status
Simulation time 4780170494 ps
CPU time 11.11 seconds
Started Jul 15 07:12:28 PM PDT 24
Finished Jul 15 07:12:49 PM PDT 24
Peak memory 214040 kb
Host smart-714a0caf-ca46-44e0-88c5-0daaa7d24a02
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313657994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.1313657994
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.575731431
Short name T1002
Test name
Test status
Simulation time 114602044 ps
CPU time 2.2 seconds
Started Jul 15 07:12:20 PM PDT 24
Finished Jul 15 07:12:26 PM PDT 24
Peak memory 213720 kb
Host smart-64f6d271-c00d-4f6a-b95b-664f21aff229
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575731431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.575731431
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.2524467012
Short name T181
Test name
Test status
Simulation time 214656728 ps
CPU time 3.64 seconds
Started Jul 15 07:12:20 PM PDT 24
Finished Jul 15 07:12:26 PM PDT 24
Peak memory 205560 kb
Host smart-9703ce4e-8db5-43c1-a139-9c95ddb510fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524467012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.2524467012
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3168346578
Short name T1047
Test name
Test status
Simulation time 509474331 ps
CPU time 8.87 seconds
Started Jul 15 07:11:59 PM PDT 24
Finished Jul 15 07:12:16 PM PDT 24
Peak memory 205544 kb
Host smart-cf621948-09e4-4bdb-9ea2-61c04f3d293f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168346578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3
168346578
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3929803814
Short name T391
Test name
Test status
Simulation time 1221544107 ps
CPU time 16.21 seconds
Started Jul 15 07:12:07 PM PDT 24
Finished Jul 15 07:12:29 PM PDT 24
Peak memory 205540 kb
Host smart-c5aeecc8-acff-4ce9-99d4-0bf133e4bf6a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929803814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.3
929803814
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3557785331
Short name T1057
Test name
Test status
Simulation time 65857493 ps
CPU time 0.97 seconds
Started Jul 15 07:11:58 PM PDT 24
Finished Jul 15 07:12:07 PM PDT 24
Peak memory 205396 kb
Host smart-eef7b7f3-7ab1-43ac-91d0-652a9265f5f7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557785331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.3
557785331
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3471304678
Short name T1056
Test name
Test status
Simulation time 57102108 ps
CPU time 0.91 seconds
Started Jul 15 07:12:07 PM PDT 24
Finished Jul 15 07:12:13 PM PDT 24
Peak memory 205396 kb
Host smart-370450e1-3420-4a71-aadf-b9fcaa15770b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471304678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.3471304678
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.3235778592
Short name T1058
Test name
Test status
Simulation time 13851321 ps
CPU time 0.75 seconds
Started Jul 15 07:11:59 PM PDT 24
Finished Jul 15 07:12:07 PM PDT 24
Peak memory 205340 kb
Host smart-fd43bb73-e2ec-4c58-bde6-aef684872c29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235778592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.3235778592
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.826765887
Short name T1042
Test name
Test status
Simulation time 96095674 ps
CPU time 1.42 seconds
Started Jul 15 07:12:00 PM PDT 24
Finished Jul 15 07:12:10 PM PDT 24
Peak memory 205508 kb
Host smart-5a37a80f-229e-4edb-8e29-8e28f793face
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826765887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sam
e_csr_outstanding.826765887
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1690515167
Short name T118
Test name
Test status
Simulation time 654028575 ps
CPU time 2.99 seconds
Started Jul 15 07:11:57 PM PDT 24
Finished Jul 15 07:12:08 PM PDT 24
Peak memory 214020 kb
Host smart-04b7ba3e-db98-47d2-b92c-f48cdc0959a4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690515167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.1690515167
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.1533620165
Short name T1035
Test name
Test status
Simulation time 779689296 ps
CPU time 5.02 seconds
Started Jul 15 07:11:56 PM PDT 24
Finished Jul 15 07:12:09 PM PDT 24
Peak memory 222180 kb
Host smart-76312a40-147b-4d66-ab30-edfe2b4e6453
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533620165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.1533620165
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3774943324
Short name T1077
Test name
Test status
Simulation time 48288443 ps
CPU time 3.39 seconds
Started Jul 15 07:11:56 PM PDT 24
Finished Jul 15 07:12:08 PM PDT 24
Peak memory 213776 kb
Host smart-b7688b65-926d-48cd-9520-9b9fefd17b81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774943324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.3774943324
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1750328921
Short name T950
Test name
Test status
Simulation time 249098162 ps
CPU time 0.87 seconds
Started Jul 15 07:12:33 PM PDT 24
Finished Jul 15 07:12:51 PM PDT 24
Peak memory 205304 kb
Host smart-8d8530d9-4283-432e-bd42-98f4806aa213
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750328921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.1750328921
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3437699580
Short name T1019
Test name
Test status
Simulation time 35841921 ps
CPU time 0.7 seconds
Started Jul 15 07:12:27 PM PDT 24
Finished Jul 15 07:12:36 PM PDT 24
Peak memory 205228 kb
Host smart-2007009d-f0f3-4dd7-bf21-bc03b6003b0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437699580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.3437699580
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2951547908
Short name T997
Test name
Test status
Simulation time 17549817 ps
CPU time 0.75 seconds
Started Jul 15 07:12:24 PM PDT 24
Finished Jul 15 07:12:31 PM PDT 24
Peak memory 205312 kb
Host smart-6433f83d-9931-4f9b-b55d-5c84a444ee6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951547908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2951547908
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.3206834130
Short name T973
Test name
Test status
Simulation time 49629769 ps
CPU time 0.84 seconds
Started Jul 15 07:12:31 PM PDT 24
Finished Jul 15 07:12:47 PM PDT 24
Peak memory 205324 kb
Host smart-f035f310-b0c6-4130-8b24-3534c21c6d5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206834130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.3206834130
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.3204423315
Short name T969
Test name
Test status
Simulation time 54002496 ps
CPU time 0.73 seconds
Started Jul 15 07:12:24 PM PDT 24
Finished Jul 15 07:12:30 PM PDT 24
Peak memory 205288 kb
Host smart-450e7ba8-aa99-43b1-ac24-995e0aaa2288
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204423315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.3204423315
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3808867629
Short name T1017
Test name
Test status
Simulation time 10973594 ps
CPU time 0.85 seconds
Started Jul 15 07:12:34 PM PDT 24
Finished Jul 15 07:12:53 PM PDT 24
Peak memory 205288 kb
Host smart-0196bb49-fda1-4c3f-8a94-54e2fa0eaa10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808867629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.3808867629
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3678599817
Short name T1065
Test name
Test status
Simulation time 37794406 ps
CPU time 0.71 seconds
Started Jul 15 07:12:32 PM PDT 24
Finished Jul 15 07:12:49 PM PDT 24
Peak memory 205208 kb
Host smart-d17cd199-0936-4083-affc-a5ea6ab41c2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678599817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.3678599817
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.1422674678
Short name T993
Test name
Test status
Simulation time 54217098 ps
CPU time 0.81 seconds
Started Jul 15 07:12:29 PM PDT 24
Finished Jul 15 07:12:40 PM PDT 24
Peak memory 205308 kb
Host smart-6a25c024-4f7d-44e9-aee6-632cd95a134b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422674678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.1422674678
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2984994617
Short name T989
Test name
Test status
Simulation time 9784924 ps
CPU time 0.7 seconds
Started Jul 15 07:12:24 PM PDT 24
Finished Jul 15 07:12:30 PM PDT 24
Peak memory 205348 kb
Host smart-fdf4e7da-67e9-46e0-81fa-2c31b010fb06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984994617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2984994617
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2194958711
Short name T981
Test name
Test status
Simulation time 19798339 ps
CPU time 0.82 seconds
Started Jul 15 07:12:31 PM PDT 24
Finished Jul 15 07:12:45 PM PDT 24
Peak memory 205256 kb
Host smart-119f5563-7d73-4522-a57e-74e1fc7c17fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194958711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.2194958711
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.1253597524
Short name T957
Test name
Test status
Simulation time 363873439 ps
CPU time 11.32 seconds
Started Jul 15 07:12:01 PM PDT 24
Finished Jul 15 07:12:20 PM PDT 24
Peak memory 205432 kb
Host smart-7eff254f-8b63-4432-a287-84be7825caed
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253597524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.1
253597524
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1968012996
Short name T986
Test name
Test status
Simulation time 2480298739 ps
CPU time 12.75 seconds
Started Jul 15 07:12:01 PM PDT 24
Finished Jul 15 07:12:22 PM PDT 24
Peak memory 205608 kb
Host smart-92031ce3-e119-4398-962a-46772ec0f488
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968012996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.1
968012996
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2694953631
Short name T1028
Test name
Test status
Simulation time 175274366 ps
CPU time 1.05 seconds
Started Jul 15 07:11:52 PM PDT 24
Finished Jul 15 07:12:01 PM PDT 24
Peak memory 205516 kb
Host smart-37904741-5c02-49fc-8a05-0de19d240135
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694953631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.2
694953631
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.1696462599
Short name T943
Test name
Test status
Simulation time 100664971 ps
CPU time 1.36 seconds
Started Jul 15 07:11:59 PM PDT 24
Finished Jul 15 07:12:08 PM PDT 24
Peak memory 205532 kb
Host smart-210da352-6d55-4bbe-8312-10db8acdb73a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696462599 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.1696462599
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3332549345
Short name T974
Test name
Test status
Simulation time 93108355 ps
CPU time 1.16 seconds
Started Jul 15 07:12:00 PM PDT 24
Finished Jul 15 07:12:09 PM PDT 24
Peak memory 205500 kb
Host smart-21084ddf-313c-416a-81ab-361ef6e34dc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332549345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3332549345
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.267572689
Short name T965
Test name
Test status
Simulation time 12165672 ps
CPU time 0.86 seconds
Started Jul 15 07:12:02 PM PDT 24
Finished Jul 15 07:12:11 PM PDT 24
Peak memory 205160 kb
Host smart-d2394d87-329f-406a-8d4a-00f633c8d3c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267572689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.267572689
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3643380100
Short name T972
Test name
Test status
Simulation time 192489940 ps
CPU time 1.35 seconds
Started Jul 15 07:12:05 PM PDT 24
Finished Jul 15 07:12:13 PM PDT 24
Peak memory 205528 kb
Host smart-d7365be5-87c8-4b94-bffd-f1429a48664b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643380100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.3643380100
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.4021475392
Short name T944
Test name
Test status
Simulation time 491988956 ps
CPU time 5.11 seconds
Started Jul 15 07:11:53 PM PDT 24
Finished Jul 15 07:12:06 PM PDT 24
Peak memory 213972 kb
Host smart-8dcb8fa6-19f4-4e35-9b3a-4fdaf9704450
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021475392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.4021475392
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2807125708
Short name T994
Test name
Test status
Simulation time 190370340 ps
CPU time 4.63 seconds
Started Jul 15 07:12:00 PM PDT 24
Finished Jul 15 07:12:13 PM PDT 24
Peak memory 213972 kb
Host smart-59be937b-3592-45ab-8bea-1fe8acdeb4f6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807125708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.2807125708
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3263597218
Short name T932
Test name
Test status
Simulation time 461168220 ps
CPU time 4.38 seconds
Started Jul 15 07:11:52 PM PDT 24
Finished Jul 15 07:12:04 PM PDT 24
Peak memory 213680 kb
Host smart-6a01221f-d405-4543-8175-a94ded34b0bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263597218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.3263597218
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2096366803
Short name T161
Test name
Test status
Simulation time 551074594 ps
CPU time 3.55 seconds
Started Jul 15 07:11:59 PM PDT 24
Finished Jul 15 07:12:11 PM PDT 24
Peak memory 213604 kb
Host smart-be8908b3-ac6a-465e-a0bc-c1b54c86572d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096366803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.2096366803
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3366945986
Short name T975
Test name
Test status
Simulation time 31987027 ps
CPU time 0.82 seconds
Started Jul 15 07:12:32 PM PDT 24
Finished Jul 15 07:12:47 PM PDT 24
Peak memory 205332 kb
Host smart-f6399c71-684c-454b-b388-8e11d43ae1fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366945986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3366945986
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.1223594788
Short name T962
Test name
Test status
Simulation time 19402245 ps
CPU time 0.83 seconds
Started Jul 15 07:12:32 PM PDT 24
Finished Jul 15 07:12:47 PM PDT 24
Peak memory 205328 kb
Host smart-f1ac87ad-745f-4572-a530-d224964aad19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223594788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.1223594788
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2624370036
Short name T1034
Test name
Test status
Simulation time 29311587 ps
CPU time 0.76 seconds
Started Jul 15 07:12:31 PM PDT 24
Finished Jul 15 07:12:45 PM PDT 24
Peak memory 205284 kb
Host smart-03eb6fb1-1377-4cd5-b3b1-0605df075d8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624370036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2624370036
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.4187255815
Short name T1059
Test name
Test status
Simulation time 57320816 ps
CPU time 0.73 seconds
Started Jul 15 07:12:32 PM PDT 24
Finished Jul 15 07:12:50 PM PDT 24
Peak memory 205316 kb
Host smart-dd48453f-c9d0-44d7-b2ba-d918c39cf717
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187255815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.4187255815
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1193170387
Short name T1080
Test name
Test status
Simulation time 35998634 ps
CPU time 0.73 seconds
Started Jul 15 07:12:31 PM PDT 24
Finished Jul 15 07:12:45 PM PDT 24
Peak memory 205332 kb
Host smart-4b036f31-356a-4d4d-9e4e-4bfc72b644ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193170387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1193170387
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.3308642184
Short name T937
Test name
Test status
Simulation time 16572563 ps
CPU time 0.75 seconds
Started Jul 15 07:12:25 PM PDT 24
Finished Jul 15 07:12:32 PM PDT 24
Peak memory 205324 kb
Host smart-a7aac39e-7e5c-4e15-beac-16e925b5b1bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308642184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.3308642184
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1016392528
Short name T1070
Test name
Test status
Simulation time 19611926 ps
CPU time 0.82 seconds
Started Jul 15 07:12:31 PM PDT 24
Finished Jul 15 07:12:45 PM PDT 24
Peak memory 205144 kb
Host smart-32a6dd03-1771-43cd-aba0-4ab26e3ae13e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016392528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.1016392528
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.3535148140
Short name T1064
Test name
Test status
Simulation time 13378377 ps
CPU time 0.74 seconds
Started Jul 15 07:12:33 PM PDT 24
Finished Jul 15 07:12:52 PM PDT 24
Peak memory 205268 kb
Host smart-5066dc37-522c-400d-8718-bf0c850130d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535148140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.3535148140
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3486257529
Short name T1082
Test name
Test status
Simulation time 42923773 ps
CPU time 0.83 seconds
Started Jul 15 07:12:32 PM PDT 24
Finished Jul 15 07:12:50 PM PDT 24
Peak memory 205288 kb
Host smart-537fee2d-de95-4cd2-968b-1830711ce9bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486257529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.3486257529
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.1948044316
Short name T1083
Test name
Test status
Simulation time 27717063 ps
CPU time 0.84 seconds
Started Jul 15 07:12:28 PM PDT 24
Finished Jul 15 07:12:38 PM PDT 24
Peak memory 205344 kb
Host smart-aad3f554-c503-486e-984d-d6b0b929994e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948044316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.1948044316
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.3564987606
Short name T144
Test name
Test status
Simulation time 285204435 ps
CPU time 4.83 seconds
Started Jul 15 07:11:59 PM PDT 24
Finished Jul 15 07:12:11 PM PDT 24
Peak memory 205460 kb
Host smart-62a21659-df4c-404d-9f50-eca6cd973e54
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564987606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.3
564987606
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.4054178440
Short name T1027
Test name
Test status
Simulation time 2844887928 ps
CPU time 31.54 seconds
Started Jul 15 07:12:00 PM PDT 24
Finished Jul 15 07:12:39 PM PDT 24
Peak memory 205544 kb
Host smart-342b79ed-7c5e-4c29-9e32-d8d459e40e4f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054178440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.4
054178440
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.4133322285
Short name T934
Test name
Test status
Simulation time 31683888 ps
CPU time 0.92 seconds
Started Jul 15 07:12:02 PM PDT 24
Finished Jul 15 07:12:11 PM PDT 24
Peak memory 205452 kb
Host smart-022f2627-ef52-4d33-a3be-c371b43d32fa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133322285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.4
133322285
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.681985732
Short name T156
Test name
Test status
Simulation time 150813579 ps
CPU time 1.35 seconds
Started Jul 15 07:12:03 PM PDT 24
Finished Jul 15 07:12:12 PM PDT 24
Peak memory 213572 kb
Host smart-bd02d976-0656-4c4d-8bba-193412093393
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681985732 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.681985732
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.3431147517
Short name T1000
Test name
Test status
Simulation time 50982783 ps
CPU time 1.23 seconds
Started Jul 15 07:12:02 PM PDT 24
Finished Jul 15 07:12:12 PM PDT 24
Peak memory 205408 kb
Host smart-e91e2df2-27db-45ec-975a-5af44b92ceab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431147517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.3431147517
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3154096900
Short name T996
Test name
Test status
Simulation time 17693745 ps
CPU time 0.8 seconds
Started Jul 15 07:11:58 PM PDT 24
Finished Jul 15 07:12:07 PM PDT 24
Peak memory 205352 kb
Host smart-33ba9f05-43fd-48c8-845a-6c24a3016134
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154096900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.3154096900
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1396833730
Short name T1087
Test name
Test status
Simulation time 80110584 ps
CPU time 1.27 seconds
Started Jul 15 07:11:59 PM PDT 24
Finished Jul 15 07:12:08 PM PDT 24
Peak memory 205516 kb
Host smart-3ffdec50-0843-4787-b690-53efc2b6122e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396833730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.1396833730
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1012581734
Short name T117
Test name
Test status
Simulation time 293660981 ps
CPU time 2.08 seconds
Started Jul 15 07:11:59 PM PDT 24
Finished Jul 15 07:12:09 PM PDT 24
Peak memory 214044 kb
Host smart-f1d3b274-9a95-4918-b7a9-57407a71d8ec
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012581734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1012581734
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.1285159000
Short name T1012
Test name
Test status
Simulation time 3477970128 ps
CPU time 12.19 seconds
Started Jul 15 07:12:02 PM PDT 24
Finished Jul 15 07:12:22 PM PDT 24
Peak memory 214024 kb
Host smart-ed3a1e5e-9ac8-4bda-ac9f-29c4450660df
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285159000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.1285159000
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.248807375
Short name T1067
Test name
Test status
Simulation time 539932352 ps
CPU time 4.65 seconds
Started Jul 15 07:11:53 PM PDT 24
Finished Jul 15 07:12:06 PM PDT 24
Peak memory 213796 kb
Host smart-53822f7e-0caa-4532-8014-50b1f9b35e44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248807375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.248807375
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.978229692
Short name T171
Test name
Test status
Simulation time 237684653 ps
CPU time 2.65 seconds
Started Jul 15 07:11:56 PM PDT 24
Finished Jul 15 07:12:07 PM PDT 24
Peak memory 213700 kb
Host smart-2d311751-8d46-4d3f-8632-ed9a83f4fa84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978229692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.
978229692
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.565113155
Short name T1060
Test name
Test status
Simulation time 27757715 ps
CPU time 0.86 seconds
Started Jul 15 07:12:27 PM PDT 24
Finished Jul 15 07:12:36 PM PDT 24
Peak memory 205320 kb
Host smart-8f45ecf4-5a03-431e-b4c6-c2b545c2831f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565113155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.565113155
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.529847690
Short name T963
Test name
Test status
Simulation time 22952546 ps
CPU time 0.74 seconds
Started Jul 15 07:12:32 PM PDT 24
Finished Jul 15 07:12:50 PM PDT 24
Peak memory 205352 kb
Host smart-8773845b-caca-404d-8577-ca5a06a87ed6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529847690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.529847690
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.59270910
Short name T1026
Test name
Test status
Simulation time 13869168 ps
CPU time 0.93 seconds
Started Jul 15 07:12:33 PM PDT 24
Finished Jul 15 07:12:52 PM PDT 24
Peak memory 205328 kb
Host smart-83beeb30-b115-4efa-b434-34d13a9dae9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59270910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.59270910
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.799416785
Short name T959
Test name
Test status
Simulation time 14769251 ps
CPU time 0.8 seconds
Started Jul 15 07:12:29 PM PDT 24
Finished Jul 15 07:12:40 PM PDT 24
Peak memory 205356 kb
Host smart-529e8a7c-923e-4389-9c28-8930be3e8cf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799416785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.799416785
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1665318002
Short name T1089
Test name
Test status
Simulation time 10583127 ps
CPU time 0.83 seconds
Started Jul 15 07:12:27 PM PDT 24
Finished Jul 15 07:12:36 PM PDT 24
Peak memory 205332 kb
Host smart-2458f8fb-bed8-44b9-81e7-9e6d2ca91dac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665318002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.1665318002
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.2539258434
Short name T964
Test name
Test status
Simulation time 8917030 ps
CPU time 0.69 seconds
Started Jul 15 07:12:30 PM PDT 24
Finished Jul 15 07:12:44 PM PDT 24
Peak memory 205348 kb
Host smart-75ccf936-e3ef-4096-bf5e-819af91858df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539258434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.2539258434
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1444087012
Short name T1050
Test name
Test status
Simulation time 39374870 ps
CPU time 0.81 seconds
Started Jul 15 07:12:31 PM PDT 24
Finished Jul 15 07:12:44 PM PDT 24
Peak memory 205292 kb
Host smart-8974f9c7-08c5-41cc-a675-dc251db5faaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444087012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.1444087012
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.277214886
Short name T999
Test name
Test status
Simulation time 24678827 ps
CPU time 0.7 seconds
Started Jul 15 07:12:34 PM PDT 24
Finished Jul 15 07:12:53 PM PDT 24
Peak memory 205212 kb
Host smart-815c3653-2ee6-4c4a-b438-b48fc0f5ba3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277214886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.277214886
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2784722285
Short name T1043
Test name
Test status
Simulation time 54066653 ps
CPU time 0.77 seconds
Started Jul 15 07:12:28 PM PDT 24
Finished Jul 15 07:12:39 PM PDT 24
Peak memory 205324 kb
Host smart-3b47645e-c068-4368-94f2-90384d91f982
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784722285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.2784722285
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.921071348
Short name T939
Test name
Test status
Simulation time 67767893 ps
CPU time 0.81 seconds
Started Jul 15 07:12:35 PM PDT 24
Finished Jul 15 07:12:56 PM PDT 24
Peak memory 205316 kb
Host smart-453f40f1-cb0a-4436-9f1f-e565971fc391
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921071348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.921071348
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3588687401
Short name T1020
Test name
Test status
Simulation time 52496646 ps
CPU time 1.49 seconds
Started Jul 15 07:12:00 PM PDT 24
Finished Jul 15 07:12:10 PM PDT 24
Peak memory 213640 kb
Host smart-0883c4d4-2bd5-4b63-94c5-4604a5e68115
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588687401 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3588687401
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2461221065
Short name T1040
Test name
Test status
Simulation time 16670824 ps
CPU time 0.93 seconds
Started Jul 15 07:12:05 PM PDT 24
Finished Jul 15 07:12:12 PM PDT 24
Peak memory 205292 kb
Host smart-54cbed3a-2630-4022-9f55-cfcfbc9f2b21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461221065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.2461221065
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.2281945201
Short name T942
Test name
Test status
Simulation time 40381326 ps
CPU time 0.86 seconds
Started Jul 15 07:12:01 PM PDT 24
Finished Jul 15 07:12:11 PM PDT 24
Peak memory 205340 kb
Host smart-987f61a3-35e5-49c4-a48e-dc72331fcdfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281945201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.2281945201
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.612120671
Short name T1068
Test name
Test status
Simulation time 102556996 ps
CPU time 2.12 seconds
Started Jul 15 07:12:00 PM PDT 24
Finished Jul 15 07:12:10 PM PDT 24
Peak memory 205496 kb
Host smart-2ac13402-88f3-4f8a-beef-a7558acbc720
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612120671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sam
e_csr_outstanding.612120671
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.2762587106
Short name T1052
Test name
Test status
Simulation time 89817659 ps
CPU time 2.3 seconds
Started Jul 15 07:11:50 PM PDT 24
Finished Jul 15 07:12:00 PM PDT 24
Peak memory 214044 kb
Host smart-4421be6a-0b1a-475d-990d-aa8c395b39b0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762587106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.2762587106
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1612679881
Short name T977
Test name
Test status
Simulation time 916763739 ps
CPU time 15.96 seconds
Started Jul 15 07:11:58 PM PDT 24
Finished Jul 15 07:12:23 PM PDT 24
Peak memory 214036 kb
Host smart-30c66158-cc2a-451a-9f6d-c4201e46dfd4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612679881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.1612679881
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.604079222
Short name T1055
Test name
Test status
Simulation time 82393027 ps
CPU time 3.09 seconds
Started Jul 15 07:12:05 PM PDT 24
Finished Jul 15 07:12:15 PM PDT 24
Peak memory 213676 kb
Host smart-3e194bc2-96cd-45bc-9291-3ea660c90191
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604079222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.604079222
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2019619404
Short name T1045
Test name
Test status
Simulation time 86817418 ps
CPU time 2.04 seconds
Started Jul 15 07:12:03 PM PDT 24
Finished Jul 15 07:12:13 PM PDT 24
Peak memory 213800 kb
Host smart-c1f003cd-8551-4395-b4b6-8343ecaf20a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019619404 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.2019619404
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.3132462266
Short name T1075
Test name
Test status
Simulation time 106891040 ps
CPU time 1.5 seconds
Started Jul 15 07:12:03 PM PDT 24
Finished Jul 15 07:12:12 PM PDT 24
Peak memory 205420 kb
Host smart-833c55d9-992c-4dde-9ea2-98e34027e940
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132462266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.3132462266
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2458825038
Short name T1086
Test name
Test status
Simulation time 9859076 ps
CPU time 0.72 seconds
Started Jul 15 07:11:59 PM PDT 24
Finished Jul 15 07:12:07 PM PDT 24
Peak memory 205268 kb
Host smart-1a5dc2ff-9664-4e8b-8a1d-6433704d877e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458825038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.2458825038
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.809186821
Short name T1023
Test name
Test status
Simulation time 41104843 ps
CPU time 1.38 seconds
Started Jul 15 07:12:03 PM PDT 24
Finished Jul 15 07:12:12 PM PDT 24
Peak memory 205496 kb
Host smart-838932a5-fbdb-4588-882c-c8fa6d71f7b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809186821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sam
e_csr_outstanding.809186821
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.4279611844
Short name T933
Test name
Test status
Simulation time 255397325 ps
CPU time 2.02 seconds
Started Jul 15 07:12:03 PM PDT 24
Finished Jul 15 07:12:13 PM PDT 24
Peak memory 205496 kb
Host smart-9fe9d66e-108c-4dd9-a1e5-60918d41a8cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279611844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.4279611844
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3983778174
Short name T386
Test name
Test status
Simulation time 148902911 ps
CPU time 4.58 seconds
Started Jul 15 07:12:02 PM PDT 24
Finished Jul 15 07:12:15 PM PDT 24
Peak memory 214904 kb
Host smart-706d7c6b-b5b6-4993-9682-fc129e2ef604
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983778174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.3983778174
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.1316460883
Short name T1033
Test name
Test status
Simulation time 46415294 ps
CPU time 2 seconds
Started Jul 15 07:12:00 PM PDT 24
Finished Jul 15 07:12:10 PM PDT 24
Peak memory 213992 kb
Host smart-c5b827a0-ab4b-4599-b11f-cb6eef461f24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316460883 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.1316460883
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3788779597
Short name T143
Test name
Test status
Simulation time 16785502 ps
CPU time 1.13 seconds
Started Jul 15 07:12:01 PM PDT 24
Finished Jul 15 07:12:11 PM PDT 24
Peak memory 205504 kb
Host smart-5e31401f-c000-439a-b66d-2465f75fa5af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788779597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.3788779597
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.4219796616
Short name T1036
Test name
Test status
Simulation time 45590053 ps
CPU time 0.69 seconds
Started Jul 15 07:12:01 PM PDT 24
Finished Jul 15 07:12:10 PM PDT 24
Peak memory 205248 kb
Host smart-e9dad737-edb4-4d92-bb01-bfe5e701a453
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219796616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.4219796616
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1053259827
Short name T1078
Test name
Test status
Simulation time 101055391 ps
CPU time 2.32 seconds
Started Jul 15 07:12:03 PM PDT 24
Finished Jul 15 07:12:13 PM PDT 24
Peak memory 205520 kb
Host smart-6769ebe6-1ec3-496b-bdf5-202e22af14c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053259827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.1053259827
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.53572900
Short name T1074
Test name
Test status
Simulation time 209756529 ps
CPU time 1.45 seconds
Started Jul 15 07:12:03 PM PDT 24
Finished Jul 15 07:12:12 PM PDT 24
Peak memory 214072 kb
Host smart-8ec07b88-deff-4b44-b7be-f8487f39a436
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53572900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow_
reg_errors.53572900
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2327863094
Short name T120
Test name
Test status
Simulation time 1877746942 ps
CPU time 14.58 seconds
Started Jul 15 07:12:00 PM PDT 24
Finished Jul 15 07:12:23 PM PDT 24
Peak memory 220160 kb
Host smart-72885197-d82e-4e6b-83be-cbc026919535
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327863094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.2327863094
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3779359849
Short name T1030
Test name
Test status
Simulation time 206350974 ps
CPU time 2.2 seconds
Started Jul 15 07:12:01 PM PDT 24
Finished Jul 15 07:12:12 PM PDT 24
Peak memory 213724 kb
Host smart-f73f61c1-e89b-47f9-a737-5475069b62cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779359849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.3779359849
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.49767253
Short name T985
Test name
Test status
Simulation time 170738621 ps
CPU time 1.55 seconds
Started Jul 15 07:12:01 PM PDT 24
Finished Jul 15 07:12:11 PM PDT 24
Peak memory 213692 kb
Host smart-a3db0a59-6fa5-4e89-b128-04d57fb5e939
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49767253 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.49767253
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.1287397133
Short name T953
Test name
Test status
Simulation time 10256351 ps
CPU time 0.97 seconds
Started Jul 15 07:12:02 PM PDT 24
Finished Jul 15 07:12:11 PM PDT 24
Peak memory 205452 kb
Host smart-9919ce48-9450-4964-9baf-5110e2c70f23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287397133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.1287397133
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.3902541255
Short name T1005
Test name
Test status
Simulation time 11793261 ps
CPU time 0.82 seconds
Started Jul 15 07:12:00 PM PDT 24
Finished Jul 15 07:12:09 PM PDT 24
Peak memory 205252 kb
Host smart-d3ce7b92-4e60-4f9b-aa72-41107adc6de9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902541255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.3902541255
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.272120472
Short name T968
Test name
Test status
Simulation time 284000875 ps
CPU time 2.97 seconds
Started Jul 15 07:11:58 PM PDT 24
Finished Jul 15 07:12:10 PM PDT 24
Peak memory 205580 kb
Host smart-7d9f34f8-7f71-4a6d-bd0c-0d673820f1c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272120472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sam
e_csr_outstanding.272120472
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1656199802
Short name T1081
Test name
Test status
Simulation time 162709030 ps
CPU time 1.84 seconds
Started Jul 15 07:12:05 PM PDT 24
Finished Jul 15 07:12:13 PM PDT 24
Peak memory 218176 kb
Host smart-b9b3e2c7-3758-4629-b203-323bf4ba6ce4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656199802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.1656199802
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.4156998160
Short name T1054
Test name
Test status
Simulation time 1459364516 ps
CPU time 8.9 seconds
Started Jul 15 07:11:58 PM PDT 24
Finished Jul 15 07:12:15 PM PDT 24
Peak memory 214052 kb
Host smart-9ab1659b-6b95-49fc-bc16-6baaca475553
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156998160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.4156998160
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.2644182697
Short name T992
Test name
Test status
Simulation time 164756604 ps
CPU time 5.49 seconds
Started Jul 15 07:12:00 PM PDT 24
Finished Jul 15 07:12:14 PM PDT 24
Peak memory 213736 kb
Host smart-2a48b22e-ed84-4437-b10c-3e22d4b8c8eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644182697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.2644182697
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.3716784806
Short name T177
Test name
Test status
Simulation time 367989330 ps
CPU time 5.35 seconds
Started Jul 15 07:12:01 PM PDT 24
Finished Jul 15 07:12:15 PM PDT 24
Peak memory 213744 kb
Host smart-8c2e9c38-bf7a-423a-96cb-b7b2c742c89f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716784806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.3716784806
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.3605001050
Short name T966
Test name
Test status
Simulation time 61439023 ps
CPU time 1.29 seconds
Started Jul 15 07:12:01 PM PDT 24
Finished Jul 15 07:12:10 PM PDT 24
Peak memory 213820 kb
Host smart-c70abfe4-068f-43ad-9dd5-17ea9cba7031
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605001050 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.3605001050
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3829592360
Short name T961
Test name
Test status
Simulation time 27657677 ps
CPU time 1.19 seconds
Started Jul 15 07:12:01 PM PDT 24
Finished Jul 15 07:12:10 PM PDT 24
Peak memory 205608 kb
Host smart-87956249-0d4d-42c9-9260-ba9cd41ca460
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829592360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.3829592360
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2348194430
Short name T983
Test name
Test status
Simulation time 30308175 ps
CPU time 0.75 seconds
Started Jul 15 07:12:01 PM PDT 24
Finished Jul 15 07:12:10 PM PDT 24
Peak memory 205324 kb
Host smart-af77b45d-629e-452e-b3ae-9a4012affa8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348194430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.2348194430
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.3531705998
Short name T987
Test name
Test status
Simulation time 257640510 ps
CPU time 2.09 seconds
Started Jul 15 07:12:01 PM PDT 24
Finished Jul 15 07:12:11 PM PDT 24
Peak memory 205516 kb
Host smart-0b80d838-61fa-488b-902d-9d479d837c3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531705998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.3531705998
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2402220544
Short name T979
Test name
Test status
Simulation time 330403505 ps
CPU time 3.31 seconds
Started Jul 15 07:11:58 PM PDT 24
Finished Jul 15 07:12:10 PM PDT 24
Peak memory 214076 kb
Host smart-01100709-cfe9-4dfd-bdf4-bdaec1e8c843
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402220544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.2402220544
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1731098248
Short name T1032
Test name
Test status
Simulation time 1311701747 ps
CPU time 8.05 seconds
Started Jul 15 07:11:59 PM PDT 24
Finished Jul 15 07:12:15 PM PDT 24
Peak memory 219912 kb
Host smart-36a5a7b3-c486-4c91-976a-c4631e70cc39
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731098248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.1731098248
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.2128222010
Short name T1072
Test name
Test status
Simulation time 318536839 ps
CPU time 2.47 seconds
Started Jul 15 07:12:01 PM PDT 24
Finished Jul 15 07:12:12 PM PDT 24
Peak memory 213732 kb
Host smart-8e85764c-82f2-4d48-bbd0-15390e2f3e45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128222010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.2128222010
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1568601991
Short name T182
Test name
Test status
Simulation time 411976601 ps
CPU time 4.59 seconds
Started Jul 15 07:12:02 PM PDT 24
Finished Jul 15 07:12:15 PM PDT 24
Peak memory 205520 kb
Host smart-cf5fa38e-c0c0-41e3-85a7-7c5ef8446f09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568601991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.1568601991
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.4134021531
Short name T525
Test name
Test status
Simulation time 51114063 ps
CPU time 0.79 seconds
Started Jul 15 07:19:09 PM PDT 24
Finished Jul 15 07:20:20 PM PDT 24
Peak memory 206048 kb
Host smart-7a318060-488c-4179-b192-17995d42803c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134021531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.4134021531
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.3930168754
Short name T135
Test name
Test status
Simulation time 36341329 ps
CPU time 2.95 seconds
Started Jul 15 07:19:03 PM PDT 24
Finished Jul 15 07:20:23 PM PDT 24
Peak memory 214684 kb
Host smart-6d7ab73d-0caf-4481-9b74-893611760006
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3930168754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3930168754
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.31186153
Short name T598
Test name
Test status
Simulation time 244485527 ps
CPU time 3.37 seconds
Started Jul 15 07:19:11 PM PDT 24
Finished Jul 15 07:20:23 PM PDT 24
Peak memory 210132 kb
Host smart-682e4a07-91e1-4c9c-b7b0-6fbcec2e04d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31186153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.31186153
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.2371734685
Short name T293
Test name
Test status
Simulation time 693700815 ps
CPU time 7.37 seconds
Started Jul 15 07:19:02 PM PDT 24
Finished Jul 15 07:20:28 PM PDT 24
Peak memory 208840 kb
Host smart-d9c4c1a0-21fa-4800-8752-51cb21efd421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371734685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.2371734685
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.24447627
Short name T592
Test name
Test status
Simulation time 1066906331 ps
CPU time 6.41 seconds
Started Jul 15 07:19:07 PM PDT 24
Finished Jul 15 07:20:25 PM PDT 24
Peak memory 209748 kb
Host smart-845f3ba9-0e55-488f-bef9-346defb7a0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24447627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.24447627
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.1490600777
Short name T370
Test name
Test status
Simulation time 1225229991 ps
CPU time 2.92 seconds
Started Jul 15 07:19:07 PM PDT 24
Finished Jul 15 07:20:21 PM PDT 24
Peak memory 214208 kb
Host smart-714503b9-5b37-497b-a121-f47e4b063b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490600777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.1490600777
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_random.248578571
Short name T791
Test name
Test status
Simulation time 188956695 ps
CPU time 5.04 seconds
Started Jul 15 07:19:01 PM PDT 24
Finished Jul 15 07:20:20 PM PDT 24
Peak memory 209392 kb
Host smart-22db8c8d-eed5-4428-901f-141ae522ef1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248578571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.248578571
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.4073954973
Short name T11
Test name
Test status
Simulation time 735154990 ps
CPU time 15.47 seconds
Started Jul 15 07:19:07 PM PDT 24
Finished Jul 15 07:20:39 PM PDT 24
Peak memory 237380 kb
Host smart-78897c91-8555-4508-8ab0-5b33b3dfaf47
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073954973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.4073954973
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.2473098558
Short name T746
Test name
Test status
Simulation time 104355040 ps
CPU time 2.8 seconds
Started Jul 15 07:19:02 PM PDT 24
Finished Jul 15 07:20:18 PM PDT 24
Peak memory 207112 kb
Host smart-ceeca0ad-6f6e-4335-b112-d58fb5657975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473098558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.2473098558
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.1516431108
Short name T354
Test name
Test status
Simulation time 211753345 ps
CPU time 5.59 seconds
Started Jul 15 07:19:07 PM PDT 24
Finished Jul 15 07:20:24 PM PDT 24
Peak memory 208860 kb
Host smart-a98b23a0-2a7d-49f2-b85e-81029cc42f59
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516431108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.1516431108
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.2827707492
Short name T579
Test name
Test status
Simulation time 264544103 ps
CPU time 3.46 seconds
Started Jul 15 07:19:02 PM PDT 24
Finished Jul 15 07:20:24 PM PDT 24
Peak memory 208748 kb
Host smart-ce29fed1-218a-48c3-9282-99c822ba0fdc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827707492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.2827707492
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.3340634741
Short name T847
Test name
Test status
Simulation time 93858909 ps
CPU time 1.83 seconds
Started Jul 15 07:19:07 PM PDT 24
Finished Jul 15 07:20:20 PM PDT 24
Peak memory 206848 kb
Host smart-72aeea5a-92a9-423d-817e-2938a77ef674
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340634741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.3340634741
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.618420559
Short name T496
Test name
Test status
Simulation time 431741065 ps
CPU time 1.78 seconds
Started Jul 15 07:19:07 PM PDT 24
Finished Jul 15 07:20:25 PM PDT 24
Peak memory 206760 kb
Host smart-39d6070a-a10b-47a5-812b-4cfcb7602676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618420559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.618420559
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.1034487302
Short name T900
Test name
Test status
Simulation time 190404343 ps
CPU time 4.96 seconds
Started Jul 15 07:19:02 PM PDT 24
Finished Jul 15 07:20:25 PM PDT 24
Peak memory 207820 kb
Host smart-55842b8a-49fc-4986-9123-769e71638f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034487302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.1034487302
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.941207898
Short name T267
Test name
Test status
Simulation time 425808534 ps
CPU time 4.69 seconds
Started Jul 15 07:19:03 PM PDT 24
Finished Jul 15 07:20:25 PM PDT 24
Peak memory 209412 kb
Host smart-11501bf4-07c1-45ca-a66d-41a18607673a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941207898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.941207898
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.1459613041
Short name T180
Test name
Test status
Simulation time 116701520 ps
CPU time 1.82 seconds
Started Jul 15 07:19:07 PM PDT 24
Finished Jul 15 07:20:25 PM PDT 24
Peak memory 209964 kb
Host smart-22c18ec5-cf76-4523-baa2-48b26c0f29f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459613041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.1459613041
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.2183069374
Short name T43
Test name
Test status
Simulation time 1099797102 ps
CPU time 3.18 seconds
Started Jul 15 07:19:09 PM PDT 24
Finished Jul 15 07:20:22 PM PDT 24
Peak memory 208244 kb
Host smart-7364df1b-e5ff-4b35-ab4f-f031746b4d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183069374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.2183069374
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.125539805
Short name T322
Test name
Test status
Simulation time 127726482 ps
CPU time 5.13 seconds
Started Jul 15 07:19:06 PM PDT 24
Finished Jul 15 07:20:28 PM PDT 24
Peak memory 214308 kb
Host smart-894a6623-1317-4a23-8f97-bc8a1b678ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125539805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.125539805
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.396575537
Short name T247
Test name
Test status
Simulation time 82747175 ps
CPU time 3.7 seconds
Started Jul 15 07:19:12 PM PDT 24
Finished Jul 15 07:20:24 PM PDT 24
Peak memory 214204 kb
Host smart-5a294784-964d-46b7-be0b-c5df4757cafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396575537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.396575537
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.923004800
Short name T817
Test name
Test status
Simulation time 152166282 ps
CPU time 7.03 seconds
Started Jul 15 07:19:11 PM PDT 24
Finished Jul 15 07:20:27 PM PDT 24
Peak memory 222456 kb
Host smart-162973e3-5da5-4b2d-82da-935230d033ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923004800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.923004800
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.1431500244
Short name T612
Test name
Test status
Simulation time 194322008 ps
CPU time 4.79 seconds
Started Jul 15 07:19:12 PM PDT 24
Finished Jul 15 07:20:25 PM PDT 24
Peak memory 209888 kb
Host smart-c7f9fe7f-a10e-464f-9528-b1867f6783f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431500244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1431500244
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.2988057191
Short name T105
Test name
Test status
Simulation time 3453439522 ps
CPU time 5.84 seconds
Started Jul 15 07:19:13 PM PDT 24
Finished Jul 15 07:20:26 PM PDT 24
Peak memory 237372 kb
Host smart-63829d5f-1f12-488b-98d8-e090533fb368
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988057191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.2988057191
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.814735476
Short name T542
Test name
Test status
Simulation time 198753345 ps
CPU time 2.62 seconds
Started Jul 15 07:19:06 PM PDT 24
Finished Jul 15 07:20:26 PM PDT 24
Peak memory 206860 kb
Host smart-c1a798ed-1c93-4449-a12b-d464e8776717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814735476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.814735476
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.173039642
Short name T929
Test name
Test status
Simulation time 180318064 ps
CPU time 2.88 seconds
Started Jul 15 07:19:14 PM PDT 24
Finished Jul 15 07:20:23 PM PDT 24
Peak memory 208556 kb
Host smart-d182c777-1249-46f4-95a8-2487b61327b9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173039642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.173039642
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.3927604434
Short name T595
Test name
Test status
Simulation time 363954094 ps
CPU time 5.28 seconds
Started Jul 15 07:19:07 PM PDT 24
Finished Jul 15 07:20:29 PM PDT 24
Peak memory 207812 kb
Host smart-5f97bb48-ae8e-474b-83f2-6e0fe084ed04
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927604434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.3927604434
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.1578716922
Short name T857
Test name
Test status
Simulation time 400759991 ps
CPU time 11.67 seconds
Started Jul 15 07:19:11 PM PDT 24
Finished Jul 15 07:20:32 PM PDT 24
Peak memory 208068 kb
Host smart-8c62e9f7-a7de-465b-bb82-ebfd9df2359b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578716922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.1578716922
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2041859585
Short name T624
Test name
Test status
Simulation time 175519070 ps
CPU time 4.72 seconds
Started Jul 15 07:19:14 PM PDT 24
Finished Jul 15 07:20:25 PM PDT 24
Peak memory 208636 kb
Host smart-43a2607e-db21-4e68-99d7-a60dad956494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041859585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2041859585
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.3109178464
Short name T232
Test name
Test status
Simulation time 472122297 ps
CPU time 18.35 seconds
Started Jul 15 07:19:15 PM PDT 24
Finished Jul 15 07:20:39 PM PDT 24
Peak memory 220764 kb
Host smart-3b2c2974-1180-41b3-9cfd-c6760d3d927d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109178464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3109178464
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.329383000
Short name T270
Test name
Test status
Simulation time 843796210 ps
CPU time 6.68 seconds
Started Jul 15 07:19:09 PM PDT 24
Finished Jul 15 07:20:25 PM PDT 24
Peak memory 209412 kb
Host smart-95953af7-45f6-4918-9ee6-014acbaecbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329383000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.329383000
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.3791802422
Short name T602
Test name
Test status
Simulation time 49979925 ps
CPU time 1.72 seconds
Started Jul 15 07:19:09 PM PDT 24
Finished Jul 15 07:20:25 PM PDT 24
Peak memory 209860 kb
Host smart-c0b244e4-d1f6-46b2-9730-28dd211c876c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791802422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.3791802422
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.3105741301
Short name T473
Test name
Test status
Simulation time 36558769 ps
CPU time 0.72 seconds
Started Jul 15 07:20:09 PM PDT 24
Finished Jul 15 07:20:47 PM PDT 24
Peak memory 206016 kb
Host smart-4a230d74-540c-455c-a138-8e421cc9a817
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105741301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.3105741301
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.1403669019
Short name T427
Test name
Test status
Simulation time 60612790 ps
CPU time 3.47 seconds
Started Jul 15 07:20:06 PM PDT 24
Finished Jul 15 07:20:47 PM PDT 24
Peak memory 214316 kb
Host smart-6c46a3c7-13c3-42bb-a9b6-3a32130929d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1403669019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.1403669019
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.112219989
Short name T607
Test name
Test status
Simulation time 43019484 ps
CPU time 2.71 seconds
Started Jul 15 07:20:10 PM PDT 24
Finished Jul 15 07:20:49 PM PDT 24
Peak memory 210380 kb
Host smart-f606f97e-0e1c-4f17-a7e0-fa7ec92589a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112219989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.112219989
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.2326525838
Short name T639
Test name
Test status
Simulation time 142379105 ps
CPU time 1.99 seconds
Started Jul 15 07:20:07 PM PDT 24
Finished Jul 15 07:20:46 PM PDT 24
Peak memory 214320 kb
Host smart-80572a9f-d8fd-40f1-85ca-557c5c1be09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326525838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.2326525838
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.3671041164
Short name T820
Test name
Test status
Simulation time 835206766 ps
CPU time 7.69 seconds
Started Jul 15 07:20:08 PM PDT 24
Finished Jul 15 07:20:54 PM PDT 24
Peak memory 222456 kb
Host smart-b9a9c869-0a85-4840-a8da-db9e37d1e9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671041164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.3671041164
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.1915445718
Short name T659
Test name
Test status
Simulation time 5161275405 ps
CPU time 22.64 seconds
Started Jul 15 07:20:12 PM PDT 24
Finished Jul 15 07:21:12 PM PDT 24
Peak memory 208476 kb
Host smart-f0d1eb94-7f61-431d-9d36-9b28731791e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915445718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.1915445718
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.2226734696
Short name T201
Test name
Test status
Simulation time 380272243 ps
CPU time 3.66 seconds
Started Jul 15 07:20:07 PM PDT 24
Finished Jul 15 07:20:47 PM PDT 24
Peak memory 208588 kb
Host smart-faaaa009-0bb0-4e6d-9106-fc1e54c6b0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226734696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.2226734696
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.2273479381
Short name T671
Test name
Test status
Simulation time 77963450 ps
CPU time 2.82 seconds
Started Jul 15 07:20:11 PM PDT 24
Finished Jul 15 07:20:52 PM PDT 24
Peak memory 207340 kb
Host smart-432a0b31-1709-4633-ba03-b15c602ceb76
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273479381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.2273479381
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.1822574080
Short name T1
Test name
Test status
Simulation time 1335363491 ps
CPU time 5.17 seconds
Started Jul 15 07:20:07 PM PDT 24
Finished Jul 15 07:20:49 PM PDT 24
Peak memory 208964 kb
Host smart-8ee4fada-dba1-44a7-b97e-257356c6fb9b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822574080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.1822574080
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.4107791172
Short name T706
Test name
Test status
Simulation time 143698896 ps
CPU time 4.68 seconds
Started Jul 15 07:20:10 PM PDT 24
Finished Jul 15 07:20:51 PM PDT 24
Peak memory 208008 kb
Host smart-b6de7d87-91af-464d-821e-7efeaec61fa5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107791172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.4107791172
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.1997915819
Short name T484
Test name
Test status
Simulation time 372610570 ps
CPU time 5.96 seconds
Started Jul 15 07:20:12 PM PDT 24
Finished Jul 15 07:20:55 PM PDT 24
Peak memory 208144 kb
Host smart-fd452f35-a5f9-420d-891e-1ce32a70af95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997915819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.1997915819
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.863067414
Short name T873
Test name
Test status
Simulation time 55491491 ps
CPU time 2.63 seconds
Started Jul 15 07:20:05 PM PDT 24
Finished Jul 15 07:20:46 PM PDT 24
Peak memory 206932 kb
Host smart-9fd5bd19-ab2a-4cec-b4ea-0c8abceb2778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863067414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.863067414
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.4025742421
Short name T184
Test name
Test status
Simulation time 581871434 ps
CPU time 21.21 seconds
Started Jul 15 07:20:10 PM PDT 24
Finished Jul 15 07:21:08 PM PDT 24
Peak memory 222804 kb
Host smart-f708e3bb-cc37-46a8-b5ec-9b16cb1db225
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025742421 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.4025742421
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.1952373083
Short name T608
Test name
Test status
Simulation time 1852186015 ps
CPU time 5.46 seconds
Started Jul 15 07:20:06 PM PDT 24
Finished Jul 15 07:20:49 PM PDT 24
Peak memory 209500 kb
Host smart-c20c50e0-dcd6-451c-b3e7-6e3a34058ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952373083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.1952373083
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.99181925
Short name T827
Test name
Test status
Simulation time 909228591 ps
CPU time 6.23 seconds
Started Jul 15 07:20:06 PM PDT 24
Finished Jul 15 07:20:50 PM PDT 24
Peak memory 210372 kb
Host smart-2cf3a9df-cc73-4f9b-85eb-203290b007f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99181925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.99181925
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.4158001165
Short name T617
Test name
Test status
Simulation time 49061334 ps
CPU time 0.75 seconds
Started Jul 15 07:20:15 PM PDT 24
Finished Jul 15 07:20:53 PM PDT 24
Peak memory 206000 kb
Host smart-1a04759d-ad8d-43ef-9b64-3f84e58b6a85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158001165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.4158001165
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.1480925981
Short name T35
Test name
Test status
Simulation time 63554069 ps
CPU time 2.35 seconds
Started Jul 15 07:20:20 PM PDT 24
Finished Jul 15 07:20:59 PM PDT 24
Peak memory 217024 kb
Host smart-74561b37-46e7-4872-a9b9-dde163e1e5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480925981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.1480925981
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.3708316030
Short name T755
Test name
Test status
Simulation time 188521492 ps
CPU time 2.21 seconds
Started Jul 15 07:20:07 PM PDT 24
Finished Jul 15 07:20:46 PM PDT 24
Peak memory 214372 kb
Host smart-ae64902f-eefc-4f34-955e-ab16ee508181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708316030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3708316030
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.3309821488
Short name T513
Test name
Test status
Simulation time 8160849239 ps
CPU time 68.48 seconds
Started Jul 15 07:20:14 PM PDT 24
Finished Jul 15 07:22:01 PM PDT 24
Peak memory 214408 kb
Host smart-b4aa31dc-eea8-40c8-80a2-41f8be4ad4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309821488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.3309821488
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.305624823
Short name T625
Test name
Test status
Simulation time 581619184 ps
CPU time 3.11 seconds
Started Jul 15 07:20:10 PM PDT 24
Finished Jul 15 07:20:50 PM PDT 24
Peak memory 222520 kb
Host smart-00272781-0b3f-4003-b0d9-b2172cf8432f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305624823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.305624823
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.3899490303
Short name T578
Test name
Test status
Simulation time 86705207 ps
CPU time 4.13 seconds
Started Jul 15 07:20:07 PM PDT 24
Finished Jul 15 07:20:48 PM PDT 24
Peak memory 207400 kb
Host smart-decd5ac6-45b1-4d57-9d13-44d84d1c2d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899490303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3899490303
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.857872562
Short name T771
Test name
Test status
Simulation time 34965081 ps
CPU time 2.55 seconds
Started Jul 15 07:20:04 PM PDT 24
Finished Jul 15 07:20:44 PM PDT 24
Peak memory 207376 kb
Host smart-f35eafea-0f16-4a49-b760-c8d7d453f010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857872562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.857872562
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.3187484388
Short name T356
Test name
Test status
Simulation time 22313095 ps
CPU time 1.78 seconds
Started Jul 15 07:20:06 PM PDT 24
Finished Jul 15 07:20:45 PM PDT 24
Peak memory 207056 kb
Host smart-c6e7e887-9f32-450a-9ed1-4cde4ee3cefd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187484388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3187484388
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.1626948248
Short name T667
Test name
Test status
Simulation time 4578285845 ps
CPU time 6.69 seconds
Started Jul 15 07:20:08 PM PDT 24
Finished Jul 15 07:20:53 PM PDT 24
Peak memory 208100 kb
Host smart-8c740330-532d-450b-a0ed-fb043a305e61
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626948248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.1626948248
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.368925897
Short name T208
Test name
Test status
Simulation time 189242335 ps
CPU time 5.49 seconds
Started Jul 15 07:20:09 PM PDT 24
Finished Jul 15 07:20:52 PM PDT 24
Peak memory 208652 kb
Host smart-f65d6aca-ee8c-4c24-9e37-784571432575
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368925897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.368925897
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.478263496
Short name T802
Test name
Test status
Simulation time 104167438 ps
CPU time 4.39 seconds
Started Jul 15 07:20:14 PM PDT 24
Finished Jul 15 07:20:57 PM PDT 24
Peak memory 222488 kb
Host smart-0e5c62c8-648c-4056-b45f-bf89690b5ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478263496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.478263496
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.2370233679
Short name T867
Test name
Test status
Simulation time 1978765141 ps
CPU time 5.95 seconds
Started Jul 15 07:20:06 PM PDT 24
Finished Jul 15 07:20:50 PM PDT 24
Peak memory 208456 kb
Host smart-dbd7d2b1-4a84-4ff4-ba86-00bf2559333f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370233679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.2370233679
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.3020779778
Short name T312
Test name
Test status
Simulation time 779712455 ps
CPU time 16.61 seconds
Started Jul 15 07:20:15 PM PDT 24
Finished Jul 15 07:21:09 PM PDT 24
Peak memory 220604 kb
Host smart-d81fb39d-bc00-4e8d-953c-3172345d01e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020779778 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.3020779778
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.3193208534
Short name T519
Test name
Test status
Simulation time 266058643 ps
CPU time 3.97 seconds
Started Jul 15 07:20:15 PM PDT 24
Finished Jul 15 07:20:56 PM PDT 24
Peak memory 209128 kb
Host smart-27191ab5-7678-491f-b8e5-b45fb075da2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193208534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.3193208534
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.2317664161
Short name T127
Test name
Test status
Simulation time 68712161 ps
CPU time 2.53 seconds
Started Jul 15 07:20:12 PM PDT 24
Finished Jul 15 07:20:52 PM PDT 24
Peak memory 210180 kb
Host smart-ae342b74-e7d7-4ac7-91b6-08332114b40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317664161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.2317664161
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.551196040
Short name T916
Test name
Test status
Simulation time 41001880 ps
CPU time 0.81 seconds
Started Jul 15 07:20:26 PM PDT 24
Finished Jul 15 07:21:05 PM PDT 24
Peak memory 205896 kb
Host smart-98d05aeb-fefc-45cd-827f-702ccfa125a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551196040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.551196040
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.1861005117
Short name T18
Test name
Test status
Simulation time 186476567 ps
CPU time 2.58 seconds
Started Jul 15 07:20:26 PM PDT 24
Finished Jul 15 07:21:07 PM PDT 24
Peak memory 209912 kb
Host smart-9bbdc54c-3608-448c-987a-6633343ab97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861005117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.1861005117
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.3501062545
Short name T520
Test name
Test status
Simulation time 592236532 ps
CPU time 3.06 seconds
Started Jul 15 07:20:21 PM PDT 24
Finished Jul 15 07:21:00 PM PDT 24
Peak memory 208160 kb
Host smart-0d0844d4-6822-4dc3-99b6-5d65abfd00c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501062545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.3501062545
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.854957246
Short name T670
Test name
Test status
Simulation time 82523938 ps
CPU time 1.89 seconds
Started Jul 15 07:20:26 PM PDT 24
Finished Jul 15 07:21:06 PM PDT 24
Peak memory 214272 kb
Host smart-5577522d-d79f-4d44-b427-ba138a332e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854957246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.854957246
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.1689745671
Short name T240
Test name
Test status
Simulation time 167324934 ps
CPU time 4.01 seconds
Started Jul 15 07:20:22 PM PDT 24
Finished Jul 15 07:21:04 PM PDT 24
Peak memory 209752 kb
Host smart-0dd4a2d7-c14a-41f6-8261-59aa410072db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689745671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1689745671
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.997697268
Short name T769
Test name
Test status
Simulation time 2268371043 ps
CPU time 29.03 seconds
Started Jul 15 07:20:19 PM PDT 24
Finished Jul 15 07:21:25 PM PDT 24
Peak memory 214384 kb
Host smart-8850734a-1807-4add-887e-6011ca655eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997697268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.997697268
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.1468830523
Short name T777
Test name
Test status
Simulation time 5327489212 ps
CPU time 33.99 seconds
Started Jul 15 07:20:12 PM PDT 24
Finished Jul 15 07:21:23 PM PDT 24
Peak memory 208916 kb
Host smart-07382859-526e-4437-a7c1-91623b546433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468830523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.1468830523
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.3637640204
Short name T40
Test name
Test status
Simulation time 4055774726 ps
CPU time 41.33 seconds
Started Jul 15 07:20:20 PM PDT 24
Finished Jul 15 07:21:38 PM PDT 24
Peak memory 208472 kb
Host smart-5652a24b-8a92-4d9a-9df0-e7137227b677
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637640204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.3637640204
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.2560465078
Short name T83
Test name
Test status
Simulation time 291061014 ps
CPU time 3.57 seconds
Started Jul 15 07:20:13 PM PDT 24
Finished Jul 15 07:20:53 PM PDT 24
Peak memory 208568 kb
Host smart-174fab9d-1b4f-4b37-bcf9-90347227fd81
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560465078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.2560465078
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.1306255266
Short name T677
Test name
Test status
Simulation time 182407759 ps
CPU time 2.71 seconds
Started Jul 15 07:20:14 PM PDT 24
Finished Jul 15 07:20:55 PM PDT 24
Peak memory 206988 kb
Host smart-958f148e-78c7-4412-b185-d6b7e4ec5bb8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306255266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.1306255266
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.576402506
Short name T443
Test name
Test status
Simulation time 32424812 ps
CPU time 1.7 seconds
Started Jul 15 07:20:28 PM PDT 24
Finished Jul 15 07:21:07 PM PDT 24
Peak memory 209120 kb
Host smart-e7f2315c-6803-48a5-b8cf-b32cec67894e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576402506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.576402506
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.4056031472
Short name T567
Test name
Test status
Simulation time 142155696 ps
CPU time 4.38 seconds
Started Jul 15 07:20:20 PM PDT 24
Finished Jul 15 07:21:01 PM PDT 24
Peak memory 208368 kb
Host smart-46d22e18-9e35-4910-8e43-d5a86536109c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056031472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.4056031472
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.171681572
Short name T605
Test name
Test status
Simulation time 189067382 ps
CPU time 3.08 seconds
Started Jul 15 07:20:21 PM PDT 24
Finished Jul 15 07:21:00 PM PDT 24
Peak memory 207440 kb
Host smart-a27f6270-b25c-4eb4-99de-fefb0f59bd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171681572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.171681572
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.3095011962
Short name T500
Test name
Test status
Simulation time 78095986 ps
CPU time 1.63 seconds
Started Jul 15 07:20:25 PM PDT 24
Finished Jul 15 07:21:03 PM PDT 24
Peak memory 209860 kb
Host smart-c392ed26-bc81-4332-abbe-ae48e09ead77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095011962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.3095011962
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.355954174
Short name T505
Test name
Test status
Simulation time 44502793 ps
CPU time 0.84 seconds
Started Jul 15 07:20:42 PM PDT 24
Finished Jul 15 07:21:21 PM PDT 24
Peak memory 205976 kb
Host smart-a31a4325-58d5-421d-bcb7-a3a277572852
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355954174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.355954174
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.3897419891
Short name T336
Test name
Test status
Simulation time 275764120 ps
CPU time 4.57 seconds
Started Jul 15 07:20:35 PM PDT 24
Finished Jul 15 07:21:16 PM PDT 24
Peak memory 222468 kb
Host smart-98a7f658-7e05-480c-942a-a41d9108cbe7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3897419891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.3897419891
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.4095676306
Short name T699
Test name
Test status
Simulation time 87022297 ps
CPU time 3.93 seconds
Started Jul 15 07:20:41 PM PDT 24
Finished Jul 15 07:21:21 PM PDT 24
Peak memory 209068 kb
Host smart-6cfb18dc-c35e-448d-b8ba-5a20c8d246cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095676306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.4095676306
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3044111914
Short name T721
Test name
Test status
Simulation time 806460208 ps
CPU time 2.47 seconds
Started Jul 15 07:20:39 PM PDT 24
Finished Jul 15 07:21:19 PM PDT 24
Peak memory 207192 kb
Host smart-d9ed4f2a-48fd-4b61-b493-45b9b8ede38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044111914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3044111914
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.3498245402
Short name T836
Test name
Test status
Simulation time 55109745 ps
CPU time 2.83 seconds
Started Jul 15 07:20:40 PM PDT 24
Finished Jul 15 07:21:20 PM PDT 24
Peak memory 214336 kb
Host smart-6812bbe1-fed9-40da-a621-7997f0b34595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498245402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3498245402
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_random.1492417184
Short name T412
Test name
Test status
Simulation time 404877305 ps
CPU time 4.91 seconds
Started Jul 15 07:20:40 PM PDT 24
Finished Jul 15 07:21:22 PM PDT 24
Peak memory 209324 kb
Host smart-abe3afb2-80e1-4de1-af0f-e4152447001b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492417184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.1492417184
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.3839040769
Short name T925
Test name
Test status
Simulation time 153089810 ps
CPU time 6.25 seconds
Started Jul 15 07:20:28 PM PDT 24
Finished Jul 15 07:21:12 PM PDT 24
Peak memory 208512 kb
Host smart-9dfd492e-968f-41e4-b252-303688a29a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839040769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3839040769
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.3434958184
Short name T860
Test name
Test status
Simulation time 74325425 ps
CPU time 3.15 seconds
Started Jul 15 07:20:27 PM PDT 24
Finished Jul 15 07:21:08 PM PDT 24
Peak memory 208436 kb
Host smart-d83bb71c-911e-41b8-8dbf-669fa2a50bae
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434958184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3434958184
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.2620349974
Short name T792
Test name
Test status
Simulation time 4469726816 ps
CPU time 67.36 seconds
Started Jul 15 07:20:27 PM PDT 24
Finished Jul 15 07:22:13 PM PDT 24
Peak memory 208828 kb
Host smart-0c4570ea-8842-403c-a79d-1f3cb6a70c12
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620349974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.2620349974
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.4193028368
Short name T774
Test name
Test status
Simulation time 425191455 ps
CPU time 4.09 seconds
Started Jul 15 07:20:32 PM PDT 24
Finished Jul 15 07:21:13 PM PDT 24
Peak memory 207836 kb
Host smart-6a5c67d9-e74f-496b-805f-6b813720cf40
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193028368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.4193028368
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.3407388856
Short name T426
Test name
Test status
Simulation time 64145076 ps
CPU time 1.94 seconds
Started Jul 15 07:20:39 PM PDT 24
Finished Jul 15 07:21:16 PM PDT 24
Peak memory 215932 kb
Host smart-ae0fdc0e-d040-4352-be21-423536a30eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407388856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.3407388856
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.85572442
Short name T848
Test name
Test status
Simulation time 924559524 ps
CPU time 15.6 seconds
Started Jul 15 07:20:28 PM PDT 24
Finished Jul 15 07:21:21 PM PDT 24
Peak memory 207908 kb
Host smart-b2c67dca-5c3c-442c-a674-4566ae7e7846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85572442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.85572442
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.2345453229
Short name T917
Test name
Test status
Simulation time 2573497871 ps
CPU time 45.57 seconds
Started Jul 15 07:20:40 PM PDT 24
Finished Jul 15 07:22:03 PM PDT 24
Peak memory 216344 kb
Host smart-46aac290-46d0-4dab-822d-4364695a0315
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345453229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.2345453229
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.369811976
Short name T908
Test name
Test status
Simulation time 1033728584 ps
CPU time 16.81 seconds
Started Jul 15 07:20:41 PM PDT 24
Finished Jul 15 07:21:34 PM PDT 24
Peak memory 208820 kb
Host smart-1eb8cd93-45f0-463c-a69a-2cbf6265252a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369811976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.369811976
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.550241463
Short name T501
Test name
Test status
Simulation time 28418416 ps
CPU time 0.73 seconds
Started Jul 15 07:20:40 PM PDT 24
Finished Jul 15 07:21:18 PM PDT 24
Peak memory 205932 kb
Host smart-e340d661-24b2-4967-ae95-a4f65611ba91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550241463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.550241463
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.808272457
Short name T417
Test name
Test status
Simulation time 252732838 ps
CPU time 6.98 seconds
Started Jul 15 07:20:41 PM PDT 24
Finished Jul 15 07:21:24 PM PDT 24
Peak memory 214384 kb
Host smart-4480e77c-e0b1-4866-9e4a-3a82edfd53e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=808272457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.808272457
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.1613600464
Short name T921
Test name
Test status
Simulation time 270317136 ps
CPU time 2.95 seconds
Started Jul 15 07:20:39 PM PDT 24
Finished Jul 15 07:21:17 PM PDT 24
Peak memory 220756 kb
Host smart-1b08dd2d-7b87-4cec-9945-ce4f7439c388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613600464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.1613600464
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.3410839596
Short name T616
Test name
Test status
Simulation time 52395100 ps
CPU time 1.67 seconds
Started Jul 15 07:20:38 PM PDT 24
Finished Jul 15 07:21:16 PM PDT 24
Peak memory 208640 kb
Host smart-86fc6b57-93bb-409d-8249-4d15877a8833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410839596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.3410839596
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.4191568837
Short name T249
Test name
Test status
Simulation time 310142490 ps
CPU time 1.79 seconds
Started Jul 15 07:20:44 PM PDT 24
Finished Jul 15 07:21:26 PM PDT 24
Peak memory 214364 kb
Host smart-20f92051-1849-43df-9502-085054ef9219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191568837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.4191568837
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.4218625236
Short name T728
Test name
Test status
Simulation time 354672268 ps
CPU time 4.38 seconds
Started Jul 15 07:20:38 PM PDT 24
Finished Jul 15 07:21:19 PM PDT 24
Peak memory 220748 kb
Host smart-e2bd1927-6429-4590-b169-c24dccba0cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218625236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.4218625236
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.4218650973
Short name T521
Test name
Test status
Simulation time 184772578 ps
CPU time 4.14 seconds
Started Jul 15 07:20:39 PM PDT 24
Finished Jul 15 07:21:21 PM PDT 24
Peak memory 209804 kb
Host smart-56083d18-c370-48a5-8d4f-a68a2804fbb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218650973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.4218650973
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.3564582362
Short name T808
Test name
Test status
Simulation time 35040243 ps
CPU time 2.47 seconds
Started Jul 15 07:20:39 PM PDT 24
Finished Jul 15 07:21:17 PM PDT 24
Peak memory 207660 kb
Host smart-066cfa71-88ab-4d70-bd52-ba0d23606cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564582362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3564582362
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.124990783
Short name T815
Test name
Test status
Simulation time 165229172 ps
CPU time 1.71 seconds
Started Jul 15 07:20:43 PM PDT 24
Finished Jul 15 07:21:22 PM PDT 24
Peak memory 206892 kb
Host smart-6b18276b-eba5-44be-a7b9-54c282ede0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124990783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.124990783
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.1914712044
Short name T881
Test name
Test status
Simulation time 67460593 ps
CPU time 3.02 seconds
Started Jul 15 07:20:43 PM PDT 24
Finished Jul 15 07:21:23 PM PDT 24
Peak memory 208480 kb
Host smart-779bee53-4ade-41c1-a761-a99587b3df34
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914712044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.1914712044
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.1634120810
Short name T82
Test name
Test status
Simulation time 546652878 ps
CPU time 4.25 seconds
Started Jul 15 07:20:42 PM PDT 24
Finished Jul 15 07:21:24 PM PDT 24
Peak memory 206924 kb
Host smart-24c1f4ce-5db1-42df-a6cd-2ebe4abd3ae0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634120810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.1634120810
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.1962161004
Short name T474
Test name
Test status
Simulation time 1191475886 ps
CPU time 3.46 seconds
Started Jul 15 07:20:41 PM PDT 24
Finished Jul 15 07:21:21 PM PDT 24
Peak memory 209072 kb
Host smart-3ab4e056-f0d7-48d7-8b44-207adb3dec28
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962161004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.1962161004
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_smoke.2520246963
Short name T865
Test name
Test status
Simulation time 186644754 ps
CPU time 3.93 seconds
Started Jul 15 07:20:39 PM PDT 24
Finished Jul 15 07:21:18 PM PDT 24
Peak memory 208280 kb
Host smart-641cb281-7eb0-41c2-9cad-c7135f7cd897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520246963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2520246963
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.264894827
Short name T317
Test name
Test status
Simulation time 249171946 ps
CPU time 6.97 seconds
Started Jul 15 07:20:41 PM PDT 24
Finished Jul 15 07:21:25 PM PDT 24
Peak memory 208672 kb
Host smart-a66aaeaf-a8d9-4333-a64c-ea27dc46a1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264894827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.264894827
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.1168767236
Short name T640
Test name
Test status
Simulation time 101103642 ps
CPU time 3.27 seconds
Started Jul 15 07:20:39 PM PDT 24
Finished Jul 15 07:21:20 PM PDT 24
Peak memory 210784 kb
Host smart-d4c50403-f4be-47b3-9178-68b456a4801d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168767236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1168767236
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.1173163210
Short name T888
Test name
Test status
Simulation time 33485711 ps
CPU time 0.82 seconds
Started Jul 15 07:20:43 PM PDT 24
Finished Jul 15 07:21:21 PM PDT 24
Peak memory 206016 kb
Host smart-b6e59676-7334-4914-8458-548f6dcb7611
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173163210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.1173163210
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.174788227
Short name T320
Test name
Test status
Simulation time 102314705 ps
CPU time 5.63 seconds
Started Jul 15 07:20:40 PM PDT 24
Finished Jul 15 07:21:23 PM PDT 24
Peak memory 215160 kb
Host smart-03fb091b-01ca-4ddc-ac58-686aaef4f256
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=174788227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.174788227
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.83683159
Short name T25
Test name
Test status
Simulation time 169042472 ps
CPU time 3.92 seconds
Started Jul 15 07:20:45 PM PDT 24
Finished Jul 15 07:21:29 PM PDT 24
Peak memory 209928 kb
Host smart-862f3468-824c-4b88-aeab-0aba1d9fbe2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83683159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.83683159
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.2813696871
Short name T272
Test name
Test status
Simulation time 204890227 ps
CPU time 4.56 seconds
Started Jul 15 07:20:44 PM PDT 24
Finished Jul 15 07:21:29 PM PDT 24
Peak memory 214344 kb
Host smart-4697ca23-5b99-46db-8c6d-7e0ba55b548a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813696871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.2813696871
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.3249832395
Short name T575
Test name
Test status
Simulation time 223532136 ps
CPU time 4.06 seconds
Started Jul 15 07:20:45 PM PDT 24
Finished Jul 15 07:21:28 PM PDT 24
Peak memory 222472 kb
Host smart-b0e9ccca-1181-430f-8038-4a6cbdf1e5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249832395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.3249832395
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.695953268
Short name T668
Test name
Test status
Simulation time 175731676 ps
CPU time 6.89 seconds
Started Jul 15 07:20:44 PM PDT 24
Finished Jul 15 07:21:30 PM PDT 24
Peak memory 219864 kb
Host smart-db31fe18-dec9-4893-86a9-336f725ea6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695953268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.695953268
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.3718526024
Short name T722
Test name
Test status
Simulation time 864232820 ps
CPU time 28.99 seconds
Started Jul 15 07:20:43 PM PDT 24
Finished Jul 15 07:21:49 PM PDT 24
Peak memory 208752 kb
Host smart-8b695bb0-eae3-4c21-8bdf-537d24876ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718526024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.3718526024
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.730070347
Short name T727
Test name
Test status
Simulation time 149427763 ps
CPU time 5.81 seconds
Started Jul 15 07:20:42 PM PDT 24
Finished Jul 15 07:21:25 PM PDT 24
Peak memory 209308 kb
Host smart-f16aa992-514d-4ea9-8fb6-977ea996c25a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730070347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.730070347
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.770840262
Short name T409
Test name
Test status
Simulation time 180479134 ps
CPU time 2.84 seconds
Started Jul 15 07:20:41 PM PDT 24
Finished Jul 15 07:21:20 PM PDT 24
Peak memory 206896 kb
Host smart-fa86d5cf-fe87-44e1-ba5b-90227aaebf12
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770840262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.770840262
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.4224300070
Short name T333
Test name
Test status
Simulation time 96302144 ps
CPU time 4.07 seconds
Started Jul 15 07:20:43 PM PDT 24
Finished Jul 15 07:21:24 PM PDT 24
Peak memory 208576 kb
Host smart-37bb3f53-5367-4865-ac3d-a3921f16e158
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224300070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.4224300070
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.1170788297
Short name T754
Test name
Test status
Simulation time 342189986 ps
CPU time 4.31 seconds
Started Jul 15 07:20:48 PM PDT 24
Finished Jul 15 07:21:32 PM PDT 24
Peak memory 214492 kb
Host smart-070eaff1-fa12-4f12-96ff-a3140dd8c692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170788297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.1170788297
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.2559942501
Short name T475
Test name
Test status
Simulation time 406330004 ps
CPU time 7.18 seconds
Started Jul 15 07:20:41 PM PDT 24
Finished Jul 15 07:21:25 PM PDT 24
Peak memory 208240 kb
Host smart-d28ccc5f-d550-406c-b152-cd030a3cc947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559942501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2559942501
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.2190311778
Short name T707
Test name
Test status
Simulation time 1586773488 ps
CPU time 15.62 seconds
Started Jul 15 07:20:48 PM PDT 24
Finished Jul 15 07:21:43 PM PDT 24
Peak memory 214360 kb
Host smart-774eeeb1-aefe-42de-ab6b-578f97a0845f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190311778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.2190311778
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.1276883675
Short name T158
Test name
Test status
Simulation time 632379805 ps
CPU time 18.56 seconds
Started Jul 15 07:20:44 PM PDT 24
Finished Jul 15 07:21:43 PM PDT 24
Peak memory 222616 kb
Host smart-895dfd9c-ef6b-4e31-992b-71fbe7f3ec6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276883675 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.1276883675
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.2759128312
Short name T709
Test name
Test status
Simulation time 6753682158 ps
CPU time 55.24 seconds
Started Jul 15 07:20:44 PM PDT 24
Finished Jul 15 07:22:19 PM PDT 24
Peak memory 216784 kb
Host smart-696db57c-f793-472d-bb50-1bf134a240bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759128312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.2759128312
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.1132847579
Short name T783
Test name
Test status
Simulation time 324057996 ps
CPU time 4 seconds
Started Jul 15 07:20:47 PM PDT 24
Finished Jul 15 07:21:31 PM PDT 24
Peak memory 210980 kb
Host smart-02dbada6-472e-4639-81c8-618067cb1e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132847579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.1132847579
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.2809875849
Short name T448
Test name
Test status
Simulation time 16988947 ps
CPU time 0.78 seconds
Started Jul 15 07:21:04 PM PDT 24
Finished Jul 15 07:21:50 PM PDT 24
Peak memory 206024 kb
Host smart-15997e46-63ec-4dcd-8d88-f466b5595320
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809875849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.2809875849
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.528169861
Short name T926
Test name
Test status
Simulation time 485865650 ps
CPU time 4.93 seconds
Started Jul 15 07:20:46 PM PDT 24
Finished Jul 15 07:21:30 PM PDT 24
Peak memory 222492 kb
Host smart-96bbef48-bc05-41ec-8e7a-aa2723723483
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=528169861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.528169861
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.1979166442
Short name T626
Test name
Test status
Simulation time 310606126 ps
CPU time 4.51 seconds
Started Jul 15 07:20:54 PM PDT 24
Finished Jul 15 07:21:42 PM PDT 24
Peak memory 222764 kb
Host smart-e3907218-141f-424c-a914-cfaca6022331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979166442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1979166442
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.2545265065
Short name T368
Test name
Test status
Simulation time 146809695 ps
CPU time 2.84 seconds
Started Jul 15 07:20:51 PM PDT 24
Finished Jul 15 07:21:37 PM PDT 24
Peak memory 214332 kb
Host smart-7a54ebf4-9fb2-4973-8030-8c723ade0263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545265065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.2545265065
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.2988801763
Short name T296
Test name
Test status
Simulation time 41849837 ps
CPU time 2.35 seconds
Started Jul 15 07:20:52 PM PDT 24
Finished Jul 15 07:21:37 PM PDT 24
Peak memory 214352 kb
Host smart-263f73a2-882a-4b58-8cdb-5768a7e5eef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988801763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.2988801763
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.1599369083
Short name T806
Test name
Test status
Simulation time 844988315 ps
CPU time 5.42 seconds
Started Jul 15 07:20:44 PM PDT 24
Finished Jul 15 07:21:30 PM PDT 24
Peak memory 215052 kb
Host smart-898b499e-15cf-4352-83ab-08b9f7263148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599369083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.1599369083
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.3739573738
Short name T604
Test name
Test status
Simulation time 286481448 ps
CPU time 8.2 seconds
Started Jul 15 07:20:44 PM PDT 24
Finished Jul 15 07:21:32 PM PDT 24
Peak memory 214228 kb
Host smart-f96b28a2-0be2-44f2-8207-886c81485ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739573738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3739573738
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.2570912505
Short name T546
Test name
Test status
Simulation time 802966584 ps
CPU time 6.8 seconds
Started Jul 15 07:20:44 PM PDT 24
Finished Jul 15 07:21:31 PM PDT 24
Peak memory 206916 kb
Host smart-187c80dc-0b63-4cf0-b78a-1dac39c57aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570912505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2570912505
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.2604080792
Short name T503
Test name
Test status
Simulation time 851183996 ps
CPU time 6.32 seconds
Started Jul 15 07:20:45 PM PDT 24
Finished Jul 15 07:21:31 PM PDT 24
Peak memory 207976 kb
Host smart-ed73e580-c174-46cb-8aae-2219ade5ff21
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604080792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.2604080792
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.3179242128
Short name T452
Test name
Test status
Simulation time 242967416 ps
CPU time 2.5 seconds
Started Jul 15 07:20:45 PM PDT 24
Finished Jul 15 07:21:27 PM PDT 24
Peak memory 206980 kb
Host smart-6c771a5e-0bb1-40c0-8fde-b790a67e90e7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179242128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3179242128
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.3011374629
Short name T243
Test name
Test status
Simulation time 1059367451 ps
CPU time 11.78 seconds
Started Jul 15 07:20:48 PM PDT 24
Finished Jul 15 07:21:39 PM PDT 24
Peak memory 208488 kb
Host smart-f598c6de-aee2-43be-b748-692bb78f5099
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011374629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.3011374629
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.665323695
Short name T462
Test name
Test status
Simulation time 111601675 ps
CPU time 4.03 seconds
Started Jul 15 07:20:51 PM PDT 24
Finished Jul 15 07:21:38 PM PDT 24
Peak memory 209920 kb
Host smart-ebb6b279-a371-4c00-99f1-e22efb9f09fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665323695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.665323695
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.3883920031
Short name T518
Test name
Test status
Simulation time 682132238 ps
CPU time 5.55 seconds
Started Jul 15 07:20:47 PM PDT 24
Finished Jul 15 07:21:33 PM PDT 24
Peak memory 208476 kb
Host smart-de9bbbaa-237b-47ff-aebe-8dc5e19ce87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883920031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.3883920031
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.2119207149
Short name T901
Test name
Test status
Simulation time 104924509 ps
CPU time 2.83 seconds
Started Jul 15 07:20:47 PM PDT 24
Finished Jul 15 07:21:30 PM PDT 24
Peak memory 208028 kb
Host smart-e430df94-35ee-42af-b4f2-3a6067383d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119207149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.2119207149
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.1346690953
Short name T880
Test name
Test status
Simulation time 106202051 ps
CPU time 2.22 seconds
Started Jul 15 07:21:04 PM PDT 24
Finished Jul 15 07:21:52 PM PDT 24
Peak memory 209976 kb
Host smart-26008553-f3ca-479e-8ae2-0daae021d3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346690953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.1346690953
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.756106038
Short name T850
Test name
Test status
Simulation time 93403719 ps
CPU time 0.82 seconds
Started Jul 15 07:20:56 PM PDT 24
Finished Jul 15 07:21:40 PM PDT 24
Peak memory 205992 kb
Host smart-3da0dabf-267c-4e64-a1bc-dd5f7968f617
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756106038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.756106038
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.38464977
Short name T60
Test name
Test status
Simulation time 669591409 ps
CPU time 5.3 seconds
Started Jul 15 07:20:53 PM PDT 24
Finished Jul 15 07:21:40 PM PDT 24
Peak memory 218328 kb
Host smart-2840c3cd-dc24-49e3-8146-bba181dd360e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38464977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.38464977
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2819218092
Short name T210
Test name
Test status
Simulation time 103044487 ps
CPU time 4.35 seconds
Started Jul 15 07:20:51 PM PDT 24
Finished Jul 15 07:21:38 PM PDT 24
Peak memory 219104 kb
Host smart-14d11945-9253-4c98-8e66-496ff5caf246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819218092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2819218092
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.2382027122
Short name T512
Test name
Test status
Simulation time 169448680 ps
CPU time 5.59 seconds
Started Jul 15 07:20:53 PM PDT 24
Finished Jul 15 07:21:40 PM PDT 24
Peak memory 220992 kb
Host smart-3f683c82-7685-4d10-a36e-d29523683bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382027122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2382027122
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.1322443002
Short name T351
Test name
Test status
Simulation time 490848405 ps
CPU time 3.9 seconds
Started Jul 15 07:20:49 PM PDT 24
Finished Jul 15 07:21:34 PM PDT 24
Peak memory 214328 kb
Host smart-e325df24-6253-4b7f-9e61-cc35be93fc85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322443002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.1322443002
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.1314851774
Short name T357
Test name
Test status
Simulation time 416307345 ps
CPU time 4.67 seconds
Started Jul 15 07:21:05 PM PDT 24
Finished Jul 15 07:21:55 PM PDT 24
Peak memory 218364 kb
Host smart-9bf4545e-48f0-4e3a-83b7-535c1a89a514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314851774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.1314851774
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.841425229
Short name T571
Test name
Test status
Simulation time 39596069 ps
CPU time 2.32 seconds
Started Jul 15 07:21:04 PM PDT 24
Finished Jul 15 07:21:52 PM PDT 24
Peak memory 206884 kb
Host smart-de3855f5-95df-48fb-a906-ce8313463d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841425229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.841425229
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.274136620
Short name T775
Test name
Test status
Simulation time 263188472 ps
CPU time 3.36 seconds
Started Jul 15 07:20:53 PM PDT 24
Finished Jul 15 07:21:38 PM PDT 24
Peak memory 208824 kb
Host smart-12ca6dc1-ccd5-4724-993e-16fae06e2097
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274136620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.274136620
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.4191757883
Short name T665
Test name
Test status
Simulation time 725326509 ps
CPU time 8.01 seconds
Started Jul 15 07:20:53 PM PDT 24
Finished Jul 15 07:21:43 PM PDT 24
Peak memory 208792 kb
Host smart-6d5ef8ea-a12a-461f-a28a-e568868576e9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191757883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.4191757883
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.3591450155
Short name T697
Test name
Test status
Simulation time 141637866 ps
CPU time 3.86 seconds
Started Jul 15 07:20:50 PM PDT 24
Finished Jul 15 07:21:35 PM PDT 24
Peak memory 208764 kb
Host smart-0a02c3c6-556e-4361-8d5f-ea30fd605116
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591450155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.3591450155
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.3178083357
Short name T841
Test name
Test status
Simulation time 67689587 ps
CPU time 2.6 seconds
Started Jul 15 07:20:52 PM PDT 24
Finished Jul 15 07:21:37 PM PDT 24
Peak memory 208064 kb
Host smart-91f186b7-bb8b-4470-a578-6b7a132f1208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178083357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3178083357
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.3066620901
Short name T476
Test name
Test status
Simulation time 417188152 ps
CPU time 2.67 seconds
Started Jul 15 07:20:51 PM PDT 24
Finished Jul 15 07:21:36 PM PDT 24
Peak memory 206944 kb
Host smart-0abfa4ce-9469-49f9-a4fa-b6db66bd0621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066620901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.3066620901
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.1495990370
Short name T662
Test name
Test status
Simulation time 1026157608 ps
CPU time 20.28 seconds
Started Jul 15 07:20:48 PM PDT 24
Finished Jul 15 07:21:48 PM PDT 24
Peak memory 222628 kb
Host smart-1e56f60c-bfd2-49b8-a7ff-bd4ee3181736
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495990370 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.1495990370
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.922139713
Short name T300
Test name
Test status
Simulation time 1291781530 ps
CPU time 26.82 seconds
Started Jul 15 07:20:52 PM PDT 24
Finished Jul 15 07:22:01 PM PDT 24
Peak memory 214284 kb
Host smart-481117b8-5716-42a4-994c-d9299ec26529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922139713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.922139713
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.702861484
Short name T730
Test name
Test status
Simulation time 102135100 ps
CPU time 2.84 seconds
Started Jul 15 07:20:49 PM PDT 24
Finished Jul 15 07:21:33 PM PDT 24
Peak memory 210580 kb
Host smart-12569bc9-d2bb-407e-91ab-937538bb3928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702861484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.702861484
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.1281362329
Short name T457
Test name
Test status
Simulation time 67246623 ps
CPU time 0.75 seconds
Started Jul 15 07:20:59 PM PDT 24
Finished Jul 15 07:21:43 PM PDT 24
Peak memory 205920 kb
Host smart-22105043-98e4-4941-80bb-8ebce565808b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281362329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.1281362329
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.1026247336
Short name T464
Test name
Test status
Simulation time 176558113 ps
CPU time 2.08 seconds
Started Jul 15 07:20:53 PM PDT 24
Finished Jul 15 07:21:37 PM PDT 24
Peak memory 209380 kb
Host smart-77a2ea12-b50b-4d52-8285-42c439fbb553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026247336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.1026247336
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.3222681483
Short name T367
Test name
Test status
Simulation time 94261798 ps
CPU time 1.82 seconds
Started Jul 15 07:20:57 PM PDT 24
Finished Jul 15 07:21:44 PM PDT 24
Peak memory 214356 kb
Host smart-975f7cc0-ca90-486f-8e68-42366fae4bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222681483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.3222681483
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.4022751388
Short name T273
Test name
Test status
Simulation time 86412425 ps
CPU time 4.09 seconds
Started Jul 15 07:20:58 PM PDT 24
Finished Jul 15 07:21:46 PM PDT 24
Peak memory 222360 kb
Host smart-bf957ab2-4523-4700-b354-1f85167f8e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022751388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.4022751388
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.1904022219
Short name T741
Test name
Test status
Simulation time 219639300 ps
CPU time 2.29 seconds
Started Jul 15 07:20:55 PM PDT 24
Finished Jul 15 07:21:41 PM PDT 24
Peak memory 220336 kb
Host smart-baa5ace2-952f-40f4-8a6d-8b454ef296f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904022219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.1904022219
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.2140276440
Short name T700
Test name
Test status
Simulation time 333838304 ps
CPU time 4.4 seconds
Started Jul 15 07:21:04 PM PDT 24
Finished Jul 15 07:21:54 PM PDT 24
Peak memory 207500 kb
Host smart-123a4749-7b23-4eca-ae79-7ed5dbd4bf3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140276440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.2140276440
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.568549023
Short name T842
Test name
Test status
Simulation time 359604970 ps
CPU time 2.47 seconds
Started Jul 15 07:21:04 PM PDT 24
Finished Jul 15 07:21:53 PM PDT 24
Peak memory 206840 kb
Host smart-f5b45e24-88c7-4f23-abd1-d8701501a7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568549023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.568549023
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.1037152885
Short name T263
Test name
Test status
Simulation time 98912069 ps
CPU time 3.25 seconds
Started Jul 15 07:20:50 PM PDT 24
Finished Jul 15 07:21:33 PM PDT 24
Peak memory 206948 kb
Host smart-10259979-2abd-419c-bb0e-8b6c30a16eb0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037152885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1037152885
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.1037493863
Short name T874
Test name
Test status
Simulation time 422547443 ps
CPU time 3.08 seconds
Started Jul 15 07:20:49 PM PDT 24
Finished Jul 15 07:21:33 PM PDT 24
Peak memory 208540 kb
Host smart-79085649-86c4-4efd-95f1-b60e5d20859c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037493863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1037493863
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.3798836426
Short name T550
Test name
Test status
Simulation time 219638006 ps
CPU time 5.14 seconds
Started Jul 15 07:20:53 PM PDT 24
Finished Jul 15 07:21:40 PM PDT 24
Peak memory 208552 kb
Host smart-e0b0ca65-5f45-4c5f-ba3b-6cd0c9c50f42
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798836426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.3798836426
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.885876997
Short name T554
Test name
Test status
Simulation time 3280899551 ps
CPU time 19.62 seconds
Started Jul 15 07:20:58 PM PDT 24
Finished Jul 15 07:22:02 PM PDT 24
Peak memory 209376 kb
Host smart-8461b01c-e40b-447c-8442-0f7a9b0bfbb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885876997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.885876997
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.1020812749
Short name T563
Test name
Test status
Simulation time 126213274 ps
CPU time 3.37 seconds
Started Jul 15 07:21:04 PM PDT 24
Finished Jul 15 07:21:53 PM PDT 24
Peak memory 206976 kb
Host smart-b61b66f0-5c31-4e9f-b878-d199ff4c1d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020812749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.1020812749
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.2245597127
Short name T230
Test name
Test status
Simulation time 999979013 ps
CPU time 25.39 seconds
Started Jul 15 07:20:58 PM PDT 24
Finished Jul 15 07:22:08 PM PDT 24
Peak memory 222616 kb
Host smart-56ac892c-56d4-4e52-ba92-60563893929a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245597127 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.2245597127
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.2269349345
Short name T109
Test name
Test status
Simulation time 449402472 ps
CPU time 5.17 seconds
Started Jul 15 07:20:55 PM PDT 24
Finished Jul 15 07:21:44 PM PDT 24
Peak memory 214308 kb
Host smart-2995c236-63a8-40cf-a165-ec3b777633f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269349345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.2269349345
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.3085428612
Short name T432
Test name
Test status
Simulation time 10797948 ps
CPU time 0.75 seconds
Started Jul 15 07:20:57 PM PDT 24
Finished Jul 15 07:21:41 PM PDT 24
Peak memory 205980 kb
Host smart-af0238e4-f1a6-4a13-8b8c-71da293ca240
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085428612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.3085428612
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.836307523
Short name T330
Test name
Test status
Simulation time 617973427 ps
CPU time 15.24 seconds
Started Jul 15 07:20:58 PM PDT 24
Finished Jul 15 07:21:57 PM PDT 24
Peak memory 214236 kb
Host smart-33e40e54-a646-4517-a679-737f831f5826
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=836307523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.836307523
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.2739605615
Short name T507
Test name
Test status
Simulation time 204882415 ps
CPU time 3.85 seconds
Started Jul 15 07:21:03 PM PDT 24
Finished Jul 15 07:21:50 PM PDT 24
Peak memory 214316 kb
Host smart-2f38b087-dd5f-49b4-9e73-b81f4bb5a718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739605615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2739605615
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.1035751336
Short name T87
Test name
Test status
Simulation time 164987664 ps
CPU time 4.18 seconds
Started Jul 15 07:20:59 PM PDT 24
Finished Jul 15 07:21:47 PM PDT 24
Peak memory 215524 kb
Host smart-037accf4-cd7f-459d-bb68-a8568b507a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035751336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.1035751336
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.3909125506
Short name T369
Test name
Test status
Simulation time 130536866 ps
CPU time 5.77 seconds
Started Jul 15 07:21:03 PM PDT 24
Finished Jul 15 07:21:52 PM PDT 24
Peak memory 214280 kb
Host smart-652e4be7-a34d-47d8-82df-e6cea94aa43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909125506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.3909125506
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.424823779
Short name T2
Test name
Test status
Simulation time 294754648 ps
CPU time 4.7 seconds
Started Jul 15 07:20:59 PM PDT 24
Finished Jul 15 07:21:47 PM PDT 24
Peak memory 220092 kb
Host smart-4983e3f3-e1a3-4bae-b608-55aa7fd99df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424823779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.424823779
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.1407772516
Short name T257
Test name
Test status
Simulation time 838706486 ps
CPU time 24.87 seconds
Started Jul 15 07:21:03 PM PDT 24
Finished Jul 15 07:22:11 PM PDT 24
Peak memory 218356 kb
Host smart-75eeae2f-1d60-405c-9014-5f321181f5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407772516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.1407772516
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.3791408413
Short name T377
Test name
Test status
Simulation time 139607556 ps
CPU time 2.75 seconds
Started Jul 15 07:20:55 PM PDT 24
Finished Jul 15 07:21:42 PM PDT 24
Peak memory 208556 kb
Host smart-583772af-6ce6-4c08-b0b1-fa727d95c00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791408413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.3791408413
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.3524801388
Short name T747
Test name
Test status
Simulation time 748597436 ps
CPU time 16.7 seconds
Started Jul 15 07:21:00 PM PDT 24
Finished Jul 15 07:22:00 PM PDT 24
Peak memory 208704 kb
Host smart-998a11a6-4f6e-469e-9c31-7ed3cf28cad3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524801388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.3524801388
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.2688669972
Short name T522
Test name
Test status
Simulation time 490487988 ps
CPU time 7.82 seconds
Started Jul 15 07:20:58 PM PDT 24
Finished Jul 15 07:21:50 PM PDT 24
Peak memory 208084 kb
Host smart-b7136289-07e5-4e57-b572-7db63230fcd6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688669972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.2688669972
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.1551317628
Short name T481
Test name
Test status
Simulation time 2436622287 ps
CPU time 4.44 seconds
Started Jul 15 07:20:58 PM PDT 24
Finished Jul 15 07:21:46 PM PDT 24
Peak memory 207020 kb
Host smart-7f0d79c4-263f-4945-9fb0-469437e32ee9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551317628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.1551317628
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.4189742703
Short name T858
Test name
Test status
Simulation time 235243306 ps
CPU time 2.25 seconds
Started Jul 15 07:20:57 PM PDT 24
Finished Jul 15 07:21:42 PM PDT 24
Peak memory 216048 kb
Host smart-8c4eeafc-c306-423e-9e66-ec84ca6222a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189742703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.4189742703
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.2172293307
Short name T663
Test name
Test status
Simulation time 52934488 ps
CPU time 2.28 seconds
Started Jul 15 07:20:56 PM PDT 24
Finished Jul 15 07:21:42 PM PDT 24
Peak memory 206136 kb
Host smart-fc762d41-354c-4f18-ab2a-ac1d41501a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172293307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.2172293307
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.2418239409
Short name T318
Test name
Test status
Simulation time 786051631 ps
CPU time 21.19 seconds
Started Jul 15 07:20:56 PM PDT 24
Finished Jul 15 07:22:01 PM PDT 24
Peak memory 219732 kb
Host smart-f417c315-91ee-49df-a25d-361eda57b3ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418239409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.2418239409
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.4136634630
Short name T866
Test name
Test status
Simulation time 241306450 ps
CPU time 8.31 seconds
Started Jul 15 07:20:57 PM PDT 24
Finished Jul 15 07:21:50 PM PDT 24
Peak memory 219932 kb
Host smart-62103201-1644-46f8-8a03-064ed13dedf1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136634630 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.4136634630
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.3231950351
Short name T319
Test name
Test status
Simulation time 1727283308 ps
CPU time 24.94 seconds
Started Jul 15 07:20:59 PM PDT 24
Finished Jul 15 07:22:07 PM PDT 24
Peak memory 209460 kb
Host smart-433ccc28-d476-417f-aa02-60f06465055d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231950351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3231950351
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.653085963
Short name T497
Test name
Test status
Simulation time 237350378 ps
CPU time 2.6 seconds
Started Jul 15 07:21:02 PM PDT 24
Finished Jul 15 07:21:49 PM PDT 24
Peak memory 210328 kb
Host smart-743d4921-0ed2-4ea0-823d-4893ffefb287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653085963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.653085963
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.3603085157
Short name T756
Test name
Test status
Simulation time 112608944 ps
CPU time 0.77 seconds
Started Jul 15 07:19:20 PM PDT 24
Finished Jul 15 07:20:23 PM PDT 24
Peak memory 205912 kb
Host smart-4cc8d0df-1fa7-4478-ae3e-7b2e5f0e9a49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603085157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.3603085157
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.2705401008
Short name T421
Test name
Test status
Simulation time 58173154 ps
CPU time 4.05 seconds
Started Jul 15 07:19:22 PM PDT 24
Finished Jul 15 07:20:27 PM PDT 24
Peak memory 214352 kb
Host smart-f922bd3a-9313-472d-8f2a-58a5330cebe3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2705401008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.2705401008
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.2098838680
Short name T648
Test name
Test status
Simulation time 250409356 ps
CPU time 3.31 seconds
Started Jul 15 07:19:19 PM PDT 24
Finished Jul 15 07:20:27 PM PDT 24
Peak memory 214340 kb
Host smart-46d13a03-fc4e-48df-8a23-eb93e609d31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098838680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.2098838680
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.3805706381
Short name T644
Test name
Test status
Simulation time 52471030 ps
CPU time 2.81 seconds
Started Jul 15 07:19:20 PM PDT 24
Finished Jul 15 07:20:26 PM PDT 24
Peak memory 214252 kb
Host smart-e97bb45e-a012-4554-97df-4d7142b9f36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805706381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.3805706381
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.3050919316
Short name T343
Test name
Test status
Simulation time 123698309 ps
CPU time 2.2 seconds
Started Jul 15 07:19:21 PM PDT 24
Finished Jul 15 07:20:25 PM PDT 24
Peak memory 222432 kb
Host smart-0bf0fb38-dc5f-45ce-8b8b-645fc4fc3fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050919316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.3050919316
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.3326503190
Short name T568
Test name
Test status
Simulation time 216148083 ps
CPU time 2.31 seconds
Started Jul 15 07:19:20 PM PDT 24
Finished Jul 15 07:20:26 PM PDT 24
Peak memory 215632 kb
Host smart-8d0a1d03-7cdf-482c-bde9-8a7be9fb0745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326503190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.3326503190
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.3495067800
Short name T516
Test name
Test status
Simulation time 301848800 ps
CPU time 4.74 seconds
Started Jul 15 07:19:28 PM PDT 24
Finished Jul 15 07:20:33 PM PDT 24
Peak memory 214296 kb
Host smart-2dbe6dc2-67f1-4f3e-8da1-c145d4e57fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495067800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3495067800
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.2086662514
Short name T10
Test name
Test status
Simulation time 575591895 ps
CPU time 10.08 seconds
Started Jul 15 07:19:18 PM PDT 24
Finished Jul 15 07:20:33 PM PDT 24
Peak memory 229840 kb
Host smart-5ff3b636-5f9c-442b-a2cf-72c88c0aafc6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086662514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.2086662514
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.3886034818
Short name T645
Test name
Test status
Simulation time 148332139 ps
CPU time 4.78 seconds
Started Jul 15 07:19:19 PM PDT 24
Finished Jul 15 07:20:28 PM PDT 24
Peak memory 208552 kb
Host smart-b6579013-09fd-4aca-8d65-f196d57e2c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886034818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3886034818
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.1547488770
Short name T471
Test name
Test status
Simulation time 421603118 ps
CPU time 6.55 seconds
Started Jul 15 07:19:20 PM PDT 24
Finished Jul 15 07:20:29 PM PDT 24
Peak memory 207944 kb
Host smart-66c40a92-9fcd-426c-988c-a635ac2fc48e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547488770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1547488770
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.3126059637
Short name T759
Test name
Test status
Simulation time 268646283 ps
CPU time 3.36 seconds
Started Jul 15 07:19:20 PM PDT 24
Finished Jul 15 07:20:26 PM PDT 24
Peak memory 208836 kb
Host smart-6cfc8d37-c95e-47d4-9d27-671b1695dd5f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126059637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.3126059637
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.3474713732
Short name T911
Test name
Test status
Simulation time 310730925 ps
CPU time 2.86 seconds
Started Jul 15 07:19:24 PM PDT 24
Finished Jul 15 07:20:28 PM PDT 24
Peak memory 207072 kb
Host smart-333dbfa3-8ad1-4795-bbff-be94d047c53d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474713732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.3474713732
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.170478463
Short name T658
Test name
Test status
Simulation time 217325575 ps
CPU time 3.35 seconds
Started Jul 15 07:19:22 PM PDT 24
Finished Jul 15 07:20:26 PM PDT 24
Peak memory 218532 kb
Host smart-3f54371c-3902-4b67-8529-12e8eb125c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170478463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.170478463
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.4059826811
Short name T784
Test name
Test status
Simulation time 30198752 ps
CPU time 1.91 seconds
Started Jul 15 07:19:24 PM PDT 24
Finished Jul 15 07:20:27 PM PDT 24
Peak memory 206772 kb
Host smart-3f224a3d-97cb-479b-9940-e8969fbe889d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059826811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.4059826811
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.775163383
Short name T800
Test name
Test status
Simulation time 2624973227 ps
CPU time 26.04 seconds
Started Jul 15 07:19:20 PM PDT 24
Finished Jul 15 07:20:48 PM PDT 24
Peak memory 222504 kb
Host smart-54b7213a-060f-49de-997d-a3aa108e21a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775163383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.775163383
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.1065718541
Short name T301
Test name
Test status
Simulation time 212184959 ps
CPU time 6.02 seconds
Started Jul 15 07:19:19 PM PDT 24
Finished Jul 15 07:20:29 PM PDT 24
Peak memory 222732 kb
Host smart-ff9843ad-79d1-4ef5-93d5-7e1628fb825d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065718541 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.1065718541
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.3981811784
Short name T660
Test name
Test status
Simulation time 341293208 ps
CPU time 9.86 seconds
Started Jul 15 07:19:20 PM PDT 24
Finished Jul 15 07:20:32 PM PDT 24
Peak memory 214352 kb
Host smart-ef38f7d1-82b6-4ee0-8964-f9d3ddc8d9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981811784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.3981811784
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.1542744091
Short name T165
Test name
Test status
Simulation time 42545453 ps
CPU time 2.43 seconds
Started Jul 15 07:19:24 PM PDT 24
Finished Jul 15 07:20:27 PM PDT 24
Peak memory 210164 kb
Host smart-db0b72ec-533a-4de9-a1ef-9780eced0ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542744091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.1542744091
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.1944499636
Short name T445
Test name
Test status
Simulation time 43161155 ps
CPU time 0.84 seconds
Started Jul 15 07:21:04 PM PDT 24
Finished Jul 15 07:21:50 PM PDT 24
Peak memory 206028 kb
Host smart-76396139-a0e0-4e50-86a5-8d1a5c642d95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944499636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.1944499636
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.420912299
Short name T884
Test name
Test status
Simulation time 75095476 ps
CPU time 2.83 seconds
Started Jul 15 07:20:57 PM PDT 24
Finished Jul 15 07:21:45 PM PDT 24
Peak memory 208284 kb
Host smart-45a29e15-f869-496b-961f-923092ed7d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420912299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.420912299
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.3283428269
Short name T248
Test name
Test status
Simulation time 58202727 ps
CPU time 2.4 seconds
Started Jul 15 07:21:05 PM PDT 24
Finished Jul 15 07:21:53 PM PDT 24
Peak memory 214304 kb
Host smart-a4f23d76-d9c7-474c-8b53-f89bc1ba2da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283428269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.3283428269
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.3054260300
Short name T691
Test name
Test status
Simulation time 30795937 ps
CPU time 1.96 seconds
Started Jul 15 07:20:58 PM PDT 24
Finished Jul 15 07:21:44 PM PDT 24
Peak memory 209404 kb
Host smart-8f2222ce-2e19-4e3b-98dc-042171508180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054260300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3054260300
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.3091486217
Short name T712
Test name
Test status
Simulation time 326955976 ps
CPU time 6.92 seconds
Started Jul 15 07:20:58 PM PDT 24
Finished Jul 15 07:21:49 PM PDT 24
Peak memory 218344 kb
Host smart-7261777f-5747-4bd6-a703-2dbc693cd2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091486217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.3091486217
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.2985635560
Short name T268
Test name
Test status
Simulation time 395420346 ps
CPU time 3.4 seconds
Started Jul 15 07:21:02 PM PDT 24
Finished Jul 15 07:21:49 PM PDT 24
Peak memory 208116 kb
Host smart-14f14b3c-f708-431f-a05b-b3f8b08a64c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985635560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.2985635560
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.573085886
Short name T839
Test name
Test status
Simulation time 1427866177 ps
CPU time 37.05 seconds
Started Jul 15 07:20:59 PM PDT 24
Finished Jul 15 07:22:19 PM PDT 24
Peak memory 208476 kb
Host smart-cdbf22c1-4702-4abc-b274-ea94b0c9238a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573085886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.573085886
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.1855846848
Short name T533
Test name
Test status
Simulation time 342081294 ps
CPU time 6.32 seconds
Started Jul 15 07:20:58 PM PDT 24
Finished Jul 15 07:21:48 PM PDT 24
Peak memory 208008 kb
Host smart-2fa366e7-4f63-4252-a8ee-eff46a2ea28f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855846848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.1855846848
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.3716311857
Short name T493
Test name
Test status
Simulation time 290933828 ps
CPU time 3.57 seconds
Started Jul 15 07:21:00 PM PDT 24
Finished Jul 15 07:21:46 PM PDT 24
Peak memory 208584 kb
Host smart-f9eaf9d8-2a65-4467-8448-cd57e0663f33
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716311857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.3716311857
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.1019749877
Short name T886
Test name
Test status
Simulation time 69844306 ps
CPU time 1.51 seconds
Started Jul 15 07:20:59 PM PDT 24
Finished Jul 15 07:21:44 PM PDT 24
Peak memory 208096 kb
Host smart-7b410d15-948e-4554-a5ba-226ae51aa5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019749877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.1019749877
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.666993035
Short name T523
Test name
Test status
Simulation time 1126688065 ps
CPU time 6.32 seconds
Started Jul 15 07:20:59 PM PDT 24
Finished Jul 15 07:21:49 PM PDT 24
Peak memory 206760 kb
Host smart-6d29e093-035f-499e-b9e4-2b71bf9f8c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666993035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.666993035
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.655168636
Short name T870
Test name
Test status
Simulation time 1102978185 ps
CPU time 11.6 seconds
Started Jul 15 07:21:07 PM PDT 24
Finished Jul 15 07:22:05 PM PDT 24
Peak memory 216956 kb
Host smart-74321965-abc4-4d1a-ad54-f574b71c6b34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655168636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.655168636
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.238020939
Short name T362
Test name
Test status
Simulation time 1898767946 ps
CPU time 5.31 seconds
Started Jul 15 07:20:57 PM PDT 24
Finished Jul 15 07:21:47 PM PDT 24
Peak memory 208080 kb
Host smart-ae8f4cd8-0b50-4f96-a7b9-14902dcc87eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238020939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.238020939
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.3099682667
Short name T853
Test name
Test status
Simulation time 1023728876 ps
CPU time 12.46 seconds
Started Jul 15 07:21:00 PM PDT 24
Finished Jul 15 07:21:55 PM PDT 24
Peak memory 210700 kb
Host smart-2ed13c61-ca7f-4816-b772-740433d665f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099682667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3099682667
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.2407300273
Short name T460
Test name
Test status
Simulation time 40551642 ps
CPU time 0.71 seconds
Started Jul 15 07:21:05 PM PDT 24
Finished Jul 15 07:21:51 PM PDT 24
Peak memory 206012 kb
Host smart-721638ee-fbee-43e2-80b5-592bde42b23f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407300273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.2407300273
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.3186725122
Short name T425
Test name
Test status
Simulation time 261723365 ps
CPU time 4.7 seconds
Started Jul 15 07:21:04 PM PDT 24
Finished Jul 15 07:21:55 PM PDT 24
Peak memory 214312 kb
Host smart-69a4e1d5-21af-40c5-8cf1-94007bf37287
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3186725122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.3186725122
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.630331888
Short name T536
Test name
Test status
Simulation time 113272906 ps
CPU time 2.44 seconds
Started Jul 15 07:21:03 PM PDT 24
Finished Jul 15 07:21:49 PM PDT 24
Peak memory 214668 kb
Host smart-236d7d5f-5025-4b30-935e-c96abd798e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630331888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.630331888
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.3099474176
Short name T50
Test name
Test status
Simulation time 158084626 ps
CPU time 4.87 seconds
Started Jul 15 07:21:03 PM PDT 24
Finished Jul 15 07:21:51 PM PDT 24
Peak memory 208536 kb
Host smart-200fe3c4-3fba-4f74-85b5-3695cf04bdea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099474176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.3099474176
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.978316447
Short name T97
Test name
Test status
Simulation time 237754048 ps
CPU time 7.53 seconds
Started Jul 15 07:21:01 PM PDT 24
Finished Jul 15 07:21:53 PM PDT 24
Peak memory 221272 kb
Host smart-332c6c66-8cb2-4cee-a957-fab0f34669ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978316447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.978316447
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.3145112420
Short name T371
Test name
Test status
Simulation time 125520675 ps
CPU time 5.29 seconds
Started Jul 15 07:21:06 PM PDT 24
Finished Jul 15 07:21:56 PM PDT 24
Peak memory 215228 kb
Host smart-7592896e-f5a8-44f5-a0d7-bfa4e5932252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145112420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.3145112420
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_random.1906242137
Short name T813
Test name
Test status
Simulation time 44595488 ps
CPU time 3.17 seconds
Started Jul 15 07:21:06 PM PDT 24
Finished Jul 15 07:21:56 PM PDT 24
Peak memory 214284 kb
Host smart-3118de06-9b49-47df-ad81-c06387e4fc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906242137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.1906242137
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.846831442
Short name T735
Test name
Test status
Simulation time 196279913 ps
CPU time 2.82 seconds
Started Jul 15 07:21:01 PM PDT 24
Finished Jul 15 07:21:49 PM PDT 24
Peak memory 206876 kb
Host smart-b40d3339-d6c4-4c8f-a432-aba3027e9259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846831442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.846831442
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.1031348739
Short name T613
Test name
Test status
Simulation time 191404843 ps
CPU time 7.11 seconds
Started Jul 15 07:21:07 PM PDT 24
Finished Jul 15 07:22:00 PM PDT 24
Peak memory 208780 kb
Host smart-b1a82da6-a369-495e-813f-f8f25298d99b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031348739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.1031348739
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.2522146245
Short name T532
Test name
Test status
Simulation time 335729925 ps
CPU time 2.71 seconds
Started Jul 15 07:21:02 PM PDT 24
Finished Jul 15 07:21:49 PM PDT 24
Peak memory 206996 kb
Host smart-1c4e65a6-a268-4b46-84c0-8798310dc55d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522146245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.2522146245
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.2965417711
Short name T290
Test name
Test status
Simulation time 192443770 ps
CPU time 4.26 seconds
Started Jul 15 07:21:06 PM PDT 24
Finished Jul 15 07:21:55 PM PDT 24
Peak memory 209804 kb
Host smart-b5f6192f-133a-4643-854f-701803226f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965417711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.2965417711
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.638111023
Short name T434
Test name
Test status
Simulation time 242293306 ps
CPU time 7.11 seconds
Started Jul 15 07:21:04 PM PDT 24
Finished Jul 15 07:21:57 PM PDT 24
Peak memory 208456 kb
Host smart-3ec221cb-b81a-4783-a74c-3acd6ff71b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638111023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.638111023
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.3001219527
Short name T228
Test name
Test status
Simulation time 16301023094 ps
CPU time 300.76 seconds
Started Jul 15 07:21:07 PM PDT 24
Finished Jul 15 07:26:54 PM PDT 24
Peak memory 222560 kb
Host smart-09d874c4-22d9-44ef-ac88-bc384db17f35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001219527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.3001219527
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.3134930170
Short name T104
Test name
Test status
Simulation time 135115332 ps
CPU time 4.66 seconds
Started Jul 15 07:21:07 PM PDT 24
Finished Jul 15 07:21:58 PM PDT 24
Peak memory 222568 kb
Host smart-cd8698f6-252c-416c-9e6b-9af7f63c6912
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134930170 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.3134930170
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.542553576
Short name T606
Test name
Test status
Simulation time 153469090 ps
CPU time 5.17 seconds
Started Jul 15 07:21:04 PM PDT 24
Finished Jul 15 07:21:55 PM PDT 24
Peak memory 214352 kb
Host smart-f5d6fd43-06a3-41e9-acdf-bc593b26b703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542553576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.542553576
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.1682627971
Short name T797
Test name
Test status
Simulation time 12265847 ps
CPU time 0.84 seconds
Started Jul 15 07:21:07 PM PDT 24
Finished Jul 15 07:21:54 PM PDT 24
Peak memory 206000 kb
Host smart-0fc6d6a0-a5b0-42b9-a61d-deba2e3fe7bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682627971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.1682627971
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.1668980642
Short name T688
Test name
Test status
Simulation time 113647959 ps
CPU time 2.4 seconds
Started Jul 15 07:21:06 PM PDT 24
Finished Jul 15 07:21:53 PM PDT 24
Peak memory 210180 kb
Host smart-d86b7e00-2955-43ec-a84d-b722712aaefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668980642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.1668980642
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.1689379709
Short name T346
Test name
Test status
Simulation time 95460157 ps
CPU time 2.09 seconds
Started Jul 15 07:21:04 PM PDT 24
Finished Jul 15 07:21:52 PM PDT 24
Peak memory 218136 kb
Host smart-e768fb39-a212-4657-a467-acc48fd41a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689379709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.1689379709
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.2990888079
Short name T99
Test name
Test status
Simulation time 103823352 ps
CPU time 2.4 seconds
Started Jul 15 07:21:06 PM PDT 24
Finished Jul 15 07:21:53 PM PDT 24
Peak memory 222052 kb
Host smart-4a324efd-1106-4102-ac33-7866965ef762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990888079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2990888079
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.3447493650
Short name T456
Test name
Test status
Simulation time 372805876 ps
CPU time 6.36 seconds
Started Jul 15 07:21:06 PM PDT 24
Finished Jul 15 07:21:57 PM PDT 24
Peak memory 214424 kb
Host smart-372634dc-db9c-41f3-83e0-21033dcce7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447493650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.3447493650
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.3675865841
Short name T242
Test name
Test status
Simulation time 166187718 ps
CPU time 3.25 seconds
Started Jul 15 07:21:04 PM PDT 24
Finished Jul 15 07:21:53 PM PDT 24
Peak memory 214340 kb
Host smart-f7d60211-b2aa-46d0-9eb0-d1808351ee9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675865841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.3675865841
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.1751147247
Short name T283
Test name
Test status
Simulation time 40889558 ps
CPU time 2.27 seconds
Started Jul 15 07:21:04 PM PDT 24
Finished Jul 15 07:21:52 PM PDT 24
Peak memory 206880 kb
Host smart-009e632f-b4a9-4a3a-b426-2a14125b9e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751147247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1751147247
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.659571954
Short name T407
Test name
Test status
Simulation time 1035417899 ps
CPU time 4.07 seconds
Started Jul 15 07:21:06 PM PDT 24
Finished Jul 15 07:21:55 PM PDT 24
Peak memory 206884 kb
Host smart-e96296b7-8492-4c17-accc-90c43ce1bcae
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659571954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.659571954
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.2473456919
Short name T431
Test name
Test status
Simulation time 502298217 ps
CPU time 3.54 seconds
Started Jul 15 07:21:05 PM PDT 24
Finished Jul 15 07:21:54 PM PDT 24
Peak memory 206916 kb
Host smart-ff0d72a2-b189-43be-a38b-f20d514a0eb3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473456919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.2473456919
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.3557592612
Short name T494
Test name
Test status
Simulation time 107411334 ps
CPU time 3.87 seconds
Started Jul 15 07:21:05 PM PDT 24
Finished Jul 15 07:21:54 PM PDT 24
Peak memory 208400 kb
Host smart-2eede05d-5d5a-4abf-a735-c9df27538792
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557592612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.3557592612
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.2188987171
Short name T920
Test name
Test status
Simulation time 737916162 ps
CPU time 4.46 seconds
Started Jul 15 07:21:04 PM PDT 24
Finished Jul 15 07:21:54 PM PDT 24
Peak memory 208704 kb
Host smart-687c83ff-d031-45d3-9246-f4448155f2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188987171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.2188987171
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.4287524395
Short name T446
Test name
Test status
Simulation time 20122742 ps
CPU time 1.7 seconds
Started Jul 15 07:21:02 PM PDT 24
Finished Jul 15 07:21:48 PM PDT 24
Peak memory 206628 kb
Host smart-7019fd87-ced0-4329-8149-2dbe0d49da53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287524395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.4287524395
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.720610954
Short name T261
Test name
Test status
Simulation time 4319271457 ps
CPU time 9.01 seconds
Started Jul 15 07:21:04 PM PDT 24
Finished Jul 15 07:21:59 PM PDT 24
Peak memory 210304 kb
Host smart-9b4bc3af-a966-42e6-b9a5-92342640bfdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720610954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.720610954
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.4030331681
Short name T390
Test name
Test status
Simulation time 81763735 ps
CPU time 3.04 seconds
Started Jul 15 07:21:04 PM PDT 24
Finished Jul 15 07:21:53 PM PDT 24
Peak memory 210172 kb
Host smart-3517fc2e-e40d-42aa-8c3a-6513a2fdeaf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030331681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.4030331681
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.1062093286
Short name T779
Test name
Test status
Simulation time 19066777 ps
CPU time 0.75 seconds
Started Jul 15 07:21:14 PM PDT 24
Finished Jul 15 07:22:02 PM PDT 24
Peak memory 205972 kb
Host smart-9b7f5cee-91d7-4e37-954a-f6e58a2b20a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062093286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.1062093286
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.2226051117
Short name T510
Test name
Test status
Simulation time 43434186 ps
CPU time 1.21 seconds
Started Jul 15 07:21:11 PM PDT 24
Finished Jul 15 07:22:00 PM PDT 24
Peak memory 218372 kb
Host smart-b209862c-f27b-481c-ba22-bcdf24e4f996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226051117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.2226051117
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.3852442077
Short name T907
Test name
Test status
Simulation time 433120015 ps
CPU time 5.06 seconds
Started Jul 15 07:21:05 PM PDT 24
Finished Jul 15 07:21:55 PM PDT 24
Peak memory 214236 kb
Host smart-51ac6145-fe4b-4ea4-9534-83865525b98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852442077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.3852442077
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.2060432929
Short name T22
Test name
Test status
Simulation time 151553077 ps
CPU time 6.28 seconds
Started Jul 15 07:21:11 PM PDT 24
Finished Jul 15 07:22:05 PM PDT 24
Peak memory 214420 kb
Host smart-db235754-135c-41b5-a62e-35a786cf02e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060432929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.2060432929
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.1712149614
Short name T868
Test name
Test status
Simulation time 139321873 ps
CPU time 5.9 seconds
Started Jul 15 07:21:12 PM PDT 24
Finished Jul 15 07:22:05 PM PDT 24
Peak memory 221572 kb
Host smart-689fcf7e-746e-4700-9567-79c625f0a772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712149614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1712149614
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.654391753
Short name T760
Test name
Test status
Simulation time 281971703 ps
CPU time 2.68 seconds
Started Jul 15 07:21:12 PM PDT 24
Finished Jul 15 07:22:02 PM PDT 24
Peak memory 222420 kb
Host smart-7d5cf939-b564-43d0-8567-446b2f22ad09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654391753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.654391753
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.1584697683
Short name T129
Test name
Test status
Simulation time 8839186507 ps
CPU time 81.02 seconds
Started Jul 15 07:21:04 PM PDT 24
Finished Jul 15 07:23:11 PM PDT 24
Peak memory 220304 kb
Host smart-1a75eb93-ec81-4eec-b341-6dd977e3868b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584697683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.1584697683
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.2882879921
Short name T81
Test name
Test status
Simulation time 208269279 ps
CPU time 2.82 seconds
Started Jul 15 07:21:04 PM PDT 24
Finished Jul 15 07:21:52 PM PDT 24
Peak memory 206828 kb
Host smart-ee71a5a8-34fc-4159-a42d-97a21f66d7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882879921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.2882879921
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.2283630198
Short name T636
Test name
Test status
Simulation time 217792903 ps
CPU time 7.88 seconds
Started Jul 15 07:21:03 PM PDT 24
Finished Jul 15 07:21:55 PM PDT 24
Peak memory 207080 kb
Host smart-08280e4c-8fac-40c8-9dc1-e2e3177adedb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283630198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.2283630198
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.502425645
Short name T924
Test name
Test status
Simulation time 3438851603 ps
CPU time 22.24 seconds
Started Jul 15 07:21:03 PM PDT 24
Finished Jul 15 07:22:09 PM PDT 24
Peak memory 208448 kb
Host smart-3196ee6c-6422-43fd-908f-3fd64f54faa2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502425645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.502425645
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.737987041
Short name T826
Test name
Test status
Simulation time 503128582 ps
CPU time 4.32 seconds
Started Jul 15 07:21:03 PM PDT 24
Finished Jul 15 07:21:51 PM PDT 24
Peak memory 208628 kb
Host smart-fa1fb534-d269-4514-9b6c-5605a2fa3738
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737987041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.737987041
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.2397456306
Short name T569
Test name
Test status
Simulation time 497513297 ps
CPU time 2.83 seconds
Started Jul 15 07:21:13 PM PDT 24
Finished Jul 15 07:22:02 PM PDT 24
Peak memory 208804 kb
Host smart-ddcec1ae-ba8e-43d3-b9cd-ee1ce179fd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397456306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2397456306
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.2243787502
Short name T398
Test name
Test status
Simulation time 1674709910 ps
CPU time 4.24 seconds
Started Jul 15 07:21:04 PM PDT 24
Finished Jul 15 07:21:54 PM PDT 24
Peak memory 208372 kb
Host smart-21492fad-53d1-432d-be21-821b0a84ec81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243787502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.2243787502
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.635085519
Short name T53
Test name
Test status
Simulation time 539253402 ps
CPU time 12.74 seconds
Started Jul 15 07:21:12 PM PDT 24
Finished Jul 15 07:22:12 PM PDT 24
Peak memory 222236 kb
Host smart-9288a8bf-310b-4a86-8e27-a3b9a32f40d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635085519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.635085519
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.2736887598
Short name T189
Test name
Test status
Simulation time 689521434 ps
CPU time 26.59 seconds
Started Jul 15 07:21:09 PM PDT 24
Finished Jul 15 07:22:21 PM PDT 24
Peak memory 222604 kb
Host smart-6cdd1f3c-c02b-4943-94df-b303a712a8b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736887598 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.2736887598
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.1923088704
Short name T111
Test name
Test status
Simulation time 309371816 ps
CPU time 6.36 seconds
Started Jul 15 07:21:12 PM PDT 24
Finished Jul 15 07:22:05 PM PDT 24
Peak memory 218452 kb
Host smart-798edb78-feb8-4d33-b748-677e38c56044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923088704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.1923088704
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.2217069080
Short name T601
Test name
Test status
Simulation time 405597721 ps
CPU time 2.86 seconds
Started Jul 15 07:21:11 PM PDT 24
Finished Jul 15 07:22:02 PM PDT 24
Peak memory 209880 kb
Host smart-26e1a3ae-240e-41fe-a120-f71154bd87bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217069080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.2217069080
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.252347878
Short name T441
Test name
Test status
Simulation time 14008046 ps
CPU time 0.82 seconds
Started Jul 15 07:21:11 PM PDT 24
Finished Jul 15 07:22:00 PM PDT 24
Peak memory 206024 kb
Host smart-705c8205-1205-40e4-b60a-e97d6cbb9e57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252347878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.252347878
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.2825272282
Short name T340
Test name
Test status
Simulation time 58728819 ps
CPU time 4.26 seconds
Started Jul 15 07:21:10 PM PDT 24
Finished Jul 15 07:22:02 PM PDT 24
Peak memory 215336 kb
Host smart-2c6122f8-d585-4605-850c-d8dbf860a4fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2825272282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.2825272282
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.1947675636
Short name T214
Test name
Test status
Simulation time 53171298 ps
CPU time 1.98 seconds
Started Jul 15 07:21:13 PM PDT 24
Finished Jul 15 07:22:03 PM PDT 24
Peak memory 208732 kb
Host smart-a57c6501-a095-4777-8083-20a0ca90c481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947675636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.1947675636
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2774000455
Short name T341
Test name
Test status
Simulation time 151938318 ps
CPU time 4.6 seconds
Started Jul 15 07:21:14 PM PDT 24
Finished Jul 15 07:22:06 PM PDT 24
Peak memory 214368 kb
Host smart-46018c33-31ed-47e0-81ec-33dc6c7b9d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774000455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2774000455
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.687111653
Short name T289
Test name
Test status
Simulation time 47758206 ps
CPU time 3.05 seconds
Started Jul 15 07:21:16 PM PDT 24
Finished Jul 15 07:22:06 PM PDT 24
Peak memory 214568 kb
Host smart-283f71af-ec76-4127-b0d4-8a69e546b92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687111653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.687111653
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.1353938249
Short name T693
Test name
Test status
Simulation time 181733378 ps
CPU time 4.04 seconds
Started Jul 15 07:21:16 PM PDT 24
Finished Jul 15 07:22:06 PM PDT 24
Peak memory 222432 kb
Host smart-aeed67d2-ff4a-4086-8ea4-7cfc81da9af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353938249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.1353938249
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.2139242619
Short name T401
Test name
Test status
Simulation time 29392262 ps
CPU time 1.58 seconds
Started Jul 15 07:21:13 PM PDT 24
Finished Jul 15 07:22:03 PM PDT 24
Peak memory 206204 kb
Host smart-1569d2e5-f3f0-48a0-8abd-2bfb673f793a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139242619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.2139242619
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.2555955758
Short name T574
Test name
Test status
Simulation time 275500123 ps
CPU time 3.7 seconds
Started Jul 15 07:21:13 PM PDT 24
Finished Jul 15 07:22:05 PM PDT 24
Peak memory 208108 kb
Host smart-b8f07e5c-555b-4331-9205-9ba6039e1aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555955758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.2555955758
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.629786626
Short name T582
Test name
Test status
Simulation time 70765769 ps
CPU time 3.24 seconds
Started Jul 15 07:21:11 PM PDT 24
Finished Jul 15 07:22:02 PM PDT 24
Peak memory 208540 kb
Host smart-ab538fd6-fefb-4089-8f32-1ea1015f9985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629786626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.629786626
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.1419283218
Short name T413
Test name
Test status
Simulation time 91935098 ps
CPU time 1.78 seconds
Started Jul 15 07:21:12 PM PDT 24
Finished Jul 15 07:22:01 PM PDT 24
Peak memory 206956 kb
Host smart-fd6f73bc-102b-460a-87d1-9a456ae0d468
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419283218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.1419283218
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.2389750629
Short name T455
Test name
Test status
Simulation time 76483484 ps
CPU time 3.5 seconds
Started Jul 15 07:21:13 PM PDT 24
Finished Jul 15 07:22:03 PM PDT 24
Peak memory 208824 kb
Host smart-6fdacf27-1fe5-4915-8ff7-546e64d78b62
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389750629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.2389750629
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.593788669
Short name T469
Test name
Test status
Simulation time 169783027 ps
CPU time 3.1 seconds
Started Jul 15 07:21:12 PM PDT 24
Finished Jul 15 07:22:02 PM PDT 24
Peak memory 206820 kb
Host smart-2d7fd5e9-0cf8-4cfb-b8a3-a8f2ba89c352
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593788669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.593788669
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.1207150225
Short name T649
Test name
Test status
Simulation time 98563707 ps
CPU time 3.96 seconds
Started Jul 15 07:21:13 PM PDT 24
Finished Jul 15 07:22:03 PM PDT 24
Peak memory 210040 kb
Host smart-362767d8-3ae5-47f1-be19-09396bea3d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207150225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.1207150225
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.4016451884
Short name T561
Test name
Test status
Simulation time 114455928 ps
CPU time 3.85 seconds
Started Jul 15 07:21:11 PM PDT 24
Finished Jul 15 07:22:02 PM PDT 24
Peak memory 206128 kb
Host smart-fb34f3f0-f05c-42ac-8403-e37c7c0e1650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016451884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.4016451884
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.1954748701
Short name T614
Test name
Test status
Simulation time 3501384016 ps
CPU time 75.19 seconds
Started Jul 15 07:21:20 PM PDT 24
Finished Jul 15 07:23:25 PM PDT 24
Peak memory 217108 kb
Host smart-143377cc-f61d-454d-af28-cc0335da7e29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954748701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.1954748701
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.1870891602
Short name T845
Test name
Test status
Simulation time 351769876 ps
CPU time 14.29 seconds
Started Jul 15 07:21:13 PM PDT 24
Finished Jul 15 07:22:15 PM PDT 24
Peak memory 222676 kb
Host smart-d741de99-5966-441e-b54d-951fb2194cea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870891602 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.1870891602
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.1553108575
Short name T910
Test name
Test status
Simulation time 380101837 ps
CPU time 4.33 seconds
Started Jul 15 07:21:21 PM PDT 24
Finished Jul 15 07:22:14 PM PDT 24
Peak memory 209960 kb
Host smart-81a374d8-2b4b-47b6-be17-3510eed97948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553108575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1553108575
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.1877423945
Short name T51
Test name
Test status
Simulation time 88136305 ps
CPU time 2.32 seconds
Started Jul 15 07:21:16 PM PDT 24
Finished Jul 15 07:22:05 PM PDT 24
Peak memory 210164 kb
Host smart-bb736203-a091-4fbe-ac77-bcf176dd3a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877423945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.1877423945
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.396713794
Short name T762
Test name
Test status
Simulation time 16773575 ps
CPU time 0.79 seconds
Started Jul 15 07:21:19 PM PDT 24
Finished Jul 15 07:22:07 PM PDT 24
Peak memory 206040 kb
Host smart-c537aa94-cef7-44f9-9e8b-df75049cb5c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396713794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.396713794
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.1237980957
Short name T906
Test name
Test status
Simulation time 274305300 ps
CPU time 5.23 seconds
Started Jul 15 07:21:16 PM PDT 24
Finished Jul 15 07:22:08 PM PDT 24
Peak memory 209548 kb
Host smart-defb784a-fb28-4455-80e2-7d9c0547a3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237980957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1237980957
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.1532510646
Short name T765
Test name
Test status
Simulation time 39381443 ps
CPU time 2.43 seconds
Started Jul 15 07:21:17 PM PDT 24
Finished Jul 15 07:22:07 PM PDT 24
Peak memory 209928 kb
Host smart-6ed0ddf9-ffdd-4bd0-a2b3-8cc0ea683fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532510646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.1532510646
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.2485682774
Short name T703
Test name
Test status
Simulation time 221718659 ps
CPU time 4.58 seconds
Started Jul 15 07:21:16 PM PDT 24
Finished Jul 15 07:22:07 PM PDT 24
Peak memory 209224 kb
Host smart-5d626d24-fc14-4384-b16a-33777031dd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485682774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.2485682774
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.400646681
Short name T382
Test name
Test status
Simulation time 514563445 ps
CPU time 3.13 seconds
Started Jul 15 07:21:16 PM PDT 24
Finished Jul 15 07:22:06 PM PDT 24
Peak memory 212040 kb
Host smart-cd136d9a-9e84-410a-a4a2-7144ddf43cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400646681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.400646681
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.1432566121
Short name T597
Test name
Test status
Simulation time 93277638 ps
CPU time 4.45 seconds
Started Jul 15 07:21:17 PM PDT 24
Finished Jul 15 07:22:10 PM PDT 24
Peak memory 216104 kb
Host smart-8bea5060-d420-4c73-beea-8e31d1b14838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432566121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.1432566121
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.4120563210
Short name T715
Test name
Test status
Simulation time 348282980 ps
CPU time 4.92 seconds
Started Jul 15 07:21:15 PM PDT 24
Finished Jul 15 07:22:07 PM PDT 24
Peak memory 214304 kb
Host smart-3a3750b7-2693-41d9-87f6-8d45830d5b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120563210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.4120563210
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.1542511650
Short name T79
Test name
Test status
Simulation time 1636128113 ps
CPU time 11.24 seconds
Started Jul 15 07:21:21 PM PDT 24
Finished Jul 15 07:22:21 PM PDT 24
Peak memory 208288 kb
Host smart-cfdc97b2-086a-4695-acde-60781229df72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542511650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.1542511650
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.2612185374
Short name T702
Test name
Test status
Simulation time 1649912471 ps
CPU time 4.44 seconds
Started Jul 15 07:21:12 PM PDT 24
Finished Jul 15 07:22:03 PM PDT 24
Peak memory 208772 kb
Host smart-6be1fc66-4ac4-4be1-9cc3-762310c4fe6d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612185374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.2612185374
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.3573937811
Short name T264
Test name
Test status
Simulation time 54155369 ps
CPU time 2.8 seconds
Started Jul 15 07:21:15 PM PDT 24
Finished Jul 15 07:22:05 PM PDT 24
Peak memory 208076 kb
Host smart-ba12d0f6-05dd-4b96-9eed-6009cba90d33
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573937811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.3573937811
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.2870341624
Short name T656
Test name
Test status
Simulation time 190618686 ps
CPU time 5.65 seconds
Started Jul 15 07:21:16 PM PDT 24
Finished Jul 15 07:22:08 PM PDT 24
Peak memory 208676 kb
Host smart-34ca3d07-4074-41cc-9c69-8c872498af4c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870341624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.2870341624
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_smoke.1164578039
Short name T620
Test name
Test status
Simulation time 350865564 ps
CPU time 2.72 seconds
Started Jul 15 07:21:13 PM PDT 24
Finished Jul 15 07:22:04 PM PDT 24
Peak memory 208356 kb
Host smart-f3267c32-38be-40af-a237-178ece4a75e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164578039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.1164578039
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.3548484691
Short name T585
Test name
Test status
Simulation time 188440727 ps
CPU time 4.22 seconds
Started Jul 15 07:21:17 PM PDT 24
Finished Jul 15 07:22:09 PM PDT 24
Peak memory 214292 kb
Host smart-f4aee45e-6729-48f5-98b3-695b884f6e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548484691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.3548484691
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.2675609285
Short name T696
Test name
Test status
Simulation time 148294109 ps
CPU time 2 seconds
Started Jul 15 07:21:17 PM PDT 24
Finished Jul 15 07:22:07 PM PDT 24
Peak memory 210156 kb
Host smart-e74a584a-c7d2-4251-9bc5-acf6b7a2af3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675609285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.2675609285
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.1812470058
Short name T463
Test name
Test status
Simulation time 14573746 ps
CPU time 0.75 seconds
Started Jul 15 07:21:21 PM PDT 24
Finished Jul 15 07:22:11 PM PDT 24
Peak memory 206012 kb
Host smart-d853fb2a-004d-4dde-91f5-a42bd1bd57a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812470058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1812470058
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.888025220
Short name T878
Test name
Test status
Simulation time 346211386 ps
CPU time 3.69 seconds
Started Jul 15 07:21:18 PM PDT 24
Finished Jul 15 07:22:09 PM PDT 24
Peak memory 214344 kb
Host smart-907cb2f5-bff3-4491-82b9-3770bab37259
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=888025220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.888025220
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.2690116076
Short name T63
Test name
Test status
Simulation time 304739023 ps
CPU time 6.26 seconds
Started Jul 15 07:21:18 PM PDT 24
Finished Jul 15 07:22:12 PM PDT 24
Peak memory 214720 kb
Host smart-c8e67c76-5737-42f8-98d4-a1e4ae882233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690116076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.2690116076
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.3092468357
Short name T315
Test name
Test status
Simulation time 133482610 ps
CPU time 4.6 seconds
Started Jul 15 07:21:17 PM PDT 24
Finished Jul 15 07:22:09 PM PDT 24
Peak memory 218472 kb
Host smart-4f1b62e8-1486-4511-830e-c7696ec3b993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092468357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.3092468357
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.1978371856
Short name T90
Test name
Test status
Simulation time 611009543 ps
CPU time 7.7 seconds
Started Jul 15 07:21:22 PM PDT 24
Finished Jul 15 07:22:18 PM PDT 24
Peak memory 214424 kb
Host smart-c778ba9a-c6e0-42d3-95a5-64f8974119ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978371856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.1978371856
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.704582435
Short name T342
Test name
Test status
Simulation time 108439039 ps
CPU time 2.93 seconds
Started Jul 15 07:21:21 PM PDT 24
Finished Jul 15 07:22:13 PM PDT 24
Peak memory 221136 kb
Host smart-4325b36a-f9a7-4e50-b465-8d209422efe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704582435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.704582435
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.1682409735
Short name T215
Test name
Test status
Simulation time 48930079 ps
CPU time 2.37 seconds
Started Jul 15 07:21:21 PM PDT 24
Finished Jul 15 07:22:12 PM PDT 24
Peak memory 208528 kb
Host smart-067215f1-0b83-4705-a35e-709bd7c7573d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682409735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.1682409735
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.1526216929
Short name T651
Test name
Test status
Simulation time 314922118 ps
CPU time 3.36 seconds
Started Jul 15 07:21:17 PM PDT 24
Finished Jul 15 07:22:08 PM PDT 24
Peak memory 209028 kb
Host smart-31731147-34b3-4475-ae5f-3d7b371c6339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526216929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.1526216929
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1710829212
Short name T508
Test name
Test status
Simulation time 67835027 ps
CPU time 3.18 seconds
Started Jul 15 07:21:19 PM PDT 24
Finished Jul 15 07:22:09 PM PDT 24
Peak memory 206896 kb
Host smart-9440c100-750d-4cf0-91da-2108b059e293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710829212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1710829212
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2908684635
Short name T717
Test name
Test status
Simulation time 728529766 ps
CPU time 3.74 seconds
Started Jul 15 07:21:16 PM PDT 24
Finished Jul 15 07:22:06 PM PDT 24
Peak memory 209240 kb
Host smart-29b77694-5478-46f0-bb2e-d1587c55d3cd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908684635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2908684635
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.3570922402
Short name T553
Test name
Test status
Simulation time 708064946 ps
CPU time 16.69 seconds
Started Jul 15 07:21:19 PM PDT 24
Finished Jul 15 07:22:23 PM PDT 24
Peak memory 208968 kb
Host smart-24ad0e92-0fdb-4e7b-8bff-1b467ba0de84
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570922402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.3570922402
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.3749288224
Short name T834
Test name
Test status
Simulation time 415192181 ps
CPU time 4.49 seconds
Started Jul 15 07:21:20 PM PDT 24
Finished Jul 15 07:22:15 PM PDT 24
Peak memory 209056 kb
Host smart-feed8d17-68b3-4fa0-a70a-e6d29ce45cfc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749288224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3749288224
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.4063475808
Short name T355
Test name
Test status
Simulation time 375416982 ps
CPU time 4.23 seconds
Started Jul 15 07:21:20 PM PDT 24
Finished Jul 15 07:22:13 PM PDT 24
Peak memory 208932 kb
Host smart-d415d9b3-b74f-4e9c-8d9e-e3e757da88d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063475808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.4063475808
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.1315593957
Short name T106
Test name
Test status
Simulation time 646632321 ps
CPU time 6.73 seconds
Started Jul 15 07:21:20 PM PDT 24
Finished Jul 15 07:22:16 PM PDT 24
Peak memory 206972 kb
Host smart-6f8d4d60-cca0-4f1a-9919-3e018a59bf83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315593957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.1315593957
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.477779692
Short name T499
Test name
Test status
Simulation time 1278557495 ps
CPU time 21.19 seconds
Started Jul 15 07:21:20 PM PDT 24
Finished Jul 15 07:22:32 PM PDT 24
Peak memory 220956 kb
Host smart-7b227aa8-e329-443d-8ecb-8ec08d54562c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477779692 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.477779692
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.632594180
Short name T251
Test name
Test status
Simulation time 292331400 ps
CPU time 5.83 seconds
Started Jul 15 07:21:21 PM PDT 24
Finished Jul 15 07:22:16 PM PDT 24
Peak memory 210348 kb
Host smart-fcfad952-c4bf-4ed8-b6af-c769a530bf43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632594180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.632594180
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2352541198
Short name T388
Test name
Test status
Simulation time 87614158 ps
CPU time 3.01 seconds
Started Jul 15 07:21:15 PM PDT 24
Finished Jul 15 07:22:05 PM PDT 24
Peak memory 210352 kb
Host smart-c409d408-773a-4fd2-9d6e-061f8ad3d4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352541198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2352541198
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.2234710797
Short name T603
Test name
Test status
Simulation time 10760458 ps
CPU time 0.83 seconds
Started Jul 15 07:21:20 PM PDT 24
Finished Jul 15 07:22:10 PM PDT 24
Peak memory 205960 kb
Host smart-b380e38c-a624-4ecc-9e52-8e1266adfc45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234710797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.2234710797
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.888269555
Short name T131
Test name
Test status
Simulation time 23839121 ps
CPU time 2.12 seconds
Started Jul 15 07:21:18 PM PDT 24
Finished Jul 15 07:22:08 PM PDT 24
Peak memory 214360 kb
Host smart-c9ec53f7-4fb6-4436-9dba-46bf86a442ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=888269555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.888269555
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.2822895259
Short name T26
Test name
Test status
Simulation time 149117847 ps
CPU time 3.35 seconds
Started Jul 15 07:21:22 PM PDT 24
Finished Jul 15 07:22:14 PM PDT 24
Peak memory 214732 kb
Host smart-230a26ab-9f22-4aff-a995-87351b6461d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822895259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.2822895259
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.3493114405
Short name T487
Test name
Test status
Simulation time 1007483263 ps
CPU time 16.99 seconds
Started Jul 15 07:21:19 PM PDT 24
Finished Jul 15 07:22:23 PM PDT 24
Peak memory 209684 kb
Host smart-5636e3e6-3e2c-4fad-b25d-e5e3daee5831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493114405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3493114405
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.1055312318
Short name T570
Test name
Test status
Simulation time 688320825 ps
CPU time 6.55 seconds
Started Jul 15 07:21:19 PM PDT 24
Finished Jul 15 07:22:13 PM PDT 24
Peak memory 209052 kb
Host smart-059b41c9-d6a3-49c4-a7ae-033c76a41eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055312318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1055312318
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.574502870
Short name T323
Test name
Test status
Simulation time 233908580 ps
CPU time 2.69 seconds
Started Jul 15 07:21:19 PM PDT 24
Finished Jul 15 07:22:09 PM PDT 24
Peak memory 214280 kb
Host smart-af2a5156-a868-48f0-984c-2f142fb1b176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574502870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.574502870
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.3631509698
Short name T397
Test name
Test status
Simulation time 444063015 ps
CPU time 4.67 seconds
Started Jul 15 07:21:18 PM PDT 24
Finished Jul 15 07:22:10 PM PDT 24
Peak memory 219684 kb
Host smart-b21f2af3-c60c-4bce-9744-9e2b92ddfafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631509698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.3631509698
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.1349731782
Short name T852
Test name
Test status
Simulation time 139105394 ps
CPU time 2.68 seconds
Started Jul 15 07:21:17 PM PDT 24
Finished Jul 15 07:22:07 PM PDT 24
Peak memory 208168 kb
Host smart-97133471-01db-4606-8010-7a8107f32932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349731782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.1349731782
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.11704363
Short name T348
Test name
Test status
Simulation time 1204746175 ps
CPU time 9.41 seconds
Started Jul 15 07:21:18 PM PDT 24
Finished Jul 15 07:22:15 PM PDT 24
Peak memory 208700 kb
Host smart-a1084aa7-b4ff-4d6f-a5ce-d07ba548874b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11704363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.11704363
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.1676087499
Short name T716
Test name
Test status
Simulation time 1385508527 ps
CPU time 30.46 seconds
Started Jul 15 07:21:19 PM PDT 24
Finished Jul 15 07:22:39 PM PDT 24
Peak memory 207872 kb
Host smart-0cf8b63f-6825-401a-9407-b607d63e41ac
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676087499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.1676087499
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.3322095119
Short name T292
Test name
Test status
Simulation time 1100300709 ps
CPU time 26.38 seconds
Started Jul 15 07:21:20 PM PDT 24
Finished Jul 15 07:22:36 PM PDT 24
Peak memory 208840 kb
Host smart-1713b843-e236-4230-bd32-132df324eebc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322095119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.3322095119
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.362360017
Short name T683
Test name
Test status
Simulation time 100964215 ps
CPU time 2.97 seconds
Started Jul 15 07:21:19 PM PDT 24
Finished Jul 15 07:22:11 PM PDT 24
Peak memory 206864 kb
Host smart-49c47f62-79ba-4f42-851e-033e9c573f9c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362360017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.362360017
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.3750392232
Short name T424
Test name
Test status
Simulation time 121123581 ps
CPU time 2.61 seconds
Started Jul 15 07:21:18 PM PDT 24
Finished Jul 15 07:22:08 PM PDT 24
Peak memory 209360 kb
Host smart-309f4cc7-7c5c-4497-a39a-29b6f9c9cdb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750392232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3750392232
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.14562755
Short name T837
Test name
Test status
Simulation time 181586861 ps
CPU time 3.94 seconds
Started Jul 15 07:21:22 PM PDT 24
Finished Jul 15 07:22:15 PM PDT 24
Peak memory 207760 kb
Host smart-858602ab-4a65-436c-b344-5dd89c4c4e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14562755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.14562755
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.946431305
Short name T216
Test name
Test status
Simulation time 3821738390 ps
CPU time 51.57 seconds
Started Jul 15 07:21:18 PM PDT 24
Finished Jul 15 07:22:57 PM PDT 24
Peak memory 216560 kb
Host smart-361e8260-9afd-4136-a0a4-9d731625f001
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946431305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.946431305
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.3967710002
Short name T187
Test name
Test status
Simulation time 1910849153 ps
CPU time 11.3 seconds
Started Jul 15 07:21:18 PM PDT 24
Finished Jul 15 07:22:17 PM PDT 24
Peak memory 222612 kb
Host smart-ff3d32c3-8755-4a76-b9c4-6970515ae09e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967710002 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.3967710002
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.3449844794
Short name T334
Test name
Test status
Simulation time 1583415761 ps
CPU time 10.06 seconds
Started Jul 15 07:21:20 PM PDT 24
Finished Jul 15 07:22:19 PM PDT 24
Peak memory 209772 kb
Host smart-ad46f4dd-7b9a-4e4f-a40d-9f6d0b0e38ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449844794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.3449844794
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.1309699201
Short name T506
Test name
Test status
Simulation time 53106774 ps
CPU time 2.09 seconds
Started Jul 15 07:21:20 PM PDT 24
Finished Jul 15 07:22:12 PM PDT 24
Peak memory 210008 kb
Host smart-35599dd1-e113-4c85-8a3b-69d0c06f16be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309699201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.1309699201
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.2154113724
Short name T892
Test name
Test status
Simulation time 103497700 ps
CPU time 0.83 seconds
Started Jul 15 07:21:25 PM PDT 24
Finished Jul 15 07:22:17 PM PDT 24
Peak memory 205980 kb
Host smart-b852e174-a1dd-4d8c-b5a6-e61a38b87ebc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154113724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.2154113724
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.152942138
Short name T218
Test name
Test status
Simulation time 66079713 ps
CPU time 2.32 seconds
Started Jul 15 07:21:23 PM PDT 24
Finished Jul 15 07:22:13 PM PDT 24
Peak memory 215792 kb
Host smart-39238876-516c-4ddb-977c-07b4348a71cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152942138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.152942138
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.388407203
Short name T804
Test name
Test status
Simulation time 239646662 ps
CPU time 4.98 seconds
Started Jul 15 07:21:24 PM PDT 24
Finished Jul 15 07:22:20 PM PDT 24
Peak memory 218172 kb
Host smart-0dbf1e45-e00a-468c-af81-f6a04871a3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388407203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.388407203
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.780294141
Short name T541
Test name
Test status
Simulation time 147854473 ps
CPU time 3.38 seconds
Started Jul 15 07:21:22 PM PDT 24
Finished Jul 15 07:22:14 PM PDT 24
Peak memory 214416 kb
Host smart-1009a666-7717-4459-a9a9-5dee333af51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780294141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.780294141
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.2318485639
Short name T495
Test name
Test status
Simulation time 359160545 ps
CPU time 3.52 seconds
Started Jul 15 07:21:21 PM PDT 24
Finished Jul 15 07:22:14 PM PDT 24
Peak memory 222348 kb
Host smart-57020c9e-135a-482e-8c30-0ea26f25b20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318485639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.2318485639
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.1658603542
Short name T411
Test name
Test status
Simulation time 234634422 ps
CPU time 3.08 seconds
Started Jul 15 07:21:25 PM PDT 24
Finished Jul 15 07:22:19 PM PDT 24
Peak memory 209088 kb
Host smart-4322f755-4b1c-4b4d-bfd5-725a5f8b4b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658603542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.1658603542
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.2413803802
Short name T539
Test name
Test status
Simulation time 609593315 ps
CPU time 18.33 seconds
Started Jul 15 07:21:23 PM PDT 24
Finished Jul 15 07:22:29 PM PDT 24
Peak memory 209760 kb
Host smart-dec7e95a-f5e6-448e-b166-f4e97488f74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413803802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.2413803802
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.1862472419
Short name T863
Test name
Test status
Simulation time 920626286 ps
CPU time 7.34 seconds
Started Jul 15 07:21:22 PM PDT 24
Finished Jul 15 07:22:18 PM PDT 24
Peak memory 208532 kb
Host smart-066bb01c-87bb-4bc2-9f22-dc96a56fab3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862472419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.1862472419
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.2057347250
Short name T478
Test name
Test status
Simulation time 180853118 ps
CPU time 4.37 seconds
Started Jul 15 07:21:29 PM PDT 24
Finished Jul 15 07:22:25 PM PDT 24
Peak memory 208080 kb
Host smart-409559d1-d9d2-47ed-a2e0-e949f9bf32f7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057347250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.2057347250
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.376102485
Short name T676
Test name
Test status
Simulation time 32843541 ps
CPU time 2.21 seconds
Started Jul 15 07:21:20 PM PDT 24
Finished Jul 15 07:22:12 PM PDT 24
Peak memory 207028 kb
Host smart-f1373741-4319-4020-b715-dc3e6c90b510
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376102485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.376102485
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.3771553403
Short name T380
Test name
Test status
Simulation time 213805148 ps
CPU time 3.26 seconds
Started Jul 15 07:21:22 PM PDT 24
Finished Jul 15 07:22:14 PM PDT 24
Peak memory 208920 kb
Host smart-2c147907-3112-4a5e-af83-739f345ea619
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771553403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.3771553403
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.3734244073
Short name T823
Test name
Test status
Simulation time 210080032 ps
CPU time 4.58 seconds
Started Jul 15 07:21:25 PM PDT 24
Finished Jul 15 07:22:21 PM PDT 24
Peak memory 208516 kb
Host smart-2fc511a6-253f-4635-bc65-263d8d50f26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734244073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.3734244073
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.4187687719
Short name T844
Test name
Test status
Simulation time 79116538 ps
CPU time 2.23 seconds
Started Jul 15 07:21:18 PM PDT 24
Finished Jul 15 07:22:08 PM PDT 24
Peak memory 206976 kb
Host smart-3c7ded35-7229-417f-aa4a-53a63bbf5f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187687719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.4187687719
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.3658870018
Short name T492
Test name
Test status
Simulation time 165667907 ps
CPU time 6.97 seconds
Started Jul 15 07:21:25 PM PDT 24
Finished Jul 15 07:22:23 PM PDT 24
Peak memory 218256 kb
Host smart-79061dce-0637-4049-a630-ee0532d39a02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658870018 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.3658870018
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.3329281549
Short name T577
Test name
Test status
Simulation time 446580983 ps
CPU time 5.44 seconds
Started Jul 15 07:21:25 PM PDT 24
Finished Jul 15 07:22:22 PM PDT 24
Peak memory 219696 kb
Host smart-d26d41c1-5c78-4944-98bf-18260379b97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329281549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3329281549
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.2926316852
Short name T198
Test name
Test status
Simulation time 44121820 ps
CPU time 2.16 seconds
Started Jul 15 07:21:26 PM PDT 24
Finished Jul 15 07:22:19 PM PDT 24
Peak memory 210072 kb
Host smart-a4a430f9-b91d-4dbf-94d9-fc3afebbca9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926316852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.2926316852
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.1238736257
Short name T101
Test name
Test status
Simulation time 19020306 ps
CPU time 0.83 seconds
Started Jul 15 07:21:26 PM PDT 24
Finished Jul 15 07:22:17 PM PDT 24
Peak memory 206016 kb
Host smart-8d65e81b-e834-42fd-95a8-5cc938418faa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238736257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1238736257
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.2502332976
Short name T265
Test name
Test status
Simulation time 145925820 ps
CPU time 7.66 seconds
Started Jul 15 07:21:27 PM PDT 24
Finished Jul 15 07:22:27 PM PDT 24
Peak memory 215060 kb
Host smart-da06d2c4-e728-41bc-800d-e52a0b2c09a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2502332976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.2502332976
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.2984459017
Short name T213
Test name
Test status
Simulation time 145533668 ps
CPU time 2.39 seconds
Started Jul 15 07:21:27 PM PDT 24
Finished Jul 15 07:22:22 PM PDT 24
Peak memory 210192 kb
Host smart-5d59c243-d9b0-4b62-862e-82fcc1fdfe52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984459017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.2984459017
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.374357282
Short name T773
Test name
Test status
Simulation time 83162509 ps
CPU time 2.89 seconds
Started Jul 15 07:21:26 PM PDT 24
Finished Jul 15 07:22:19 PM PDT 24
Peak memory 207932 kb
Host smart-535a7844-445e-4276-8951-a4303b61b0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374357282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.374357282
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.1640559822
Short name T752
Test name
Test status
Simulation time 1061862048 ps
CPU time 2.71 seconds
Started Jul 15 07:21:25 PM PDT 24
Finished Jul 15 07:22:19 PM PDT 24
Peak memory 214384 kb
Host smart-88b7d4b7-b546-4fce-b200-cdac699a187c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640559822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.1640559822
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.263707996
Short name T862
Test name
Test status
Simulation time 98142697 ps
CPU time 3.64 seconds
Started Jul 15 07:21:25 PM PDT 24
Finished Jul 15 07:22:20 PM PDT 24
Peak memory 222448 kb
Host smart-e6aa61ea-2dee-477e-9633-b5e0dcb63e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263707996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.263707996
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.1911178833
Short name T5
Test name
Test status
Simulation time 173224635 ps
CPU time 2.77 seconds
Started Jul 15 07:21:22 PM PDT 24
Finished Jul 15 07:22:14 PM PDT 24
Peak memory 220140 kb
Host smart-ee228c8f-2025-49a8-ad4c-71e0a729d090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911178833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.1911178833
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.4250983724
Short name T772
Test name
Test status
Simulation time 193228996 ps
CPU time 3.05 seconds
Started Jul 15 07:21:25 PM PDT 24
Finished Jul 15 07:22:19 PM PDT 24
Peak memory 207928 kb
Host smart-873fd537-90b4-4189-8956-55d2be876bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250983724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.4250983724
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.3881997444
Short name T576
Test name
Test status
Simulation time 196661082 ps
CPU time 2.93 seconds
Started Jul 15 07:21:27 PM PDT 24
Finished Jul 15 07:22:22 PM PDT 24
Peak memory 207468 kb
Host smart-3dc59f1c-b4bf-45ad-bc47-ef62d7062508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881997444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.3881997444
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.1483084346
Short name T515
Test name
Test status
Simulation time 643865572 ps
CPU time 22.02 seconds
Started Jul 15 07:21:24 PM PDT 24
Finished Jul 15 07:22:38 PM PDT 24
Peak memory 207392 kb
Host smart-e5da752f-db37-47ca-a9e6-97059d18b994
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483084346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.1483084346
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.4258269759
Short name T557
Test name
Test status
Simulation time 74259651 ps
CPU time 2.81 seconds
Started Jul 15 07:21:26 PM PDT 24
Finished Jul 15 07:22:19 PM PDT 24
Peak memory 208920 kb
Host smart-e4ddaa05-8094-4ca3-b563-0de0b24c4840
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258269759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.4258269759
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.1939628687
Short name T237
Test name
Test status
Simulation time 149974659 ps
CPU time 5.68 seconds
Started Jul 15 07:21:27 PM PDT 24
Finished Jul 15 07:22:26 PM PDT 24
Peak memory 208968 kb
Host smart-7e9e3729-3910-4aee-bfea-2d0b16ac9a7d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939628687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1939628687
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.3718385024
Short name T529
Test name
Test status
Simulation time 81073715 ps
CPU time 3.38 seconds
Started Jul 15 07:21:25 PM PDT 24
Finished Jul 15 07:22:20 PM PDT 24
Peak memory 208700 kb
Host smart-c3a1ff9e-997b-4b18-bcc7-4b34d606e1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718385024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.3718385024
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.2244590604
Short name T743
Test name
Test status
Simulation time 71142365 ps
CPU time 1.77 seconds
Started Jul 15 07:21:24 PM PDT 24
Finished Jul 15 07:22:17 PM PDT 24
Peak memory 207444 kb
Host smart-d888f534-94fc-4a7a-b787-12d3292aeea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244590604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.2244590604
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.991329164
Short name T379
Test name
Test status
Simulation time 1186942414 ps
CPU time 31.25 seconds
Started Jul 15 07:21:27 PM PDT 24
Finished Jul 15 07:22:50 PM PDT 24
Peak memory 221176 kb
Host smart-7a9beacc-12e7-4dd4-9702-77b6558b86de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991329164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.991329164
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.3093792981
Short name T112
Test name
Test status
Simulation time 232569372 ps
CPU time 9.36 seconds
Started Jul 15 07:21:26 PM PDT 24
Finished Jul 15 07:22:26 PM PDT 24
Peak memory 219176 kb
Host smart-8129f757-4fd5-43a3-bde9-4708d5e303b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093792981 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.3093792981
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.2131793531
Short name T339
Test name
Test status
Simulation time 49636382 ps
CPU time 2.9 seconds
Started Jul 15 07:21:23 PM PDT 24
Finished Jul 15 07:22:14 PM PDT 24
Peak memory 209864 kb
Host smart-358f8853-d005-4583-959a-10d90577ddad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131793531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2131793531
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.2234932077
Short name T796
Test name
Test status
Simulation time 30578082 ps
CPU time 1.86 seconds
Started Jul 15 07:21:23 PM PDT 24
Finished Jul 15 07:22:13 PM PDT 24
Peak memory 210172 kb
Host smart-d5a691ed-aa02-4868-9124-53ce7a887f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234932077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.2234932077
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.3268214510
Short name T436
Test name
Test status
Simulation time 14235463 ps
CPU time 0.95 seconds
Started Jul 15 07:19:22 PM PDT 24
Finished Jul 15 07:20:24 PM PDT 24
Peak memory 206012 kb
Host smart-ce36db24-06ff-4e58-8fe1-e8615c5ea052
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268214510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.3268214510
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.2843675514
Short name T416
Test name
Test status
Simulation time 53419763 ps
CPU time 3.78 seconds
Started Jul 15 07:19:24 PM PDT 24
Finished Jul 15 07:20:29 PM PDT 24
Peak memory 214012 kb
Host smart-77ed7710-863c-4bf3-9d56-43466e02dfba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2843675514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.2843675514
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.1888446169
Short name T642
Test name
Test status
Simulation time 244338263 ps
CPU time 2.61 seconds
Started Jul 15 07:19:19 PM PDT 24
Finished Jul 15 07:20:26 PM PDT 24
Peak memory 208300 kb
Host smart-914643e9-f4e9-48d3-84a6-ff5e6cc7176e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888446169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.1888446169
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.2622264351
Short name T96
Test name
Test status
Simulation time 503789089 ps
CPU time 3.64 seconds
Started Jul 15 07:19:21 PM PDT 24
Finished Jul 15 07:20:26 PM PDT 24
Peak memory 221152 kb
Host smart-697aff06-04a6-4773-8f86-c22b307fb6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622264351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.2622264351
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.147025517
Short name T274
Test name
Test status
Simulation time 103715339 ps
CPU time 4.92 seconds
Started Jul 15 07:19:18 PM PDT 24
Finished Jul 15 07:20:28 PM PDT 24
Peak memory 214236 kb
Host smart-db41ceeb-3a9f-475b-9933-584d9b64c99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147025517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.147025517
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.4000555825
Short name T308
Test name
Test status
Simulation time 240487036 ps
CPU time 3.36 seconds
Started Jul 15 07:19:21 PM PDT 24
Finished Jul 15 07:20:26 PM PDT 24
Peak memory 207256 kb
Host smart-1b6d7615-9456-4a3e-bd28-9c8f183ea15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000555825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.4000555825
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.1813039443
Short name T108
Test name
Test status
Simulation time 1042356295 ps
CPU time 5.91 seconds
Started Jul 15 07:19:24 PM PDT 24
Finished Jul 15 07:20:31 PM PDT 24
Peak memory 210420 kb
Host smart-c7dcb380-fcea-4495-83b6-390501bb45fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813039443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.1813039443
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.2893139265
Short name T39
Test name
Test status
Simulation time 1466427220 ps
CPU time 12.19 seconds
Started Jul 15 07:19:19 PM PDT 24
Finished Jul 15 07:20:36 PM PDT 24
Peak memory 229516 kb
Host smart-b2c481e7-d2ac-4bbe-a5a4-623e96e6324a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893139265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.2893139265
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.614080694
Short name T331
Test name
Test status
Simulation time 418662642 ps
CPU time 3.32 seconds
Started Jul 15 07:19:21 PM PDT 24
Finished Jul 15 07:20:26 PM PDT 24
Peak memory 208540 kb
Host smart-61f6d339-4186-4308-8bb2-acbcd3ac59e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614080694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.614080694
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.142255532
Short name T450
Test name
Test status
Simulation time 154040985 ps
CPU time 3.67 seconds
Started Jul 15 07:19:20 PM PDT 24
Finished Jul 15 07:20:26 PM PDT 24
Peak memory 208784 kb
Host smart-df8535d4-857f-491a-9597-e98ad4359c64
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142255532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.142255532
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.4076308816
Short name T304
Test name
Test status
Simulation time 481825167 ps
CPU time 10.21 seconds
Started Jul 15 07:19:19 PM PDT 24
Finished Jul 15 07:20:34 PM PDT 24
Peak memory 208660 kb
Host smart-56124302-6a8f-41d7-8737-e4048f09237e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076308816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.4076308816
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.2417047457
Short name T548
Test name
Test status
Simulation time 79416480 ps
CPU time 3.76 seconds
Started Jul 15 07:19:24 PM PDT 24
Finished Jul 15 07:20:29 PM PDT 24
Peak memory 208808 kb
Host smart-3a2ffa5b-54a7-4f44-9a78-a580e4a48159
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417047457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.2417047457
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.334456796
Short name T454
Test name
Test status
Simulation time 99574269 ps
CPU time 2.99 seconds
Started Jul 15 07:19:24 PM PDT 24
Finished Jul 15 07:20:28 PM PDT 24
Peak memory 208948 kb
Host smart-a7208ef1-6f74-44de-9778-9ec411330a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334456796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.334456796
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.2582930412
Short name T435
Test name
Test status
Simulation time 59906178 ps
CPU time 2.46 seconds
Started Jul 15 07:19:20 PM PDT 24
Finished Jul 15 07:20:25 PM PDT 24
Peak memory 208364 kb
Host smart-9f4e6adb-cc9f-491d-91e6-e3b7d05a0159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582930412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.2582930412
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.4151345001
Short name T822
Test name
Test status
Simulation time 477622171 ps
CPU time 10.33 seconds
Started Jul 15 07:19:28 PM PDT 24
Finished Jul 15 07:20:39 PM PDT 24
Peak memory 220132 kb
Host smart-082e8599-5224-41a6-812c-16faa61f7c0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151345001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.4151345001
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.514299877
Short name T185
Test name
Test status
Simulation time 526936924 ps
CPU time 19.41 seconds
Started Jul 15 07:19:18 PM PDT 24
Finished Jul 15 07:20:43 PM PDT 24
Peak memory 222568 kb
Host smart-e4ffb4cf-aa71-4e2e-a0f9-d4ae87bbf31d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514299877 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.514299877
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.3015062704
Short name T714
Test name
Test status
Simulation time 1894474090 ps
CPU time 38.12 seconds
Started Jul 15 07:19:22 PM PDT 24
Finished Jul 15 07:21:01 PM PDT 24
Peak memory 218116 kb
Host smart-20c443c9-b18e-4434-a7c6-de8ba55cc481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015062704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.3015062704
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.1041135599
Short name T166
Test name
Test status
Simulation time 553102363 ps
CPU time 3.23 seconds
Started Jul 15 07:19:28 PM PDT 24
Finished Jul 15 07:20:32 PM PDT 24
Peak memory 210068 kb
Host smart-eb361e6f-a166-42fe-9943-94be734ede0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041135599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1041135599
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.527402553
Short name T467
Test name
Test status
Simulation time 43623889 ps
CPU time 0.74 seconds
Started Jul 15 07:21:25 PM PDT 24
Finished Jul 15 07:22:17 PM PDT 24
Peak memory 205988 kb
Host smart-4f728d37-1590-4ef5-9266-c22e35e4429f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527402553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.527402553
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.732267814
Short name T428
Test name
Test status
Simulation time 89158298 ps
CPU time 5.28 seconds
Started Jul 15 07:21:23 PM PDT 24
Finished Jul 15 07:22:19 PM PDT 24
Peak memory 214292 kb
Host smart-805bbbe5-0386-42d3-b409-ee836b58970c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=732267814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.732267814
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.2076378538
Short name T641
Test name
Test status
Simulation time 80299455 ps
CPU time 3.64 seconds
Started Jul 15 07:21:23 PM PDT 24
Finished Jul 15 07:22:14 PM PDT 24
Peak memory 210076 kb
Host smart-c621452f-57a6-4314-89f9-288ec1798d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076378538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.2076378538
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.3279981084
Short name T669
Test name
Test status
Simulation time 192833479 ps
CPU time 2.34 seconds
Started Jul 15 07:21:25 PM PDT 24
Finished Jul 15 07:22:19 PM PDT 24
Peak memory 214328 kb
Host smart-3df5d241-0a1c-4384-97bf-ce9a818d0ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279981084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.3279981084
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.135417943
Short name T86
Test name
Test status
Simulation time 82682228 ps
CPU time 2.76 seconds
Started Jul 15 07:21:24 PM PDT 24
Finished Jul 15 07:22:18 PM PDT 24
Peak memory 214276 kb
Host smart-fa47d220-b388-467f-bb0f-a8f9c0142762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135417943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.135417943
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.2132026382
Short name T927
Test name
Test status
Simulation time 172102205 ps
CPU time 2.33 seconds
Started Jul 15 07:21:27 PM PDT 24
Finished Jul 15 07:22:19 PM PDT 24
Peak memory 206464 kb
Host smart-de7017c7-5002-4954-b199-51810642ecd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132026382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.2132026382
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.2291986203
Short name T373
Test name
Test status
Simulation time 380610474 ps
CPU time 5.65 seconds
Started Jul 15 07:21:22 PM PDT 24
Finished Jul 15 07:22:16 PM PDT 24
Peak memory 210240 kb
Host smart-921ea359-04c0-4430-adf2-08f9168e4607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291986203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.2291986203
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.2232071451
Short name T623
Test name
Test status
Simulation time 65284625 ps
CPU time 3.06 seconds
Started Jul 15 07:21:26 PM PDT 24
Finished Jul 15 07:22:20 PM PDT 24
Peak memory 208828 kb
Host smart-84f5b811-3bd0-4aba-89b9-fbbba1ad4e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232071451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.2232071451
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.3002693471
Short name T440
Test name
Test status
Simulation time 57634341 ps
CPU time 2.61 seconds
Started Jul 15 07:21:25 PM PDT 24
Finished Jul 15 07:22:19 PM PDT 24
Peak memory 207380 kb
Host smart-2b15903a-73c8-422e-b60c-03b37689b6fe
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002693471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3002693471
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.1525596651
Short name T705
Test name
Test status
Simulation time 90882937 ps
CPU time 2.69 seconds
Started Jul 15 07:21:23 PM PDT 24
Finished Jul 15 07:22:14 PM PDT 24
Peak memory 208424 kb
Host smart-744fa56e-7926-449d-b44e-a8a0ba032ccd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525596651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.1525596651
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.4113578249
Short name T701
Test name
Test status
Simulation time 618554638 ps
CPU time 7.32 seconds
Started Jul 15 07:21:26 PM PDT 24
Finished Jul 15 07:22:24 PM PDT 24
Peak memory 207028 kb
Host smart-382e644c-5336-4cab-a7d8-42cd52bd506c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113578249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.4113578249
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.3522997733
Short name T695
Test name
Test status
Simulation time 65154285 ps
CPU time 3.18 seconds
Started Jul 15 07:21:26 PM PDT 24
Finished Jul 15 07:22:20 PM PDT 24
Peak memory 208184 kb
Host smart-88cdbde5-1065-4219-b7be-cefb23904fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522997733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3522997733
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.2394659626
Short name T396
Test name
Test status
Simulation time 216033395 ps
CPU time 4.09 seconds
Started Jul 15 07:21:24 PM PDT 24
Finished Jul 15 07:22:20 PM PDT 24
Peak memory 206692 kb
Host smart-42423a26-98b4-4627-afaf-bfe35e6582b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394659626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.2394659626
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.2633000365
Short name T254
Test name
Test status
Simulation time 22877624789 ps
CPU time 60.76 seconds
Started Jul 15 07:21:25 PM PDT 24
Finished Jul 15 07:23:17 PM PDT 24
Peak memory 217272 kb
Host smart-1dd04185-9413-48e7-8075-ff1b755b3802
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633000365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2633000365
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.3040827664
Short name T887
Test name
Test status
Simulation time 576966037 ps
CPU time 6.95 seconds
Started Jul 15 07:21:26 PM PDT 24
Finished Jul 15 07:22:23 PM PDT 24
Peak memory 207500 kb
Host smart-681318bb-0aef-431a-b47e-b6202fa8b233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040827664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.3040827664
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.3134182840
Short name T918
Test name
Test status
Simulation time 224926555 ps
CPU time 1.86 seconds
Started Jul 15 07:21:26 PM PDT 24
Finished Jul 15 07:22:18 PM PDT 24
Peak memory 209984 kb
Host smart-484c626c-21e8-4279-a370-8ead9ff27fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134182840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3134182840
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.2129761454
Short name T643
Test name
Test status
Simulation time 17123427 ps
CPU time 0.71 seconds
Started Jul 15 07:21:31 PM PDT 24
Finished Jul 15 07:22:23 PM PDT 24
Peak memory 205996 kb
Host smart-a81e7fe5-9544-4545-91c4-c3dd48e31d4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129761454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.2129761454
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.1948376164
Short name T429
Test name
Test status
Simulation time 110333481 ps
CPU time 2.33 seconds
Started Jul 15 07:21:31 PM PDT 24
Finished Jul 15 07:22:24 PM PDT 24
Peak memory 214320 kb
Host smart-1e33dcb0-2b7e-4500-b35e-31b4960ae365
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1948376164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.1948376164
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.4015318122
Short name T66
Test name
Test status
Simulation time 204870515 ps
CPU time 4.17 seconds
Started Jul 15 07:21:31 PM PDT 24
Finished Jul 15 07:22:26 PM PDT 24
Peak memory 215272 kb
Host smart-cfcb824a-3834-476e-af40-0667e4878ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015318122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.4015318122
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.4018119923
Short name T795
Test name
Test status
Simulation time 29956971 ps
CPU time 1.83 seconds
Started Jul 15 07:21:31 PM PDT 24
Finished Jul 15 07:22:24 PM PDT 24
Peak memory 207468 kb
Host smart-80e5159f-dda6-4c9c-a664-b0dad39f70df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018119923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.4018119923
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.3966369528
Short name T275
Test name
Test status
Simulation time 68098160 ps
CPU time 2.43 seconds
Started Jul 15 07:21:30 PM PDT 24
Finished Jul 15 07:22:24 PM PDT 24
Peak memory 214280 kb
Host smart-a2a5554f-4eed-4c26-9e38-f1f9d9d21260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966369528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.3966369528
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.1194497891
Short name T479
Test name
Test status
Simulation time 743007121 ps
CPU time 7.06 seconds
Started Jul 15 07:21:31 PM PDT 24
Finished Jul 15 07:22:30 PM PDT 24
Peak memory 218408 kb
Host smart-7cf64b76-b17c-4663-992a-7e2a87352536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194497891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.1194497891
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.2247891846
Short name T622
Test name
Test status
Simulation time 690491381 ps
CPU time 5.79 seconds
Started Jul 15 07:21:33 PM PDT 24
Finished Jul 15 07:22:32 PM PDT 24
Peak memory 209572 kb
Host smart-c1a46ab7-2270-49b3-8970-c2a25b36fa45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247891846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.2247891846
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.3661449622
Short name T782
Test name
Test status
Simulation time 76422790 ps
CPU time 1.91 seconds
Started Jul 15 07:21:34 PM PDT 24
Finished Jul 15 07:22:28 PM PDT 24
Peak memory 206936 kb
Host smart-b4c981d3-b945-4398-a4a9-cbaf5538f9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661449622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.3661449622
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.2669856907
Short name T374
Test name
Test status
Simulation time 102610719 ps
CPU time 3.93 seconds
Started Jul 15 07:21:30 PM PDT 24
Finished Jul 15 07:22:25 PM PDT 24
Peak memory 208716 kb
Host smart-5f83c318-e213-4de0-ad1d-62f2b980da44
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669856907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.2669856907
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.3859672820
Short name T890
Test name
Test status
Simulation time 356943437 ps
CPU time 1.81 seconds
Started Jul 15 07:21:32 PM PDT 24
Finished Jul 15 07:22:25 PM PDT 24
Peak memory 207024 kb
Host smart-de02c193-0ca7-4a0e-b060-ca589925e8cd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859672820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.3859672820
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.1179425194
Short name T438
Test name
Test status
Simulation time 44634445 ps
CPU time 2.03 seconds
Started Jul 15 07:21:32 PM PDT 24
Finished Jul 15 07:22:25 PM PDT 24
Peak memory 208944 kb
Host smart-b7fa175d-aa15-463b-90da-3dc7be963903
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179425194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.1179425194
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.623613049
Short name T672
Test name
Test status
Simulation time 190897119 ps
CPU time 2.07 seconds
Started Jul 15 07:21:33 PM PDT 24
Finished Jul 15 07:22:28 PM PDT 24
Peak memory 214436 kb
Host smart-67dcfa05-db38-447a-a6c3-1c0c78acb278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623613049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.623613049
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.2249570862
Short name T745
Test name
Test status
Simulation time 100791025 ps
CPU time 3.01 seconds
Started Jul 15 07:21:33 PM PDT 24
Finished Jul 15 07:22:26 PM PDT 24
Peak memory 208388 kb
Host smart-dfdca6d4-1ad1-4f38-86f1-0ab5cacaa285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249570862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.2249570862
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.540837701
Short name T126
Test name
Test status
Simulation time 4987241850 ps
CPU time 19.48 seconds
Started Jul 15 07:21:30 PM PDT 24
Finished Jul 15 07:22:41 PM PDT 24
Peak memory 208844 kb
Host smart-8d2b8ef9-a6a9-4e7e-9e50-209452ea8a84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540837701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.540837701
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.1152754141
Short name T855
Test name
Test status
Simulation time 244772090 ps
CPU time 6.07 seconds
Started Jul 15 07:21:31 PM PDT 24
Finished Jul 15 07:22:28 PM PDT 24
Peak memory 218340 kb
Host smart-62e23470-606b-4604-a0e1-3df65ed2c90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152754141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.1152754141
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.2854490510
Short name T183
Test name
Test status
Simulation time 144764045 ps
CPU time 1.81 seconds
Started Jul 15 07:21:34 PM PDT 24
Finished Jul 15 07:22:28 PM PDT 24
Peak memory 210068 kb
Host smart-0c14077c-0498-4afa-b1b8-eb94c0f05de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854490510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.2854490510
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.142443453
Short name T621
Test name
Test status
Simulation time 11366901 ps
CPU time 0.79 seconds
Started Jul 15 07:21:37 PM PDT 24
Finished Jul 15 07:22:29 PM PDT 24
Peak memory 205956 kb
Host smart-d82a9f57-e49b-4c08-83d8-1a2ec7526c46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142443453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.142443453
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.634827191
Short name T415
Test name
Test status
Simulation time 183561962 ps
CPU time 3.57 seconds
Started Jul 15 07:21:32 PM PDT 24
Finished Jul 15 07:22:27 PM PDT 24
Peak memory 214352 kb
Host smart-6df1f390-0ee9-4992-8c3c-44e778aaa303
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=634827191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.634827191
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.4107896236
Short name T233
Test name
Test status
Simulation time 121056229 ps
CPU time 3.13 seconds
Started Jul 15 07:21:40 PM PDT 24
Finished Jul 15 07:22:35 PM PDT 24
Peak memory 210328 kb
Host smart-5bdff556-a138-4570-9ded-64d0fd24cd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107896236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.4107896236
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.689653916
Short name T295
Test name
Test status
Simulation time 156652825 ps
CPU time 3.1 seconds
Started Jul 15 07:21:33 PM PDT 24
Finished Jul 15 07:22:26 PM PDT 24
Peak memory 208116 kb
Host smart-8c58cc24-a13e-4ac1-a740-10293c316fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689653916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.689653916
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.50432263
Short name T912
Test name
Test status
Simulation time 1163246599 ps
CPU time 4.44 seconds
Started Jul 15 07:21:34 PM PDT 24
Finished Jul 15 07:22:30 PM PDT 24
Peak memory 210476 kb
Host smart-378bf38f-b29c-412f-9c28-1d4377a02668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50432263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.50432263
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.233787557
Short name T535
Test name
Test status
Simulation time 115008323 ps
CPU time 3.6 seconds
Started Jul 15 07:21:29 PM PDT 24
Finished Jul 15 07:22:24 PM PDT 24
Peak memory 208988 kb
Host smart-ce55b1e8-350d-4338-8bcc-b80a5931f6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233787557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.233787557
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.3150354418
Short name T654
Test name
Test status
Simulation time 132830292 ps
CPU time 2.52 seconds
Started Jul 15 07:21:33 PM PDT 24
Finished Jul 15 07:22:26 PM PDT 24
Peak memory 207352 kb
Host smart-8abf5268-93f6-496f-a04c-27065a762935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150354418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.3150354418
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.399401292
Short name T204
Test name
Test status
Simulation time 28447253 ps
CPU time 1.88 seconds
Started Jul 15 07:21:33 PM PDT 24
Finished Jul 15 07:22:25 PM PDT 24
Peak memory 208028 kb
Host smart-59563d0a-2c98-4c0e-9631-90ace0d83b6f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399401292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.399401292
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.1490789312
Short name T740
Test name
Test status
Simulation time 94969418 ps
CPU time 2.51 seconds
Started Jul 15 07:21:32 PM PDT 24
Finished Jul 15 07:22:25 PM PDT 24
Peak memory 208624 kb
Host smart-71a221fd-1904-4003-9059-ffb4df65bd49
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490789312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.1490789312
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.3691604349
Short name T711
Test name
Test status
Simulation time 797290855 ps
CPU time 11.12 seconds
Started Jul 15 07:21:33 PM PDT 24
Finished Jul 15 07:22:34 PM PDT 24
Peak memory 208112 kb
Host smart-b955faad-8f23-45a8-a2b7-1033b5824eb0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691604349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.3691604349
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.600422640
Short name T869
Test name
Test status
Simulation time 763491118 ps
CPU time 3.52 seconds
Started Jul 15 07:21:41 PM PDT 24
Finished Jul 15 07:22:37 PM PDT 24
Peak memory 215920 kb
Host smart-db2b5c13-7ec5-4406-bbee-c8f2140c0f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600422640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.600422640
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.1170956356
Short name T540
Test name
Test status
Simulation time 32721133 ps
CPU time 2.01 seconds
Started Jul 15 07:21:31 PM PDT 24
Finished Jul 15 07:22:24 PM PDT 24
Peak memory 206852 kb
Host smart-21cbd48e-9690-4ba2-84b6-c367d358a4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170956356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.1170956356
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.3603962437
Short name T217
Test name
Test status
Simulation time 18871306726 ps
CPU time 47.4 seconds
Started Jul 15 07:21:39 PM PDT 24
Finished Jul 15 07:23:20 PM PDT 24
Peak memory 216472 kb
Host smart-28d38cdf-4c21-4b61-830e-59f3de413043
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603962437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.3603962437
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.710992149
Short name T812
Test name
Test status
Simulation time 213952726 ps
CPU time 5.24 seconds
Started Jul 15 07:21:30 PM PDT 24
Finished Jul 15 07:22:27 PM PDT 24
Peak memory 208916 kb
Host smart-85b5634e-ca9b-434d-a77c-305a71eb6b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710992149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.710992149
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.1560687266
Short name T591
Test name
Test status
Simulation time 204462027 ps
CPU time 3.85 seconds
Started Jul 15 07:21:38 PM PDT 24
Finished Jul 15 07:22:36 PM PDT 24
Peak memory 210180 kb
Host smart-0fffadd3-faa6-41dd-a415-fcba8ef91bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560687266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.1560687266
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.83986595
Short name T673
Test name
Test status
Simulation time 14902830 ps
CPU time 0.76 seconds
Started Jul 15 07:21:43 PM PDT 24
Finished Jul 15 07:22:38 PM PDT 24
Peak memory 206020 kb
Host smart-0d8787ba-9538-4297-9982-1bf7dade2ada
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83986595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.83986595
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.4126735658
Short name T422
Test name
Test status
Simulation time 343236641 ps
CPU time 9.37 seconds
Started Jul 15 07:21:38 PM PDT 24
Finished Jul 15 07:22:38 PM PDT 24
Peak memory 214360 kb
Host smart-b2117bcc-69ef-45e5-9909-8c5726b37ec0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4126735658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.4126735658
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.2673998074
Short name T64
Test name
Test status
Simulation time 76623452 ps
CPU time 1.93 seconds
Started Jul 15 07:21:40 PM PDT 24
Finished Jul 15 07:22:34 PM PDT 24
Peak memory 208584 kb
Host smart-756f87a2-8808-4bbc-90b5-bc971333c1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673998074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.2673998074
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.639677004
Short name T679
Test name
Test status
Simulation time 76907277 ps
CPU time 2.66 seconds
Started Jul 15 07:21:37 PM PDT 24
Finished Jul 15 07:22:31 PM PDT 24
Peak memory 208764 kb
Host smart-1480f590-972f-4f83-a3dd-9bf3aa2f0dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639677004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.639677004
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.1138352345
Short name T502
Test name
Test status
Simulation time 348245018 ps
CPU time 4.01 seconds
Started Jul 15 07:21:39 PM PDT 24
Finished Jul 15 07:22:36 PM PDT 24
Peak memory 209524 kb
Host smart-13ef22a7-3a9b-46c0-8fc0-269eecf03e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138352345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.1138352345
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.2060919413
Short name T803
Test name
Test status
Simulation time 532690595 ps
CPU time 2.63 seconds
Started Jul 15 07:21:35 PM PDT 24
Finished Jul 15 07:22:29 PM PDT 24
Peak memory 206904 kb
Host smart-272f51db-e9c6-4cc7-8e6f-867183118cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060919413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.2060919413
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.1715137171
Short name T410
Test name
Test status
Simulation time 539339775 ps
CPU time 3.87 seconds
Started Jul 15 07:21:41 PM PDT 24
Finished Jul 15 07:22:37 PM PDT 24
Peak memory 209064 kb
Host smart-0c106b7d-7c50-447a-9292-098bd6c47f02
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715137171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.1715137171
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.3211235253
Short name T442
Test name
Test status
Simulation time 733039872 ps
CPU time 8.04 seconds
Started Jul 15 07:21:37 PM PDT 24
Finished Jul 15 07:22:36 PM PDT 24
Peak memory 208124 kb
Host smart-73922b75-20e2-4515-b5ba-f1dc44ba0c04
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211235253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.3211235253
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.3305345539
Short name T731
Test name
Test status
Simulation time 218511542 ps
CPU time 3.07 seconds
Started Jul 15 07:21:36 PM PDT 24
Finished Jul 15 07:22:31 PM PDT 24
Peak memory 207000 kb
Host smart-27c0bab1-7b2d-4142-ab7f-975010bdfbff
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305345539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.3305345539
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.1777379565
Short name T537
Test name
Test status
Simulation time 426368962 ps
CPU time 8.4 seconds
Started Jul 15 07:21:41 PM PDT 24
Finished Jul 15 07:22:42 PM PDT 24
Peak memory 208476 kb
Host smart-1e4dded8-a883-441d-8813-71ab51a40236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777379565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1777379565
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.2802725497
Short name T444
Test name
Test status
Simulation time 700991194 ps
CPU time 4.19 seconds
Started Jul 15 07:21:40 PM PDT 24
Finished Jul 15 07:22:37 PM PDT 24
Peak memory 207072 kb
Host smart-904ac9d2-b058-4aa7-97ef-3a65d70c3a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802725497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.2802725497
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.4206417256
Short name T360
Test name
Test status
Simulation time 488229386 ps
CPU time 7.23 seconds
Started Jul 15 07:21:42 PM PDT 24
Finished Jul 15 07:22:41 PM PDT 24
Peak memory 214352 kb
Host smart-246f5d7c-36e7-4a94-b8ca-70b150597c58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206417256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.4206417256
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.1285410725
Short name T223
Test name
Test status
Simulation time 798704343 ps
CPU time 5.92 seconds
Started Jul 15 07:21:44 PM PDT 24
Finished Jul 15 07:22:44 PM PDT 24
Peak memory 222696 kb
Host smart-9eead3a0-f8ed-402d-8d98-0a6dae56f781
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285410725 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.1285410725
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.4035696537
Short name T347
Test name
Test status
Simulation time 147964001 ps
CPU time 5.32 seconds
Started Jul 15 07:21:36 PM PDT 24
Finished Jul 15 07:22:33 PM PDT 24
Peak memory 214284 kb
Host smart-d28d65a0-59ce-4653-8029-a827990d2488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035696537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.4035696537
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.3252819234
Short name T385
Test name
Test status
Simulation time 169761495 ps
CPU time 2.6 seconds
Started Jul 15 07:21:44 PM PDT 24
Finished Jul 15 07:22:41 PM PDT 24
Peak memory 210440 kb
Host smart-a05b74d4-ddc1-4626-ae52-e2d8398f094b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252819234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.3252819234
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.429658609
Short name T737
Test name
Test status
Simulation time 8036501 ps
CPU time 0.84 seconds
Started Jul 15 07:21:57 PM PDT 24
Finished Jul 15 07:22:57 PM PDT 24
Peak memory 206008 kb
Host smart-f63e3e23-f40a-41f6-b261-fa08a0a0bd70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429658609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.429658609
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.230262419
Short name T28
Test name
Test status
Simulation time 140461079 ps
CPU time 3.23 seconds
Started Jul 15 07:21:49 PM PDT 24
Finished Jul 15 07:22:45 PM PDT 24
Peak memory 210024 kb
Host smart-0351824f-4449-4297-ae3c-6625dd79ef92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230262419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.230262419
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.2853154121
Short name T726
Test name
Test status
Simulation time 147977937 ps
CPU time 4.27 seconds
Started Jul 15 07:21:50 PM PDT 24
Finished Jul 15 07:22:49 PM PDT 24
Peak memory 214256 kb
Host smart-aef04d9c-7c5a-4445-a313-8fdb3889d729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853154121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.2853154121
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.896918769
Short name T549
Test name
Test status
Simulation time 102610569 ps
CPU time 4.16 seconds
Started Jul 15 07:21:49 PM PDT 24
Finished Jul 15 07:22:49 PM PDT 24
Peak memory 209696 kb
Host smart-a29ea455-5f0f-4296-936b-f4bf01b5602d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896918769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.896918769
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.704303042
Short name T245
Test name
Test status
Simulation time 463683648 ps
CPU time 3.31 seconds
Started Jul 15 07:21:51 PM PDT 24
Finished Jul 15 07:22:49 PM PDT 24
Peak memory 215196 kb
Host smart-fa7e91ad-357c-4c3d-87fb-935e880cbc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704303042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.704303042
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.1292984424
Short name T224
Test name
Test status
Simulation time 591137077 ps
CPU time 4.49 seconds
Started Jul 15 07:21:50 PM PDT 24
Finished Jul 15 07:22:50 PM PDT 24
Peak memory 222576 kb
Host smart-1697f7b9-26a3-4958-a986-20c3cc91a379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292984424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.1292984424
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.1446533815
Short name T763
Test name
Test status
Simulation time 1467209570 ps
CPU time 3.54 seconds
Started Jul 15 07:21:55 PM PDT 24
Finished Jul 15 07:22:59 PM PDT 24
Peak memory 208592 kb
Host smart-0864deb9-3ae3-462d-aced-e5f2b46811e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446533815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.1446533815
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.629914090
Short name T200
Test name
Test status
Simulation time 2147033588 ps
CPU time 5.72 seconds
Started Jul 15 07:21:42 PM PDT 24
Finished Jul 15 07:22:43 PM PDT 24
Peak memory 208484 kb
Host smart-8778578c-b80a-46ce-86b5-24816b9e080a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629914090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.629914090
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.274152946
Short name T509
Test name
Test status
Simulation time 312496051 ps
CPU time 2.98 seconds
Started Jul 15 07:21:54 PM PDT 24
Finished Jul 15 07:22:55 PM PDT 24
Peak memory 208740 kb
Host smart-95596a66-9c1d-4137-a9ed-afa846d60a37
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274152946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.274152946
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.843803361
Short name T872
Test name
Test status
Simulation time 42243701 ps
CPU time 1.85 seconds
Started Jul 15 07:21:43 PM PDT 24
Finished Jul 15 07:22:39 PM PDT 24
Peak memory 206908 kb
Host smart-cb6f183e-e123-46f0-af10-6ece52a715d7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843803361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.843803361
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.2460980334
Short name T710
Test name
Test status
Simulation time 563762424 ps
CPU time 3.94 seconds
Started Jul 15 07:21:54 PM PDT 24
Finished Jul 15 07:22:56 PM PDT 24
Peak memory 207968 kb
Host smart-c0787b10-dd29-471b-9d7a-bf2b955ff83e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460980334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2460980334
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.3374092084
Short name T692
Test name
Test status
Simulation time 39488294 ps
CPU time 2.28 seconds
Started Jul 15 07:21:50 PM PDT 24
Finished Jul 15 07:22:48 PM PDT 24
Peak memory 207556 kb
Host smart-c5eacf15-68af-400e-9a4f-264d83a4f695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374092084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.3374092084
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.2433088573
Short name T485
Test name
Test status
Simulation time 321334877 ps
CPU time 2 seconds
Started Jul 15 07:21:43 PM PDT 24
Finished Jul 15 07:22:40 PM PDT 24
Peak memory 208652 kb
Host smart-aa375df6-750b-432f-980e-96323067d84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433088573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.2433088573
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.2638754056
Short name T231
Test name
Test status
Simulation time 194056390 ps
CPU time 10.59 seconds
Started Jul 15 07:21:55 PM PDT 24
Finished Jul 15 07:23:06 PM PDT 24
Peak memory 216444 kb
Host smart-99f3a9ad-953c-4e31-ae79-4e4599d39c55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638754056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.2638754056
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3139621472
Short name T517
Test name
Test status
Simulation time 1025913344 ps
CPU time 5.36 seconds
Started Jul 15 07:21:50 PM PDT 24
Finished Jul 15 07:22:51 PM PDT 24
Peak memory 209120 kb
Host smart-217726d4-1817-4ffa-bc15-7f0e793091d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139621472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3139621472
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.989653254
Short name T538
Test name
Test status
Simulation time 125557315 ps
CPU time 2.48 seconds
Started Jul 15 07:21:50 PM PDT 24
Finished Jul 15 07:22:48 PM PDT 24
Peak memory 210596 kb
Host smart-5295e385-ead2-4eee-9c23-ac591d44d3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989653254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.989653254
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.2577709723
Short name T580
Test name
Test status
Simulation time 40285682 ps
CPU time 0.75 seconds
Started Jul 15 07:21:59 PM PDT 24
Finished Jul 15 07:22:57 PM PDT 24
Peak memory 205960 kb
Host smart-b75898e3-6331-4ed5-935c-c39bf68b92b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577709723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.2577709723
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.1212780937
Short name T418
Test name
Test status
Simulation time 58880014 ps
CPU time 4.32 seconds
Started Jul 15 07:21:56 PM PDT 24
Finished Jul 15 07:23:00 PM PDT 24
Peak memory 222484 kb
Host smart-80a878d7-6c84-401d-9b86-fc7b3a7e4817
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1212780937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.1212780937
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.2469891286
Short name T226
Test name
Test status
Simulation time 84004327 ps
CPU time 2.18 seconds
Started Jul 15 07:21:57 PM PDT 24
Finished Jul 15 07:22:58 PM PDT 24
Peak memory 214312 kb
Host smart-61f148dc-ed58-41f2-a1be-2180db20cfb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469891286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.2469891286
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.3190031499
Short name T655
Test name
Test status
Simulation time 34666729 ps
CPU time 2.01 seconds
Started Jul 15 07:21:58 PM PDT 24
Finished Jul 15 07:22:59 PM PDT 24
Peak memory 214416 kb
Host smart-2f5dbf72-fd6a-4964-8243-b969a84b7302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190031499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.3190031499
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1294236958
Short name T325
Test name
Test status
Simulation time 75141630 ps
CPU time 2.42 seconds
Started Jul 15 07:21:57 PM PDT 24
Finished Jul 15 07:22:58 PM PDT 24
Peak memory 214344 kb
Host smart-433ad5d7-6114-45ec-8ba4-74221154bfde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294236958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1294236958
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.2726088289
Short name T31
Test name
Test status
Simulation time 247697734 ps
CPU time 5.88 seconds
Started Jul 15 07:22:01 PM PDT 24
Finished Jul 15 07:23:06 PM PDT 24
Peak memory 220364 kb
Host smart-cdce857f-eb3e-44f5-a9ad-48dfcd75a010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726088289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2726088289
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.3234243857
Short name T110
Test name
Test status
Simulation time 3674515575 ps
CPU time 38.31 seconds
Started Jul 15 07:21:57 PM PDT 24
Finished Jul 15 07:23:34 PM PDT 24
Peak memory 209296 kb
Host smart-9c87cfd6-0630-45e0-a9d9-acbb2366e4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234243857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.3234243857
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.3568424969
Short name T790
Test name
Test status
Simulation time 207046092 ps
CPU time 2.62 seconds
Started Jul 15 07:21:57 PM PDT 24
Finished Jul 15 07:22:59 PM PDT 24
Peak memory 206948 kb
Host smart-5026697c-5491-450f-855d-6c268b89107f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568424969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.3568424969
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.3973814480
Short name T562
Test name
Test status
Simulation time 189586314 ps
CPU time 3.77 seconds
Started Jul 15 07:21:57 PM PDT 24
Finished Jul 15 07:23:00 PM PDT 24
Peak memory 206904 kb
Host smart-ae944097-1683-482b-a9eb-90cb37cd7438
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973814480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.3973814480
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.505018287
Short name T482
Test name
Test status
Simulation time 234107658 ps
CPU time 3.09 seconds
Started Jul 15 07:21:57 PM PDT 24
Finished Jul 15 07:22:59 PM PDT 24
Peak memory 206996 kb
Host smart-62cc1c46-99b3-423d-90bb-3dc664052829
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505018287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.505018287
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.2380067346
Short name T646
Test name
Test status
Simulation time 378231005 ps
CPU time 3.27 seconds
Started Jul 15 07:21:56 PM PDT 24
Finished Jul 15 07:22:59 PM PDT 24
Peak memory 206904 kb
Host smart-664929db-f258-4a4c-8bbd-269a3cb09872
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380067346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.2380067346
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.3566804734
Short name T447
Test name
Test status
Simulation time 33631679 ps
CPU time 2.28 seconds
Started Jul 15 07:21:57 PM PDT 24
Finished Jul 15 07:22:58 PM PDT 24
Peak memory 218316 kb
Host smart-23a78c3b-5334-4e9d-833a-df338506ebd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566804734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3566804734
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.180342749
Short name T915
Test name
Test status
Simulation time 258094017 ps
CPU time 2.61 seconds
Started Jul 15 07:21:55 PM PDT 24
Finished Jul 15 07:22:58 PM PDT 24
Peak memory 206692 kb
Host smart-b3083cd4-7331-4ac9-84ec-52a063de8135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180342749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.180342749
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.2152086373
Short name T219
Test name
Test status
Simulation time 7270318862 ps
CPU time 148.33 seconds
Started Jul 15 07:21:55 PM PDT 24
Finished Jul 15 07:25:23 PM PDT 24
Peak memory 222544 kb
Host smart-e61c5363-b9ab-4ca7-bd94-aad438acbcac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152086373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.2152086373
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.3949742003
Short name T167
Test name
Test status
Simulation time 281519854 ps
CPU time 10.16 seconds
Started Jul 15 07:21:57 PM PDT 24
Finished Jul 15 07:23:06 PM PDT 24
Peak memory 219728 kb
Host smart-3cbc671e-4073-4abe-aee9-86c296d9821e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949742003 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.3949742003
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.3750399296
Short name T829
Test name
Test status
Simulation time 633534716 ps
CPU time 2.87 seconds
Started Jul 15 07:21:56 PM PDT 24
Finished Jul 15 07:22:59 PM PDT 24
Peak memory 208204 kb
Host smart-fb2a58a6-2184-4e1b-ae6f-3f528d99f96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750399296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.3750399296
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.3871443387
Short name T593
Test name
Test status
Simulation time 125325705 ps
CPU time 1.85 seconds
Started Jul 15 07:22:00 PM PDT 24
Finished Jul 15 07:23:02 PM PDT 24
Peak memory 209768 kb
Host smart-f093b297-a4ba-4870-96fc-4c72022391f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871443387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.3871443387
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.1189549029
Short name T757
Test name
Test status
Simulation time 41612152 ps
CPU time 0.85 seconds
Started Jul 15 07:22:04 PM PDT 24
Finished Jul 15 07:23:07 PM PDT 24
Peak memory 205964 kb
Host smart-e2480693-7b25-45c9-b504-18c8aef79f16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189549029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.1189549029
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.1892238168
Short name T776
Test name
Test status
Simulation time 120584170 ps
CPU time 2.33 seconds
Started Jul 15 07:22:05 PM PDT 24
Finished Jul 15 07:23:09 PM PDT 24
Peak memory 215596 kb
Host smart-27f3c887-e8da-41ce-bca3-3416ebe18a32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1892238168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.1892238168
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.3518245390
Short name T220
Test name
Test status
Simulation time 186243208 ps
CPU time 2.69 seconds
Started Jul 15 07:22:05 PM PDT 24
Finished Jul 15 07:23:09 PM PDT 24
Peak memory 214432 kb
Host smart-a93af9fc-bcbd-4fbe-9450-b530476028fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518245390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.3518245390
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2920871321
Short name T55
Test name
Test status
Simulation time 65391952 ps
CPU time 2.82 seconds
Started Jul 15 07:22:03 PM PDT 24
Finished Jul 15 07:23:08 PM PDT 24
Peak memory 209616 kb
Host smart-48028f1d-a20a-4e6c-9f60-bcd976d9ed0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920871321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2920871321
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.1073332631
Short name T615
Test name
Test status
Simulation time 960169185 ps
CPU time 11.79 seconds
Started Jul 15 07:22:03 PM PDT 24
Finished Jul 15 07:23:14 PM PDT 24
Peak memory 214588 kb
Host smart-e6fa856b-5a10-4024-8321-2a4068437362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073332631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.1073332631
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.4176611749
Short name T809
Test name
Test status
Simulation time 43244658 ps
CPU time 2.66 seconds
Started Jul 15 07:22:04 PM PDT 24
Finished Jul 15 07:23:09 PM PDT 24
Peak memory 214348 kb
Host smart-4a8112d2-28ba-4681-8902-ee37336a7812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176611749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.4176611749
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.375308866
Short name T528
Test name
Test status
Simulation time 699649763 ps
CPU time 10.11 seconds
Started Jul 15 07:22:03 PM PDT 24
Finished Jul 15 07:23:16 PM PDT 24
Peak memory 209288 kb
Host smart-fe87c40b-80c9-44e8-a604-7ec882062258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375308866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.375308866
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.1358202692
Short name T472
Test name
Test status
Simulation time 5574271447 ps
CPU time 35.46 seconds
Started Jul 15 07:22:02 PM PDT 24
Finished Jul 15 07:23:37 PM PDT 24
Peak memory 208068 kb
Host smart-0bdcbfab-cb10-4d3b-a8e5-a85e6d8e52a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358202692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.1358202692
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.940980985
Short name T203
Test name
Test status
Simulation time 329744026 ps
CPU time 2.01 seconds
Started Jul 15 07:22:05 PM PDT 24
Finished Jul 15 07:23:08 PM PDT 24
Peak memory 208948 kb
Host smart-6c13ac1e-6f58-4f1b-bc74-e7bb52adc99d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940980985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.940980985
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.2335066690
Short name T835
Test name
Test status
Simulation time 55631197 ps
CPU time 2.88 seconds
Started Jul 15 07:22:06 PM PDT 24
Finished Jul 15 07:23:09 PM PDT 24
Peak memory 206968 kb
Host smart-1fbfb4ac-91c2-4ae4-a1e8-df0cd46fa6be
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335066690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.2335066690
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.2674330064
Short name T875
Test name
Test status
Simulation time 55090312 ps
CPU time 2.89 seconds
Started Jul 15 07:22:05 PM PDT 24
Finished Jul 15 07:23:09 PM PDT 24
Peak memory 207080 kb
Host smart-edade875-123b-4016-9916-649c9b1cfbdd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674330064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.2674330064
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.564621440
Short name T423
Test name
Test status
Simulation time 280005668 ps
CPU time 3.44 seconds
Started Jul 15 07:22:05 PM PDT 24
Finished Jul 15 07:23:10 PM PDT 24
Peak memory 209844 kb
Host smart-a5f6b940-b754-4e48-a276-b57c0babb821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564621440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.564621440
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.2384922727
Short name T897
Test name
Test status
Simulation time 163891461 ps
CPU time 4.6 seconds
Started Jul 15 07:22:03 PM PDT 24
Finished Jul 15 07:23:06 PM PDT 24
Peak memory 208088 kb
Host smart-b4ea801b-4b7d-47d8-83e8-5abc776d6ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384922727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.2384922727
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.2174166844
Short name T914
Test name
Test status
Simulation time 8907608610 ps
CPU time 28.02 seconds
Started Jul 15 07:22:04 PM PDT 24
Finished Jul 15 07:23:34 PM PDT 24
Peak memory 222472 kb
Host smart-17a50464-765b-4610-bae6-b1dcdc72ab8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174166844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.2174166844
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.2634314462
Short name T122
Test name
Test status
Simulation time 231286209 ps
CPU time 8.61 seconds
Started Jul 15 07:22:05 PM PDT 24
Finished Jul 15 07:23:15 PM PDT 24
Peak memory 222576 kb
Host smart-4e5085c1-a60c-44b4-86aa-12c9f7540d0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634314462 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.2634314462
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.2345962556
Short name T781
Test name
Test status
Simulation time 4685070212 ps
CPU time 36.31 seconds
Started Jul 15 07:22:03 PM PDT 24
Finished Jul 15 07:23:42 PM PDT 24
Peak memory 218324 kb
Host smart-af546ac8-dbd2-48c6-98a8-9deaf4c74b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345962556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.2345962556
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.1805599355
Short name T170
Test name
Test status
Simulation time 121306492 ps
CPU time 2.65 seconds
Started Jul 15 07:22:03 PM PDT 24
Finished Jul 15 07:23:04 PM PDT 24
Peak memory 209952 kb
Host smart-bfa26b6c-efe0-4028-ac64-4b1dc2825511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805599355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.1805599355
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.1304986143
Short name T477
Test name
Test status
Simulation time 14321100 ps
CPU time 0.9 seconds
Started Jul 15 07:22:13 PM PDT 24
Finished Jul 15 07:23:18 PM PDT 24
Peak memory 205908 kb
Host smart-48f12c17-beee-424f-9041-67d131c7eeaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304986143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.1304986143
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.1757774284
Short name T238
Test name
Test status
Simulation time 459757773 ps
CPU time 3.9 seconds
Started Jul 15 07:22:06 PM PDT 24
Finished Jul 15 07:23:10 PM PDT 24
Peak memory 214308 kb
Host smart-6a198214-a3aa-4ff4-93e4-f3d35fe1bb5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1757774284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1757774284
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.1391087276
Short name T466
Test name
Test status
Simulation time 135596183 ps
CPU time 2.62 seconds
Started Jul 15 07:22:13 PM PDT 24
Finished Jul 15 07:23:20 PM PDT 24
Peak memory 208084 kb
Host smart-ea2ec1be-3a15-4303-8414-66476e147cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391087276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.1391087276
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.3409050268
Short name T67
Test name
Test status
Simulation time 685417557 ps
CPU time 2.59 seconds
Started Jul 15 07:22:03 PM PDT 24
Finished Jul 15 07:23:08 PM PDT 24
Peak memory 218396 kb
Host smart-cd4cf154-aa6c-4b71-8961-c6fae48649f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409050268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.3409050268
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.598707054
Short name T95
Test name
Test status
Simulation time 113028898 ps
CPU time 4.43 seconds
Started Jul 15 07:22:12 PM PDT 24
Finished Jul 15 07:23:21 PM PDT 24
Peak memory 218944 kb
Host smart-4ba5b726-9eae-4293-a1f2-c3c7e40f84b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598707054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.598707054
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.4217908683
Short name T690
Test name
Test status
Simulation time 211962685 ps
CPU time 5.07 seconds
Started Jul 15 07:22:13 PM PDT 24
Finished Jul 15 07:23:22 PM PDT 24
Peak memory 214288 kb
Host smart-6f106e25-e09f-413d-9e22-1a4160e827a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217908683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.4217908683
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.3205526715
Short name T297
Test name
Test status
Simulation time 184968153 ps
CPU time 4.19 seconds
Started Jul 15 07:22:03 PM PDT 24
Finished Jul 15 07:23:10 PM PDT 24
Peak memory 222492 kb
Host smart-4a706bcc-2c6d-4f5f-a79a-3832ff848c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205526715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3205526715
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.1068287511
Short name T16
Test name
Test status
Simulation time 72058983 ps
CPU time 3.25 seconds
Started Jul 15 07:22:03 PM PDT 24
Finished Jul 15 07:23:05 PM PDT 24
Peak memory 207472 kb
Host smart-f3133d79-b299-46ef-8739-8ca3fccaf090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068287511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1068287511
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.3153477149
Short name T470
Test name
Test status
Simulation time 361083849 ps
CPU time 5.51 seconds
Started Jul 15 07:22:04 PM PDT 24
Finished Jul 15 07:23:11 PM PDT 24
Peak memory 208004 kb
Host smart-b435d8b1-7342-43c6-a092-7e37a72eb139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153477149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.3153477149
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.1781848296
Short name T305
Test name
Test status
Simulation time 843635857 ps
CPU time 3.53 seconds
Started Jul 15 07:22:03 PM PDT 24
Finished Jul 15 07:23:09 PM PDT 24
Peak memory 207364 kb
Host smart-4c87188c-a729-4128-8adf-b50e56080cf6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781848296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.1781848296
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.1352761516
Short name T818
Test name
Test status
Simulation time 39016715 ps
CPU time 2.34 seconds
Started Jul 15 07:22:02 PM PDT 24
Finished Jul 15 07:23:04 PM PDT 24
Peak memory 206972 kb
Host smart-41737b39-a247-414e-b60a-519deb7ae6c9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352761516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.1352761516
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.1769688749
Short name T564
Test name
Test status
Simulation time 429035005 ps
CPU time 3.53 seconds
Started Jul 15 07:22:05 PM PDT 24
Finished Jul 15 07:23:10 PM PDT 24
Peak memory 207176 kb
Host smart-19b1993a-3407-4075-8031-87aee11266f6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769688749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.1769688749
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.3123351958
Short name T611
Test name
Test status
Simulation time 282430302 ps
CPU time 3.59 seconds
Started Jul 15 07:22:14 PM PDT 24
Finished Jul 15 07:23:22 PM PDT 24
Peak memory 209084 kb
Host smart-e6eaed9d-74d8-483d-8351-b67e0c5d9c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123351958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.3123351958
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.1710449244
Short name T449
Test name
Test status
Simulation time 532424721 ps
CPU time 3.28 seconds
Started Jul 15 07:22:01 PM PDT 24
Finished Jul 15 07:23:04 PM PDT 24
Peak memory 208792 kb
Host smart-f9f8f054-c750-41e4-ad45-33ce8ee60e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710449244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.1710449244
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.37117871
Short name T816
Test name
Test status
Simulation time 2374622434 ps
CPU time 36.43 seconds
Started Jul 15 07:22:14 PM PDT 24
Finished Jul 15 07:23:55 PM PDT 24
Peak memory 215028 kb
Host smart-c126ad90-465d-494f-8d01-4785348e71a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37117871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.37117871
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.2325481858
Short name T54
Test name
Test status
Simulation time 907154440 ps
CPU time 8.67 seconds
Started Jul 15 07:22:13 PM PDT 24
Finished Jul 15 07:23:25 PM PDT 24
Peak memory 222640 kb
Host smart-780b09ba-b79b-48b6-a63d-7d165a99501a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325481858 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.2325481858
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.2089106685
Short name T895
Test name
Test status
Simulation time 196457974 ps
CPU time 3.05 seconds
Started Jul 15 07:22:06 PM PDT 24
Finished Jul 15 07:23:09 PM PDT 24
Peak memory 207456 kb
Host smart-d79dcd62-a804-429e-8ae2-e6d37ec534dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089106685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.2089106685
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.3507902644
Short name T794
Test name
Test status
Simulation time 157133901 ps
CPU time 3.02 seconds
Started Jul 15 07:22:14 PM PDT 24
Finished Jul 15 07:23:22 PM PDT 24
Peak memory 209908 kb
Host smart-5878b3fb-b565-4870-8634-2880cbf7b420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507902644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.3507902644
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.4205623343
Short name T100
Test name
Test status
Simulation time 46106515 ps
CPU time 0.88 seconds
Started Jul 15 07:22:20 PM PDT 24
Finished Jul 15 07:23:25 PM PDT 24
Peak memory 206000 kb
Host smart-b1f75ba9-fe2a-4d23-a900-ddbb5b499725
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205623343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.4205623343
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.2910654917
Short name T27
Test name
Test status
Simulation time 479160529 ps
CPU time 2.39 seconds
Started Jul 15 07:22:14 PM PDT 24
Finished Jul 15 07:23:21 PM PDT 24
Peak memory 215560 kb
Host smart-e335584c-4178-4a56-bf54-d3d7c47de007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910654917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.2910654917
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.660539771
Short name T44
Test name
Test status
Simulation time 24421560 ps
CPU time 1.76 seconds
Started Jul 15 07:22:14 PM PDT 24
Finished Jul 15 07:23:20 PM PDT 24
Peak memory 214432 kb
Host smart-e644d525-8726-493d-8948-0c517160ee9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660539771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.660539771
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.4138025576
Short name T80
Test name
Test status
Simulation time 120497117 ps
CPU time 2.13 seconds
Started Jul 15 07:22:13 PM PDT 24
Finished Jul 15 07:23:19 PM PDT 24
Peak memory 214424 kb
Host smart-3dc7a875-417d-4a67-9378-aa9cd658405d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138025576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.4138025576
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.2550883550
Short name T212
Test name
Test status
Simulation time 211278910 ps
CPU time 2.41 seconds
Started Jul 15 07:22:15 PM PDT 24
Finished Jul 15 07:23:22 PM PDT 24
Peak memory 209512 kb
Host smart-fec43150-75ab-4bb4-9077-3b0bf5aa15fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550883550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.2550883550
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.1283071036
Short name T278
Test name
Test status
Simulation time 103147917 ps
CPU time 3.45 seconds
Started Jul 15 07:22:14 PM PDT 24
Finished Jul 15 07:23:22 PM PDT 24
Peak memory 208344 kb
Host smart-9abc408d-c58f-46d3-8304-553f7ce4c7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283071036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.1283071036
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.3627549860
Short name T202
Test name
Test status
Simulation time 77943533 ps
CPU time 3.18 seconds
Started Jul 15 07:22:13 PM PDT 24
Finished Jul 15 07:23:20 PM PDT 24
Peak memory 208496 kb
Host smart-23011949-0be7-48ed-acaf-60bb2d7c65e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627549860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.3627549860
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2813575086
Short name T893
Test name
Test status
Simulation time 209530239 ps
CPU time 2.76 seconds
Started Jul 15 07:22:14 PM PDT 24
Finished Jul 15 07:23:21 PM PDT 24
Peak memory 208476 kb
Host smart-4db3d1f1-ab08-44b9-8e4d-0572f43bf567
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813575086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2813575086
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.4257404095
Short name T107
Test name
Test status
Simulation time 22672243 ps
CPU time 1.83 seconds
Started Jul 15 07:22:14 PM PDT 24
Finished Jul 15 07:23:20 PM PDT 24
Peak memory 207044 kb
Host smart-7fc088ab-1368-474a-92a9-b7939a0550a0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257404095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.4257404095
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.137014579
Short name T687
Test name
Test status
Simulation time 341067118 ps
CPU time 5.11 seconds
Started Jul 15 07:22:13 PM PDT 24
Finished Jul 15 07:23:22 PM PDT 24
Peak memory 208824 kb
Host smart-f5de6c31-0560-49a9-b8f2-f2e49cb6222a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137014579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.137014579
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.2539842752
Short name T851
Test name
Test status
Simulation time 2652035641 ps
CPU time 12.24 seconds
Started Jul 15 07:22:17 PM PDT 24
Finished Jul 15 07:23:35 PM PDT 24
Peak memory 208008 kb
Host smart-8779b29d-2eb6-469c-8c2e-584d82eff229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539842752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.2539842752
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.553338501
Short name T628
Test name
Test status
Simulation time 185765069 ps
CPU time 3.27 seconds
Started Jul 15 07:22:13 PM PDT 24
Finished Jul 15 07:23:20 PM PDT 24
Peak memory 206828 kb
Host smart-9e9cd5f2-a357-4f78-a580-1098b3b59de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553338501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.553338501
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.3565780037
Short name T891
Test name
Test status
Simulation time 5166326485 ps
CPU time 61.07 seconds
Started Jul 15 07:22:18 PM PDT 24
Finished Jul 15 07:24:24 PM PDT 24
Peak memory 216412 kb
Host smart-e2583269-f15d-413d-80f0-5f6050ac4d3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565780037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.3565780037
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.3713436295
Short name T793
Test name
Test status
Simulation time 237320983 ps
CPU time 4.12 seconds
Started Jul 15 07:22:16 PM PDT 24
Finished Jul 15 07:23:23 PM PDT 24
Peak memory 208100 kb
Host smart-c233a69f-31e4-47a4-b029-d707f6b1193e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713436295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.3713436295
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.1049309257
Short name T17
Test name
Test status
Simulation time 212446431 ps
CPU time 2.21 seconds
Started Jul 15 07:22:18 PM PDT 24
Finished Jul 15 07:23:25 PM PDT 24
Peak memory 209960 kb
Host smart-5880d7d6-788b-43a7-b720-f8a863030e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049309257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.1049309257
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.1682305429
Short name T861
Test name
Test status
Simulation time 16828072 ps
CPU time 0.92 seconds
Started Jul 15 07:22:25 PM PDT 24
Finished Jul 15 07:23:31 PM PDT 24
Peak memory 206204 kb
Host smart-2e31cdf8-e2c3-4258-b383-05f7b2f9d86f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682305429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1682305429
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.3537877740
Short name T392
Test name
Test status
Simulation time 197085179 ps
CPU time 3.33 seconds
Started Jul 15 07:22:20 PM PDT 24
Finished Jul 15 07:23:27 PM PDT 24
Peak memory 214416 kb
Host smart-909bb399-f5eb-4538-82ff-c6e6fcaa6763
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3537877740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.3537877740
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.705688119
Short name T922
Test name
Test status
Simulation time 237005176 ps
CPU time 4.46 seconds
Started Jul 15 07:22:19 PM PDT 24
Finished Jul 15 07:23:28 PM PDT 24
Peak memory 222876 kb
Host smart-d7c4d9f8-7831-4b05-aa0a-dfd06b6e5738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705688119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.705688119
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.1264811844
Short name T68
Test name
Test status
Simulation time 359079234 ps
CPU time 2.83 seconds
Started Jul 15 07:22:20 PM PDT 24
Finished Jul 15 07:23:27 PM PDT 24
Peak memory 207220 kb
Host smart-84bdbb40-90b9-474b-8557-78c24656a733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264811844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.1264811844
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.2762074512
Short name T94
Test name
Test status
Simulation time 268816003 ps
CPU time 5.93 seconds
Started Jul 15 07:22:18 PM PDT 24
Finished Jul 15 07:23:29 PM PDT 24
Peak memory 209504 kb
Host smart-f8c40e67-28f7-4dc9-80a3-b87e84f994e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762074512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.2762074512
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.2136710140
Short name T89
Test name
Test status
Simulation time 53535707 ps
CPU time 3.68 seconds
Started Jul 15 07:22:19 PM PDT 24
Finished Jul 15 07:23:27 PM PDT 24
Peak memory 222316 kb
Host smart-28298b09-1c43-4de3-bb3f-5fcd1042cb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136710140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2136710140
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.2419265746
Short name T6
Test name
Test status
Simulation time 416643894 ps
CPU time 2.46 seconds
Started Jul 15 07:22:20 PM PDT 24
Finished Jul 15 07:23:26 PM PDT 24
Peak memory 215664 kb
Host smart-f6326733-7f11-41d8-a658-bb78349da38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419265746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.2419265746
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_sideload.834511889
Short name T685
Test name
Test status
Simulation time 41707765 ps
CPU time 2.32 seconds
Started Jul 15 07:22:20 PM PDT 24
Finished Jul 15 07:23:26 PM PDT 24
Peak memory 206972 kb
Host smart-0dde5964-b27f-4c76-9886-7b0eac8e2c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834511889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.834511889
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.3891701532
Short name T674
Test name
Test status
Simulation time 89976157 ps
CPU time 3.28 seconds
Started Jul 15 07:22:18 PM PDT 24
Finished Jul 15 07:23:26 PM PDT 24
Peak memory 208936 kb
Host smart-a4342924-5f0f-4685-b5b1-7a037daeb02c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891701532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.3891701532
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.480246215
Short name T404
Test name
Test status
Simulation time 360658460 ps
CPU time 3.94 seconds
Started Jul 15 07:22:21 PM PDT 24
Finished Jul 15 07:23:32 PM PDT 24
Peak memory 208892 kb
Host smart-b6cc2f83-8fbb-44e8-8c51-6b04bee4f73a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480246215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.480246215
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.638418946
Short name T723
Test name
Test status
Simulation time 25681299 ps
CPU time 2.12 seconds
Started Jul 15 07:22:19 PM PDT 24
Finished Jul 15 07:23:26 PM PDT 24
Peak memory 208808 kb
Host smart-8f7b8606-836a-4534-8d1e-bec686ee6eea
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638418946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.638418946
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.188035418
Short name T879
Test name
Test status
Simulation time 100011307 ps
CPU time 2.98 seconds
Started Jul 15 07:22:30 PM PDT 24
Finished Jul 15 07:23:40 PM PDT 24
Peak memory 208552 kb
Host smart-fdfca298-d1d1-4ee6-a762-72632df40ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188035418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.188035418
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.1824302124
Short name T778
Test name
Test status
Simulation time 236952553 ps
CPU time 2.96 seconds
Started Jul 15 07:22:18 PM PDT 24
Finished Jul 15 07:23:26 PM PDT 24
Peak memory 206700 kb
Host smart-679d24c7-7fdc-496a-9ea9-b5cf7d57c051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824302124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.1824302124
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.3058983420
Short name T840
Test name
Test status
Simulation time 2520045613 ps
CPU time 55.45 seconds
Started Jul 15 07:22:27 PM PDT 24
Finished Jul 15 07:24:31 PM PDT 24
Peak memory 216528 kb
Host smart-63580698-f832-4f8a-b8e3-45b6cd639918
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058983420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.3058983420
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.3263837120
Short name T627
Test name
Test status
Simulation time 214982989 ps
CPU time 11.7 seconds
Started Jul 15 07:22:27 PM PDT 24
Finished Jul 15 07:23:47 PM PDT 24
Peak memory 222712 kb
Host smart-145c8a46-4801-42bf-b7c0-977548fe283f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263837120 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.3263837120
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.3508045594
Short name T666
Test name
Test status
Simulation time 248942051 ps
CPU time 5.56 seconds
Started Jul 15 07:22:20 PM PDT 24
Finished Jul 15 07:23:29 PM PDT 24
Peak memory 210356 kb
Host smart-63abb421-9eef-4798-a079-47ddbddb2813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508045594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.3508045594
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.1418449411
Short name T483
Test name
Test status
Simulation time 17762728 ps
CPU time 0.7 seconds
Started Jul 15 07:19:32 PM PDT 24
Finished Jul 15 07:20:29 PM PDT 24
Peak memory 205928 kb
Host smart-59085bbf-17e6-4d98-992d-0f860d784bac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418449411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1418449411
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.1314518154
Short name T394
Test name
Test status
Simulation time 36787302 ps
CPU time 2.95 seconds
Started Jul 15 07:19:21 PM PDT 24
Finished Jul 15 07:20:26 PM PDT 24
Peak memory 215260 kb
Host smart-30cf0a24-bdd6-4409-bd36-e0dac7b32991
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1314518154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1314518154
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.4066457503
Short name T34
Test name
Test status
Simulation time 109708166 ps
CPU time 3.91 seconds
Started Jul 15 07:19:21 PM PDT 24
Finished Jul 15 07:20:27 PM PDT 24
Peak memory 220916 kb
Host smart-83e65132-56dd-47ad-847f-45a088b89588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066457503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.4066457503
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.750149316
Short name T686
Test name
Test status
Simulation time 175231521 ps
CPU time 2.15 seconds
Started Jul 15 07:19:20 PM PDT 24
Finished Jul 15 07:20:26 PM PDT 24
Peak memory 207504 kb
Host smart-2f9836d3-806f-43e3-98e2-00ee710ce7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750149316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.750149316
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.1666569756
Short name T352
Test name
Test status
Simulation time 1346868785 ps
CPU time 5.23 seconds
Started Jul 15 07:19:21 PM PDT 24
Finished Jul 15 07:20:28 PM PDT 24
Peak memory 220512 kb
Host smart-7c207374-7c50-42d4-9c5e-929a072db32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666569756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1666569756
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.2097477033
Short name T327
Test name
Test status
Simulation time 466258189 ps
CPU time 3.21 seconds
Started Jul 15 07:19:23 PM PDT 24
Finished Jul 15 07:20:28 PM PDT 24
Peak memory 214268 kb
Host smart-4a0c1f92-77df-4200-adbf-304f7656fd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097477033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.2097477033
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.462278656
Short name T47
Test name
Test status
Simulation time 118546946 ps
CPU time 4.85 seconds
Started Jul 15 07:19:20 PM PDT 24
Finished Jul 15 07:20:27 PM PDT 24
Peak memory 219920 kb
Host smart-f5afb285-696c-4fef-982e-320a487b91bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462278656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.462278656
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.155976497
Short name T738
Test name
Test status
Simulation time 13184788370 ps
CPU time 53.39 seconds
Started Jul 15 07:19:24 PM PDT 24
Finished Jul 15 07:21:18 PM PDT 24
Peak memory 214376 kb
Host smart-077e1b67-0445-4809-b1e0-9a7d5e84d875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155976497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.155976497
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sideload.1650989959
Short name T630
Test name
Test status
Simulation time 544953207 ps
CPU time 3.74 seconds
Started Jul 15 07:19:22 PM PDT 24
Finished Jul 15 07:20:27 PM PDT 24
Peak memory 208816 kb
Host smart-bd211ecd-eede-4678-bdb5-ec589584ce2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650989959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1650989959
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.3242739105
Short name T698
Test name
Test status
Simulation time 161103366 ps
CPU time 2.97 seconds
Started Jul 15 07:19:28 PM PDT 24
Finished Jul 15 07:20:31 PM PDT 24
Peak memory 206884 kb
Host smart-6e348f2e-f095-4d98-aac7-027c5153a587
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242739105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.3242739105
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.3263535043
Short name T898
Test name
Test status
Simulation time 294436403 ps
CPU time 3.45 seconds
Started Jul 15 07:19:21 PM PDT 24
Finished Jul 15 07:20:26 PM PDT 24
Peak memory 208668 kb
Host smart-4c0c8603-f9bb-4e76-afb7-dd79f6f4375b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263535043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.3263535043
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.333901050
Short name T465
Test name
Test status
Simulation time 758867577 ps
CPU time 2.78 seconds
Started Jul 15 07:19:21 PM PDT 24
Finished Jul 15 07:20:25 PM PDT 24
Peak memory 207108 kb
Host smart-0a2c4f01-8e8d-4fb3-aeee-a18f03fd6928
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333901050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.333901050
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.2324231394
Short name T786
Test name
Test status
Simulation time 386035642 ps
CPU time 3.55 seconds
Started Jul 15 07:19:24 PM PDT 24
Finished Jul 15 07:20:28 PM PDT 24
Peak memory 208756 kb
Host smart-145bc70c-f36f-48b1-859a-03f783a2ea39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324231394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.2324231394
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.2124783484
Short name T565
Test name
Test status
Simulation time 1079423522 ps
CPU time 14.57 seconds
Started Jul 15 07:19:24 PM PDT 24
Finished Jul 15 07:20:40 PM PDT 24
Peak memory 207768 kb
Host smart-893c77b5-3495-427d-98d1-05a90fa8bf98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124783484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.2124783484
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.4217630558
Short name T708
Test name
Test status
Simulation time 2484894579 ps
CPU time 17.81 seconds
Started Jul 15 07:19:25 PM PDT 24
Finished Jul 15 07:20:43 PM PDT 24
Peak memory 216336 kb
Host smart-e3e045df-ac52-446b-b465-b7f723e0743c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217630558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.4217630558
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.2789380082
Short name T361
Test name
Test status
Simulation time 1536180575 ps
CPU time 9.28 seconds
Started Jul 15 07:19:32 PM PDT 24
Finished Jul 15 07:20:38 PM PDT 24
Peak memory 218116 kb
Host smart-651fa19d-acb1-4bd5-8d60-da469159db0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789380082 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.2789380082
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.2613889058
Short name T408
Test name
Test status
Simulation time 99662568 ps
CPU time 3.87 seconds
Started Jul 15 07:19:22 PM PDT 24
Finished Jul 15 07:20:27 PM PDT 24
Peak memory 214404 kb
Host smart-f47c8557-56c6-4784-84ce-45405e53f8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613889058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.2613889058
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.2481200892
Short name T543
Test name
Test status
Simulation time 160108272 ps
CPU time 3.39 seconds
Started Jul 15 07:19:21 PM PDT 24
Finished Jul 15 07:20:26 PM PDT 24
Peak memory 210328 kb
Host smart-fd2b5588-be02-47c8-a32c-89fad2c11c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481200892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2481200892
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.1132100262
Short name T618
Test name
Test status
Simulation time 11341021 ps
CPU time 0.72 seconds
Started Jul 15 07:22:27 PM PDT 24
Finished Jul 15 07:23:36 PM PDT 24
Peak memory 206004 kb
Host smart-a935391b-1709-4e3b-9bd3-30289ed79a01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132100262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.1132100262
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.711323275
Short name T634
Test name
Test status
Simulation time 47166685 ps
CPU time 1.53 seconds
Started Jul 15 07:22:25 PM PDT 24
Finished Jul 15 07:23:32 PM PDT 24
Peak memory 209304 kb
Host smart-3d298cef-0c29-43d2-9497-960d4b0ec7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711323275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.711323275
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.2959189993
Short name T91
Test name
Test status
Simulation time 1857040466 ps
CPU time 8.12 seconds
Started Jul 15 07:22:27 PM PDT 24
Finished Jul 15 07:23:43 PM PDT 24
Peak memory 214284 kb
Host smart-8d8cb178-1dbb-4353-adfd-9daa08ac4fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959189993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.2959189993
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.2886978433
Short name T328
Test name
Test status
Simulation time 1056085832 ps
CPU time 5.14 seconds
Started Jul 15 07:22:28 PM PDT 24
Finished Jul 15 07:23:41 PM PDT 24
Peak memory 214212 kb
Host smart-3092d3c0-13c6-4919-bc40-2b6a5d824020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886978433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.2886978433
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.2011000923
Short name T41
Test name
Test status
Simulation time 174495021 ps
CPU time 3.73 seconds
Started Jul 15 07:22:30 PM PDT 24
Finished Jul 15 07:23:41 PM PDT 24
Peak memory 209768 kb
Host smart-086227b3-7ab0-481c-9394-c370bd0f0ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011000923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2011000923
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.2631021868
Short name T524
Test name
Test status
Simulation time 1944470456 ps
CPU time 8.32 seconds
Started Jul 15 07:22:25 PM PDT 24
Finished Jul 15 07:23:39 PM PDT 24
Peak memory 208920 kb
Host smart-f5b3df6f-a54d-49bf-90a1-fc5aac01cdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631021868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.2631021868
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.2921255715
Short name T807
Test name
Test status
Simulation time 919816463 ps
CPU time 6.85 seconds
Started Jul 15 07:22:26 PM PDT 24
Finished Jul 15 07:23:42 PM PDT 24
Peak memory 208312 kb
Host smart-1b5bc0b8-a42c-4b21-9bc4-bef2de35f00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921255715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.2921255715
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.3304247165
Short name T359
Test name
Test status
Simulation time 417333242 ps
CPU time 5.57 seconds
Started Jul 15 07:22:27 PM PDT 24
Finished Jul 15 07:23:41 PM PDT 24
Peak memory 208460 kb
Host smart-3e625360-adf3-4839-8f9c-519eac321b9c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304247165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.3304247165
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.3553579163
Short name T590
Test name
Test status
Simulation time 261481954 ps
CPU time 2.26 seconds
Started Jul 15 07:22:25 PM PDT 24
Finished Jul 15 07:23:33 PM PDT 24
Peak memory 208620 kb
Host smart-a33d5ac0-b965-4b9d-bd16-a659698d3350
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553579163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.3553579163
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1658307698
Short name T403
Test name
Test status
Simulation time 24690153 ps
CPU time 1.8 seconds
Started Jul 15 07:22:28 PM PDT 24
Finished Jul 15 07:23:38 PM PDT 24
Peak memory 206972 kb
Host smart-c9f38993-036d-48aa-b516-2f2bdc53c944
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658307698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1658307698
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.2184668688
Short name T681
Test name
Test status
Simulation time 71788889 ps
CPU time 2.28 seconds
Started Jul 15 07:22:26 PM PDT 24
Finished Jul 15 07:23:37 PM PDT 24
Peak memory 208912 kb
Host smart-fa8e6038-b097-4ba7-b020-262a0f8e1c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184668688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.2184668688
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.497953527
Short name T459
Test name
Test status
Simulation time 94765910 ps
CPU time 2.6 seconds
Started Jul 15 07:22:26 PM PDT 24
Finished Jul 15 07:23:37 PM PDT 24
Peak memory 208616 kb
Host smart-93297c86-ce1a-460f-a3ed-b78bc612a80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497953527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.497953527
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.78373408
Short name T76
Test name
Test status
Simulation time 1842779311 ps
CPU time 24.31 seconds
Started Jul 15 07:22:27 PM PDT 24
Finished Jul 15 07:24:00 PM PDT 24
Peak memory 222700 kb
Host smart-ec5a1808-ed0a-4be5-9dae-e29d38c1fc6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78373408 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.78373408
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.1432192056
Short name T652
Test name
Test status
Simulation time 3650304651 ps
CPU time 25.12 seconds
Started Jul 15 07:22:29 PM PDT 24
Finished Jul 15 07:24:02 PM PDT 24
Peak memory 209232 kb
Host smart-5e44b55d-0be5-47e2-affb-7fb25a0e3102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432192056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1432192056
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.1933702765
Short name T37
Test name
Test status
Simulation time 220007902 ps
CPU time 6.84 seconds
Started Jul 15 07:22:31 PM PDT 24
Finished Jul 15 07:23:44 PM PDT 24
Peak memory 211108 kb
Host smart-e3671e7f-78e1-4374-89b8-32b50c03840c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933702765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.1933702765
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.2733481662
Short name T511
Test name
Test status
Simulation time 28023485 ps
CPU time 0.77 seconds
Started Jul 15 07:22:33 PM PDT 24
Finished Jul 15 07:23:42 PM PDT 24
Peak memory 205984 kb
Host smart-42225c80-8cf6-4e1f-9883-f14eae9edd7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733481662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2733481662
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.4260199644
Short name T551
Test name
Test status
Simulation time 36586778 ps
CPU time 2.31 seconds
Started Jul 15 07:22:25 PM PDT 24
Finished Jul 15 07:23:33 PM PDT 24
Peak memory 207556 kb
Host smart-e21083b3-bf13-489c-b700-cd3702c674c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260199644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.4260199644
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.2546580230
Short name T894
Test name
Test status
Simulation time 513964983 ps
CPU time 5.65 seconds
Started Jul 15 07:22:26 PM PDT 24
Finished Jul 15 07:23:41 PM PDT 24
Peak memory 222480 kb
Host smart-2bd78ee8-946d-4003-a916-c6dcff169c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546580230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.2546580230
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.3658199251
Short name T609
Test name
Test status
Simulation time 49961788 ps
CPU time 2.26 seconds
Started Jul 15 07:22:26 PM PDT 24
Finished Jul 15 07:23:37 PM PDT 24
Peak memory 210456 kb
Host smart-879ad326-b604-4fae-ad94-55848721fc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658199251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.3658199251
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.1061213056
Short name T402
Test name
Test status
Simulation time 251909983 ps
CPU time 5.48 seconds
Started Jul 15 07:22:28 PM PDT 24
Finished Jul 15 07:23:42 PM PDT 24
Peak memory 209324 kb
Host smart-7fe2c05b-a884-48fc-9598-3ac6baaa311f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061213056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.1061213056
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.990440745
Short name T313
Test name
Test status
Simulation time 98736262 ps
CPU time 2.81 seconds
Started Jul 15 07:22:30 PM PDT 24
Finished Jul 15 07:23:40 PM PDT 24
Peak memory 207412 kb
Host smart-6392f350-043b-4e23-9148-0a00c8cdc99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990440745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.990440745
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.3053034369
Short name T859
Test name
Test status
Simulation time 112028593 ps
CPU time 2.84 seconds
Started Jul 15 07:22:28 PM PDT 24
Finished Jul 15 07:23:39 PM PDT 24
Peak memory 208084 kb
Host smart-37533976-f91d-4e34-9526-5e5837370400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053034369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.3053034369
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.540028917
Short name T547
Test name
Test status
Simulation time 247528744 ps
CPU time 6.66 seconds
Started Jul 15 07:22:29 PM PDT 24
Finished Jul 15 07:23:44 PM PDT 24
Peak memory 208120 kb
Host smart-5beb3a3f-3d5f-4ed1-8a1f-64e1e8c3e0fe
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540028917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.540028917
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.3522294613
Short name T206
Test name
Test status
Simulation time 151334190 ps
CPU time 3.56 seconds
Started Jul 15 07:22:29 PM PDT 24
Finished Jul 15 07:23:40 PM PDT 24
Peak memory 208632 kb
Host smart-a877f923-1488-44d7-9e54-2d044b2dcf43
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522294613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3522294613
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.4049217791
Short name T833
Test name
Test status
Simulation time 31557213 ps
CPU time 2.18 seconds
Started Jul 15 07:22:25 PM PDT 24
Finished Jul 15 07:23:33 PM PDT 24
Peak memory 206988 kb
Host smart-4e993e73-3db1-4963-ada2-c5ab726962aa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049217791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.4049217791
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.1074900208
Short name T753
Test name
Test status
Simulation time 16943527 ps
CPU time 1.41 seconds
Started Jul 15 07:22:33 PM PDT 24
Finished Jul 15 07:23:42 PM PDT 24
Peak memory 208092 kb
Host smart-8e8735b0-eb61-4175-9cec-8c39aa1497cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074900208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1074900208
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.1362232340
Short name T430
Test name
Test status
Simulation time 328894062 ps
CPU time 5.45 seconds
Started Jul 15 07:22:30 PM PDT 24
Finished Jul 15 07:23:43 PM PDT 24
Peak memory 208788 kb
Host smart-5be17a64-6984-4735-a44b-f49d6194560c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362232340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.1362232340
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.3995825462
Short name T788
Test name
Test status
Simulation time 6242032204 ps
CPU time 56.62 seconds
Started Jul 15 07:22:33 PM PDT 24
Finished Jul 15 07:24:37 PM PDT 24
Peak memory 222624 kb
Host smart-e17090be-3a1f-404e-a846-ee5131dcff40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995825462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.3995825462
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.3655231045
Short name T733
Test name
Test status
Simulation time 729182706 ps
CPU time 6.03 seconds
Started Jul 15 07:22:27 PM PDT 24
Finished Jul 15 07:23:42 PM PDT 24
Peak memory 218392 kb
Host smart-3d97f6f4-21ec-429b-8d9c-02cbf2155e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655231045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.3655231045
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.2754716239
Short name T770
Test name
Test status
Simulation time 345166986 ps
CPU time 2.46 seconds
Started Jul 15 07:22:34 PM PDT 24
Finished Jul 15 07:23:44 PM PDT 24
Peak memory 210356 kb
Host smart-e11427f9-79d4-4ee1-a2be-3887cd9888f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754716239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.2754716239
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.322138654
Short name T583
Test name
Test status
Simulation time 35949664 ps
CPU time 0.82 seconds
Started Jul 15 07:22:33 PM PDT 24
Finished Jul 15 07:23:42 PM PDT 24
Peak memory 206028 kb
Host smart-9d0ddfd7-2797-4003-9b98-f3642e4d2264
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322138654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.322138654
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.898216754
Short name T420
Test name
Test status
Simulation time 263365699 ps
CPU time 3.7 seconds
Started Jul 15 07:22:32 PM PDT 24
Finished Jul 15 07:23:44 PM PDT 24
Peak memory 215556 kb
Host smart-3976bb22-ede7-4d1e-9e48-36f3acb31088
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=898216754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.898216754
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.3559135119
Short name T74
Test name
Test status
Simulation time 18520805 ps
CPU time 1.53 seconds
Started Jul 15 07:22:32 PM PDT 24
Finished Jul 15 07:23:42 PM PDT 24
Peak memory 207656 kb
Host smart-b7574d33-5a05-48f0-bf4a-8db977159254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559135119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.3559135119
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.2970248039
Short name T88
Test name
Test status
Simulation time 706565550 ps
CPU time 19.57 seconds
Started Jul 15 07:22:33 PM PDT 24
Finished Jul 15 07:24:00 PM PDT 24
Peak memory 214284 kb
Host smart-90b864dc-af8c-416f-bc08-ac5707f8360e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970248039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.2970248039
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.3966049199
Short name T345
Test name
Test status
Simulation time 119800135 ps
CPU time 3.32 seconds
Started Jul 15 07:22:35 PM PDT 24
Finished Jul 15 07:23:45 PM PDT 24
Peak memory 222380 kb
Host smart-449971f2-a643-4a8c-9eaa-874f07efdff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966049199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.3966049199
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.2163389795
Short name T98
Test name
Test status
Simulation time 426443151 ps
CPU time 3.67 seconds
Started Jul 15 07:22:32 PM PDT 24
Finished Jul 15 07:23:44 PM PDT 24
Peak memory 222544 kb
Host smart-648027e6-42c4-4aca-a38d-e449f76c0b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163389795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.2163389795
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.1097416667
Short name T742
Test name
Test status
Simulation time 4033863515 ps
CPU time 69.82 seconds
Started Jul 15 07:22:37 PM PDT 24
Finished Jul 15 07:24:52 PM PDT 24
Peak memory 209712 kb
Host smart-8a4d2e85-16ec-495a-bfe2-6f824c398bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097416667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.1097416667
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.4063267938
Short name T832
Test name
Test status
Simulation time 59122447 ps
CPU time 2.79 seconds
Started Jul 15 07:22:33 PM PDT 24
Finished Jul 15 07:23:44 PM PDT 24
Peak memory 207916 kb
Host smart-66c90eec-1b6a-4b37-b5df-725871fd9a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063267938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.4063267938
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.1864624903
Short name T498
Test name
Test status
Simulation time 240015285 ps
CPU time 2.71 seconds
Started Jul 15 07:22:36 PM PDT 24
Finished Jul 15 07:23:44 PM PDT 24
Peak memory 206884 kb
Host smart-08566f5b-36ef-4f05-bae3-015ce8b65ddf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864624903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.1864624903
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.1926258618
Short name T489
Test name
Test status
Simulation time 69535896 ps
CPU time 3.41 seconds
Started Jul 15 07:22:35 PM PDT 24
Finished Jul 15 07:23:45 PM PDT 24
Peak memory 208340 kb
Host smart-1eb06409-fc12-4e8c-8424-f8b68c182ddd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926258618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.1926258618
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.323927831
Short name T559
Test name
Test status
Simulation time 603447681 ps
CPU time 7.03 seconds
Started Jul 15 07:22:35 PM PDT 24
Finished Jul 15 07:23:49 PM PDT 24
Peak memory 208840 kb
Host smart-0546eb03-f2a8-4529-90cf-60d2555c7fe7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323927831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.323927831
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.3551798228
Short name T631
Test name
Test status
Simulation time 145060902 ps
CPU time 2.45 seconds
Started Jul 15 07:22:33 PM PDT 24
Finished Jul 15 07:23:43 PM PDT 24
Peak memory 209688 kb
Host smart-8f850e7a-8a3b-423a-b5c5-01ebb8322370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551798228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.3551798228
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.168928070
Short name T586
Test name
Test status
Simulation time 144281340 ps
CPU time 2.13 seconds
Started Jul 15 07:22:34 PM PDT 24
Finished Jul 15 07:23:43 PM PDT 24
Peak memory 206816 kb
Host smart-6261bff1-697c-4c73-814e-5784d0f231fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168928070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.168928070
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.161493584
Short name T350
Test name
Test status
Simulation time 2220773112 ps
CPU time 26.74 seconds
Started Jul 15 07:22:32 PM PDT 24
Finished Jul 15 07:24:07 PM PDT 24
Peak memory 216680 kb
Host smart-eb8afc5d-651f-4e8c-904d-846bb0487398
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161493584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.161493584
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.3792074692
Short name T889
Test name
Test status
Simulation time 420843158 ps
CPU time 5.29 seconds
Started Jul 15 07:22:33 PM PDT 24
Finished Jul 15 07:23:46 PM PDT 24
Peak memory 207548 kb
Host smart-2b6fc9b3-c0c4-421e-8cc0-a00ed37da4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792074692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.3792074692
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.2071842430
Short name T48
Test name
Test status
Simulation time 84565986 ps
CPU time 2.11 seconds
Started Jul 15 07:22:36 PM PDT 24
Finished Jul 15 07:23:44 PM PDT 24
Peak memory 209864 kb
Host smart-d5826ec9-f26e-40c0-9763-1281057d5df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071842430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.2071842430
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.1456319945
Short name T675
Test name
Test status
Simulation time 230404039 ps
CPU time 0.99 seconds
Started Jul 15 07:22:46 PM PDT 24
Finished Jul 15 07:23:57 PM PDT 24
Peak memory 206136 kb
Host smart-a3cda487-ac0c-45cc-b541-1bfa212c28ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456319945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.1456319945
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.4286676180
Short name T132
Test name
Test status
Simulation time 166335112 ps
CPU time 5.06 seconds
Started Jul 15 07:22:33 PM PDT 24
Finished Jul 15 07:23:46 PM PDT 24
Peak memory 215228 kb
Host smart-57320964-a877-466f-87e4-0a8e9fa504eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4286676180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.4286676180
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.3366218023
Short name T534
Test name
Test status
Simulation time 560737711 ps
CPU time 1.64 seconds
Started Jul 15 07:22:35 PM PDT 24
Finished Jul 15 07:23:43 PM PDT 24
Peak memory 209424 kb
Host smart-39065cea-5935-4f0d-a67b-2caefd847e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366218023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.3366218023
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.2167718134
Short name T864
Test name
Test status
Simulation time 92607094 ps
CPU time 4.04 seconds
Started Jul 15 07:22:32 PM PDT 24
Finished Jul 15 07:23:45 PM PDT 24
Peak memory 209624 kb
Host smart-5f8c2728-5fc1-495f-b485-e317e5304f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167718134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.2167718134
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.2523092831
Short name T209
Test name
Test status
Simulation time 1738180986 ps
CPU time 5.27 seconds
Started Jul 15 07:22:34 PM PDT 24
Finished Jul 15 07:23:46 PM PDT 24
Peak memory 214440 kb
Host smart-e79161f0-1fb0-4857-96f0-89f3d3a0e964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523092831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.2523092831
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.1123246650
Short name T876
Test name
Test status
Simulation time 95611774 ps
CPU time 1.91 seconds
Started Jul 15 07:22:34 PM PDT 24
Finished Jul 15 07:23:43 PM PDT 24
Peak memory 214236 kb
Host smart-f6155029-5a49-471f-9d70-ed46f58cb25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123246650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.1123246650
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.3037988668
Short name T780
Test name
Test status
Simulation time 162750041 ps
CPU time 3.56 seconds
Started Jul 15 07:22:34 PM PDT 24
Finished Jul 15 07:23:45 PM PDT 24
Peak memory 220544 kb
Host smart-92227bc0-7603-41b4-9b5e-a15736d58ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037988668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3037988668
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.1441143596
Short name T713
Test name
Test status
Simulation time 226755542 ps
CPU time 5.17 seconds
Started Jul 15 07:22:34 PM PDT 24
Finished Jul 15 07:23:46 PM PDT 24
Peak memory 214240 kb
Host smart-20351f97-2aa4-4e9e-a47f-26382ff3bd74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441143596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.1441143596
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.1860563117
Short name T439
Test name
Test status
Simulation time 131705625 ps
CPU time 3.15 seconds
Started Jul 15 07:22:35 PM PDT 24
Finished Jul 15 07:23:45 PM PDT 24
Peak memory 208580 kb
Host smart-a6aad18f-c9fb-4288-b87f-24126f0a4a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860563117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.1860563117
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.3815693567
Short name T526
Test name
Test status
Simulation time 1220616402 ps
CPU time 25.11 seconds
Started Jul 15 07:22:34 PM PDT 24
Finished Jul 15 07:24:06 PM PDT 24
Peak memory 208876 kb
Host smart-7dc0317a-4e10-4ccc-ba1c-9941895eb19c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815693567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.3815693567
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.1757183049
Short name T761
Test name
Test status
Simulation time 70213744 ps
CPU time 2.64 seconds
Started Jul 15 07:22:38 PM PDT 24
Finished Jul 15 07:23:46 PM PDT 24
Peak memory 208776 kb
Host smart-10c8cafc-0f3c-487b-abab-46ccb81c68e2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757183049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.1757183049
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.2855007273
Short name T281
Test name
Test status
Simulation time 78249824 ps
CPU time 1.8 seconds
Started Jul 15 07:22:34 PM PDT 24
Finished Jul 15 07:23:43 PM PDT 24
Peak memory 207560 kb
Host smart-5db4cbf6-e25c-4ac8-9fb1-c4994383cc4c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855007273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2855007273
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.2687231893
Short name T303
Test name
Test status
Simulation time 130183379 ps
CPU time 4.78 seconds
Started Jul 15 07:22:51 PM PDT 24
Finished Jul 15 07:24:06 PM PDT 24
Peak memory 214388 kb
Host smart-c11f4995-03b1-4ff0-992b-697b76b71211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687231893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.2687231893
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.3929347217
Short name T414
Test name
Test status
Simulation time 247346293 ps
CPU time 3.79 seconds
Started Jul 15 07:22:33 PM PDT 24
Finished Jul 15 07:23:45 PM PDT 24
Peak memory 208340 kb
Host smart-69637c46-dfd0-4918-91fd-2f9da0f95149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929347217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.3929347217
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.2213787187
Short name T193
Test name
Test status
Simulation time 3009407043 ps
CPU time 35.05 seconds
Started Jul 15 07:22:40 PM PDT 24
Finished Jul 15 07:24:20 PM PDT 24
Peak memory 222540 kb
Host smart-089d1900-20fc-4ab2-bbd1-bb6235002263
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213787187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.2213787187
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.3771384888
Short name T787
Test name
Test status
Simulation time 454302299 ps
CPU time 6.76 seconds
Started Jul 15 07:22:34 PM PDT 24
Finished Jul 15 07:23:48 PM PDT 24
Peak memory 207364 kb
Host smart-cb98b835-0c64-4dd1-9895-c461029d7642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771384888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.3771384888
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.3249123515
Short name T33
Test name
Test status
Simulation time 81973423 ps
CPU time 2.99 seconds
Started Jul 15 07:22:41 PM PDT 24
Finished Jul 15 07:23:52 PM PDT 24
Peak memory 210144 kb
Host smart-d0f6c463-88e3-462b-b63a-57ecb4f9f578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249123515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.3249123515
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.2777176613
Short name T650
Test name
Test status
Simulation time 18655689 ps
CPU time 0.91 seconds
Started Jul 15 07:22:50 PM PDT 24
Finished Jul 15 07:24:00 PM PDT 24
Peak memory 206052 kb
Host smart-38030fd3-73c2-4e4c-841d-57fcd0aaa48c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777176613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2777176613
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.3444363249
Short name T266
Test name
Test status
Simulation time 111079853 ps
CPU time 5.92 seconds
Started Jul 15 07:22:51 PM PDT 24
Finished Jul 15 07:24:08 PM PDT 24
Peak memory 214656 kb
Host smart-146ca0fb-4aa3-42cc-bd4f-879e74405646
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3444363249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.3444363249
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.594314648
Short name T36
Test name
Test status
Simulation time 317665985 ps
CPU time 6.99 seconds
Started Jul 15 07:22:43 PM PDT 24
Finished Jul 15 07:23:58 PM PDT 24
Peak memory 209548 kb
Host smart-f672cd39-ca77-4d9c-860c-398e69bbccdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594314648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.594314648
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.1702384045
Short name T294
Test name
Test status
Simulation time 257293591 ps
CPU time 5.65 seconds
Started Jul 15 07:22:44 PM PDT 24
Finished Jul 15 07:23:56 PM PDT 24
Peak memory 214312 kb
Host smart-89c702fa-c34e-4228-90bd-5ef0343cac7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702384045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.1702384045
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.4033117180
Short name T486
Test name
Test status
Simulation time 413239152 ps
CPU time 4.43 seconds
Started Jul 15 07:22:46 PM PDT 24
Finished Jul 15 07:24:01 PM PDT 24
Peak memory 209160 kb
Host smart-5cf907fb-6343-49b4-b6c1-9e1151c343b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033117180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.4033117180
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.2947744317
Short name T805
Test name
Test status
Simulation time 69319648 ps
CPU time 4.26 seconds
Started Jul 15 07:22:40 PM PDT 24
Finished Jul 15 07:23:50 PM PDT 24
Peak memory 209940 kb
Host smart-fc3ff8e8-e6f1-42aa-b03f-a96b8789ccb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947744317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.2947744317
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.1508054420
Short name T321
Test name
Test status
Simulation time 36617765 ps
CPU time 2.55 seconds
Started Jul 15 07:22:43 PM PDT 24
Finished Jul 15 07:23:53 PM PDT 24
Peak memory 207608 kb
Host smart-76666e77-14f8-4059-8e93-23daa58aaf35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508054420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1508054420
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.1951560800
Short name T725
Test name
Test status
Simulation time 222807832 ps
CPU time 2.81 seconds
Started Jul 15 07:22:41 PM PDT 24
Finished Jul 15 07:23:53 PM PDT 24
Peak memory 207048 kb
Host smart-fc83ddaa-14dc-4a0c-b984-c8e07d456341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951560800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.1951560800
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.3978251792
Short name T381
Test name
Test status
Simulation time 142622319 ps
CPU time 5.21 seconds
Started Jul 15 07:22:43 PM PDT 24
Finished Jul 15 07:23:56 PM PDT 24
Peak memory 207896 kb
Host smart-d442bfa2-8774-44df-af55-a8df4f8323d2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978251792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3978251792
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3493960442
Short name T256
Test name
Test status
Simulation time 978312680 ps
CPU time 25.27 seconds
Started Jul 15 07:22:46 PM PDT 24
Finished Jul 15 07:24:21 PM PDT 24
Peak memory 208716 kb
Host smart-68b9888d-dc90-44ad-82d2-32282b8a4e65
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493960442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3493960442
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.1809505007
Short name T689
Test name
Test status
Simulation time 76970368 ps
CPU time 2.29 seconds
Started Jul 15 07:22:46 PM PDT 24
Finished Jul 15 07:23:58 PM PDT 24
Peak memory 206972 kb
Host smart-f84a9799-4564-4578-8e3a-078fb1a5a1b4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809505007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.1809505007
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.1563322732
Short name T259
Test name
Test status
Simulation time 45036275 ps
CPU time 1.66 seconds
Started Jul 15 07:22:41 PM PDT 24
Finished Jul 15 07:23:50 PM PDT 24
Peak memory 209632 kb
Host smart-800aecb1-822b-49e0-9338-1280320a1816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563322732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.1563322732
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.756735602
Short name T896
Test name
Test status
Simulation time 388053977 ps
CPU time 2.86 seconds
Started Jul 15 07:22:39 PM PDT 24
Finished Jul 15 07:23:48 PM PDT 24
Peak memory 206856 kb
Host smart-6331cccf-b209-4067-a3e1-e7e13a54c839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756735602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.756735602
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.2970604474
Short name T596
Test name
Test status
Simulation time 1207392175 ps
CPU time 7.61 seconds
Started Jul 15 07:22:43 PM PDT 24
Finished Jul 15 07:23:58 PM PDT 24
Peak memory 208552 kb
Host smart-a0d8aaf5-2c92-45fb-ac35-047c1541038c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970604474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.2970604474
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.1011090419
Short name T635
Test name
Test status
Simulation time 236353810 ps
CPU time 6.3 seconds
Started Jul 15 07:22:41 PM PDT 24
Finished Jul 15 07:23:55 PM PDT 24
Peak memory 209640 kb
Host smart-c9b789fa-3a85-4dd2-8440-2d5ab94e832c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011090419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.1011090419
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.4081202621
Short name T197
Test name
Test status
Simulation time 243947468 ps
CPU time 2.24 seconds
Started Jul 15 07:22:39 PM PDT 24
Finished Jul 15 07:23:47 PM PDT 24
Peak memory 210064 kb
Host smart-098b785c-8be2-4fd4-ac02-8d246374ed86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081202621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.4081202621
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.3271457953
Short name T904
Test name
Test status
Simulation time 69422648 ps
CPU time 1.01 seconds
Started Jul 15 07:22:41 PM PDT 24
Finished Jul 15 07:23:51 PM PDT 24
Peak memory 206144 kb
Host smart-b35735ef-9fba-45b3-b1bc-4d4b3e9cfc98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271457953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.3271457953
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.3671950083
Short name T241
Test name
Test status
Simulation time 1023182553 ps
CPU time 6.38 seconds
Started Jul 15 07:22:42 PM PDT 24
Finished Jul 15 07:23:57 PM PDT 24
Peak memory 214340 kb
Host smart-f3776b7b-d200-455a-90f5-37379cfb3581
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3671950083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.3671950083
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.923720045
Short name T594
Test name
Test status
Simulation time 64805599 ps
CPU time 1.65 seconds
Started Jul 15 07:22:43 PM PDT 24
Finished Jul 15 07:23:52 PM PDT 24
Peak memory 214668 kb
Host smart-33c34e83-9cbb-474e-a20e-1254c315c36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923720045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.923720045
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.3598419966
Short name T75
Test name
Test status
Simulation time 37321841 ps
CPU time 2.09 seconds
Started Jul 15 07:22:45 PM PDT 24
Finished Jul 15 07:23:57 PM PDT 24
Peak memory 209564 kb
Host smart-daf8b09a-0db2-4f44-9c50-790178a12525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598419966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.3598419966
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.2934228202
Short name T288
Test name
Test status
Simulation time 312568226 ps
CPU time 3.72 seconds
Started Jul 15 07:22:50 PM PDT 24
Finished Jul 15 07:24:02 PM PDT 24
Peak memory 214380 kb
Host smart-082aaadf-8642-4b60-a2d2-6cff79b37128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934228202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.2934228202
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.3477853109
Short name T619
Test name
Test status
Simulation time 120903653 ps
CPU time 2.48 seconds
Started Jul 15 07:22:50 PM PDT 24
Finished Jul 15 07:24:01 PM PDT 24
Peak memory 209664 kb
Host smart-4b446509-0d38-48d7-9b50-933ab5c9efdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477853109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.3477853109
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.2219331846
Short name T78
Test name
Test status
Simulation time 340205082 ps
CPU time 9.84 seconds
Started Jul 15 07:22:42 PM PDT 24
Finished Jul 15 07:24:00 PM PDT 24
Peak memory 210332 kb
Host smart-df4990f1-2d79-47c9-9c7c-5fab70f8543e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219331846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.2219331846
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.385510220
Short name T684
Test name
Test status
Simulation time 704578856 ps
CPU time 3.45 seconds
Started Jul 15 07:22:40 PM PDT 24
Finished Jul 15 07:23:49 PM PDT 24
Peak memory 206776 kb
Host smart-2d39f51c-3405-4dad-a8f8-8e540829a6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385510220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.385510220
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.3631144108
Short name T814
Test name
Test status
Simulation time 108287177 ps
CPU time 2.78 seconds
Started Jul 15 07:22:43 PM PDT 24
Finished Jul 15 07:23:53 PM PDT 24
Peak memory 206892 kb
Host smart-2bb2eff3-950c-47e8-aab8-c7add295b9a6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631144108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.3631144108
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.1148956012
Short name T680
Test name
Test status
Simulation time 332092841 ps
CPU time 3.39 seconds
Started Jul 15 07:22:43 PM PDT 24
Finished Jul 15 07:23:54 PM PDT 24
Peak memory 208980 kb
Host smart-80353025-92ec-4b47-81a1-f6b5ad7dadcb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148956012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.1148956012
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.1035210252
Short name T558
Test name
Test status
Simulation time 1972412201 ps
CPU time 6.79 seconds
Started Jul 15 07:22:42 PM PDT 24
Finished Jul 15 07:23:57 PM PDT 24
Peak memory 208816 kb
Host smart-6d8e3743-a581-4706-aeea-87a7cac41e74
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035210252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.1035210252
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.1053224194
Short name T854
Test name
Test status
Simulation time 227539684 ps
CPU time 2.08 seconds
Started Jul 15 07:22:44 PM PDT 24
Finished Jul 15 07:23:53 PM PDT 24
Peak memory 214380 kb
Host smart-bdf6de92-e654-439e-b09e-7b69373a5152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053224194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.1053224194
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.825213848
Short name T824
Test name
Test status
Simulation time 153579784 ps
CPU time 1.69 seconds
Started Jul 15 07:22:42 PM PDT 24
Finished Jul 15 07:23:52 PM PDT 24
Peak memory 206880 kb
Host smart-14567c56-5294-426a-b1b2-85e2590ea8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825213848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.825213848
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.1251782778
Short name T65
Test name
Test status
Simulation time 3804322044 ps
CPU time 16.54 seconds
Started Jul 15 07:22:42 PM PDT 24
Finished Jul 15 07:24:07 PM PDT 24
Peak memory 221920 kb
Host smart-fb60fdc9-b5ba-41da-9fb8-324c4016abb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251782778 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.1251782778
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3393729685
Short name T395
Test name
Test status
Simulation time 477492974 ps
CPU time 5.81 seconds
Started Jul 15 07:22:41 PM PDT 24
Finished Jul 15 07:23:55 PM PDT 24
Peak memory 209800 kb
Host smart-b120406d-9f82-44ba-8746-478977dbab7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393729685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3393729685
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.3226010066
Short name T38
Test name
Test status
Simulation time 204986992 ps
CPU time 2.32 seconds
Started Jul 15 07:22:43 PM PDT 24
Finished Jul 15 07:23:53 PM PDT 24
Peak memory 210124 kb
Host smart-502ad2b7-f54e-4e55-914d-287511559f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226010066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.3226010066
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.112497269
Short name T767
Test name
Test status
Simulation time 91458021 ps
CPU time 0.72 seconds
Started Jul 15 07:22:47 PM PDT 24
Finished Jul 15 07:23:58 PM PDT 24
Peak memory 205996 kb
Host smart-477aa918-dd69-421a-858c-0291205a82a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112497269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.112497269
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.1553821398
Short name T73
Test name
Test status
Simulation time 515429934 ps
CPU time 2.83 seconds
Started Jul 15 07:22:44 PM PDT 24
Finished Jul 15 07:23:53 PM PDT 24
Peak memory 209100 kb
Host smart-1bdba366-1683-4295-8fec-2b6eb433080f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553821398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.1553821398
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.1028275550
Short name T581
Test name
Test status
Simulation time 88181598 ps
CPU time 2.11 seconds
Started Jul 15 07:22:47 PM PDT 24
Finished Jul 15 07:23:59 PM PDT 24
Peak memory 214300 kb
Host smart-61cf8d61-b4b0-41d2-8251-30a90d08b37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028275550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.1028275550
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.3062167411
Short name T810
Test name
Test status
Simulation time 490433705 ps
CPU time 4.07 seconds
Started Jul 15 07:22:49 PM PDT 24
Finished Jul 15 07:24:02 PM PDT 24
Peak memory 214292 kb
Host smart-1c7ccbe5-a561-405c-b3be-37992f8c2332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062167411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.3062167411
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.1230440235
Short name T653
Test name
Test status
Simulation time 284254636 ps
CPU time 4.22 seconds
Started Jul 15 07:22:46 PM PDT 24
Finished Jul 15 07:24:01 PM PDT 24
Peak memory 214344 kb
Host smart-1e5030c1-f92e-4678-9d9d-34a50ff54136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230440235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.1230440235
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.988198544
Short name T338
Test name
Test status
Simulation time 1319512309 ps
CPU time 8.92 seconds
Started Jul 15 07:22:50 PM PDT 24
Finished Jul 15 07:24:10 PM PDT 24
Peak memory 209216 kb
Host smart-458662f9-1007-42b8-a5da-a9c51b45f86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988198544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.988198544
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.1830373584
Short name T262
Test name
Test status
Simulation time 175975188 ps
CPU time 3.97 seconds
Started Jul 15 07:22:40 PM PDT 24
Finished Jul 15 07:23:49 PM PDT 24
Peak memory 206884 kb
Host smart-92ac5306-aa45-4979-b558-c097b1c59b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830373584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.1830373584
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.2643417865
Short name T310
Test name
Test status
Simulation time 63668606 ps
CPU time 3.29 seconds
Started Jul 15 07:22:41 PM PDT 24
Finished Jul 15 07:23:53 PM PDT 24
Peak memory 208928 kb
Host smart-c963bd1c-f522-4580-bd6c-0b36b05401fd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643417865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.2643417865
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.613683479
Short name T332
Test name
Test status
Simulation time 363019847 ps
CPU time 4.24 seconds
Started Jul 15 07:22:51 PM PDT 24
Finished Jul 15 07:24:06 PM PDT 24
Peak memory 208624 kb
Host smart-ad1e8f03-912d-490b-9a3a-11ac2f5a16cf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613683479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.613683479
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.3248199626
Short name T720
Test name
Test status
Simulation time 622260787 ps
CPU time 17.55 seconds
Started Jul 15 07:22:46 PM PDT 24
Finished Jul 15 07:24:14 PM PDT 24
Peak memory 209052 kb
Host smart-f1dfc363-d5ce-447f-bb95-2fb0e6d8fb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248199626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.3248199626
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.3816792732
Short name T128
Test name
Test status
Simulation time 553132892 ps
CPU time 11.12 seconds
Started Jul 15 07:22:43 PM PDT 24
Finished Jul 15 07:24:02 PM PDT 24
Peak memory 208000 kb
Host smart-d7c38214-7078-4524-b870-ecf7e3f562eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816792732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.3816792732
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.2928866930
Short name T838
Test name
Test status
Simulation time 933094573 ps
CPU time 13.98 seconds
Started Jul 15 07:22:47 PM PDT 24
Finished Jul 15 07:24:11 PM PDT 24
Peak memory 216128 kb
Host smart-bf7d9103-9918-416e-bf09-00197fc211de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928866930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2928866930
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.2575671097
Short name T664
Test name
Test status
Simulation time 2729904897 ps
CPU time 10.54 seconds
Started Jul 15 07:22:48 PM PDT 24
Finished Jul 15 07:24:08 PM PDT 24
Peak memory 220280 kb
Host smart-12763be9-59d9-4e75-a602-0c8736015307
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575671097 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.2575671097
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.1144186264
Short name T488
Test name
Test status
Simulation time 1061915916 ps
CPU time 7.53 seconds
Started Jul 15 07:22:49 PM PDT 24
Finished Jul 15 07:24:06 PM PDT 24
Peak memory 209040 kb
Host smart-db4aa9f4-648a-4474-b1d5-fd3b97ba0b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144186264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.1144186264
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.2802251278
Short name T57
Test name
Test status
Simulation time 264677003 ps
CPU time 4.3 seconds
Started Jul 15 07:22:49 PM PDT 24
Finished Jul 15 07:24:02 PM PDT 24
Peak memory 210200 kb
Host smart-73e45f94-5ce5-4d32-ba35-4843efa9f7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802251278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.2802251278
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.2458948312
Short name T566
Test name
Test status
Simulation time 10702278 ps
CPU time 0.8 seconds
Started Jul 15 07:22:51 PM PDT 24
Finished Jul 15 07:24:02 PM PDT 24
Peak memory 205992 kb
Host smart-ae6d9b14-f2c3-4b71-820b-d59e965ba5c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458948312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.2458948312
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.2060182489
Short name T235
Test name
Test status
Simulation time 171009068 ps
CPU time 9.1 seconds
Started Jul 15 07:22:47 PM PDT 24
Finished Jul 15 07:24:06 PM PDT 24
Peak memory 214432 kb
Host smart-15256744-d963-4882-a995-3c8cc712e29a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2060182489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.2060182489
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.1429470949
Short name T573
Test name
Test status
Simulation time 83622432 ps
CPU time 3.53 seconds
Started Jul 15 07:22:48 PM PDT 24
Finished Jul 15 07:24:01 PM PDT 24
Peak memory 210236 kb
Host smart-0ed32b0c-044b-4842-9cd8-b61936445c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429470949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.1429470949
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.1580492805
Short name T819
Test name
Test status
Simulation time 80240127 ps
CPU time 2.59 seconds
Started Jul 15 07:22:49 PM PDT 24
Finished Jul 15 07:24:01 PM PDT 24
Peak memory 209312 kb
Host smart-7d0bb742-c4ba-4aa1-92f8-25d32b1c537a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580492805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.1580492805
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.4149339177
Short name T366
Test name
Test status
Simulation time 357126858 ps
CPU time 3.31 seconds
Started Jul 15 07:22:53 PM PDT 24
Finished Jul 15 07:24:06 PM PDT 24
Peak memory 214320 kb
Host smart-4afbccae-989c-40f2-b38b-a5068df3acf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149339177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.4149339177
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.3406751866
Short name T147
Test name
Test status
Simulation time 257050203 ps
CPU time 3 seconds
Started Jul 15 07:22:50 PM PDT 24
Finished Jul 15 07:24:04 PM PDT 24
Peak memory 206132 kb
Host smart-be3af215-13da-497d-90ee-ea5e6ebba5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406751866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.3406751866
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.1315843535
Short name T744
Test name
Test status
Simulation time 61555743 ps
CPU time 3.57 seconds
Started Jul 15 07:22:47 PM PDT 24
Finished Jul 15 07:24:01 PM PDT 24
Peak memory 206920 kb
Host smart-d59fcd11-54ac-4ee0-b763-bfba282067f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315843535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1315843535
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1002452880
Short name T736
Test name
Test status
Simulation time 218929376 ps
CPU time 2.99 seconds
Started Jul 15 07:22:54 PM PDT 24
Finished Jul 15 07:24:06 PM PDT 24
Peak memory 208512 kb
Host smart-041c6a6f-189e-4373-be50-b99bd094b883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002452880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1002452880
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.4282225400
Short name T704
Test name
Test status
Simulation time 271134251 ps
CPU time 3.19 seconds
Started Jul 15 07:22:47 PM PDT 24
Finished Jul 15 07:24:00 PM PDT 24
Peak memory 208540 kb
Host smart-d685db43-94d1-46aa-8527-241d4899b847
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282225400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.4282225400
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.428345406
Short name T316
Test name
Test status
Simulation time 126009796 ps
CPU time 3.08 seconds
Started Jul 15 07:22:54 PM PDT 24
Finished Jul 15 07:24:06 PM PDT 24
Peak memory 208484 kb
Host smart-eb9a9d5f-96c9-4bea-84e5-d4b19404a46b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428345406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.428345406
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.893744623
Short name T544
Test name
Test status
Simulation time 89426574 ps
CPU time 2.2 seconds
Started Jul 15 07:22:47 PM PDT 24
Finished Jul 15 07:23:59 PM PDT 24
Peak memory 207088 kb
Host smart-350feffc-d3d7-4405-8af5-5c67592bd75e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893744623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.893744623
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.1285683086
Short name T785
Test name
Test status
Simulation time 1012341737 ps
CPU time 2.6 seconds
Started Jul 15 07:22:48 PM PDT 24
Finished Jul 15 07:24:01 PM PDT 24
Peak memory 207736 kb
Host smart-4b44e70e-86c0-4057-b22f-e2ac3c7312a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285683086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.1285683086
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.1552693736
Short name T405
Test name
Test status
Simulation time 1289460639 ps
CPU time 27.08 seconds
Started Jul 15 07:22:50 PM PDT 24
Finished Jul 15 07:24:28 PM PDT 24
Peak memory 208080 kb
Host smart-54e26f70-d7c0-46ee-afbb-c2153eae6401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552693736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.1552693736
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.2939529122
Short name T253
Test name
Test status
Simulation time 660806488 ps
CPU time 17.12 seconds
Started Jul 15 07:22:54 PM PDT 24
Finished Jul 15 07:24:20 PM PDT 24
Peak memory 216700 kb
Host smart-e4740430-b1a5-44fa-ad93-9c70f8a55a37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939529122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.2939529122
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.3018718093
Short name T527
Test name
Test status
Simulation time 1708213635 ps
CPU time 29.18 seconds
Started Jul 15 07:22:47 PM PDT 24
Finished Jul 15 07:24:26 PM PDT 24
Peak memory 208864 kb
Host smart-1feb6d9d-121d-49bf-9e45-d5b5d307c128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018718093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.3018718093
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.1039388837
Short name T530
Test name
Test status
Simulation time 72221756 ps
CPU time 1.8 seconds
Started Jul 15 07:22:54 PM PDT 24
Finished Jul 15 07:24:04 PM PDT 24
Peak memory 209892 kb
Host smart-84a9bf2b-2402-4bdf-93f2-3ca209d7b80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039388837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.1039388837
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.3730870994
Short name T556
Test name
Test status
Simulation time 7096787 ps
CPU time 0.79 seconds
Started Jul 15 07:22:53 PM PDT 24
Finished Jul 15 07:24:03 PM PDT 24
Peak memory 205944 kb
Host smart-8af1a1e8-deef-47cc-9f51-72163357e048
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730870994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.3730870994
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.1775964851
Short name T285
Test name
Test status
Simulation time 69060097 ps
CPU time 2.96 seconds
Started Jul 15 07:22:56 PM PDT 24
Finished Jul 15 07:24:09 PM PDT 24
Peak memory 214256 kb
Host smart-1bca8ee8-add2-4d2c-8d71-1a2a5ecfc511
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1775964851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.1775964851
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.1384777699
Short name T821
Test name
Test status
Simulation time 134350228 ps
CPU time 3.38 seconds
Started Jul 15 07:22:55 PM PDT 24
Finished Jul 15 07:24:09 PM PDT 24
Peak memory 209992 kb
Host smart-d93e90ad-1b09-49cf-9d73-2c14320421a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384777699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.1384777699
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.3866623309
Short name T545
Test name
Test status
Simulation time 1742492295 ps
CPU time 46.38 seconds
Started Jul 15 07:22:55 PM PDT 24
Finished Jul 15 07:24:52 PM PDT 24
Peak memory 214348 kb
Host smart-e37622d9-6c3c-4a54-b3c8-b8819d5f17c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866623309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.3866623309
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.3712122111
Short name T831
Test name
Test status
Simulation time 200091780 ps
CPU time 5.16 seconds
Started Jul 15 07:22:54 PM PDT 24
Finished Jul 15 07:24:08 PM PDT 24
Peak memory 214280 kb
Host smart-aa4ac457-89b3-44aa-82a1-c215247b8d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712122111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.3712122111
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_random.3187950423
Short name T694
Test name
Test status
Simulation time 709649704 ps
CPU time 12.56 seconds
Started Jul 15 07:22:47 PM PDT 24
Finished Jul 15 07:24:10 PM PDT 24
Peak memory 207456 kb
Host smart-fb8fa10b-d206-403a-be9a-ead11d7c2694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187950423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3187950423
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.492412675
Short name T718
Test name
Test status
Simulation time 83700932 ps
CPU time 3.4 seconds
Started Jul 15 07:22:48 PM PDT 24
Finished Jul 15 07:24:01 PM PDT 24
Peak memory 208540 kb
Host smart-0dcd2161-ee84-4a1c-abab-2b927680f2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492412675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.492412675
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1093278943
Short name T451
Test name
Test status
Simulation time 1875939498 ps
CPU time 9.83 seconds
Started Jul 15 07:22:53 PM PDT 24
Finished Jul 15 07:24:12 PM PDT 24
Peak memory 208668 kb
Host smart-7c2612d3-6cf4-4bd0-b517-3a5d5f424066
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093278943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1093278943
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.1696411593
Short name T923
Test name
Test status
Simulation time 208335335 ps
CPU time 2.8 seconds
Started Jul 15 07:22:51 PM PDT 24
Finished Jul 15 07:24:04 PM PDT 24
Peak memory 208696 kb
Host smart-f835cdb2-93d8-4958-b0bf-0741e978ad76
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696411593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.1696411593
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.541418177
Short name T337
Test name
Test status
Simulation time 492676000 ps
CPU time 6.12 seconds
Started Jul 15 07:22:49 PM PDT 24
Finished Jul 15 07:24:04 PM PDT 24
Peak memory 208700 kb
Host smart-3e5399c4-9550-42ee-a7f1-20a11272e520
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541418177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.541418177
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.648430483
Short name T335
Test name
Test status
Simulation time 216411560 ps
CPU time 2.13 seconds
Started Jul 15 07:22:53 PM PDT 24
Finished Jul 15 07:24:05 PM PDT 24
Peak memory 207372 kb
Host smart-0877a8e6-c35d-4f1e-8319-15835a619da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648430483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.648430483
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.1977211699
Short name T589
Test name
Test status
Simulation time 4618838650 ps
CPU time 25.92 seconds
Started Jul 15 07:22:50 PM PDT 24
Finished Jul 15 07:24:25 PM PDT 24
Peak memory 209008 kb
Host smart-856ca587-8134-4402-b4fc-d8da23922514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977211699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.1977211699
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.3561757452
Short name T811
Test name
Test status
Simulation time 267003142 ps
CPU time 11.17 seconds
Started Jul 15 07:22:54 PM PDT 24
Finished Jul 15 07:24:14 PM PDT 24
Peak memory 222656 kb
Host smart-84c6f15a-f6e2-41f7-8d21-9f3fd64c7851
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561757452 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.3561757452
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.3501427806
Short name T358
Test name
Test status
Simulation time 101040902 ps
CPU time 4.26 seconds
Started Jul 15 07:22:55 PM PDT 24
Finished Jul 15 07:24:07 PM PDT 24
Peak memory 207836 kb
Host smart-b6711ab1-8838-4d79-9709-42d70a6c6814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501427806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.3501427806
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.467040622
Short name T905
Test name
Test status
Simulation time 181404284 ps
CPU time 2.19 seconds
Started Jul 15 07:22:55 PM PDT 24
Finished Jul 15 07:24:08 PM PDT 24
Peak memory 210188 kb
Host smart-3cd1aa87-adc7-4f44-bc6b-0003ac14eafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467040622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.467040622
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.749002561
Short name T102
Test name
Test status
Simulation time 40025345 ps
CPU time 0.86 seconds
Started Jul 15 07:22:54 PM PDT 24
Finished Jul 15 07:24:03 PM PDT 24
Peak memory 205972 kb
Host smart-8467e051-7425-410e-92a3-0f53066f5762
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749002561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.749002561
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.930292628
Short name T724
Test name
Test status
Simulation time 196357370 ps
CPU time 1.94 seconds
Started Jul 15 07:22:55 PM PDT 24
Finished Jul 15 07:24:05 PM PDT 24
Peak memory 207516 kb
Host smart-024f7140-df0e-4ae5-bf83-520703d50c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930292628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.930292628
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.757316179
Short name T364
Test name
Test status
Simulation time 95141163 ps
CPU time 1.84 seconds
Started Jul 15 07:22:55 PM PDT 24
Finished Jul 15 07:24:07 PM PDT 24
Peak memory 214316 kb
Host smart-67bea4af-2700-42d0-a896-3f01d24b8ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757316179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.757316179
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.3229787329
Short name T789
Test name
Test status
Simulation time 104377437 ps
CPU time 2.54 seconds
Started Jul 15 07:22:55 PM PDT 24
Finished Jul 15 07:24:08 PM PDT 24
Peak memory 214332 kb
Host smart-41c35b8a-0988-40e3-b318-72f27a11f1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229787329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.3229787329
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.2165275708
Short name T406
Test name
Test status
Simulation time 142962366 ps
CPU time 2.42 seconds
Started Jul 15 07:22:54 PM PDT 24
Finished Jul 15 07:24:05 PM PDT 24
Peak memory 206688 kb
Host smart-f74426fb-d522-4e04-baa3-0502762247ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165275708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2165275708
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.2330326592
Short name T490
Test name
Test status
Simulation time 17406992333 ps
CPU time 39.54 seconds
Started Jul 15 07:22:55 PM PDT 24
Finished Jul 15 07:24:42 PM PDT 24
Peak memory 219840 kb
Host smart-18999c59-fbf1-49c4-b66e-85ea986c3b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330326592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.2330326592
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.1932940113
Short name T372
Test name
Test status
Simulation time 255381024 ps
CPU time 4.19 seconds
Started Jul 15 07:22:55 PM PDT 24
Finished Jul 15 07:24:07 PM PDT 24
Peak memory 208496 kb
Host smart-88a48020-9c3e-426c-82d7-d29d75e47d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932940113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.1932940113
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.2752574007
Short name T588
Test name
Test status
Simulation time 53486364 ps
CPU time 2.98 seconds
Started Jul 15 07:22:55 PM PDT 24
Finished Jul 15 07:24:06 PM PDT 24
Peak memory 208508 kb
Host smart-e677a488-bbd5-4be7-bfe6-6ca5eb2f3e4b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752574007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.2752574007
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.517867944
Short name T629
Test name
Test status
Simulation time 1314983461 ps
CPU time 15.17 seconds
Started Jul 15 07:22:55 PM PDT 24
Finished Jul 15 07:24:18 PM PDT 24
Peak memory 207856 kb
Host smart-534e3e8e-973f-4898-bab9-21d4401853d5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517867944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.517867944
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.2111868322
Short name T856
Test name
Test status
Simulation time 236649411 ps
CPU time 3.37 seconds
Started Jul 15 07:22:55 PM PDT 24
Finished Jul 15 07:24:09 PM PDT 24
Peak memory 208708 kb
Host smart-a2306aca-14f1-48bd-b24c-1324726b5b07
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111868322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2111868322
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.1132998156
Short name T461
Test name
Test status
Simulation time 123694634 ps
CPU time 3.66 seconds
Started Jul 15 07:22:54 PM PDT 24
Finished Jul 15 07:24:06 PM PDT 24
Peak memory 210172 kb
Host smart-b632e419-22d3-4c90-ae8c-421fb9da1fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132998156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.1132998156
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.236796947
Short name T514
Test name
Test status
Simulation time 38417300 ps
CPU time 1.62 seconds
Started Jul 15 07:22:55 PM PDT 24
Finished Jul 15 07:24:04 PM PDT 24
Peak memory 206952 kb
Host smart-9209d298-f24f-42ed-830d-f6a287d6de41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236796947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.236796947
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.3454709000
Short name T363
Test name
Test status
Simulation time 1133688322 ps
CPU time 12.59 seconds
Started Jul 15 07:22:56 PM PDT 24
Finished Jul 15 07:24:18 PM PDT 24
Peak memory 220276 kb
Host smart-febf860e-5fc5-433e-a897-96873cc0e12a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454709000 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.3454709000
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.1446082981
Short name T801
Test name
Test status
Simulation time 202636013 ps
CPU time 4.98 seconds
Started Jul 15 07:22:52 PM PDT 24
Finished Jul 15 07:24:07 PM PDT 24
Peak memory 207512 kb
Host smart-011b8c9d-a709-457f-9f98-08aad9d04591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446082981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1446082981
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.646736207
Short name T504
Test name
Test status
Simulation time 52945008 ps
CPU time 1.64 seconds
Started Jul 15 07:22:56 PM PDT 24
Finished Jul 15 07:24:07 PM PDT 24
Peak memory 209920 kb
Host smart-2db3ce20-d53e-4f64-9d5c-547c93d6a813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646736207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.646736207
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.3135799986
Short name T600
Test name
Test status
Simulation time 44814316 ps
CPU time 0.88 seconds
Started Jul 15 07:19:31 PM PDT 24
Finished Jul 15 07:20:29 PM PDT 24
Peak memory 206016 kb
Host smart-e6559601-932c-4aca-a6c2-3c03140dde3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135799986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.3135799986
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.4171617940
Short name T30
Test name
Test status
Simulation time 117184868 ps
CPU time 2.57 seconds
Started Jul 15 07:19:31 PM PDT 24
Finished Jul 15 07:20:31 PM PDT 24
Peak memory 215632 kb
Host smart-b1b443fb-5b0f-4879-890e-f152cd40b4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171617940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.4171617940
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.1375757035
Short name T909
Test name
Test status
Simulation time 274003419 ps
CPU time 6.26 seconds
Started Jul 15 07:19:29 PM PDT 24
Finished Jul 15 07:20:35 PM PDT 24
Peak memory 210368 kb
Host smart-1dcdc325-45a5-41cd-a4fa-c4a39cc93c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375757035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.1375757035
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.3927020732
Short name T739
Test name
Test status
Simulation time 137883089 ps
CPU time 2.39 seconds
Started Jul 15 07:19:31 PM PDT 24
Finished Jul 15 07:20:31 PM PDT 24
Peak memory 215340 kb
Host smart-5d7c8790-c091-4b8b-b17c-085facd9896a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927020732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.3927020732
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.1461786864
Short name T384
Test name
Test status
Simulation time 73183911 ps
CPU time 3.35 seconds
Started Jul 15 07:19:31 PM PDT 24
Finished Jul 15 07:20:32 PM PDT 24
Peak memory 210516 kb
Host smart-70d81e5b-905f-4452-8314-7539f9654a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461786864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.1461786864
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_random.3121184282
Short name T599
Test name
Test status
Simulation time 55038086 ps
CPU time 3.48 seconds
Started Jul 15 07:19:28 PM PDT 24
Finished Jul 15 07:20:32 PM PDT 24
Peak memory 209752 kb
Host smart-a8210860-bbb7-486f-8501-ca232a44e614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121184282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3121184282
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.2211142225
Short name T830
Test name
Test status
Simulation time 4504705574 ps
CPU time 40.61 seconds
Started Jul 15 07:19:30 PM PDT 24
Finished Jul 15 07:21:09 PM PDT 24
Peak memory 208804 kb
Host smart-62d287db-4b60-4664-a62c-278d871d7f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211142225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.2211142225
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.1168883258
Short name T928
Test name
Test status
Simulation time 2617236632 ps
CPU time 18.45 seconds
Started Jul 15 07:19:29 PM PDT 24
Finished Jul 15 07:20:47 PM PDT 24
Peak memory 208336 kb
Host smart-3334245f-905c-40b8-b35b-6f16c7d828fe
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168883258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.1168883258
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.2651899188
Short name T647
Test name
Test status
Simulation time 132348310 ps
CPU time 2.31 seconds
Started Jul 15 07:19:29 PM PDT 24
Finished Jul 15 07:20:31 PM PDT 24
Peak memory 207084 kb
Host smart-45fc9345-d39b-4d9c-aee9-bdbb915133cc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651899188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2651899188
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.2149616280
Short name T584
Test name
Test status
Simulation time 1088336596 ps
CPU time 25.72 seconds
Started Jul 15 07:19:26 PM PDT 24
Finished Jul 15 07:20:51 PM PDT 24
Peak memory 208896 kb
Host smart-59601756-a51e-4e5c-a31b-d456d3c72bba
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149616280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.2149616280
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.3871725821
Short name T376
Test name
Test status
Simulation time 198737778 ps
CPU time 2.87 seconds
Started Jul 15 07:19:31 PM PDT 24
Finished Jul 15 07:20:31 PM PDT 24
Peak memory 215756 kb
Host smart-a8fe569e-f47f-4797-bc05-4bcc14ba040b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871725821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.3871725821
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.2606071122
Short name T610
Test name
Test status
Simulation time 70114657 ps
CPU time 2.26 seconds
Started Jul 15 07:19:32 PM PDT 24
Finished Jul 15 07:20:30 PM PDT 24
Peak memory 206696 kb
Host smart-cdc488a4-82f0-477e-a102-6b8100c1cc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606071122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.2606071122
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.3857935359
Short name T194
Test name
Test status
Simulation time 692489966 ps
CPU time 25.66 seconds
Started Jul 15 07:19:32 PM PDT 24
Finished Jul 15 07:20:54 PM PDT 24
Peak memory 216736 kb
Host smart-a28b0b0c-7cae-4332-b32e-42ba34a09ccb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857935359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.3857935359
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.1536733266
Short name T168
Test name
Test status
Simulation time 778885119 ps
CPU time 15.76 seconds
Started Jul 15 07:19:32 PM PDT 24
Finished Jul 15 07:20:44 PM PDT 24
Peak memory 222472 kb
Host smart-5dae2b26-16fa-4f6c-8b5e-612b5e42567b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536733266 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.1536733266
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.525422710
Short name T399
Test name
Test status
Simulation time 3044764044 ps
CPU time 14.17 seconds
Started Jul 15 07:19:32 PM PDT 24
Finished Jul 15 07:20:43 PM PDT 24
Peak memory 216400 kb
Host smart-5b9e1b18-1a26-46a2-8702-547da11bfd4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525422710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.525422710
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.1338100588
Short name T903
Test name
Test status
Simulation time 2584341565 ps
CPU time 19.29 seconds
Started Jul 15 07:19:26 PM PDT 24
Finished Jul 15 07:20:44 PM PDT 24
Peak memory 211352 kb
Host smart-d9158ef5-033c-42ae-ad48-3f41e0aa87f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338100588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.1338100588
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.1051552918
Short name T632
Test name
Test status
Simulation time 27144381 ps
CPU time 0.92 seconds
Started Jul 15 07:19:56 PM PDT 24
Finished Jul 15 07:20:42 PM PDT 24
Peak memory 205996 kb
Host smart-37503427-36f8-400f-9be8-0fac297f229d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051552918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.1051552918
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.2463382815
Short name T136
Test name
Test status
Simulation time 190292030 ps
CPU time 4.13 seconds
Started Jul 15 07:19:39 PM PDT 24
Finished Jul 15 07:20:36 PM PDT 24
Peak memory 214340 kb
Host smart-a243097b-c432-4e63-8e50-c5e3347a4e16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2463382815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.2463382815
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.752735728
Short name T560
Test name
Test status
Simulation time 84251736 ps
CPU time 1.16 seconds
Started Jul 15 07:19:46 PM PDT 24
Finished Jul 15 07:20:36 PM PDT 24
Peak memory 214332 kb
Host smart-b8b85c8a-9eb9-48bb-91c5-4e478171f0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752735728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.752735728
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.4081527850
Short name T682
Test name
Test status
Simulation time 173120667 ps
CPU time 2.66 seconds
Started Jul 15 07:19:39 PM PDT 24
Finished Jul 15 07:20:34 PM PDT 24
Peak memory 208328 kb
Host smart-41dfc5eb-aad6-4a98-aea0-b1382fd84840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081527850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.4081527850
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.4182765900
Short name T458
Test name
Test status
Simulation time 63211907 ps
CPU time 3.54 seconds
Started Jul 15 07:19:45 PM PDT 24
Finished Jul 15 07:20:39 PM PDT 24
Peak memory 209464 kb
Host smart-6df0561b-f197-423e-8819-70a00c815443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182765900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.4182765900
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.1375864783
Short name T344
Test name
Test status
Simulation time 49120990 ps
CPU time 2.77 seconds
Started Jul 15 07:19:45 PM PDT 24
Finished Jul 15 07:20:38 PM PDT 24
Peak memory 222340 kb
Host smart-50ea964c-e683-4081-962a-ffbef039df4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375864783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.1375864783
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.578635250
Short name T882
Test name
Test status
Simulation time 154154632 ps
CPU time 2.34 seconds
Started Jul 15 07:19:39 PM PDT 24
Finished Jul 15 07:20:34 PM PDT 24
Peak memory 215784 kb
Host smart-917a488e-ac87-4ebe-89ad-d0f1e5cd63c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578635250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.578635250
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.3582341205
Short name T468
Test name
Test status
Simulation time 1163792293 ps
CPU time 12.62 seconds
Started Jul 15 07:19:39 PM PDT 24
Finished Jul 15 07:20:44 PM PDT 24
Peak memory 209496 kb
Host smart-c264d21b-6d33-40b5-bed7-1c9818fdf3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582341205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.3582341205
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.3957660807
Short name T280
Test name
Test status
Simulation time 591523425 ps
CPU time 4.27 seconds
Started Jul 15 07:19:34 PM PDT 24
Finished Jul 15 07:20:35 PM PDT 24
Peak memory 208368 kb
Host smart-eee34e02-59b6-43db-a42d-f921b3659bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957660807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.3957660807
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.333094417
Short name T552
Test name
Test status
Simulation time 55271964 ps
CPU time 3 seconds
Started Jul 15 07:19:38 PM PDT 24
Finished Jul 15 07:20:34 PM PDT 24
Peak memory 208160 kb
Host smart-f5260b9e-3907-48d3-a9a4-bb50d9ab78ae
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333094417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.333094417
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.916037758
Short name T732
Test name
Test status
Simulation time 123470700 ps
CPU time 3.74 seconds
Started Jul 15 07:19:39 PM PDT 24
Finished Jul 15 07:20:35 PM PDT 24
Peak memory 208892 kb
Host smart-ee1565a3-1b55-4e81-b3c9-4f4fec5c77f8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916037758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.916037758
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.1540952163
Short name T279
Test name
Test status
Simulation time 116185108 ps
CPU time 2.5 seconds
Started Jul 15 07:19:40 PM PDT 24
Finished Jul 15 07:20:37 PM PDT 24
Peak memory 208924 kb
Host smart-794cf6ec-9b40-43e8-b17a-a1ef685694b2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540952163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.1540952163
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.3119371745
Short name T748
Test name
Test status
Simulation time 40232609 ps
CPU time 1.75 seconds
Started Jul 15 07:19:45 PM PDT 24
Finished Jul 15 07:20:37 PM PDT 24
Peak memory 207840 kb
Host smart-5d8ef78a-6a94-41eb-9633-ddc7a9cff516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119371745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.3119371745
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.2337192707
Short name T453
Test name
Test status
Simulation time 172855196 ps
CPU time 3.84 seconds
Started Jul 15 07:19:34 PM PDT 24
Finished Jul 15 07:20:35 PM PDT 24
Peak memory 208356 kb
Host smart-e62bf419-4c23-470f-9cad-7b2a375be3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337192707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2337192707
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.2499302606
Short name T186
Test name
Test status
Simulation time 2183398873 ps
CPU time 17.74 seconds
Started Jul 15 07:19:45 PM PDT 24
Finished Jul 15 07:20:53 PM PDT 24
Peak memory 222804 kb
Host smart-2900373c-2017-47c0-b4d1-181106b6af40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499302606 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.2499302606
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2593893275
Short name T729
Test name
Test status
Simulation time 386886656 ps
CPU time 4.48 seconds
Started Jul 15 07:19:41 PM PDT 24
Finished Jul 15 07:20:39 PM PDT 24
Peak memory 210248 kb
Host smart-319de47b-29e9-4db7-835d-5c354f432587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593893275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2593893275
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.1268571649
Short name T199
Test name
Test status
Simulation time 120224455 ps
CPU time 3.78 seconds
Started Jul 15 07:19:45 PM PDT 24
Finished Jul 15 07:20:39 PM PDT 24
Peak memory 210252 kb
Host smart-846be1bd-28e9-4ac8-9ee8-2c45982a1d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268571649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.1268571649
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.3556697953
Short name T572
Test name
Test status
Simulation time 14733411 ps
CPU time 0.78 seconds
Started Jul 15 07:19:55 PM PDT 24
Finished Jul 15 07:20:38 PM PDT 24
Peak memory 205952 kb
Host smart-c3f37c2e-d787-43ec-bb9d-f4db902196a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556697953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.3556697953
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.4274037637
Short name T306
Test name
Test status
Simulation time 4329715582 ps
CPU time 61.26 seconds
Started Jul 15 07:19:55 PM PDT 24
Finished Jul 15 07:21:38 PM PDT 24
Peak memory 214368 kb
Host smart-074558d4-6adc-4ff8-b199-d3e2b5c816b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4274037637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.4274037637
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.2149447319
Short name T899
Test name
Test status
Simulation time 88596245 ps
CPU time 2.45 seconds
Started Jul 15 07:19:55 PM PDT 24
Finished Jul 15 07:20:40 PM PDT 24
Peak memory 206456 kb
Host smart-7cce554e-f55b-41f3-9b41-db4fde2208e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149447319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.2149447319
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.2712979154
Short name T309
Test name
Test status
Simulation time 103337464 ps
CPU time 2.05 seconds
Started Jul 15 07:19:51 PM PDT 24
Finished Jul 15 07:20:39 PM PDT 24
Peak memory 214844 kb
Host smart-9e81a301-4c6f-4710-a695-a776d795910d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712979154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2712979154
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.2323921410
Short name T919
Test name
Test status
Simulation time 97895810 ps
CPU time 4 seconds
Started Jul 15 07:19:55 PM PDT 24
Finished Jul 15 07:20:41 PM PDT 24
Peak memory 214348 kb
Host smart-0a85dc56-e71e-4fbb-8569-a43215a13725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323921410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.2323921410
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.2616593035
Short name T287
Test name
Test status
Simulation time 56186284 ps
CPU time 1.87 seconds
Started Jul 15 07:19:54 PM PDT 24
Finished Jul 15 07:20:39 PM PDT 24
Peak memory 214284 kb
Host smart-0698737a-dac8-4cb1-bbef-ab314b5a8b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616593035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.2616593035
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.4219769810
Short name T134
Test name
Test status
Simulation time 102074821 ps
CPU time 4.35 seconds
Started Jul 15 07:19:54 PM PDT 24
Finished Jul 15 07:20:42 PM PDT 24
Peak memory 219764 kb
Host smart-0501305a-e5bd-4f9e-b5f3-1734e3740a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219769810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.4219769810
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.3854975804
Short name T298
Test name
Test status
Simulation time 536030962 ps
CPU time 5.78 seconds
Started Jul 15 07:19:54 PM PDT 24
Finished Jul 15 07:20:44 PM PDT 24
Peak memory 214320 kb
Host smart-53b8cc5a-b900-4ef4-89b9-913b82c39d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854975804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.3854975804
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.3994246166
Short name T15
Test name
Test status
Simulation time 218081982 ps
CPU time 2.63 seconds
Started Jul 15 07:19:55 PM PDT 24
Finished Jul 15 07:20:41 PM PDT 24
Peak memory 206928 kb
Host smart-9ea5d54c-fd62-4ab4-a4f3-3b417a520f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994246166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.3994246166
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.1827289507
Short name T661
Test name
Test status
Simulation time 86412956 ps
CPU time 3.99 seconds
Started Jul 15 07:19:54 PM PDT 24
Finished Jul 15 07:20:41 PM PDT 24
Peak memory 208580 kb
Host smart-7e11ddcf-7ded-496d-8d41-18f6dac9c0cb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827289507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.1827289507
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.2230107613
Short name T768
Test name
Test status
Simulation time 161173582 ps
CPU time 4.23 seconds
Started Jul 15 07:19:53 PM PDT 24
Finished Jul 15 07:20:42 PM PDT 24
Peak memory 208728 kb
Host smart-d0690abf-c3d7-43c1-9fdc-2506ddbd2879
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230107613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.2230107613
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.1807138341
Short name T749
Test name
Test status
Simulation time 1677246599 ps
CPU time 40.91 seconds
Started Jul 15 07:19:57 PM PDT 24
Finished Jul 15 07:21:22 PM PDT 24
Peak memory 208392 kb
Host smart-4111cd98-d055-4e92-bc72-2a30245e3d6b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807138341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.1807138341
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.61928102
Short name T302
Test name
Test status
Simulation time 240160789 ps
CPU time 3.73 seconds
Started Jul 15 07:19:55 PM PDT 24
Finished Jul 15 07:20:41 PM PDT 24
Peak memory 214440 kb
Host smart-e842ab84-485e-4ae7-8063-5886c844ff5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61928102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.61928102
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.2864180594
Short name T678
Test name
Test status
Simulation time 232714228 ps
CPU time 2.59 seconds
Started Jul 15 07:19:54 PM PDT 24
Finished Jul 15 07:20:40 PM PDT 24
Peak memory 207172 kb
Host smart-8c4e4dd8-64a4-4e16-bdf3-8fdfc84dcb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864180594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.2864180594
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.953141316
Short name T828
Test name
Test status
Simulation time 2568393074 ps
CPU time 33.74 seconds
Started Jul 15 07:19:54 PM PDT 24
Finished Jul 15 07:21:11 PM PDT 24
Peak memory 216460 kb
Host smart-1d927fc4-bad1-4a5b-9713-51157066ca1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953141316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.953141316
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.1382838696
Short name T188
Test name
Test status
Simulation time 331207059 ps
CPU time 12.46 seconds
Started Jul 15 07:19:54 PM PDT 24
Finished Jul 15 07:20:50 PM PDT 24
Peak memory 222656 kb
Host smart-ab00a342-a3b5-4272-a477-9d2c1d2eb52e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382838696 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.1382838696
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2773850696
Short name T587
Test name
Test status
Simulation time 1707287905 ps
CPU time 10.23 seconds
Started Jul 15 07:19:53 PM PDT 24
Finished Jul 15 07:20:48 PM PDT 24
Peak memory 214252 kb
Host smart-c09ca890-be9b-4803-bfa5-c4ef9b3389f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773850696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2773850696
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3155513333
Short name T179
Test name
Test status
Simulation time 374003361 ps
CPU time 7.01 seconds
Started Jul 15 07:19:57 PM PDT 24
Finished Jul 15 07:20:47 PM PDT 24
Peak memory 210872 kb
Host smart-f513b28e-bd3d-423f-855e-0c23eb56e1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155513333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3155513333
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.2208395175
Short name T555
Test name
Test status
Simulation time 14570976 ps
CPU time 0.78 seconds
Started Jul 15 07:20:03 PM PDT 24
Finished Jul 15 07:20:42 PM PDT 24
Peak memory 206008 kb
Host smart-d78c49b7-24e7-41be-870f-a9b155d41e47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208395175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.2208395175
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.1845072714
Short name T766
Test name
Test status
Simulation time 107888475 ps
CPU time 2.73 seconds
Started Jul 15 07:19:59 PM PDT 24
Finished Jul 15 07:20:43 PM PDT 24
Peak memory 215024 kb
Host smart-8efb582d-4b0f-4e2e-bfc6-53ddd0c8e2d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1845072714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.1845072714
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.169646589
Short name T637
Test name
Test status
Simulation time 100656620 ps
CPU time 3.94 seconds
Started Jul 15 07:20:02 PM PDT 24
Finished Jul 15 07:20:46 PM PDT 24
Peak memory 209620 kb
Host smart-231d49a4-a814-47f2-b499-94c66ae18438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169646589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.169646589
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.921913583
Short name T480
Test name
Test status
Simulation time 128197914 ps
CPU time 1.77 seconds
Started Jul 15 07:20:00 PM PDT 24
Finished Jul 15 07:20:43 PM PDT 24
Peak memory 207112 kb
Host smart-1bcabfea-a134-4f66-8761-135287ce77cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921913583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.921913583
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.1785317484
Short name T4
Test name
Test status
Simulation time 881637697 ps
CPU time 6.44 seconds
Started Jul 15 07:20:00 PM PDT 24
Finished Jul 15 07:20:47 PM PDT 24
Peak memory 209800 kb
Host smart-7648e4a4-177f-4b97-8002-ae1cb8a8e366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785317484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1785317484
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.2575901203
Short name T877
Test name
Test status
Simulation time 35896978 ps
CPU time 2.08 seconds
Started Jul 15 07:20:02 PM PDT 24
Finished Jul 15 07:20:43 PM PDT 24
Peak memory 214212 kb
Host smart-eb92fe36-7ba9-4018-987e-33e306b89251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575901203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.2575901203
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1057806966
Short name T885
Test name
Test status
Simulation time 253423374 ps
CPU time 3.46 seconds
Started Jul 15 07:20:00 PM PDT 24
Finished Jul 15 07:20:44 PM PDT 24
Peak memory 220188 kb
Host smart-52c000c6-26c4-47d7-9d36-a160fb01358c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057806966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1057806966
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.4280602702
Short name T902
Test name
Test status
Simulation time 65117816 ps
CPU time 3.61 seconds
Started Jul 15 07:20:02 PM PDT 24
Finished Jul 15 07:20:45 PM PDT 24
Peak memory 214288 kb
Host smart-7be3d53f-2c55-4ee4-9f0e-74d3a993c889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280602702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.4280602702
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.664103078
Short name T491
Test name
Test status
Simulation time 2061827986 ps
CPU time 21.02 seconds
Started Jul 15 07:19:57 PM PDT 24
Finished Jul 15 07:21:01 PM PDT 24
Peak memory 208860 kb
Host smart-5cdf37a9-60e0-442c-8970-42b6643b41a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664103078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.664103078
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.482818913
Short name T638
Test name
Test status
Simulation time 97857780 ps
CPU time 2.24 seconds
Started Jul 15 07:19:57 PM PDT 24
Finished Jul 15 07:20:43 PM PDT 24
Peak memory 206796 kb
Host smart-b828fb76-4792-4caa-9df8-2214826e0e98
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482818913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.482818913
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.1741231468
Short name T913
Test name
Test status
Simulation time 37702866 ps
CPU time 2.54 seconds
Started Jul 15 07:19:55 PM PDT 24
Finished Jul 15 07:20:40 PM PDT 24
Peak memory 208620 kb
Host smart-02095817-f3a4-47cd-b150-34c27411a660
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741231468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.1741231468
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.2514981619
Short name T734
Test name
Test status
Simulation time 109762814 ps
CPU time 3.5 seconds
Started Jul 15 07:19:54 PM PDT 24
Finished Jul 15 07:20:41 PM PDT 24
Peak memory 206972 kb
Host smart-991eed23-5219-457b-b157-9e8516a79b97
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514981619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.2514981619
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.1838260899
Short name T130
Test name
Test status
Simulation time 115121218 ps
CPU time 2.08 seconds
Started Jul 15 07:19:58 PM PDT 24
Finished Jul 15 07:20:43 PM PDT 24
Peak memory 208292 kb
Host smart-39e5b845-a013-4665-9de8-3e148df3627e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838260899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.1838260899
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.134383912
Short name T400
Test name
Test status
Simulation time 105408105 ps
CPU time 2.05 seconds
Started Jul 15 07:19:53 PM PDT 24
Finished Jul 15 07:20:39 PM PDT 24
Peak memory 206784 kb
Host smart-c17bce7b-6ce2-4b98-a01c-12a938c8b28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134383912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.134383912
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.2283554899
Short name T195
Test name
Test status
Simulation time 2166456124 ps
CPU time 16.73 seconds
Started Jul 15 07:20:01 PM PDT 24
Finished Jul 15 07:20:58 PM PDT 24
Peak memory 221696 kb
Host smart-445af9ec-7cb6-40b6-9198-af4124ca5837
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283554899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.2283554899
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.1698386410
Short name T798
Test name
Test status
Simulation time 691812150 ps
CPU time 9.36 seconds
Started Jul 15 07:19:59 PM PDT 24
Finished Jul 15 07:20:50 PM PDT 24
Peak memory 222580 kb
Host smart-59a7fd1a-9c50-41bc-82cf-0acc98d410ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698386410 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.1698386410
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.42998746
Short name T633
Test name
Test status
Simulation time 571686653 ps
CPU time 6.62 seconds
Started Jul 15 07:19:58 PM PDT 24
Finished Jul 15 07:20:47 PM PDT 24
Peak memory 209132 kb
Host smart-b32fd1b5-c384-4c17-a3af-504029f9d89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42998746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.42998746
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.2508818408
Short name T751
Test name
Test status
Simulation time 285199341 ps
CPU time 3 seconds
Started Jul 15 07:19:57 PM PDT 24
Finished Jul 15 07:20:44 PM PDT 24
Peak memory 210028 kb
Host smart-e4126dd4-7653-4049-ab3a-3fbff0b5ae11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508818408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.2508818408
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.887266824
Short name T657
Test name
Test status
Simulation time 17160065 ps
CPU time 0.79 seconds
Started Jul 15 07:20:06 PM PDT 24
Finished Jul 15 07:20:44 PM PDT 24
Peak memory 205940 kb
Host smart-67086445-b0ee-46d8-9cba-189e8dfe170f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887266824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.887266824
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.3622008591
Short name T239
Test name
Test status
Simulation time 59820167 ps
CPU time 4.04 seconds
Started Jul 15 07:20:00 PM PDT 24
Finished Jul 15 07:20:45 PM PDT 24
Peak memory 215016 kb
Host smart-c5038296-3d7a-4a68-a050-fdaa0bcf083e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3622008591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3622008591
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.3311508741
Short name T24
Test name
Test status
Simulation time 140720803 ps
CPU time 2.23 seconds
Started Jul 15 07:19:59 PM PDT 24
Finished Jul 15 07:20:43 PM PDT 24
Peak memory 222344 kb
Host smart-ff00059b-014a-44d5-ac20-63160e519918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311508741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.3311508741
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.2011214609
Short name T56
Test name
Test status
Simulation time 75672791 ps
CPU time 3.51 seconds
Started Jul 15 07:20:03 PM PDT 24
Finished Jul 15 07:20:45 PM PDT 24
Peak memory 214344 kb
Host smart-80aa5510-9d7f-4b9f-b075-0eb11f33ad66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011214609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.2011214609
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.3376146908
Short name T45
Test name
Test status
Simulation time 360919326 ps
CPU time 2.44 seconds
Started Jul 15 07:20:04 PM PDT 24
Finished Jul 15 07:20:44 PM PDT 24
Peak memory 214308 kb
Host smart-fdfcc007-3601-4237-8ea2-cd121cde63f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376146908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.3376146908
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.2195212251
Short name T103
Test name
Test status
Simulation time 388062836 ps
CPU time 4.71 seconds
Started Jul 15 07:20:01 PM PDT 24
Finished Jul 15 07:20:46 PM PDT 24
Peak memory 222340 kb
Host smart-ae9cc3d9-4288-4a46-ad8a-fde0a7516f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195212251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.2195212251
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.3431724913
Short name T353
Test name
Test status
Simulation time 58959715 ps
CPU time 3.32 seconds
Started Jul 15 07:19:59 PM PDT 24
Finished Jul 15 07:20:44 PM PDT 24
Peak memory 209800 kb
Host smart-05999903-6412-4de1-87b7-62e71e14a8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431724913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.3431724913
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.2058026088
Short name T284
Test name
Test status
Simulation time 3027592609 ps
CPU time 36.33 seconds
Started Jul 15 07:20:04 PM PDT 24
Finished Jul 15 07:21:18 PM PDT 24
Peak memory 210404 kb
Host smart-55c873bf-1fb8-4558-a303-82556f180f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058026088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2058026088
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.4083801879
Short name T846
Test name
Test status
Simulation time 97718929 ps
CPU time 2.73 seconds
Started Jul 15 07:19:58 PM PDT 24
Finished Jul 15 07:20:44 PM PDT 24
Peak memory 208804 kb
Host smart-e478716c-3f24-4306-ab0c-77b9e976372f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083801879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.4083801879
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.2486308681
Short name T531
Test name
Test status
Simulation time 490505991 ps
CPU time 5.8 seconds
Started Jul 15 07:20:00 PM PDT 24
Finished Jul 15 07:20:47 PM PDT 24
Peak memory 208472 kb
Host smart-923b90fa-866e-475b-87b4-4a048bfbaeab
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486308681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.2486308681
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.182354653
Short name T437
Test name
Test status
Simulation time 70715149 ps
CPU time 2.74 seconds
Started Jul 15 07:20:04 PM PDT 24
Finished Jul 15 07:20:44 PM PDT 24
Peak memory 208692 kb
Host smart-af62899f-d7d0-4f5e-aeb4-9ffb044ff5ac
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182354653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.182354653
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.2229028768
Short name T719
Test name
Test status
Simulation time 315296348 ps
CPU time 5.06 seconds
Started Jul 15 07:20:04 PM PDT 24
Finished Jul 15 07:20:47 PM PDT 24
Peak memory 208736 kb
Host smart-87da2006-187d-4a67-8e7b-ccc48aff7bba
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229028768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.2229028768
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.443455590
Short name T825
Test name
Test status
Simulation time 129212108 ps
CPU time 3.24 seconds
Started Jul 15 07:20:00 PM PDT 24
Finished Jul 15 07:20:44 PM PDT 24
Peak memory 218220 kb
Host smart-6a9c4e40-4294-4af6-90ce-d87d57068715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443455590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.443455590
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.1075537984
Short name T843
Test name
Test status
Simulation time 440219247 ps
CPU time 3.9 seconds
Started Jul 15 07:19:59 PM PDT 24
Finished Jul 15 07:20:45 PM PDT 24
Peak memory 206756 kb
Host smart-b3cde11a-0b50-4f36-8bad-6eecfbc9839a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075537984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1075537984
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.359074228
Short name T329
Test name
Test status
Simulation time 5214715166 ps
CPU time 50.21 seconds
Started Jul 15 07:20:00 PM PDT 24
Finished Jul 15 07:21:31 PM PDT 24
Peak memory 222480 kb
Host smart-d53fcb7c-b7ba-471e-b427-3124b6222eab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359074228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.359074228
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.2116882336
Short name T125
Test name
Test status
Simulation time 1333493480 ps
CPU time 18.8 seconds
Started Jul 15 07:20:01 PM PDT 24
Finished Jul 15 07:21:00 PM PDT 24
Peak memory 222568 kb
Host smart-df441791-e010-4456-95f1-f1d16ffa7dab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116882336 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.2116882336
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.3525354727
Short name T849
Test name
Test status
Simulation time 888805535 ps
CPU time 26.04 seconds
Started Jul 15 07:20:00 PM PDT 24
Finished Jul 15 07:21:07 PM PDT 24
Peak memory 218416 kb
Host smart-46353adc-9115-4f43-a672-3303561b0790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525354727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.3525354727
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.3078449752
Short name T799
Test name
Test status
Simulation time 106483844 ps
CPU time 2.78 seconds
Started Jul 15 07:20:01 PM PDT 24
Finished Jul 15 07:20:44 PM PDT 24
Peak memory 210476 kb
Host smart-a0544031-8c83-4114-97fe-19c6850ab0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078449752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.3078449752
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%