Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
76.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	14	35	71.43

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	13	22	62.86	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	44	1			T17	1		T26	1		T28	1
auto[OpGenId]	8	1			T59	1		T63	1		T146	1
auto[OpGenSwOut]	21	1			T225	1		T7	1		T36	1
auto[OpGenHwOut]	16	1			T29	1		T7	1		T12	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1663	1			T3	90		T28	3		T57	1
auto[StInit]	82	1			T43	1		T28	1		T47	1
auto[StCreatorRootKey]	53	1			T6	1		T17	1		T26	1
auto[StOwnerIntKey]	57	1			T57	2		T62	1		T123	1
auto[StOwnerKey]	44	1			T57	1		T85	1		T112	1
auto[StDisabled]	428	1			T17	16		T28	7		T140	3
auto[StInvalid]	50	1			T41	1		T39	1		T27	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3372

1

T1

1

T2

1

T3

91

auto[1]

89

1

T17

1

T26

1

T59

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1657	1			T3	90		T28	3		T57	1
auto[StReset]	auto[1]	6	1			T55	1		T147	1		T45	1
auto[StInit]	auto[0]	51	1			T43	1		T47	1		T33	1
auto[StInit]	auto[1]	31	1			T28	1		T7	2		T226	1
auto[StCreatorRootKey]	auto[0]	33	1			T6	1		T17	1		T28	1
auto[StCreatorRootKey]	auto[1]	20	1			T26	1		T59	1		T29	1
auto[StOwnerIntKey]	auto[0]	45	1			T57	2		T62	1		T123	1
auto[StOwnerIntKey]	auto[1]	12	1			T63	1		T11	1		T12	1
auto[StOwnerKey]	auto[0]	36	1			T57	1		T85	1		T112	1
auto[StOwnerKey]	auto[1]	8	1			T227	1		T228	1		T229	2
auto[StDisabled]	auto[0]	416	1			T17	15		T28	7		T140	3
auto[StDisabled]	auto[1]	12	1			T17	1		T230	1		T231	1
auto[StInvalid]	auto[0]	50	1			T41	1		T39	1		T27	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	13	22	62.86	13

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId]]	0	1	1
[auto[StReset]]	[auto[OpGenHwOut] , auto[OpDisable]]	--	--	2
[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey] , auto[StDisabled]]	[auto[OpDisable]]	--	--	5

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	5	1			T55	1		T147	1		T232	2
auto[StReset]	auto[OpGenSwOut]	1	1			T45	1		-	-		-	-
auto[StInit]	auto[OpAdvance]	15	1			T28	1		T226	1		T9	1
auto[StInit]	auto[OpGenId]	1	1			T233	1		-	-		-	-
auto[StInit]	auto[OpGenSwOut]	10	1			T7	1		T58	2		T182	1
auto[StInit]	auto[OpGenHwOut]	5	1			T7	1		T234	1		T235	1
auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T26	1		T236	1		T237	1
auto[StCreatorRootKey]	auto[OpGenId]	2	1			T59	1		T146	1		-	-
auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T225	1		T36	1		T238	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	4	1			T29	1		T52	2		T239	1
auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T11	1		T240	1		T241	1
auto[StOwnerIntKey]	auto[OpGenId]	2	1			T63	1		T34	1		-	-
auto[StOwnerIntKey]	auto[OpGenSwOut]	1	1			T242	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpGenHwOut]	3	1			T12	1		T8	1		T232	1
auto[StOwnerKey]	auto[OpAdvance]	3	1			T227	1		T229	1		T243	1
auto[StOwnerKey]	auto[OpGenId]	2	1			T244	1		T32	1		-	-
auto[StOwnerKey]	auto[OpGenSwOut]	1	1			T245	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	2	1			T228	1		T229	1		-	-
auto[StDisabled]	auto[OpAdvance]	7	1			T17	1		T230	1		T246	1
auto[StDisabled]	auto[OpGenId]	1	1			T231	1		-	-		-	-
auto[StDisabled]	auto[OpGenSwOut]	2	1			T52	1		T247	1		-	-
auto[StDisabled]	auto[OpGenHwOut]	2	1			T248	1		T249	1		-	-