Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.58	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	74	256	77.58

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	55	225	80.36	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4806

1

T2

2

T4

4

T17

62

auto[1]

546

1

T4

4

T17

3

T38

2

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4806

1

T2

2

T4

4

T17

62

auto[1]

546

1

T4

4

T17

3

T38

2

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4833

1

T2

1

T4

8

T17

60

auto[1]

519

1

T2

1

T17

5

T28

7

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4833

1

T2

1

T4

8

T17

60

auto[1]

519

1

T2

1

T17

5

T28

7

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	432	1			T2	1		T17	6		T41	1
auto[OpGenId]	1172	1			T17	20		T18	2		T41	2
auto[OpGenSwOut]	1133	1			T17	21		T18	3		T41	3
auto[OpGenHwOut]	2552	1			T2	1		T4	8		T17	16
auto[OpDisable]	63	1			T17	2		T28	2		T53	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	432	1			T2	1		T17	6		T41	1
auto[OpGenId]	1172	1			T17	20		T18	2		T41	2
auto[OpGenSwOut]	1133	1			T17	21		T18	3		T41	3
auto[OpGenHwOut]	2552	1			T2	1		T4	8		T17	16
auto[OpDisable]	63	1			T17	2		T28	2		T53	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4778

1

T2

1

T4

8

T17

58

auto[1]

574

1

T2

1

T17

7

T18

1

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4778

1

T2

1

T4

8

T17

58

auto[1]

574

1

T2

1

T17

7

T18

1

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5051

1

T2

2

T4

8

T17

65

auto[1]

301

1

T88

6

T91

5

T130

3

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1759	1			T2	1		T4	2		T17	17
auto[1]	744	1			T17	11		T19	2		T38	3
auto[2]	713	1			T17	6		T19	2		T41	1
auto[3]	713	1			T4	3		T17	9		T18	2
auto[4]	356	1			T17	4		T18	1		T41	1
auto[5]	347	1			T2	1		T4	1		T17	5
auto[6]	354	1			T4	1		T17	8		T18	1
auto[7]	366	1			T4	1		T17	5		T18	2

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1423	1			T2	1		T4	3		T17	22
clear_one[1]	744	1			T17	11		T19	2		T38	3
clear_one[2]	713	1			T17	6		T19	2		T41	1
clear_one[3]	713	1			T4	3		T17	9		T18	2
clear_none	1759	1			T2	1		T4	2		T17	17

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	995	1			T17	20		T18	3		T38	2
auto[StInit]	640	1			T4	1		T17	6		T19	1
auto[StCreatorRootKey]	588	1			T2	1		T4	1		T17	6
auto[StOwnerIntKey]	518	1			T2	1		T4	1		T17	6
auto[StOwnerKey]	481	1			T4	1		T17	6		T18	1
auto[StDisabled]	1823	1			T4	4		T17	21		T18	3
auto[StInvalid]	307	1			T41	6		T42	3		T39	4

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	995	1			T17	20		T18	3		T38	2
auto[StInit]	640	1			T4	1		T17	6		T19	1
auto[StCreatorRootKey]	588	1			T2	1		T4	1		T17	6
auto[StOwnerIntKey]	518	1			T2	1		T4	1		T17	6
auto[StOwnerKey]	481	1			T4	1		T17	6		T18	1
auto[StDisabled]	1823	1			T4	4		T17	21		T18	3
auto[StInvalid]	307	1			T41	6		T42	3		T39	4

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	55	225	80.36	55

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[1]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[1]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[1]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[2]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[2]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[3]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[3]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[3]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[4]]	[auto[StInvalid]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[5] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	3
[auto[5] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	3
[auto[5] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	12
[auto[5] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	4	1			T141	1		T250	1		T251	1
auto[0]	auto[StReset]	auto[OpGenId]	176	1			T17	2		T18	1		T59	2
auto[0]	auto[StReset]	auto[OpGenSwOut]	155	1			T17	4		T27	2		T28	2
auto[0]	auto[StReset]	auto[OpGenHwOut]	231	1			T17	2		T38	1		T42	1
auto[0]	auto[StInit]	auto[OpAdvance]	44	1			T17	1		T85	1		T91	1
auto[0]	auto[StInit]	auto[OpGenId]	91	1			T28	2		T93	1		T23	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	91	1			T17	1		T27	1		T28	2
auto[0]	auto[StInit]	auto[OpGenHwOut]	174	1			T4	1		T19	1		T38	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	22	1			T17	1		T57	1		T220	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	56	1			T17	1		T26	1		T139	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	48	1			T28	1		T88	1		T77	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	87	1			T2	1		T40	1		T92	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	11	1			T252	1		T253	1		T250	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	30	1			T254	1		T141	1		T123	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	29	1			T140	1		T57	1		T134	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	59	1			T4	1		T17	1		T40	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T130	1		T58	1		T255	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	20	1			T17	1		T140	1		T125	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	17	1			T28	1		T57	1		T7	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	44	1			T28	1		T212	1		T256	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	30	1			T17	1		T88	3		T130	1
auto[0]	auto[StDisabled]	auto[OpGenId]	52	1			T17	1		T28	1		T140	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	49	1			T17	1		T18	1		T28	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	141	1			T38	1		T40	2		T140	1
auto[0]	auto[StDisabled]	auto[OpDisable]	13	1			T7	1		T75	1		T257	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	8	1			T41	1		T42	1		T90	1
auto[0]	auto[StInvalid]	auto[OpGenId]	26	1			T258	1		T111	1		T98	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	31	1			T259	2		T258	1		T96	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	14	1			T39	1		T260	1		T261	1
auto[1]	auto[StReset]	auto[OpGenId]	22	1			T28	1		T33	1		T74	2
auto[1]	auto[StReset]	auto[OpGenSwOut]	24	1			T17	1		T112	2		T81	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	37	1			T27	1		T140	1		T57	1
auto[1]	auto[StInit]	auto[OpAdvance]	6	1			T262	1		T201	1		T263	1
auto[1]	auto[StInit]	auto[OpGenId]	17	1			T17	2		T94	1		T71	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	6	1			T94	1		T223	1		T58	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	17	1			T264	1		T265	1		T266	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T257	1		T267	2		T232	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	15	1			T91	1		T7	1		T262	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	22	1			T53	1		T57	1		T268	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	39	1			T38	1		T264	1		T72	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	16	1			T269	2		T263	1		T52	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	17	1			T17	1		T140	1		T219	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	23	1			T17	1		T92	1		T112	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	51	1			T19	1		T28	1		T91	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T270	1		T271	1		T272	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	17	1			T112	1		T7	1		T262	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	21	1			T17	1		T57	1		T91	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	47	1			T38	1		T40	1		T140	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	17	1			T88	1		T7	1		T131	1
auto[1]	auto[StDisabled]	auto[OpGenId]	59	1			T17	4		T28	1		T57	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	47	1			T17	1		T28	1		T140	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	154	1			T19	1		T38	1		T28	1
auto[1]	auto[StDisabled]	auto[OpDisable]	8	1			T28	2		T200	1		T273	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	10	1			T259	1		T97	1		T274	1
auto[1]	auto[StInvalid]	auto[OpGenId]	13	1			T90	1		T99	1		T60	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	18	1			T23	1		T259	1		T275	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T39	1		T276	1		T277	1
auto[2]	auto[StReset]	auto[OpAdvance]	1	1			T201	1		-	-		-	-
auto[2]	auto[StReset]	auto[OpGenId]	24	1			T278	1		T262	1		T279	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	17	1			T17	1		T29	1		T275	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	40	1			T17	2		T86	3		T280	1
auto[2]	auto[StInit]	auto[OpAdvance]	6	1			T201	1		T95	1		T281	1
auto[2]	auto[StInit]	auto[OpGenId]	7	1			T7	1		T282	1		T242	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	11	1			T81	1		T283	1		T242	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	28	1			T40	1		T112	1		T284	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T8	1		T285	1		T270	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	17	1			T74	1		T286	1		T183	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T123	1		T278	1		T11	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	45	1			T86	1		T284	1		T287	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	10	1			T65	1		T288	1		T289	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	21	1			T125	1		T290	1		T257	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	16	1			T17	1		T28	1		T291	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	36	1			T264	1		T292	1		T265	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T293	1		T52	1		T294	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	10	1			T72	1		T110	1		T58	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	13	1			T17	1		T295	1		T131	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	42	1			T139	1		T265	1		T7	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	28	1			T296	1		T262	1		T269	1
auto[2]	auto[StDisabled]	auto[OpGenId]	65	1			T93	1		T140	2		T85	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	52	1			T112	1		T77	1		T141	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	146	1			T19	2		T211	1		T140	1
auto[2]	auto[StDisabled]	auto[OpDisable]	10	1			T17	1		T53	1		T81	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	7	1			T27	1		T97	1		T297	1
auto[2]	auto[StInvalid]	auto[OpGenId]	10	1			T258	1		T111	1		T98	2
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	16	1			T41	1		T60	1		T260	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T99	1		T298	1		T260	1
auto[3]	auto[StReset]	auto[OpGenId]	23	1			T17	1		T57	1		T111	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	16	1			T28	1		T140	1		T299	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	49	1			T17	1		T18	1		T280	1
auto[3]	auto[StInit]	auto[OpAdvance]	6	1			T295	1		T300	1		T133	1
auto[3]	auto[StInit]	auto[OpGenId]	11	1			T108	1		T228	1		T301	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	15	1			T57	1		T262	3		T227	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	29	1			T57	1		T292	1		T94	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T29	1		T223	1		T302	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T17	1		T81	1		T253	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T133	1		T303	1		T237	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	37	1			T4	1		T19	1		T89	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T71	1		T7	1		T257	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T7	1		T304	1		T305	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	13	1			T17	1		T81	1		T306	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	37	1			T85	1		T280	1		T284	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T307	1		T308	1		T241	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	18	1			T220	1		T71	1		T123	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	21	1			T18	1		T57	1		T112	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	43	1			T28	1		T89	1		T264	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	19	1			T17	1		T92	1		T123	1
auto[3]	auto[StDisabled]	auto[OpGenId]	53	1			T17	1		T28	2		T112	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	56	1			T17	1		T28	1		T140	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	173	1			T4	2		T17	2		T38	1
auto[3]	auto[StDisabled]	auto[OpDisable]	8	1			T253	1		T309	1		T52	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	11	1			T23	1		T96	2		T310	1
auto[3]	auto[StInvalid]	auto[OpGenId]	11	1			T96	1		T111	1		T260	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	13	1			T259	1		T258	1		T111	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T311	1		T312	1		T313	1
auto[4]	auto[StReset]	auto[OpGenId]	11	1			T85	1		T54	1		T7	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	11	1			T28	2		T314	1		T315	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	30	1			T17	1		T38	1		T140	1
auto[4]	auto[StInit]	auto[OpAdvance]	2	1			T316	1		T207	1		-	-
auto[4]	auto[StInit]	auto[OpGenId]	1	1			T242	1		-	-		-	-
auto[4]	auto[StInit]	auto[OpGenSwOut]	4	1			T223	1		T228	1		T233	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	11	1			T24	1		T124	1		T317	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T318	1		T319	1		T320	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T24	1		T124	1		T321	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T322	1		T309	1		T229	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	19	1			T17	1		T256	1		T323	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	10	1			T27	1		T88	1		T7	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T324	1		T244	1		T207	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T321	1		T279	1		T325	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	11	1			T86	1		T326	1		T327	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T328	1		T7	1		T133	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	4	1			T81	1		T257	1		T229	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T17	1		T329	1		T286	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	25	1			T211	1		T330	1		T317	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	13	1			T7	1		T305	1		T110	1
auto[4]	auto[StDisabled]	auto[OpGenId]	32	1			T18	1		T130	1		T7	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	26	1			T123	1		T58	2		T329	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	77	1			T28	1		T89	1		T112	1
auto[4]	auto[StDisabled]	auto[OpDisable]	10	1			T17	1		T123	1		T70	1
auto[4]	auto[StInvalid]	auto[OpGenId]	3	1			T90	1		T331	1		T312	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T41	1		T205	1		T277	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T54	1		T97	1		T332	1
auto[5]	auto[StReset]	auto[OpGenId]	7	1			T253	1		T105	1		T333	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	10	1			T33	1		T295	1		T74	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	13	1			T17	2		T29	1		T79	1
auto[5]	auto[StInit]	auto[OpAdvance]	1	1			T334	1		-	-		-	-
auto[5]	auto[StInit]	auto[OpGenId]	3	1			T7	1		T183	1		T335	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	5	1			T133	1		T309	1		T244	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	13	1			T131	1		T336	1		T337	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T7	1		T34	1		-	-
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T123	1		T79	1		T315	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T17	1		T131	2		T70	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	19	1			T211	1		T280	1		T292	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T2	1		T123	1		T307	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T57	1		T133	1		T52	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T85	1		T286	1		T309	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T38	1		T330	1		T338	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T324	1		T339	1		T340	2
auto[5]	auto[StOwnerKey]	auto[OpGenId]	6	1			T125	1		T293	1		T341	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	11	1			T85	1		T342	1		T343	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	19	1			T4	1		T19	1		T86	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	10	1			T28	1		T7	1		T344	1
auto[5]	auto[StDisabled]	auto[OpGenId]	29	1			T17	1		T85	1		T58	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	32	1			T295	1		T300	1		T286	2
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	84	1			T17	1		T40	1		T212	1
auto[5]	auto[StDisabled]	auto[OpDisable]	4	1			T77	1		T123	1		T345	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	6	1			T42	1		T23	2		T332	1
auto[5]	auto[StInvalid]	auto[OpGenId]	7	1			T346	1		T274	1		T347	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T39	1		T60	1		T111	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T313	1		T348	1		T349	2
auto[6]	auto[StReset]	auto[OpGenId]	15	1			T53	1		T112	1		T315	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	11	1			T17	1		T18	1		T350	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	24	1			T17	1		T89	1		T287	3
auto[6]	auto[StInit]	auto[OpAdvance]	3	1			T17	1		T251	1		T351	1
auto[6]	auto[StInit]	auto[OpGenId]	7	1			T218	1		T112	1		T257	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	3	1			T28	1		T253	1		T344	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	8	1			T17	1		T59	1		T352	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T353	1		T354	1		T355	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T17	1		T57	1		T85	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T85	1		T356	1		T251	2
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	18	1			T212	1		T357	1		T266	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T358	1		T359	1		T360	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	2	1			T237	1		T361	1		-	-
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T7	1		T68	1		T362	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	16	1			T363	1		T364	1		T52	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T365	2		T103	1		T366	2
auto[6]	auto[StOwnerKey]	auto[OpGenId]	3	1			T299	1		T74	1		T367	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T17	1		T181	1		T52	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	19	1			T368	1		T7	1		T279	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	19	1			T7	1		T132	2		T134	1
auto[6]	auto[StDisabled]	auto[OpGenId]	24	1			T17	1		T369	1		T7	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	26	1			T141	1		T370	1		T134	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	80	1			T4	1		T17	1		T86	2
auto[6]	auto[StDisabled]	auto[OpDisable]	7	1			T371	1		T58	1		T372	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	4	1			T99	2		T373	1		T374	1
auto[6]	auto[StInvalid]	auto[OpGenId]	9	1			T41	2		T275	1		T375	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T41	1		T331	1		T376	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T99	1		T375	1		T377	1
auto[7]	auto[StReset]	auto[OpGenId]	8	1			T236	1		T253	1		T52	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	9	1			T17	1		T291	1		T275	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	27	1			T89	1		T284	1		T299	1
auto[7]	auto[StInit]	auto[OpAdvance]	1	1			T378	1		-	-		-	-
auto[7]	auto[StInit]	auto[OpGenId]	6	1			T53	1		T379	1		T324	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	2	1			T253	1		T359	1		-	-
auto[7]	auto[StInit]	auto[OpGenHwOut]	11	1			T86	1		T280	1		T380	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T381	1		T382	1		-	-
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T57	1		T63	1		T58	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T7	1		T360	1		T241	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	17	1			T57	1		T202	1		T383	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T382	1		T384	3		T385	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	3	1			T201	1		T386	1		T387	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T17	1		T220	1		T71	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	22	1			T18	1		T211	1		T89	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T102	1		T388	1		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenId]	9	1			T17	1		T58	1		T389	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	3	1			T362	1		T384	1		T247	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	18	1			T280	1		T357	1		T390	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	10	1			T17	1		T28	1		T132	1
auto[7]	auto[StDisabled]	auto[OpGenId]	28	1			T17	1		T28	1		T53	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	24	1			T57	1		T112	1		T71	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	105	1			T4	1		T18	1		T19	1
auto[7]	auto[StDisabled]	auto[OpDisable]	3	1			T237	1		T248	1		T391	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	5	1			T261	1		T310	1		T347	1
auto[7]	auto[StInvalid]	auto[OpGenId]	5	1			T39	1		T258	1		T261	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	13	1			T27	1		T99	1		T98	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T42	1		T276	1		T392	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1423

1

T2

1

T4

3

T17

22

clear_one[1]

auto[0]

auto[0]

auto[0]

428

1

T17

5

T38

3

T39

1

clear_one[1]

auto[0]

auto[0]

auto[1]

142

1

T17

5

T19

2

T40

1

clear_one[1]

auto[0]

auto[1]

auto[0]

119

1

T17

1

T92

1

T211

2

clear_one[1]

auto[0]

auto[1]

auto[1]

55

1

T28

3

T57

2

T91

1

clear_one[2]

auto[0]

auto[0]

auto[0]

425

1

T17

4

T41

1

T40

1

clear_one[2]

auto[0]

auto[0]

auto[1]

119

1

T19

2

T140

1

T86

2

clear_one[2]

auto[1]

auto[0]

auto[0]

126

1

T17

1

T140

1

T264

1

clear_one[2]

auto[1]

auto[0]

auto[1]

43

1

T17

1

T140

1

T69

1

clear_one[3]

auto[0]

auto[0]

auto[0]

401

1

T17

6

T18

2

T19

1

clear_one[3]

auto[0]

auto[1]

auto[0]

130

1

T17

3

T28

2

T92

1

clear_one[3]

auto[1]

auto[0]

auto[0]

153

1

T4

3

T38

1

T140

1

clear_one[3]

auto[1]

auto[1]

auto[0]

29

1

T28

1

T322

1

T71

1

clear_none

auto[0]

auto[0]

auto[0]

1289

1

T4

1

T17

14

T18

1

clear_none

auto[0]

auto[0]

auto[1]

129

1

T17

1

T18

1

T40

4

clear_none

auto[0]

auto[1]

auto[0]

116

1

T17

1

T28

1

T92

1

clear_none

auto[0]

auto[1]

auto[1]

30

1

T2

1

T140

1

T141

1

clear_none

auto[1]

auto[0]

auto[0]

114

1

T4

1

T17

1

T38

1

clear_none

auto[1]

auto[0]

auto[1]

41

1

T28

1

T140

2

T88

3

clear_none

auto[1]

auto[1]

auto[0]

25

1

T393

1

T394

1

T395

1

clear_none

auto[1]

auto[1]

auto[1]

15

1

T69

1

T134

1

T329

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1336	1			T2	1		T4	3		T17	22
clear_all	auto[1]	87	1			T131	2		T132	11		T134	3
clear_one[1]	auto[0]	684	1			T17	11		T19	2		T38	3
clear_one[1]	auto[1]	60	1			T88	1		T91	2		T131	1
clear_one[2]	auto[0]	660	1			T17	6		T19	2		T41	1
clear_one[2]	auto[1]	53	1			T130	1		T296	2		T262	1
clear_one[3]	auto[0]	680	1			T4	3		T17	9		T18	2
clear_one[3]	auto[1]	33	1			T91	3		T133	3		T296	1
clear_none	auto[0]	1691	1			T2	1		T4	2		T17	17
clear_none	auto[1]	68	1			T88	5		T130	2		T141	9