Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10845

1

T2

6

T4

2

T5

14

auto[Attestation]

7560

1

T2

5

T4

6

T5

6

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2667	1			T2	1		T17	54		T18	4
auto[Aes]	3254	1			T2	2		T4	8		T5	4
auto[Kmac]	3330	1			T2	2		T5	4		T6	1
auto[Otbn]	3362	1			T2	5		T5	1		T6	2

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7536	1			T2	3		T4	8		T5	8
auto[OpGenId]	5792	1			T2	1		T5	11		T6	1
auto[OpGenSwOut]	5702	1			T2	3		T5	9		T6	2
auto[OpGenHwOut]	6911	1			T2	7		T4	8		T6	1
auto[OpDisable]	132	1			T17	2		T28	3		T53	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10483

1

T2

11

T4

8

T5

8

auto[OpDoneFail]

15590

1

T2

3

T4

8

T5

20

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6438	1			T2	1		T4	1		T5	13
auto[StInit]	3629	1			T2	4		T4	2		T5	2
auto[StCreatorRootKey]	3180	1			T2	5		T4	2		T5	2
auto[StOwnerIntKey]	2703	1			T2	4		T4	2		T5	2
auto[StOwnerKey]	2394	1			T4	2		T5	2		T17	39
auto[StDisabled]	7729	1			T4	7		T5	7		T17	127

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	319	1			T17	10		T18	1		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	108	1			T28	2		T23	1		T57	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	87	1			T17	2		T28	1		T93	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	74	1			T17	2		T28	1		T129	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	62	1			T17	2		T28	2		T57	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	202	1			T17	5		T28	1		T93	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	315	1			T5	3		T17	2		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	118	1			T17	1		T28	1		T218	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	84	1			T17	2		T28	1		T93	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	56	1			T17	1		T18	1		T218	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	57	1			T28	2		T24	1		T219	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	186	1			T17	5		T28	2		T140	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	331	1			T5	2		T17	1		T26	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	102	1			T5	1		T17	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	77	1			T17	1		T28	2		T57	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	55	1			T17	1		T92	1		T218	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	64	1			T17	1		T139	1		T112	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	220	1			T17	5		T18	1		T28	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	324	1			T17	6		T18	1		T42	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	101	1			T2	1		T17	1		T28	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	84	1			T6	1		T17	1		T57	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	60	1			T17	2		T85	1		T91	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	58	1			T17	4		T18	1		T85	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	211	1			T17	1		T28	1		T93	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	93	1			T17	8		T28	4		T57	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	104	1			T17	2		T59	1		T28	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	88	1			T2	1		T17	1		T57	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	67	1			T17	4		T28	1		T112	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	67	1			T17	1		T220	1		T141	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	179	1			T17	4		T28	3		T92	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	82	1			T17	7		T57	4		T99	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	95	1			T17	1		T139	1		T57	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	80	1			T17	1		T28	1		T140	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	74	1			T17	1		T28	1		T140	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	65	1			T5	1		T17	1		T92	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	197	1			T17	5		T18	1		T28	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	82	1			T17	10		T28	2		T57	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	88	1			T17	2		T27	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	71	1			T5	1		T6	1		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	89	1			T17	1		T139	1		T57	6
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	64	1			T17	1		T28	2		T85	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	186	1			T17	5		T28	1		T139	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	80	1			T17	5		T28	2		T112	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	79	1			T2	1		T28	1		T139	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	85	1			T17	3		T28	2		T92	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	65	1			T17	1		T92	1		T93	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	63	1			T17	2		T140	1		T57	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	204	1			T5	1		T17	3		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	265	1			T17	1		T18	2		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	80	1			T17	1		T43	1		T28	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	75	1			T140	1		T112	1		T219	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	57	1			T28	2		T57	1		T24	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	39	1			T17	1		T57	1		T71	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	176	1			T17	2		T18	1		T28	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	399	1			T38	3		T59	1		T27	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	138	1			T38	1		T28	2		T92	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	111	1			T28	1		T57	1		T87	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	96	1			T2	1		T17	1		T129	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	92	1			T4	1		T17	1		T38	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	270	1			T4	1		T18	1		T38	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	472	1			T42	3		T27	2		T53	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	127	1			T59	1		T28	3		T53	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	119	1			T2	1		T28	1		T92	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	84	1			T2	1		T57	1		T91	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	81	1			T92	1		T211	1		T139	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	295	1			T17	4		T28	2		T211	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	480	1			T42	2		T40	2		T59	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	103	1			T6	1		T17	2		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	106	1			T2	1		T17	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	91	1			T18	1		T40	1		T57	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	85	1			T40	1		T212	1		T140	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	295	1			T17	2		T18	3		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	60	1			T17	3		T85	1		T99	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	90	1			T17	1		T28	1		T33	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	82	1			T28	2		T88	1		T221	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	69	1			T17	2		T57	1		T141	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	41	1			T28	1		T139	2		T140	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	183	1			T17	2		T28	5		T93	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	76	1			T17	12		T28	2		T85	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	107	1			T4	1		T43	1		T28	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	100	1			T4	1		T38	1		T57	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	105	1			T2	1		T4	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	85	1			T17	1		T28	1		T57	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	266	1			T4	3		T17	3		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	61	1			T17	3		T28	2		T57	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	104	1			T17	1		T28	3		T87	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	106	1			T17	2		T93	1		T129	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	91	1			T18	1		T28	1		T211	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	91	1			T17	1		T28	2		T140	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	270	1			T17	7		T18	2		T28	4
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	77	1			T17	7		T28	1		T57	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	117	1			T17	1		T40	1		T24	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	134	1			T2	1		T17	2		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	85	1			T2	1		T17	2		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	91	1			T19	1		T28	1		T92	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	284	1			T17	2		T18	1		T19	3

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	208	1			T17	6		T28	4		T93	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	644	1			T17	15		T18	1		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	184	1			T17	3		T18	1		T28	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	632	1			T5	3		T17	8		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	186	1			T17	3		T28	1		T92	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	663	1			T5	3		T17	7		T18	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	182	1			T6	1		T17	7		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	656	1			T2	1		T17	8		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	197	1			T2	1		T17	5		T28	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	401	1			T17	15		T59	1		T28	9
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	204	1			T5	1		T17	3		T28	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	389	1			T17	13		T18	1		T28	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	213	1			T5	1		T6	1		T17	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	367	1			T17	17		T27	1		T28	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	198	1			T17	6		T28	1		T92	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	378	1			T2	1		T5	1		T17	8
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	157	1			T17	1		T28	2		T140	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	535	1			T17	4		T18	3		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	285	1			T2	1		T4	1		T17	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	821	1			T4	1		T18	1		T38	7
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	271	1			T2	2		T28	1		T92	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	907	1			T17	4		T42	3		T59	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	262	1			T2	1		T17	1		T18	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	898	1			T6	1		T17	4		T18	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	174	1			T17	2		T28	3		T140	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	351	1			T17	6		T28	6		T93	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	274	1			T2	1		T4	2		T17	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	465	1			T4	4		T17	15		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	279	1			T17	3		T18	1		T28	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	444	1			T17	11		T18	2		T28	9
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	293	1			T2	2		T17	4		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	495	1			T17	10		T18	1		T19	3