Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32107

1

T2

15

T4

17

T5

30

auto[1]

341

1

T88

3

T91

8

T130

7

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	32120	1			T2	15		T4	17		T5	30
auto[134217728:268435455]	13	1			T91	3		T133	2		T329	1
auto[268435456:402653183]	10	1			T132	1		T316	1		T250	1
auto[402653184:536870911]	13	1			T134	1		T329	1		T250	1
auto[536870912:671088639]	13	1			T134	1		T293	1		T250	2
auto[671088640:805306367]	7	1			T132	1		T251	1		T384	1
auto[805306368:939524095]	12	1			T132	1		T133	1		T134	1
auto[939524096:1073741823]	12	1			T130	1		T132	1		T250	1
auto[1073741824:1207959551]	10	1			T88	1		T262	1		T269	1
auto[1207959552:1342177279]	14	1			T133	1		T134	1		T262	1
auto[1342177280:1476395007]	5	1			T263	1		T270	2		T413	2
auto[1476395008:1610612735]	13	1			T141	1		T133	1		T329	1
auto[1610612736:1744830463]	5	1			T262	1		T329	1		T270	2
auto[1744830464:1879048191]	11	1			T88	1		T365	1		T414	1
auto[1879048192:2013265919]	11	1			T133	1		T296	1		T365	1
auto[2013265920:2147483647]	9	1			T91	1		T262	1		T415	1
auto[2147483648:2281701375]	12	1			T201	2		T329	1		T251	1
auto[2281701376:2415919103]	9	1			T91	1		T133	1		T270	1
auto[2415919104:2550136831]	9	1			T91	1		T141	1		T133	1
auto[2550136832:2684354559]	5	1			T130	1		T296	1		T251	1
auto[2684354560:2818572287]	18	1			T88	1		T132	1		T134	1
auto[2818572288:2952790015]	10	1			T130	1		T141	1		T132	1
auto[2952790016:3087007743]	9	1			T130	1		T365	1		T354	1
auto[3087007744:3221225471]	15	1			T91	1		T132	1		T296	1
auto[3221225472:3355443199]	15	1			T130	2		T262	1		T201	1
auto[3355443200:3489660927]	8	1			T141	1		T134	1		T365	1
auto[3489660928:3623878655]	9	1			T365	1		T414	1		T270	1
auto[3623878656:3758096383]	12	1			T131	1		T134	2		T262	1
auto[3758096384:3892314111]	13	1			T91	1		T130	1		T141	1
auto[3892314112:4026531839]	5	1			T329	1		T251	1		T416	1
auto[4026531840:4160749567]	10	1			T132	1		T296	1		T262	2
auto[4160749568:4294967295]	11	1			T141	1		T133	1		T329	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	32107	1			T2	15		T4	17		T5	30
auto[0:134217727]	auto[1]	13	1			T132	1		T365	1		T267	1
auto[134217728:268435455]	auto[1]	13	1			T91	3		T133	2		T329	1
auto[268435456:402653183]	auto[1]	10	1			T132	1		T316	1		T250	1
auto[402653184:536870911]	auto[1]	13	1			T134	1		T329	1		T250	1
auto[536870912:671088639]	auto[1]	13	1			T134	1		T293	1		T250	2
auto[671088640:805306367]	auto[1]	7	1			T132	1		T251	1		T384	1
auto[805306368:939524095]	auto[1]	12	1			T132	1		T133	1		T134	1
auto[939524096:1073741823]	auto[1]	12	1			T130	1		T132	1		T250	1
auto[1073741824:1207959551]	auto[1]	10	1			T88	1		T262	1		T269	1
auto[1207959552:1342177279]	auto[1]	14	1			T133	1		T134	1		T262	1
auto[1342177280:1476395007]	auto[1]	5	1			T263	1		T270	2		T413	2
auto[1476395008:1610612735]	auto[1]	13	1			T141	1		T133	1		T329	1
auto[1610612736:1744830463]	auto[1]	5	1			T262	1		T329	1		T270	2
auto[1744830464:1879048191]	auto[1]	11	1			T88	1		T365	1		T414	1
auto[1879048192:2013265919]	auto[1]	11	1			T133	1		T296	1		T365	1
auto[2013265920:2147483647]	auto[1]	9	1			T91	1		T262	1		T415	1
auto[2147483648:2281701375]	auto[1]	12	1			T201	2		T329	1		T251	1
auto[2281701376:2415919103]	auto[1]	9	1			T91	1		T133	1		T270	1
auto[2415919104:2550136831]	auto[1]	9	1			T91	1		T141	1		T133	1
auto[2550136832:2684354559]	auto[1]	5	1			T130	1		T296	1		T251	1
auto[2684354560:2818572287]	auto[1]	18	1			T88	1		T132	1		T134	1
auto[2818572288:2952790015]	auto[1]	10	1			T130	1		T141	1		T132	1
auto[2952790016:3087007743]	auto[1]	9	1			T130	1		T365	1		T354	1
auto[3087007744:3221225471]	auto[1]	15	1			T91	1		T132	1		T296	1
auto[3221225472:3355443199]	auto[1]	15	1			T130	2		T262	1		T201	1
auto[3355443200:3489660927]	auto[1]	8	1			T141	1		T134	1		T365	1
auto[3489660928:3623878655]	auto[1]	9	1			T365	1		T414	1		T270	1
auto[3623878656:3758096383]	auto[1]	12	1			T131	1		T134	2		T262	1
auto[3758096384:3892314111]	auto[1]	13	1			T91	1		T130	1		T141	1
auto[3892314112:4026531839]	auto[1]	5	1			T329	1		T251	1		T416	1
auto[4026531840:4160749567]	auto[1]	10	1			T132	1		T296	1		T262	2
auto[4160749568:4294967295]	auto[1]	11	1			T141	1		T133	1		T329	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1589

1

T17

18

T18

2

T41

3

auto[1]

1693

1

T2

1

T17

20

T18

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	107	1			T17	2		T140	1		T57	1
auto[134217728:268435455]	90	1			T2	1		T17	1		T26	1
auto[268435456:402653183]	104	1			T17	1		T41	1		T28	2
auto[402653184:536870911]	107	1			T41	1		T39	1		T28	2
auto[536870912:671088639]	111	1			T17	2		T42	1		T39	1
auto[671088640:805306367]	88	1			T42	1		T39	2		T28	1
auto[805306368:939524095]	81	1			T57	2		T112	1		T225	1
auto[939524096:1073741823]	107	1			T17	2		T39	1		T26	1
auto[1073741824:1207959551]	101	1			T28	1		T140	1		T57	3
auto[1207959552:1342177279]	112	1			T59	1		T28	1		T92	2
auto[1342177280:1476395007]	118	1			T17	3		T28	1		T130	1
auto[1476395008:1610612735]	90	1			T17	1		T26	2		T28	1
auto[1610612736:1744830463]	95	1			T17	3		T27	1		T129	1
auto[1744830464:1879048191]	104	1			T17	2		T39	1		T28	1
auto[1879048192:2013265919]	103	1			T17	2		T28	3		T220	1
auto[2013265920:2147483647]	90	1			T17	2		T18	1		T28	2
auto[2147483648:2281701375]	101	1			T17	1		T28	1		T92	1
auto[2281701376:2415919103]	122	1			T17	2		T27	2		T28	3
auto[2415919104:2550136831]	96	1			T17	1		T139	1		T140	1
auto[2550136832:2684354559]	103	1			T18	2		T42	1		T59	1
auto[2684354560:2818572287]	113	1			T17	2		T28	2		T85	1
auto[2818572288:2952790015]	115	1			T17	1		T27	1		T28	1
auto[2952790016:3087007743]	99	1			T17	1		T27	1		T28	1
auto[3087007744:3221225471]	99	1			T17	1		T39	1		T28	1
auto[3221225472:3355443199]	101	1			T17	3		T59	1		T28	1
auto[3355443200:3489660927]	99	1			T41	1		T26	1		T140	2
auto[3489660928:3623878655]	119	1			T17	1		T26	1		T28	1
auto[3623878656:3758096383]	117	1			T17	1		T57	1		T24	1
auto[3758096384:3892314111]	105	1			T17	1		T41	1		T28	2
auto[3892314112:4026531839]	80	1			T42	1		T59	2		T27	1
auto[4026531840:4160749567]	104	1			T17	1		T42	2		T28	1
auto[4160749568:4294967295]	101	1			T17	1		T18	1		T26	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	57	1			T17	1		T140	1		T295	1
auto[0:134217727]	auto[1]	50	1			T17	1		T57	1		T90	1
auto[134217728:268435455]	auto[0]	43	1			T17	1		T26	1		T28	2
auto[134217728:268435455]	auto[1]	47	1			T2	1		T28	2		T218	1
auto[268435456:402653183]	auto[0]	54	1			T41	1		T28	1		T33	1
auto[268435456:402653183]	auto[1]	50	1			T17	1		T28	1		T92	1
auto[402653184:536870911]	auto[0]	42	1			T41	1		T39	1		T112	1
auto[402653184:536870911]	auto[1]	65	1			T28	2		T140	1		T57	1
auto[536870912:671088639]	auto[0]	52	1			T17	1		T42	1		T39	1
auto[536870912:671088639]	auto[1]	59	1			T17	1		T27	1		T254	1
auto[671088640:805306367]	auto[0]	40	1			T42	1		T39	2		T28	1
auto[671088640:805306367]	auto[1]	48	1			T140	1		T57	2		T85	1
auto[805306368:939524095]	auto[0]	39	1			T71	1		T111	1		T142	1
auto[805306368:939524095]	auto[1]	42	1			T57	2		T112	1		T225	1
auto[939524096:1073741823]	auto[0]	54	1			T39	1		T53	1		T140	2
auto[939524096:1073741823]	auto[1]	53	1			T17	2		T26	1		T23	1
auto[1073741824:1207959551]	auto[0]	43	1			T71	1		T7	2		T142	1
auto[1073741824:1207959551]	auto[1]	58	1			T28	1		T140	1		T57	3
auto[1207959552:1342177279]	auto[0]	44	1			T123	1		T74	1		T261	1
auto[1207959552:1342177279]	auto[1]	68	1			T59	1		T28	1		T92	2
auto[1342177280:1476395007]	auto[0]	54	1			T130	1		T29	1		T393	1
auto[1342177280:1476395007]	auto[1]	64	1			T17	3		T28	1		T25	1
auto[1476395008:1610612735]	auto[0]	49	1			T17	1		T140	1		T24	1
auto[1476395008:1610612735]	auto[1]	41	1			T26	2		T28	1		T85	1
auto[1610612736:1744830463]	auto[0]	52	1			T17	2		T27	1		T85	1
auto[1610612736:1744830463]	auto[1]	43	1			T17	1		T129	1		T57	1
auto[1744830464:1879048191]	auto[0]	45	1			T17	1		T39	1		T57	1
auto[1744830464:1879048191]	auto[1]	59	1			T17	1		T28	1		T93	1
auto[1879048192:2013265919]	auto[0]	49	1			T28	1		T220	1		T393	1
auto[1879048192:2013265919]	auto[1]	54	1			T17	2		T28	2		T393	1
auto[2013265920:2147483647]	auto[0]	45	1			T17	1		T28	1		T21	1
auto[2013265920:2147483647]	auto[1]	45	1			T17	1		T18	1		T28	1
auto[2147483648:2281701375]	auto[0]	50	1			T17	1		T92	1		T140	1
auto[2147483648:2281701375]	auto[1]	51	1			T28	1		T57	3		T63	1
auto[2281701376:2415919103]	auto[0]	70	1			T17	2		T27	2		T28	1
auto[2281701376:2415919103]	auto[1]	52	1			T28	2		T140	1		T57	2
auto[2415919104:2550136831]	auto[0]	40	1			T17	1		T140	1		T112	1
auto[2415919104:2550136831]	auto[1]	56	1			T139	1		T77	1		T259	1
auto[2550136832:2684354559]	auto[0]	54	1			T18	1		T59	1		T92	1
auto[2550136832:2684354559]	auto[1]	49	1			T18	1		T42	1		T28	1
auto[2684354560:2818572287]	auto[0]	50	1			T17	1		T28	1		T96	1
auto[2684354560:2818572287]	auto[1]	63	1			T17	1		T28	1		T85	1
auto[2818572288:2952790015]	auto[0]	58	1			T17	1		T27	1		T28	1
auto[2818572288:2952790015]	auto[1]	57	1			T140	1		T141	1		T60	1
auto[2952790016:3087007743]	auto[0]	45	1			T27	1		T140	1		T57	1
auto[2952790016:3087007743]	auto[1]	54	1			T17	1		T28	1		T92	1
auto[3087007744:3221225471]	auto[0]	45	1			T39	1		T28	1		T25	1
auto[3087007744:3221225471]	auto[1]	54	1			T17	1		T93	1		T139	1
auto[3221225472:3355443199]	auto[0]	50	1			T17	2		T59	1		T28	1
auto[3221225472:3355443199]	auto[1]	51	1			T17	1		T23	1		T33	1
auto[3355443200:3489660927]	auto[0]	56	1			T41	1		T26	1		T140	1
auto[3355443200:3489660927]	auto[1]	43	1			T140	1		T85	1		T218	1
auto[3489660928:3623878655]	auto[0]	58	1			T17	1		T28	1		T57	1
auto[3489660928:3623878655]	auto[1]	61	1			T26	1		T57	1		T322	1
auto[3623878656:3758096383]	auto[0]	61	1			T54	1		T90	1		T299	1
auto[3623878656:3758096383]	auto[1]	56	1			T17	1		T57	1		T24	1
auto[3758096384:3892314111]	auto[0]	50	1			T28	2		T393	1		T68	1
auto[3758096384:3892314111]	auto[1]	55	1			T17	1		T41	1		T57	1
auto[3892314112:4026531839]	auto[0]	40	1			T42	1		T59	1		T27	1
auto[3892314112:4026531839]	auto[1]	40	1			T59	1		T28	1		T139	1
auto[4026531840:4160749567]	auto[0]	59	1			T42	2		T28	1		T140	1
auto[4026531840:4160749567]	auto[1]	45	1			T17	1		T7	1		T72	1
auto[4160749568:4294967295]	auto[0]	41	1			T17	1		T18	1		T26	1
auto[4160749568:4294967295]	auto[1]	60	1			T28	1		T139	1		T91	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1605

1

T17

20

T18

2

T41

4

auto[1]

1677

1

T2

1

T17

18

T18

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	104	1			T39	1		T85	1		T24	1
auto[134217728:268435455]	94	1			T39	1		T59	1		T27	1
auto[268435456:402653183]	116	1			T17	1		T26	1		T28	1
auto[402653184:536870911]	110	1			T18	1		T28	2		T139	1
auto[536870912:671088639]	113	1			T28	2		T57	2		T54	1
auto[671088640:805306367]	99	1			T17	1		T26	1		T28	1
auto[805306368:939524095]	117	1			T17	1		T26	1		T27	1
auto[939524096:1073741823]	110	1			T28	1		T92	1		T140	2
auto[1073741824:1207959551]	114	1			T17	1		T42	1		T28	2
auto[1207959552:1342177279]	107	1			T17	2		T42	1		T39	1
auto[1342177280:1476395007]	116	1			T17	1		T59	1		T27	1
auto[1476395008:1610612735]	97	1			T17	2		T28	2		T91	1
auto[1610612736:1744830463]	83	1			T17	1		T28	1		T33	1
auto[1744830464:1879048191]	97	1			T17	1		T18	1		T26	2
auto[1879048192:2013265919]	114	1			T17	1		T42	1		T59	2
auto[2013265920:2147483647]	107	1			T17	2		T39	2		T28	6
auto[2147483648:2281701375]	87	1			T17	2		T26	1		T28	3
auto[2281701376:2415919103]	97	1			T17	1		T41	1		T42	1
auto[2415919104:2550136831]	113	1			T27	1		T28	1		T23	1
auto[2550136832:2684354559]	99	1			T17	1		T41	1		T26	1
auto[2684354560:2818572287]	99	1			T27	1		T28	1		T92	1
auto[2818572288:2952790015]	97	1			T17	2		T28	1		T57	1
auto[2952790016:3087007743]	107	1			T17	2		T41	1		T28	1
auto[3087007744:3221225471]	100	1			T17	1		T28	1		T23	1
auto[3221225472:3355443199]	83	1			T17	1		T28	3		T92	1
auto[3355443200:3489660927]	100	1			T17	2		T27	2		T53	1
auto[3489660928:3623878655]	87	1			T17	3		T42	1		T57	2
auto[3623878656:3758096383]	97	1			T18	1		T41	1		T59	1
auto[3758096384:3892314111]	127	1			T17	3		T42	1		T28	1
auto[3892314112:4026531839]	96	1			T17	2		T18	1		T39	2
auto[4026531840:4160749567]	103	1			T17	2		T92	1		T129	1
auto[4160749568:4294967295]	92	1			T2	1		T17	2		T28	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	52	1			T39	1		T24	1		T220	1
auto[0:134217727]	auto[1]	52	1			T85	1		T123	2		T58	2
auto[134217728:268435455]	auto[0]	56	1			T39	1		T27	1		T85	1
auto[134217728:268435455]	auto[1]	38	1			T59	1		T139	1		T57	1
auto[268435456:402653183]	auto[0]	48	1			T28	1		T54	1		T29	1
auto[268435456:402653183]	auto[1]	68	1			T17	1		T26	1		T140	1
auto[402653184:536870911]	auto[0]	61	1			T18	1		T140	1		T90	1
auto[402653184:536870911]	auto[1]	49	1			T28	2		T139	1		T140	1
auto[536870912:671088639]	auto[0]	51	1			T28	1		T299	1		T393	1
auto[536870912:671088639]	auto[1]	62	1			T28	1		T57	2		T54	1
auto[671088640:805306367]	auto[0]	50	1			T140	1		T112	1		T7	1
auto[671088640:805306367]	auto[1]	49	1			T17	1		T26	1		T28	1
auto[805306368:939524095]	auto[0]	51	1			T17	1		T27	1		T140	1
auto[805306368:939524095]	auto[1]	66	1			T26	1		T28	1		T23	1
auto[939524096:1073741823]	auto[0]	54	1			T28	1		T130	1		T369	1
auto[939524096:1073741823]	auto[1]	56	1			T92	1		T140	2		T225	1
auto[1073741824:1207959551]	auto[0]	61	1			T17	1		T42	1		T140	2
auto[1073741824:1207959551]	auto[1]	53	1			T28	2		T140	1		T369	1
auto[1207959552:1342177279]	auto[0]	51	1			T17	1		T28	1		T409	1
auto[1207959552:1342177279]	auto[1]	56	1			T17	1		T42	1		T39	1
auto[1342177280:1476395007]	auto[0]	51	1			T17	1		T59	1		T27	1
auto[1342177280:1476395007]	auto[1]	65	1			T33	1		T130	1		T7	1
auto[1476395008:1610612735]	auto[0]	44	1			T28	1		T91	1		T29	1
auto[1476395008:1610612735]	auto[1]	53	1			T17	2		T28	1		T299	1
auto[1610612736:1744830463]	auto[0]	34	1			T17	1		T33	1		T57	1
auto[1610612736:1744830463]	auto[1]	49	1			T28	1		T77	1		T259	1
auto[1744830464:1879048191]	auto[0]	48	1			T26	1		T90	1		T299	1
auto[1744830464:1879048191]	auto[1]	49	1			T17	1		T18	1		T26	1
auto[1879048192:2013265919]	auto[0]	60	1			T17	1		T42	1		T59	1
auto[1879048192:2013265919]	auto[1]	54	1			T59	1		T92	1		T53	1
auto[2013265920:2147483647]	auto[0]	47	1			T39	2		T28	4		T53	1
auto[2013265920:2147483647]	auto[1]	60	1			T17	2		T28	2		T57	2
auto[2147483648:2281701375]	auto[0]	48	1			T17	1		T26	1		T28	2
auto[2147483648:2281701375]	auto[1]	39	1			T17	1		T28	1		T93	1
auto[2281701376:2415919103]	auto[0]	44	1			T17	1		T41	1		T42	1
auto[2281701376:2415919103]	auto[1]	53	1			T139	1		T140	1		T7	2
auto[2415919104:2550136831]	auto[0]	58	1			T23	1		T24	1		T71	1
auto[2415919104:2550136831]	auto[1]	55	1			T27	1		T28	1		T57	1
auto[2550136832:2684354559]	auto[0]	55	1			T17	1		T41	1		T26	1
auto[2550136832:2684354559]	auto[1]	44	1			T57	1		T85	2		T88	1
auto[2684354560:2818572287]	auto[0]	49	1			T27	1		T28	1		T259	1
auto[2684354560:2818572287]	auto[1]	50	1			T92	1		T69	1		T60	1
auto[2818572288:2952790015]	auto[0]	48	1			T17	2		T28	1		T254	1
auto[2818572288:2952790015]	auto[1]	49	1			T57	1		T85	2		T65	2
auto[2952790016:3087007743]	auto[0]	52	1			T17	1		T41	1		T90	1
auto[2952790016:3087007743]	auto[1]	55	1			T17	1		T28	1		T93	1
auto[3087007744:3221225471]	auto[0]	59	1			T57	1		T54	2		T393	1
auto[3087007744:3221225471]	auto[1]	41	1			T17	1		T28	1		T23	1
auto[3221225472:3355443199]	auto[0]	49	1			T17	1		T28	2		T92	1
auto[3221225472:3355443199]	auto[1]	34	1			T28	1		T112	1		T295	1
auto[3355443200:3489660927]	auto[0]	45	1			T27	1		T53	1		T57	1
auto[3355443200:3489660927]	auto[1]	55	1			T17	2		T27	1		T57	2
auto[3489660928:3623878655]	auto[0]	37	1			T17	2		T42	1		T111	1
auto[3489660928:3623878655]	auto[1]	50	1			T17	1		T57	2		T24	1
auto[3623878656:3758096383]	auto[0]	49	1			T18	1		T41	1		T59	1
auto[3623878656:3758096383]	auto[1]	48	1			T71	1		T7	1		T131	1
auto[3758096384:3892314111]	auto[0]	69	1			T17	2		T42	1		T140	1
auto[3758096384:3892314111]	auto[1]	58	1			T17	1		T28	1		T92	1
auto[3892314112:4026531839]	auto[0]	38	1			T17	2		T39	2		T92	1
auto[3892314112:4026531839]	auto[1]	58	1			T18	1		T140	1		T57	3
auto[4026531840:4160749567]	auto[0]	46	1			T92	1		T57	1		T123	2
auto[4026531840:4160749567]	auto[1]	57	1			T17	2		T129	1		T57	1
auto[4160749568:4294967295]	auto[0]	40	1			T17	1		T28	1		T133	1
auto[4160749568:4294967295]	auto[1]	52	1			T2	1		T17	1		T28	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1577

1

T17

17

T18

2

T41

3

auto[1]

1706

1

T2

1

T17

21

T18

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	111	1			T17	1		T39	1		T27	2
auto[134217728:268435455]	96	1			T17	1		T26	1		T28	1
auto[268435456:402653183]	97	1			T17	1		T26	1		T92	1
auto[402653184:536870911]	105	1			T2	1		T41	1		T28	2
auto[536870912:671088639]	117	1			T17	2		T39	1		T26	1
auto[671088640:805306367]	105	1			T17	2		T18	1		T42	1
auto[805306368:939524095]	99	1			T17	2		T59	1		T57	2
auto[939524096:1073741823]	113	1			T17	2		T28	1		T57	3
auto[1073741824:1207959551]	100	1			T17	2		T28	1		T140	1
auto[1207959552:1342177279]	102	1			T17	2		T41	1		T59	1
auto[1342177280:1476395007]	104	1			T39	1		T26	1		T28	2
auto[1476395008:1610612735]	91	1			T17	1		T28	1		T92	1
auto[1610612736:1744830463]	103	1			T17	2		T59	1		T28	1
auto[1744830464:1879048191]	95	1			T17	1		T42	1		T140	2
auto[1879048192:2013265919]	118	1			T17	1		T42	1		T59	1
auto[2013265920:2147483647]	105	1			T17	1		T59	1		T92	1
auto[2147483648:2281701375]	96	1			T18	1		T41	1		T42	1
auto[2281701376:2415919103]	93	1			T18	1		T39	1		T28	1
auto[2415919104:2550136831]	101	1			T17	2		T28	1		T90	1
auto[2550136832:2684354559]	95	1			T17	1		T28	1		T139	1
auto[2684354560:2818572287]	89	1			T17	1		T28	1		T29	1
auto[2818572288:2952790015]	111	1			T17	2		T92	2		T129	1
auto[2952790016:3087007743]	105	1			T17	1		T26	1		T27	1
auto[3087007744:3221225471]	82	1			T42	1		T28	1		T140	1
auto[3221225472:3355443199]	118	1			T17	1		T18	1		T41	1
auto[3355443200:3489660927]	95	1			T17	1		T26	1		T28	1
auto[3489660928:3623878655]	115	1			T17	1		T139	1		T140	3
auto[3623878656:3758096383]	103	1			T17	3		T28	2		T93	1
auto[3758096384:3892314111]	98	1			T17	1		T28	2		T57	1
auto[3892314112:4026531839]	95	1			T17	1		T140	1		T57	1
auto[4026531840:4160749567]	115	1			T17	1		T39	1		T28	2
auto[4160749568:4294967295]	111	1			T17	1		T27	2		T28	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	65	1			T39	1		T27	1		T28	1
auto[0:134217727]	auto[1]	46	1			T17	1		T27	1		T28	2
auto[134217728:268435455]	auto[0]	38	1			T28	1		T75	1		T296	1
auto[134217728:268435455]	auto[1]	58	1			T17	1		T26	1		T85	1
auto[268435456:402653183]	auto[0]	45	1			T140	1		T71	1		T7	2
auto[268435456:402653183]	auto[1]	52	1			T17	1		T26	1		T92	1
auto[402653184:536870911]	auto[0]	58	1			T28	2		T33	1		T54	1
auto[402653184:536870911]	auto[1]	47	1			T2	1		T41	1		T92	1
auto[536870912:671088639]	auto[0]	61	1			T39	1		T26	1		T27	1
auto[536870912:671088639]	auto[1]	56	1			T17	2		T28	1		T57	1
auto[671088640:805306367]	auto[0]	53	1			T18	1		T42	1		T39	1
auto[671088640:805306367]	auto[1]	52	1			T17	2		T140	1		T254	1
auto[805306368:939524095]	auto[0]	57	1			T17	2		T59	1		T393	1
auto[805306368:939524095]	auto[1]	42	1			T57	2		T85	1		T112	1
auto[939524096:1073741823]	auto[0]	49	1			T17	2		T57	2		T54	1
auto[939524096:1073741823]	auto[1]	64	1			T28	1		T57	1		T85	1
auto[1073741824:1207959551]	auto[0]	41	1			T140	1		T275	1		T353	1
auto[1073741824:1207959551]	auto[1]	59	1			T17	2		T28	1		T57	1
auto[1207959552:1342177279]	auto[0]	52	1			T17	1		T41	1		T27	1
auto[1207959552:1342177279]	auto[1]	50	1			T17	1		T59	1		T140	1
auto[1342177280:1476395007]	auto[0]	51	1			T39	1		T140	1		T220	1
auto[1342177280:1476395007]	auto[1]	53	1			T26	1		T28	2		T140	1
auto[1476395008:1610612735]	auto[0]	44	1			T17	1		T33	1		T328	1
auto[1476395008:1610612735]	auto[1]	47	1			T28	1		T92	1		T140	1
auto[1610612736:1744830463]	auto[0]	39	1			T17	1		T28	1		T54	1
auto[1610612736:1744830463]	auto[1]	64	1			T17	1		T59	1		T57	1
auto[1744830464:1879048191]	auto[0]	48	1			T17	1		T42	1		T140	1
auto[1744830464:1879048191]	auto[1]	47	1			T140	1		T57	1		T299	1
auto[1879048192:2013265919]	auto[0]	51	1			T42	1		T59	1		T28	1
auto[1879048192:2013265919]	auto[1]	67	1			T17	1		T28	2		T23	1
auto[2013265920:2147483647]	auto[0]	49	1			T17	1		T59	1		T24	1
auto[2013265920:2147483647]	auto[1]	56	1			T92	1		T299	1		T225	1
auto[2147483648:2281701375]	auto[0]	39	1			T41	1		T39	1		T111	1
auto[2147483648:2281701375]	auto[1]	57	1			T18	1		T42	1		T53	1
auto[2281701376:2415919103]	auto[0]	44	1			T18	1		T39	1		T92	1
auto[2281701376:2415919103]	auto[1]	49	1			T28	1		T139	1		T85	1
auto[2415919104:2550136831]	auto[0]	48	1			T90	1		T220	1		T254	1
auto[2415919104:2550136831]	auto[1]	53	1			T17	2		T28	1		T91	1
auto[2550136832:2684354559]	auto[0]	39	1			T139	1		T7	1		T142	1
auto[2550136832:2684354559]	auto[1]	56	1			T17	1		T28	1		T57	1
auto[2684354560:2818572287]	auto[0]	43	1			T17	1		T28	1		T225	1
auto[2684354560:2818572287]	auto[1]	46	1			T29	1		T417	1		T255	1
auto[2818572288:2952790015]	auto[0]	52	1			T17	2		T129	1		T57	1
auto[2818572288:2952790015]	auto[1]	59	1			T92	2		T57	1		T254	1
auto[2952790016:3087007743]	auto[0]	58	1			T26	1		T27	1		T28	3
auto[2952790016:3087007743]	auto[1]	47	1			T17	1		T140	1		T78	1
auto[3087007744:3221225471]	auto[0]	37	1			T42	1		T28	1		T140	1
auto[3087007744:3221225471]	auto[1]	45	1			T85	1		T24	1		T54	1
auto[3221225472:3355443199]	auto[0]	65	1			T17	1		T41	1		T42	1
auto[3221225472:3355443199]	auto[1]	53	1			T18	1		T26	1		T28	1
auto[3355443200:3489660927]	auto[0]	54	1			T28	1		T53	1		T99	1
auto[3355443200:3489660927]	auto[1]	41	1			T17	1		T26	1		T53	1
auto[3489660928:3623878655]	auto[0]	55	1			T140	2		T57	1		T299	1
auto[3489660928:3623878655]	auto[1]	60	1			T17	1		T139	1		T140	1
auto[3623878656:3758096383]	auto[0]	45	1			T17	2		T57	1		T85	1
auto[3623878656:3758096383]	auto[1]	58	1			T17	1		T28	2		T93	1
auto[3758096384:3892314111]	auto[0]	56	1			T17	1		T28	1		T57	1
auto[3758096384:3892314111]	auto[1]	42	1			T28	1		T85	1		T218	1
auto[3892314112:4026531839]	auto[0]	39	1			T17	1		T54	1		T94	1
auto[3892314112:4026531839]	auto[1]	56	1			T140	1		T57	1		T85	1
auto[4026531840:4160749567]	auto[0]	51	1			T39	1		T28	1		T24	1
auto[4026531840:4160749567]	auto[1]	64	1			T17	1		T28	1		T88	1
auto[4160749568:4294967295]	auto[0]	51	1			T27	1		T112	1		T7	1
auto[4160749568:4294967295]	auto[1]	60	1			T17	1		T27	1		T28	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1586

1

T17

18

T18

2

T41

3

auto[1]

1696

1

T2

1

T17

20

T18

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	97	1			T17	2		T18	1		T42	1
auto[134217728:268435455]	110	1			T39	1		T28	2		T139	1
auto[268435456:402653183]	94	1			T17	3		T41	1		T42	1
auto[402653184:536870911]	106	1			T27	1		T139	1		T77	1
auto[536870912:671088639]	105	1			T17	1		T39	1		T26	1
auto[671088640:805306367]	97	1			T33	1		T140	1		T57	1
auto[805306368:939524095]	95	1			T28	3		T92	1		T139	1
auto[939524096:1073741823]	107	1			T17	1		T59	1		T28	2
auto[1073741824:1207959551]	112	1			T17	2		T28	1		T140	3
auto[1207959552:1342177279]	88	1			T17	1		T26	1		T59	1
auto[1342177280:1476395007]	112	1			T17	1		T42	3		T39	1
auto[1476395008:1610612735]	105	1			T59	1		T28	3		T140	2
auto[1610612736:1744830463]	115	1			T2	1		T28	1		T140	1
auto[1744830464:1879048191]	108	1			T17	1		T27	1		T28	1
auto[1879048192:2013265919]	89	1			T17	3		T53	1		T140	1
auto[2013265920:2147483647]	115	1			T41	1		T28	1		T53	1
auto[2147483648:2281701375]	98	1			T17	1		T18	1		T139	1
auto[2281701376:2415919103]	103	1			T59	1		T28	2		T57	2
auto[2415919104:2550136831]	97	1			T17	2		T26	1		T28	2
auto[2550136832:2684354559]	107	1			T17	4		T42	1		T26	1
auto[2684354560:2818572287]	82	1			T28	2		T57	2		T85	1
auto[2818572288:2952790015]	105	1			T17	2		T92	1		T140	1
auto[2952790016:3087007743]	88	1			T17	3		T59	1		T27	1
auto[3087007744:3221225471]	108	1			T92	1		T140	1		T85	1
auto[3221225472:3355443199]	93	1			T17	1		T18	1		T28	1
auto[3355443200:3489660927]	121	1			T17	2		T92	1		T129	1
auto[3489660928:3623878655]	102	1			T17	1		T39	2		T26	1
auto[3623878656:3758096383]	98	1			T17	2		T39	1		T27	2
auto[3758096384:3892314111]	115	1			T17	2		T18	1		T41	1
auto[3892314112:4026531839]	101	1			T17	1		T26	1		T28	1
auto[4026531840:4160749567]	105	1			T41	1		T28	1		T57	2
auto[4160749568:4294967295]	104	1			T17	2		T26	1		T23	1