Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.74 99.04 97.95 98.44 100.00 99.11 98.41 91.22


Total test records in report: 1084
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T1011 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.1612630688 Jul 16 07:10:53 PM PDT 24 Jul 16 07:11:01 PM PDT 24 772325647 ps
T1012 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3588283049 Jul 16 07:10:48 PM PDT 24 Jul 16 07:10:50 PM PDT 24 15076576 ps
T1013 /workspace/coverage/cover_reg_top/22.keymgr_intr_test.849321505 Jul 16 07:11:12 PM PDT 24 Jul 16 07:12:00 PM PDT 24 30802291 ps
T1014 /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.782463268 Jul 16 07:10:46 PM PDT 24 Jul 16 07:10:48 PM PDT 24 211089724 ps
T401 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.1547993180 Jul 16 07:11:03 PM PDT 24 Jul 16 07:11:11 PM PDT 24 166222118 ps
T1015 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3101740602 Jul 16 07:11:06 PM PDT 24 Jul 16 07:11:15 PM PDT 24 99575786 ps
T1016 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.685786198 Jul 16 07:11:11 PM PDT 24 Jul 16 07:11:54 PM PDT 24 216984156 ps
T1017 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.835871943 Jul 16 07:11:05 PM PDT 24 Jul 16 07:11:10 PM PDT 24 39449431 ps
T1018 /workspace/coverage/cover_reg_top/18.keymgr_intr_test.4081176341 Jul 16 07:11:09 PM PDT 24 Jul 16 07:11:34 PM PDT 24 43491838 ps
T1019 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2199956405 Jul 16 07:10:49 PM PDT 24 Jul 16 07:10:52 PM PDT 24 37866879 ps
T1020 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3541595126 Jul 16 07:10:47 PM PDT 24 Jul 16 07:10:54 PM PDT 24 999136015 ps
T169 /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.681069629 Jul 16 07:10:48 PM PDT 24 Jul 16 07:11:00 PM PDT 24 478832188 ps
T1021 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1708201968 Jul 16 07:10:48 PM PDT 24 Jul 16 07:10:52 PM PDT 24 190782432 ps
T1022 /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1805156938 Jul 16 07:10:50 PM PDT 24 Jul 16 07:10:55 PM PDT 24 32586357 ps
T1023 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.2737720066 Jul 16 07:11:04 PM PDT 24 Jul 16 07:11:11 PM PDT 24 672646663 ps
T1024 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2248012583 Jul 16 07:11:03 PM PDT 24 Jul 16 07:11:05 PM PDT 24 49238229 ps
T1025 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1604485340 Jul 16 07:11:01 PM PDT 24 Jul 16 07:11:03 PM PDT 24 64069312 ps
T1026 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3009627068 Jul 16 07:11:07 PM PDT 24 Jul 16 07:11:17 PM PDT 24 16672187 ps
T1027 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.2473015847 Jul 16 07:11:03 PM PDT 24 Jul 16 07:11:06 PM PDT 24 116791902 ps
T160 /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2513485505 Jul 16 07:10:50 PM PDT 24 Jul 16 07:10:57 PM PDT 24 96509260 ps
T1028 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1502676977 Jul 16 07:11:07 PM PDT 24 Jul 16 07:11:15 PM PDT 24 13670827 ps
T1029 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.873132344 Jul 16 07:11:18 PM PDT 24 Jul 16 07:12:19 PM PDT 24 12165298 ps
T1030 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3176685316 Jul 16 07:11:09 PM PDT 24 Jul 16 07:11:35 PM PDT 24 103122142 ps
T1031 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2091561256 Jul 16 07:11:05 PM PDT 24 Jul 16 07:11:10 PM PDT 24 10777457 ps
T1032 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.3698695608 Jul 16 07:11:05 PM PDT 24 Jul 16 07:11:10 PM PDT 24 9349549 ps
T1033 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1581498003 Jul 16 07:10:48 PM PDT 24 Jul 16 07:10:51 PM PDT 24 31357038 ps
T1034 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1193844316 Jul 16 07:11:05 PM PDT 24 Jul 16 07:11:15 PM PDT 24 147928753 ps
T1035 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2384380838 Jul 16 07:10:52 PM PDT 24 Jul 16 07:10:55 PM PDT 24 25897859 ps
T1036 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.4158015011 Jul 16 07:11:19 PM PDT 24 Jul 16 07:12:26 PM PDT 24 70444264 ps
T1037 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.598853313 Jul 16 07:11:14 PM PDT 24 Jul 16 07:12:07 PM PDT 24 1046178612 ps
T1038 /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1767693109 Jul 16 07:11:10 PM PDT 24 Jul 16 07:11:41 PM PDT 24 48780942 ps
T1039 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1077466986 Jul 16 07:11:18 PM PDT 24 Jul 16 07:12:18 PM PDT 24 16865447 ps
T1040 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.3796169694 Jul 16 07:11:05 PM PDT 24 Jul 16 07:11:10 PM PDT 24 56337372 ps
T1041 /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1503255714 Jul 16 07:10:52 PM PDT 24 Jul 16 07:10:56 PM PDT 24 36105641 ps
T168 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3071141191 Jul 16 07:11:09 PM PDT 24 Jul 16 07:11:37 PM PDT 24 1689475761 ps
T1042 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.926971058 Jul 16 07:10:36 PM PDT 24 Jul 16 07:10:45 PM PDT 24 228516509 ps
T1043 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3525081170 Jul 16 07:10:47 PM PDT 24 Jul 16 07:10:50 PM PDT 24 41758101 ps
T172 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.1418534631 Jul 16 07:11:09 PM PDT 24 Jul 16 07:11:39 PM PDT 24 487607356 ps
T1044 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.3914515737 Jul 16 07:11:19 PM PDT 24 Jul 16 07:12:26 PM PDT 24 13404011 ps
T1045 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.103294331 Jul 16 07:11:01 PM PDT 24 Jul 16 07:11:03 PM PDT 24 25935017 ps
T1046 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.333258650 Jul 16 07:11:03 PM PDT 24 Jul 16 07:11:08 PM PDT 24 1122013344 ps
T1047 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2580282299 Jul 16 07:11:04 PM PDT 24 Jul 16 07:11:09 PM PDT 24 134341688 ps
T1048 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.875440958 Jul 16 07:11:02 PM PDT 24 Jul 16 07:11:04 PM PDT 24 11210492 ps
T165 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3385992028 Jul 16 07:11:09 PM PDT 24 Jul 16 07:11:36 PM PDT 24 241430001 ps
T1049 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.4284569212 Jul 16 07:10:50 PM PDT 24 Jul 16 07:10:53 PM PDT 24 65841377 ps
T1050 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.720040502 Jul 16 07:11:04 PM PDT 24 Jul 16 07:11:07 PM PDT 24 190253881 ps
T1051 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2835655872 Jul 16 07:11:05 PM PDT 24 Jul 16 07:11:12 PM PDT 24 43267775 ps
T156 /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.138261601 Jul 16 07:11:04 PM PDT 24 Jul 16 07:11:12 PM PDT 24 265573298 ps
T1052 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1878393292 Jul 16 07:10:35 PM PDT 24 Jul 16 07:10:41 PM PDT 24 297201222 ps
T1053 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.879123189 Jul 16 07:11:09 PM PDT 24 Jul 16 07:11:27 PM PDT 24 565451684 ps
T1054 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.126134321 Jul 16 07:11:03 PM PDT 24 Jul 16 07:11:07 PM PDT 24 56546440 ps
T1055 /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.2352984818 Jul 16 07:11:04 PM PDT 24 Jul 16 07:11:10 PM PDT 24 401521046 ps
T1056 /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.715899463 Jul 16 07:11:04 PM PDT 24 Jul 16 07:11:07 PM PDT 24 15374373 ps
T1057 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1522609257 Jul 16 07:10:52 PM PDT 24 Jul 16 07:11:01 PM PDT 24 533667493 ps
T1058 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2592671111 Jul 16 07:11:03 PM PDT 24 Jul 16 07:11:07 PM PDT 24 315897155 ps
T1059 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3107523143 Jul 16 07:10:53 PM PDT 24 Jul 16 07:10:57 PM PDT 24 23389675 ps
T1060 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1060362633 Jul 16 07:11:06 PM PDT 24 Jul 16 07:11:17 PM PDT 24 380557918 ps
T1061 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2199511019 Jul 16 07:11:09 PM PDT 24 Jul 16 07:11:36 PM PDT 24 82298128 ps
T1062 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2584566174 Jul 16 07:11:10 PM PDT 24 Jul 16 07:11:40 PM PDT 24 121154290 ps
T1063 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1569297558 Jul 16 07:11:05 PM PDT 24 Jul 16 07:11:11 PM PDT 24 398442317 ps
T1064 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3905186498 Jul 16 07:11:08 PM PDT 24 Jul 16 07:11:22 PM PDT 24 36868964 ps
T1065 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.4042998959 Jul 16 07:11:04 PM PDT 24 Jul 16 07:11:11 PM PDT 24 798145317 ps
T1066 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1070164381 Jul 16 07:10:52 PM PDT 24 Jul 16 07:10:56 PM PDT 24 29092130 ps
T1067 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1085964226 Jul 16 07:10:48 PM PDT 24 Jul 16 07:10:52 PM PDT 24 38547008 ps
T1068 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.886069442 Jul 16 07:11:04 PM PDT 24 Jul 16 07:11:08 PM PDT 24 117873243 ps
T1069 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1244518300 Jul 16 07:11:09 PM PDT 24 Jul 16 07:11:35 PM PDT 24 213292084 ps
T1070 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2530947324 Jul 16 07:11:05 PM PDT 24 Jul 16 07:11:11 PM PDT 24 112730717 ps
T1071 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2644395581 Jul 16 07:10:50 PM PDT 24 Jul 16 07:10:54 PM PDT 24 53766758 ps
T1072 /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1088728171 Jul 16 07:11:09 PM PDT 24 Jul 16 07:11:25 PM PDT 24 35127013 ps
T1073 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2906631800 Jul 16 07:11:17 PM PDT 24 Jul 16 07:12:17 PM PDT 24 18099078 ps
T1074 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.158375236 Jul 16 07:10:52 PM PDT 24 Jul 16 07:10:56 PM PDT 24 27549896 ps
T157 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2762799655 Jul 16 07:11:01 PM PDT 24 Jul 16 07:11:07 PM PDT 24 452587551 ps
T164 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2460373410 Jul 16 07:10:48 PM PDT 24 Jul 16 07:10:58 PM PDT 24 494904067 ps
T163 /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.1018600906 Jul 16 07:10:49 PM PDT 24 Jul 16 07:10:55 PM PDT 24 465268623 ps
T1075 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.320857302 Jul 16 07:11:08 PM PDT 24 Jul 16 07:11:20 PM PDT 24 21009792 ps
T1076 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2179457329 Jul 16 07:11:18 PM PDT 24 Jul 16 07:12:18 PM PDT 24 11022685 ps
T1077 /workspace/coverage/cover_reg_top/15.keymgr_intr_test.627483846 Jul 16 07:11:05 PM PDT 24 Jul 16 07:11:11 PM PDT 24 36686010 ps
T1078 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3458831297 Jul 16 07:11:04 PM PDT 24 Jul 16 07:11:11 PM PDT 24 198621038 ps
T1079 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.3732529426 Jul 16 07:11:03 PM PDT 24 Jul 16 07:11:08 PM PDT 24 76687839 ps
T1080 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.198125464 Jul 16 07:10:51 PM PDT 24 Jul 16 07:11:13 PM PDT 24 650606864 ps
T1081 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.1962800870 Jul 16 07:11:03 PM PDT 24 Jul 16 07:11:07 PM PDT 24 32981205 ps
T1082 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1064603072 Jul 16 07:10:45 PM PDT 24 Jul 16 07:10:47 PM PDT 24 17993555 ps
T1083 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1925877576 Jul 16 07:11:04 PM PDT 24 Jul 16 07:11:08 PM PDT 24 57070292 ps
T1084 /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.938256299 Jul 16 07:10:50 PM PDT 24 Jul 16 07:10:55 PM PDT 24 382254219 ps

Test location /workspace/coverage/default/20.keymgr_stress_all.3078365484
Short name T17
Test name
Test status
Simulation time 1733629142 ps
CPU time 59.65 seconds
Started Jul 16 07:57:49 PM PDT 24
Finished Jul 16 07:58:55 PM PDT 24
Peak memory 222512 kb
Host smart-183a3e19-47a8-44a8-9505-ecd33eea4fe5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078365484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.3078365484
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.2113574745
Short name T57
Test name
Test status
Simulation time 1278771864 ps
CPU time 21.56 seconds
Started Jul 16 07:59:04 PM PDT 24
Finished Jul 16 07:59:27 PM PDT 24
Peak memory 222616 kb
Host smart-47b16ca6-3fb7-49a2-b293-f9c5f2f4cd6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113574745 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.2113574745
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.692123614
Short name T7
Test name
Test status
Simulation time 20183548190 ps
CPU time 550.21 seconds
Started Jul 16 07:58:01 PM PDT 24
Finished Jul 16 08:07:19 PM PDT 24
Peak memory 218312 kb
Host smart-f4ce7a2b-ff9a-4d7e-b5db-ed6cdb551d8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692123614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.692123614
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.1231237157
Short name T3
Test name
Test status
Simulation time 992252491 ps
CPU time 5.96 seconds
Started Jul 16 07:56:40 PM PDT 24
Finished Jul 16 07:56:48 PM PDT 24
Peak memory 231576 kb
Host smart-40188582-b1c9-4678-8e29-a27cdd3b1c99
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231237157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1231237157
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.3239552304
Short name T115
Test name
Test status
Simulation time 1880773496 ps
CPU time 11.84 seconds
Started Jul 16 07:11:04 PM PDT 24
Finished Jul 16 07:11:18 PM PDT 24
Peak memory 214044 kb
Host smart-06fcdfca-e12d-46d8-b637-b824cf0d3d75
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239552304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.3239552304
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.1715497430
Short name T12
Test name
Test status
Simulation time 50334428 ps
CPU time 2.4 seconds
Started Jul 16 07:56:57 PM PDT 24
Finished Jul 16 07:57:01 PM PDT 24
Peak memory 216792 kb
Host smart-aec9fad2-4689-4308-9d6d-4b2fb4090478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715497430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.1715497430
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.1861410891
Short name T28
Test name
Test status
Simulation time 5285678137 ps
CPU time 33.55 seconds
Started Jul 16 07:59:17 PM PDT 24
Finished Jul 16 07:59:55 PM PDT 24
Peak memory 216812 kb
Host smart-94181083-2f3f-4178-a237-adba79252de2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861410891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.1861410891
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.1658645049
Short name T132
Test name
Test status
Simulation time 10156150291 ps
CPU time 138.12 seconds
Started Jul 16 07:58:09 PM PDT 24
Finished Jul 16 08:00:33 PM PDT 24
Peak memory 218840 kb
Host smart-7f7800ae-e0d9-421b-bf6f-2d6aed699c41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1658645049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.1658645049
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.2021486587
Short name T111
Test name
Test status
Simulation time 327765060 ps
CPU time 4.21 seconds
Started Jul 16 07:56:43 PM PDT 24
Finished Jul 16 07:56:49 PM PDT 24
Peak memory 214376 kb
Host smart-461ef5d6-02e0-4e7e-b808-d102a61910a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021486587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.2021486587
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.1921206647
Short name T270
Test name
Test status
Simulation time 520556071 ps
CPU time 14.74 seconds
Started Jul 16 07:56:40 PM PDT 24
Finished Jul 16 07:56:56 PM PDT 24
Peak memory 215944 kb
Host smart-915cd4d4-632a-446a-8b52-059ef86a2212
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1921206647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.1921206647
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.2596075881
Short name T123
Test name
Test status
Simulation time 3525945748 ps
CPU time 25.8 seconds
Started Jul 16 07:58:16 PM PDT 24
Finished Jul 16 07:58:45 PM PDT 24
Peak memory 222700 kb
Host smart-1ad9bb3c-528b-4770-8f5a-32d3e9151123
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596075881 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.2596075881
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.1818025876
Short name T133
Test name
Test status
Simulation time 617047879 ps
CPU time 9.25 seconds
Started Jul 16 07:58:45 PM PDT 24
Finished Jul 16 07:58:57 PM PDT 24
Peak memory 215952 kb
Host smart-ce83e9f4-523f-4d21-a6ff-4aa8934a4d67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1818025876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1818025876
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.984831392
Short name T95
Test name
Test status
Simulation time 319818673 ps
CPU time 4 seconds
Started Jul 16 07:59:08 PM PDT 24
Finished Jul 16 07:59:14 PM PDT 24
Peak memory 222524 kb
Host smart-98ba6a76-66ea-447d-9467-f0f26d3ba89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984831392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.984831392
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.1731309142
Short name T39
Test name
Test status
Simulation time 240910756 ps
CPU time 3.37 seconds
Started Jul 16 07:59:13 PM PDT 24
Finished Jul 16 07:59:22 PM PDT 24
Peak memory 220168 kb
Host smart-69f1971e-8125-4b92-8aad-7c2da1560375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731309142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.1731309142
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.3004762160
Short name T329
Test name
Test status
Simulation time 110408188 ps
CPU time 5.89 seconds
Started Jul 16 07:57:04 PM PDT 24
Finished Jul 16 07:57:11 PM PDT 24
Peak memory 214672 kb
Host smart-5a6a9798-0d4d-411e-8e67-887821fd0d92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3004762160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.3004762160
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2006527140
Short name T116
Test name
Test status
Simulation time 514105321 ps
CPU time 2.8 seconds
Started Jul 16 07:11:02 PM PDT 24
Finished Jul 16 07:11:06 PM PDT 24
Peak memory 214096 kb
Host smart-3548d1a5-56eb-41b4-96bc-fe75b6a8647b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006527140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.2006527140
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.2825594668
Short name T91
Test name
Test status
Simulation time 1143509790 ps
CPU time 60.53 seconds
Started Jul 16 07:58:57 PM PDT 24
Finished Jul 16 08:00:01 PM PDT 24
Peak memory 214420 kb
Host smart-df8c05a5-fc6b-4467-8344-ed2b14a2d23d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2825594668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2825594668
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.3264057815
Short name T58
Test name
Test status
Simulation time 70405525307 ps
CPU time 256.98 seconds
Started Jul 16 07:59:15 PM PDT 24
Finished Jul 16 08:03:38 PM PDT 24
Peak memory 219964 kb
Host smart-f1d93ae7-4897-44cd-b531-1560edfd69f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264057815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.3264057815
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.1772024671
Short name T421
Test name
Test status
Simulation time 336908202 ps
CPU time 9.11 seconds
Started Jul 16 07:57:50 PM PDT 24
Finished Jul 16 07:58:06 PM PDT 24
Peak memory 214312 kb
Host smart-7e3370b1-c551-422f-9727-d19cdf608a9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1772024671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.1772024671
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.2897077550
Short name T32
Test name
Test status
Simulation time 81828941 ps
CPU time 2.47 seconds
Started Jul 16 07:58:09 PM PDT 24
Finished Jul 16 07:58:18 PM PDT 24
Peak memory 208560 kb
Host smart-0c6c2c7f-62f6-4a9e-98e3-2dc2a481778c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897077550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.2897077550
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.3926894822
Short name T45
Test name
Test status
Simulation time 745051886 ps
CPU time 9.03 seconds
Started Jul 16 07:58:44 PM PDT 24
Finished Jul 16 07:58:54 PM PDT 24
Peak memory 219820 kb
Host smart-837df970-5003-4572-b20d-dd75024bbdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926894822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.3926894822
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.4264995963
Short name T33
Test name
Test status
Simulation time 136092463 ps
CPU time 5.76 seconds
Started Jul 16 07:59:14 PM PDT 24
Finished Jul 16 07:59:25 PM PDT 24
Peak memory 218532 kb
Host smart-942fe907-f20c-42e0-8eb4-a7d413c5afa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264995963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.4264995963
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.2967848041
Short name T253
Test name
Test status
Simulation time 1177762427 ps
CPU time 29.97 seconds
Started Jul 16 07:57:59 PM PDT 24
Finished Jul 16 07:58:36 PM PDT 24
Peak memory 222716 kb
Host smart-9532188f-9de3-4cf7-ab54-9adb9a70a360
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967848041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2967848041
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.1943260835
Short name T384
Test name
Test status
Simulation time 97065278 ps
CPU time 5.41 seconds
Started Jul 16 07:58:14 PM PDT 24
Finished Jul 16 07:58:24 PM PDT 24
Peak memory 215008 kb
Host smart-b903068b-b413-4885-915e-9c350029d068
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1943260835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.1943260835
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.1320393204
Short name T144
Test name
Test status
Simulation time 68890930 ps
CPU time 3.87 seconds
Started Jul 16 07:57:40 PM PDT 24
Finished Jul 16 07:57:48 PM PDT 24
Peak memory 217728 kb
Host smart-29234ffe-4b92-4209-9a4d-8ad2f8a8a72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320393204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1320393204
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.3196482653
Short name T141
Test name
Test status
Simulation time 189397988 ps
CPU time 9.19 seconds
Started Jul 16 07:58:45 PM PDT 24
Finished Jul 16 07:58:57 PM PDT 24
Peak memory 214312 kb
Host smart-07cc6ad9-5c80-40ae-987a-946744748533
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3196482653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.3196482653
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.2835112685
Short name T94
Test name
Test status
Simulation time 321717164 ps
CPU time 3.88 seconds
Started Jul 16 07:59:11 PM PDT 24
Finished Jul 16 07:59:20 PM PDT 24
Peak memory 214332 kb
Host smart-2a82d372-5232-4189-8366-f89e1f706299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835112685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.2835112685
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3343546506
Short name T161
Test name
Test status
Simulation time 1033123775 ps
CPU time 7.55 seconds
Started Jul 16 07:10:36 PM PDT 24
Finished Jul 16 07:10:46 PM PDT 24
Peak memory 213684 kb
Host smart-9056b2fd-aafb-459a-a462-679f93fd2ee0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343546506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.3343546506
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.1611744682
Short name T52
Test name
Test status
Simulation time 22302710947 ps
CPU time 85.81 seconds
Started Jul 16 07:59:12 PM PDT 24
Finished Jul 16 08:00:43 PM PDT 24
Peak memory 216908 kb
Host smart-b1aaf6b3-e839-44ab-ac1f-8c6c77c06c5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611744682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.1611744682
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.1688111095
Short name T201
Test name
Test status
Simulation time 264137748 ps
CPU time 4.46 seconds
Started Jul 16 07:59:21 PM PDT 24
Finished Jul 16 07:59:27 PM PDT 24
Peak memory 222488 kb
Host smart-af2926c6-e6f5-44e9-915c-a3ad2e4ee548
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1688111095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1688111095
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.2864473277
Short name T47
Test name
Test status
Simulation time 63186537 ps
CPU time 2.73 seconds
Started Jul 16 07:58:53 PM PDT 24
Finished Jul 16 07:58:57 PM PDT 24
Peak memory 209812 kb
Host smart-db490e67-df34-4d85-9205-c66ef37ef82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864473277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.2864473277
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.1468140230
Short name T15
Test name
Test status
Simulation time 48118912 ps
CPU time 0.74 seconds
Started Jul 16 07:57:18 PM PDT 24
Finished Jul 16 07:57:20 PM PDT 24
Peak memory 206104 kb
Host smart-4b2a5511-1d32-4f76-9111-29eb10b843f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468140230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.1468140230
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.2063557849
Short name T36
Test name
Test status
Simulation time 121916860 ps
CPU time 4.06 seconds
Started Jul 16 07:56:44 PM PDT 24
Finished Jul 16 07:56:49 PM PDT 24
Peak memory 210392 kb
Host smart-4fdf00a8-65c5-49c2-b87f-1bb5307dd8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063557849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.2063557849
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1782802321
Short name T154
Test name
Test status
Simulation time 405921273 ps
CPU time 4.16 seconds
Started Jul 16 07:11:04 PM PDT 24
Finished Jul 16 07:11:11 PM PDT 24
Peak memory 215164 kb
Host smart-de90f5d0-6ae8-4c3f-bd07-e2ecb0767e2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782802321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.1782802321
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.2222318533
Short name T257
Test name
Test status
Simulation time 5832767379 ps
CPU time 20.13 seconds
Started Jul 16 07:57:43 PM PDT 24
Finished Jul 16 07:58:07 PM PDT 24
Peak memory 222556 kb
Host smart-81aa9732-7ab9-4a41-b33e-4c4080c9d778
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222318533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2222318533
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.4056311869
Short name T320
Test name
Test status
Simulation time 812211597 ps
CPU time 43.62 seconds
Started Jul 16 07:58:54 PM PDT 24
Finished Jul 16 07:59:39 PM PDT 24
Peak memory 215656 kb
Host smart-effc1bb0-4dd9-4168-a8f1-7e36c62423fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4056311869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.4056311869
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.2152557009
Short name T241
Test name
Test status
Simulation time 21165918917 ps
CPU time 113.31 seconds
Started Jul 16 07:58:54 PM PDT 24
Finished Jul 16 08:00:48 PM PDT 24
Peak memory 216500 kb
Host smart-f9cbcbba-4a53-4f79-958d-a1cdbaf79d20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152557009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.2152557009
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.661007400
Short name T259
Test name
Test status
Simulation time 83951203 ps
CPU time 1.68 seconds
Started Jul 16 07:56:48 PM PDT 24
Finished Jul 16 07:56:54 PM PDT 24
Peak memory 214392 kb
Host smart-f8a9203c-4951-48a9-bed3-afc93d37f21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661007400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.661007400
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.2764637144
Short name T41
Test name
Test status
Simulation time 52332243 ps
CPU time 2.17 seconds
Started Jul 16 07:57:24 PM PDT 24
Finished Jul 16 07:57:27 PM PDT 24
Peak memory 214224 kb
Host smart-0c27c51b-e16c-4bd2-bb58-2b7d2ddf7265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764637144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.2764637144
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.4186286625
Short name T103
Test name
Test status
Simulation time 449900501 ps
CPU time 4.21 seconds
Started Jul 16 07:59:08 PM PDT 24
Finished Jul 16 07:59:14 PM PDT 24
Peak memory 209612 kb
Host smart-c04b9c68-1afe-4378-8bdf-468cec57ba8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186286625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.4186286625
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.3242205638
Short name T112
Test name
Test status
Simulation time 423449931 ps
CPU time 17.1 seconds
Started Jul 16 07:57:03 PM PDT 24
Finished Jul 16 07:57:21 PM PDT 24
Peak memory 222628 kb
Host smart-1562899b-b22b-4cd7-90c2-9d51311a67ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242205638 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.3242205638
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.4137144155
Short name T309
Test name
Test status
Simulation time 963289161 ps
CPU time 34.71 seconds
Started Jul 16 07:57:21 PM PDT 24
Finished Jul 16 07:57:57 PM PDT 24
Peak memory 222388 kb
Host smart-229914b4-75b2-4173-8c39-0feea4a0b392
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137144155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.4137144155
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.3332405179
Short name T99
Test name
Test status
Simulation time 144942132 ps
CPU time 3.98 seconds
Started Jul 16 07:57:56 PM PDT 24
Finished Jul 16 07:58:04 PM PDT 24
Peak memory 214344 kb
Host smart-3c9127cf-792e-4a69-8c76-abeb7e8d29dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332405179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.3332405179
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.2709227927
Short name T162
Test name
Test status
Simulation time 704176258 ps
CPU time 8.79 seconds
Started Jul 16 07:11:05 PM PDT 24
Finished Jul 16 07:11:18 PM PDT 24
Peak memory 213724 kb
Host smart-35b4fea9-297d-4d79-9b09-12de9bd66515
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709227927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.2709227927
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.3769577340
Short name T55
Test name
Test status
Simulation time 193112013 ps
CPU time 1.75 seconds
Started Jul 16 07:57:22 PM PDT 24
Finished Jul 16 07:57:25 PM PDT 24
Peak memory 214340 kb
Host smart-e42ab535-d010-47c5-87fc-888d0f154c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769577340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.3769577340
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.1898746132
Short name T148
Test name
Test status
Simulation time 47180335 ps
CPU time 2.84 seconds
Started Jul 16 07:59:16 PM PDT 24
Finished Jul 16 07:59:24 PM PDT 24
Peak memory 222684 kb
Host smart-6581f91d-65c6-4eeb-a90d-d2e6d99d1c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898746132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.1898746132
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1905178006
Short name T145
Test name
Test status
Simulation time 338468962 ps
CPU time 3.87 seconds
Started Jul 16 07:57:03 PM PDT 24
Finished Jul 16 07:57:08 PM PDT 24
Peak memory 218280 kb
Host smart-274cfb75-0bc9-47e1-98ed-dd54035c965a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905178006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1905178006
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.3730873757
Short name T382
Test name
Test status
Simulation time 126211066 ps
CPU time 4.04 seconds
Started Jul 16 07:57:05 PM PDT 24
Finished Jul 16 07:57:10 PM PDT 24
Peak memory 214288 kb
Host smart-3deb94dd-90a4-4116-afba-92822850bb54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3730873757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.3730873757
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.415386463
Short name T143
Test name
Test status
Simulation time 106886691 ps
CPU time 5.18 seconds
Started Jul 16 07:56:52 PM PDT 24
Finished Jul 16 07:57:00 PM PDT 24
Peak memory 222652 kb
Host smart-20640f18-99c1-428a-9f1b-5efe403f292c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415386463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.415386463
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.1018600906
Short name T163
Test name
Test status
Simulation time 465268623 ps
CPU time 5.17 seconds
Started Jul 16 07:10:49 PM PDT 24
Finished Jul 16 07:10:55 PM PDT 24
Peak memory 213796 kb
Host smart-6924f772-8ca2-4211-ab57-252bfa66ef5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018600906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.1018600906
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.1356998175
Short name T155
Test name
Test status
Simulation time 475321438 ps
CPU time 9.66 seconds
Started Jul 16 07:10:49 PM PDT 24
Finished Jul 16 07:11:00 PM PDT 24
Peak memory 205604 kb
Host smart-349629bb-ac9f-4b65-9f2f-77db215326e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356998175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.1356998175
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2513485505
Short name T160
Test name
Test status
Simulation time 96509260 ps
CPU time 4.27 seconds
Started Jul 16 07:10:50 PM PDT 24
Finished Jul 16 07:10:57 PM PDT 24
Peak memory 213708 kb
Host smart-22821ec3-f504-45ba-ac31-0c42267cdc6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513485505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.2513485505
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.578579152
Short name T889
Test name
Test status
Simulation time 2446918263 ps
CPU time 19.57 seconds
Started Jul 16 07:57:03 PM PDT 24
Finished Jul 16 07:57:24 PM PDT 24
Peak memory 214848 kb
Host smart-f36fcedd-3338-4a7b-8166-33e959d49c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578579152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.578579152
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.4072446991
Short name T248
Test name
Test status
Simulation time 1186159835 ps
CPU time 31.47 seconds
Started Jul 16 07:56:40 PM PDT 24
Finished Jul 16 07:57:12 PM PDT 24
Peak memory 215360 kb
Host smart-6d7b7781-c421-4075-90a3-8316aa62579a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072446991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.4072446991
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.191025205
Short name T349
Test name
Test status
Simulation time 65337439 ps
CPU time 3.69 seconds
Started Jul 16 07:57:17 PM PDT 24
Finished Jul 16 07:57:22 PM PDT 24
Peak memory 222372 kb
Host smart-b8ae25b5-2c91-4a50-ba97-be18bd00ba05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191025205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.191025205
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.33386368
Short name T242
Test name
Test status
Simulation time 1132618820 ps
CPU time 19.19 seconds
Started Jul 16 07:57:41 PM PDT 24
Finished Jul 16 07:58:05 PM PDT 24
Peak memory 222524 kb
Host smart-528f7ae5-be4e-43f0-9a0f-63e290a7ea5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33386368 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.33386368
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.3655390391
Short name T233
Test name
Test status
Simulation time 4999411037 ps
CPU time 27.1 seconds
Started Jul 16 07:57:48 PM PDT 24
Finished Jul 16 07:58:21 PM PDT 24
Peak memory 215760 kb
Host smart-d4468cd8-fb23-4203-b046-de01f7148fcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655390391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.3655390391
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.943176672
Short name T430
Test name
Test status
Simulation time 2427648188 ps
CPU time 62.19 seconds
Started Jul 16 07:56:46 PM PDT 24
Finished Jul 16 07:57:52 PM PDT 24
Peak memory 215920 kb
Host smart-4b3968a2-7699-4534-a242-6e45c3cbfa7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=943176672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.943176672
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.1355223556
Short name T261
Test name
Test status
Simulation time 414407150 ps
CPU time 2.98 seconds
Started Jul 16 07:56:47 PM PDT 24
Finished Jul 16 07:56:53 PM PDT 24
Peak memory 214268 kb
Host smart-31691a83-1099-48a5-a899-9c2534038d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355223556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.1355223556
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.3202076210
Short name T184
Test name
Test status
Simulation time 275555515 ps
CPU time 3.41 seconds
Started Jul 16 07:58:42 PM PDT 24
Finished Jul 16 07:58:47 PM PDT 24
Peak memory 211144 kb
Host smart-be3668bc-5693-4bc8-8639-c8698e1a5036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202076210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.3202076210
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.3710241161
Short name T4
Test name
Test status
Simulation time 180957119 ps
CPU time 5.28 seconds
Started Jul 16 07:56:47 PM PDT 24
Finished Jul 16 07:56:56 PM PDT 24
Peak memory 208028 kb
Host smart-9410040a-0292-4032-9a95-d6d26bf66451
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710241161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.3710241161
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.1418600588
Short name T149
Test name
Test status
Simulation time 248452650 ps
CPU time 3.91 seconds
Started Jul 16 07:56:42 PM PDT 24
Finished Jul 16 07:56:47 PM PDT 24
Peak memory 222692 kb
Host smart-977ea40c-e398-48a9-8861-cbc6c840f265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418600588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.1418600588
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.3432106500
Short name T63
Test name
Test status
Simulation time 156662164 ps
CPU time 5.15 seconds
Started Jul 16 07:57:55 PM PDT 24
Finished Jul 16 07:58:05 PM PDT 24
Peak memory 218608 kb
Host smart-2142ec5a-3e53-490d-b1a3-694093d6492d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432106500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.3432106500
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.344976266
Short name T147
Test name
Test status
Simulation time 104981367 ps
CPU time 2.61 seconds
Started Jul 16 07:56:57 PM PDT 24
Finished Jul 16 07:57:02 PM PDT 24
Peak memory 222716 kb
Host smart-f2fd9ec4-903f-40db-a6af-d94f4ce6bba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344976266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.344976266
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.2674395025
Short name T423
Test name
Test status
Simulation time 236943783 ps
CPU time 13.18 seconds
Started Jul 16 07:56:26 PM PDT 24
Finished Jul 16 07:56:42 PM PDT 24
Peak memory 215520 kb
Host smart-c4daeb20-58c6-472d-a5bf-4526fa631b43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2674395025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.2674395025
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.1258691103
Short name T229
Test name
Test status
Simulation time 1261825752 ps
CPU time 26.2 seconds
Started Jul 16 07:56:43 PM PDT 24
Finished Jul 16 07:57:10 PM PDT 24
Peak memory 222612 kb
Host smart-14ad8917-126f-4f88-94cc-518a47899d48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258691103 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.1258691103
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.2983320569
Short name T23
Test name
Test status
Simulation time 70984394 ps
CPU time 1.71 seconds
Started Jul 16 07:57:11 PM PDT 24
Finished Jul 16 07:57:14 PM PDT 24
Peak memory 222076 kb
Host smart-5a84e4c2-38ba-4dfc-ae3a-353fbd2bf57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983320569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.2983320569
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.3677743834
Short name T312
Test name
Test status
Simulation time 143183795 ps
CPU time 2.64 seconds
Started Jul 16 07:57:05 PM PDT 24
Finished Jul 16 07:57:09 PM PDT 24
Peak memory 214268 kb
Host smart-d47f0643-f0b2-40a1-ae39-8a31a9991ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677743834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.3677743834
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.1108964520
Short name T818
Test name
Test status
Simulation time 379797137 ps
CPU time 2.91 seconds
Started Jul 16 07:57:51 PM PDT 24
Finished Jul 16 07:58:00 PM PDT 24
Peak memory 214308 kb
Host smart-cc6a6802-d42e-4cb4-8a47-773696f0ed01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108964520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.1108964520
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.367021790
Short name T337
Test name
Test status
Simulation time 228959382 ps
CPU time 3.47 seconds
Started Jul 16 07:56:46 PM PDT 24
Finished Jul 16 07:56:53 PM PDT 24
Peak memory 208760 kb
Host smart-4c0a1fa2-25ce-49a2-a848-c6c09fb6e308
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367021790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.367021790
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.1475224763
Short name T351
Test name
Test status
Simulation time 163743284 ps
CPU time 3.24 seconds
Started Jul 16 07:58:02 PM PDT 24
Finished Jul 16 07:58:12 PM PDT 24
Peak memory 215836 kb
Host smart-9a6b2fdd-8721-4299-85d2-dee9d333e2b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1475224763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.1475224763
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.455993078
Short name T207
Test name
Test status
Simulation time 3395855876 ps
CPU time 26.63 seconds
Started Jul 16 07:58:50 PM PDT 24
Finished Jul 16 07:59:18 PM PDT 24
Peak memory 220312 kb
Host smart-4f1e8099-59b5-4ae7-9b88-f6e67d6001df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455993078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.455993078
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.525769658
Short name T223
Test name
Test status
Simulation time 636823625 ps
CPU time 4 seconds
Started Jul 16 07:58:48 PM PDT 24
Finished Jul 16 07:58:54 PM PDT 24
Peak memory 214316 kb
Host smart-db9aa49b-28ab-4938-a922-014b3ce8ec11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525769658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.525769658
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.2876207476
Short name T425
Test name
Test status
Simulation time 99679551 ps
CPU time 5.5 seconds
Started Jul 16 07:56:46 PM PDT 24
Finished Jul 16 07:56:55 PM PDT 24
Peak memory 214320 kb
Host smart-bae3be2c-27ef-40a0-9091-84f808e8cafc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2876207476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.2876207476
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.2303637571
Short name T367
Test name
Test status
Simulation time 89275330 ps
CPU time 3.38 seconds
Started Jul 16 07:58:57 PM PDT 24
Finished Jul 16 07:59:04 PM PDT 24
Peak memory 214364 kb
Host smart-d3151926-d71c-4224-a3ed-8e7d6d5d6341
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2303637571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.2303637571
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2762799655
Short name T157
Test name
Test status
Simulation time 452587551 ps
CPU time 4.81 seconds
Started Jul 16 07:11:01 PM PDT 24
Finished Jul 16 07:11:07 PM PDT 24
Peak memory 214860 kb
Host smart-199d3232-7020-4682-ae79-74a9f6080ca3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762799655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.2762799655
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.1418534631
Short name T172
Test name
Test status
Simulation time 487607356 ps
CPU time 5.92 seconds
Started Jul 16 07:11:09 PM PDT 24
Finished Jul 16 07:11:39 PM PDT 24
Peak memory 205616 kb
Host smart-dbe0345b-0c58-4979-b5c6-ee9ef55184f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418534631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.1418534631
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2888206160
Short name T166
Test name
Test status
Simulation time 277563346 ps
CPU time 5.48 seconds
Started Jul 16 07:10:52 PM PDT 24
Finished Jul 16 07:11:00 PM PDT 24
Peak memory 213700 kb
Host smart-3699d56c-c124-4abc-9025-571e82b45931
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888206160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.2888206160
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.681069629
Short name T169
Test name
Test status
Simulation time 478832188 ps
CPU time 9.93 seconds
Started Jul 16 07:10:48 PM PDT 24
Finished Jul 16 07:11:00 PM PDT 24
Peak memory 213764 kb
Host smart-e03d7f40-a603-48b5-bdf2-11d11264dba8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681069629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.
681069629
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2460373410
Short name T164
Test name
Test status
Simulation time 494904067 ps
CPU time 8.83 seconds
Started Jul 16 07:10:48 PM PDT 24
Finished Jul 16 07:10:58 PM PDT 24
Peak memory 213692 kb
Host smart-13ec2a21-80a7-425f-aa82-2791ae770722
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460373410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.2460373410
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.857636070
Short name T51
Test name
Test status
Simulation time 3505672574 ps
CPU time 24.16 seconds
Started Jul 16 07:56:44 PM PDT 24
Finished Jul 16 07:57:11 PM PDT 24
Peak memory 231584 kb
Host smart-f293fd47-c2af-4c21-9c4f-cef4f14790c1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857636070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.857636070
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.3642015766
Short name T50
Test name
Test status
Simulation time 733907595 ps
CPU time 18.44 seconds
Started Jul 16 07:56:50 PM PDT 24
Finished Jul 16 07:57:13 PM PDT 24
Peak memory 237568 kb
Host smart-2e30a124-ecc7-4967-a9dd-7168ed485ba8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642015766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.3642015766
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.1531825031
Short name T31
Test name
Test status
Simulation time 259072707 ps
CPU time 2.45 seconds
Started Jul 16 07:57:50 PM PDT 24
Finished Jul 16 07:57:58 PM PDT 24
Peak memory 214680 kb
Host smart-528aa4bc-83e6-480a-aa26-718a4cc8643e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531825031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.1531825031
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.3296283468
Short name T237
Test name
Test status
Simulation time 3616753548 ps
CPU time 42.5 seconds
Started Jul 16 07:56:41 PM PDT 24
Finished Jul 16 07:57:24 PM PDT 24
Peak memory 216772 kb
Host smart-b4193547-eefd-457c-916e-32d6a25a9418
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296283468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3296283468
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.3472554949
Short name T48
Test name
Test status
Simulation time 5850652492 ps
CPU time 30.8 seconds
Started Jul 16 07:56:45 PM PDT 24
Finished Jul 16 07:57:19 PM PDT 24
Peak memory 211736 kb
Host smart-a3969358-f73e-452c-a0ec-27e873e51888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472554949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.3472554949
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_random.4203778953
Short name T467
Test name
Test status
Simulation time 304952398 ps
CPU time 5.31 seconds
Started Jul 16 07:57:22 PM PDT 24
Finished Jul 16 07:57:28 PM PDT 24
Peak memory 207152 kb
Host smart-f4c88aad-977a-4c20-be92-ea90adb199af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203778953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.4203778953
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.432047107
Short name T353
Test name
Test status
Simulation time 126396332 ps
CPU time 3.45 seconds
Started Jul 16 07:57:41 PM PDT 24
Finished Jul 16 07:57:49 PM PDT 24
Peak memory 208624 kb
Host smart-5465026a-4b71-412f-8d33-bbe5793f5fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432047107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.432047107
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_random.1161532315
Short name T747
Test name
Test status
Simulation time 1034568503 ps
CPU time 7.56 seconds
Started Jul 16 07:57:41 PM PDT 24
Finished Jul 16 07:57:51 PM PDT 24
Peak memory 207196 kb
Host smart-f68b8fcf-4826-4b08-8548-a5b7bdc262b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161532315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.1161532315
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.3980073387
Short name T340
Test name
Test status
Simulation time 78329630 ps
CPU time 4.62 seconds
Started Jul 16 07:58:08 PM PDT 24
Finished Jul 16 07:58:19 PM PDT 24
Peak memory 214380 kb
Host smart-d10afc26-64be-4958-9c28-755dc87c59f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3980073387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.3980073387
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.1563427325
Short name T378
Test name
Test status
Simulation time 43762687 ps
CPU time 3.15 seconds
Started Jul 16 07:58:05 PM PDT 24
Finished Jul 16 07:58:16 PM PDT 24
Peak memory 210432 kb
Host smart-892b8f10-eaf5-45ed-9892-43cfc41db26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563427325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.1563427325
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.3822264331
Short name T231
Test name
Test status
Simulation time 142965976 ps
CPU time 2.89 seconds
Started Jul 16 07:58:08 PM PDT 24
Finished Jul 16 07:58:18 PM PDT 24
Peak memory 209344 kb
Host smart-8e99f5fe-f548-4864-abdb-6bd20a3974a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822264331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.3822264331
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.2178892335
Short name T102
Test name
Test status
Simulation time 165103622 ps
CPU time 3.87 seconds
Started Jul 16 07:58:22 PM PDT 24
Finished Jul 16 07:58:27 PM PDT 24
Peak memory 222536 kb
Host smart-047e300f-ef68-4836-838d-47aa88ebb2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178892335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.2178892335
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.2468644233
Short name T222
Test name
Test status
Simulation time 165164383 ps
CPU time 7.17 seconds
Started Jul 16 07:58:46 PM PDT 24
Finished Jul 16 07:58:56 PM PDT 24
Peak memory 222600 kb
Host smart-9584c460-399c-47ce-be6c-fdc409aa0d5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468644233 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.2468644233
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.1134556544
Short name T334
Test name
Test status
Simulation time 579519493 ps
CPU time 3.61 seconds
Started Jul 16 07:56:45 PM PDT 24
Finished Jul 16 07:56:53 PM PDT 24
Peak memory 214352 kb
Host smart-5c61627d-1fc7-4d4a-b98e-4373060dec1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134556544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.1134556544
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.3860441943
Short name T130
Test name
Test status
Simulation time 199958792 ps
CPU time 10.18 seconds
Started Jul 16 07:59:11 PM PDT 24
Finished Jul 16 07:59:27 PM PDT 24
Peak memory 222400 kb
Host smart-25e3c530-66ac-475a-9cfb-d914afcdcd41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3860441943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.3860441943
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.293176283
Short name T245
Test name
Test status
Simulation time 202909200 ps
CPU time 3.64 seconds
Started Jul 16 07:59:08 PM PDT 24
Finished Jul 16 07:59:14 PM PDT 24
Peak memory 215912 kb
Host smart-817a68a8-5dfb-4e32-a00d-182bf51afeb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293176283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.293176283
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.2791346685
Short name T59
Test name
Test status
Simulation time 127870720 ps
CPU time 3.6 seconds
Started Jul 16 07:59:20 PM PDT 24
Finished Jul 16 07:59:26 PM PDT 24
Peak memory 214340 kb
Host smart-9520ca6a-053d-42d0-805f-1b80a8ec84ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791346685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2791346685
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3541595126
Short name T1020
Test name
Test status
Simulation time 999136015 ps
CPU time 6.22 seconds
Started Jul 16 07:10:47 PM PDT 24
Finished Jul 16 07:10:54 PM PDT 24
Peak memory 205668 kb
Host smart-c3a33c6d-ac3a-438f-a027-d0965892c8f3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541595126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.3
541595126
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1600639136
Short name T970
Test name
Test status
Simulation time 5112506569 ps
CPU time 31.86 seconds
Started Jul 16 07:10:47 PM PDT 24
Finished Jul 16 07:11:20 PM PDT 24
Peak memory 205608 kb
Host smart-c7a7d34c-6655-463c-8552-66596fb76496
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600639136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.1
600639136
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.4128347967
Short name T1000
Test name
Test status
Simulation time 115768746 ps
CPU time 1.12 seconds
Started Jul 16 07:10:37 PM PDT 24
Finished Jul 16 07:10:41 PM PDT 24
Peak memory 205504 kb
Host smart-a755c149-b280-4f5d-8526-9572f088f9e3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128347967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.4
128347967
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3069848150
Short name T945
Test name
Test status
Simulation time 43257892 ps
CPU time 1.47 seconds
Started Jul 16 07:10:50 PM PDT 24
Finished Jul 16 07:10:54 PM PDT 24
Peak memory 213952 kb
Host smart-c240922c-34f7-4feb-b28c-fc8f35b9eae7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069848150 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.3069848150
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1109987100
Short name T978
Test name
Test status
Simulation time 118839023 ps
CPU time 1.56 seconds
Started Jul 16 07:10:37 PM PDT 24
Finished Jul 16 07:10:41 PM PDT 24
Peak memory 205528 kb
Host smart-8629b167-f31a-40bc-89b6-9581eb923fd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109987100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1109987100
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3214191652
Short name T949
Test name
Test status
Simulation time 85711734 ps
CPU time 0.96 seconds
Started Jul 16 07:10:33 PM PDT 24
Finished Jul 16 07:10:36 PM PDT 24
Peak memory 205392 kb
Host smart-221f940b-0b7b-49cf-8981-cec94c7e807e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214191652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.3214191652
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3525081170
Short name T1043
Test name
Test status
Simulation time 41758101 ps
CPU time 1.42 seconds
Started Jul 16 07:10:47 PM PDT 24
Finished Jul 16 07:10:50 PM PDT 24
Peak memory 205468 kb
Host smart-d437a189-5f1a-41fe-a98b-de03bd04d895
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525081170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.3525081170
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1937730112
Short name T948
Test name
Test status
Simulation time 498532387 ps
CPU time 2.09 seconds
Started Jul 16 07:10:34 PM PDT 24
Finished Jul 16 07:10:37 PM PDT 24
Peak memory 214076 kb
Host smart-11b9df79-4879-4991-8e09-fc535a1621ef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937730112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.1937730112
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.926971058
Short name T1042
Test name
Test status
Simulation time 228516509 ps
CPU time 5.33 seconds
Started Jul 16 07:10:36 PM PDT 24
Finished Jul 16 07:10:45 PM PDT 24
Peak memory 214008 kb
Host smart-65a29e44-7217-4acd-a330-f538e6656c35
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926971058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_shadow_reg_errors_with_csr_rw.926971058
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1878393292
Short name T1052
Test name
Test status
Simulation time 297201222 ps
CPU time 2.94 seconds
Started Jul 16 07:10:35 PM PDT 24
Finished Jul 16 07:10:41 PM PDT 24
Peak memory 213748 kb
Host smart-fe82f551-30c5-429e-80b1-73e7e17d9472
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878393292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1878393292
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.1612630688
Short name T1011
Test name
Test status
Simulation time 772325647 ps
CPU time 5.07 seconds
Started Jul 16 07:10:53 PM PDT 24
Finished Jul 16 07:11:01 PM PDT 24
Peak memory 205524 kb
Host smart-b4f888fc-54e2-46c3-9529-0312d190c356
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612630688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.1
612630688
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3652773926
Short name T972
Test name
Test status
Simulation time 4246610642 ps
CPU time 16.61 seconds
Started Jul 16 07:10:49 PM PDT 24
Finished Jul 16 07:11:07 PM PDT 24
Peak memory 205556 kb
Host smart-025d9807-46ae-41c5-b829-8fddcae9432a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652773926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.3
652773926
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1085964226
Short name T1067
Test name
Test status
Simulation time 38547008 ps
CPU time 1.54 seconds
Started Jul 16 07:10:48 PM PDT 24
Finished Jul 16 07:10:52 PM PDT 24
Peak memory 205416 kb
Host smart-b0c0bcb0-542a-4a87-ba17-5c7d041399ae
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085964226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.1
085964226
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3437158948
Short name T939
Test name
Test status
Simulation time 12653500 ps
CPU time 1.01 seconds
Started Jul 16 07:11:22 PM PDT 24
Finished Jul 16 07:12:36 PM PDT 24
Peak memory 205504 kb
Host smart-8b20b8a9-12fa-4d35-b0a9-a47f0965065d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437158948 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.3437158948
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3588283049
Short name T1012
Test name
Test status
Simulation time 15076576 ps
CPU time 0.92 seconds
Started Jul 16 07:10:48 PM PDT 24
Finished Jul 16 07:10:50 PM PDT 24
Peak memory 205388 kb
Host smart-a1f04e47-6e3e-40bb-b348-f7c9abff8321
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588283049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.3588283049
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.193163437
Short name T955
Test name
Test status
Simulation time 13486721 ps
CPU time 0.88 seconds
Started Jul 16 07:10:48 PM PDT 24
Finished Jul 16 07:10:51 PM PDT 24
Peak memory 205372 kb
Host smart-cad273e3-7643-4896-babc-e2dcfe5af8bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193163437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.193163437
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.919418618
Short name T953
Test name
Test status
Simulation time 46454599 ps
CPU time 1.51 seconds
Started Jul 16 07:10:49 PM PDT 24
Finished Jul 16 07:10:52 PM PDT 24
Peak memory 205460 kb
Host smart-0338e14f-e74d-4d38-8a7d-cb49d484b337
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919418618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sam
e_csr_outstanding.919418618
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.58844390
Short name T946
Test name
Test status
Simulation time 125059353 ps
CPU time 3.66 seconds
Started Jul 16 07:10:50 PM PDT 24
Finished Jul 16 07:10:55 PM PDT 24
Peak memory 214068 kb
Host smart-029a5a0d-2190-4fec-adab-67b0d1eca864
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58844390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow_
reg_errors.58844390
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3185627299
Short name T991
Test name
Test status
Simulation time 699952670 ps
CPU time 6.34 seconds
Started Jul 16 07:10:48 PM PDT 24
Finished Jul 16 07:10:56 PM PDT 24
Peak memory 219892 kb
Host smart-40fd26ad-4489-4f59-b6b2-9e458643e93c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185627299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.3185627299
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.4284569212
Short name T1049
Test name
Test status
Simulation time 65841377 ps
CPU time 1.85 seconds
Started Jul 16 07:10:50 PM PDT 24
Finished Jul 16 07:10:53 PM PDT 24
Peak memory 214864 kb
Host smart-142f2e08-6b60-482d-9133-30743e69d263
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284569212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.4284569212
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.103294331
Short name T1045
Test name
Test status
Simulation time 25935017 ps
CPU time 1.09 seconds
Started Jul 16 07:11:01 PM PDT 24
Finished Jul 16 07:11:03 PM PDT 24
Peak memory 205600 kb
Host smart-a910218e-043d-479c-ba54-c0c55d8337e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103294331 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.103294331
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2248012583
Short name T1024
Test name
Test status
Simulation time 49238229 ps
CPU time 1.05 seconds
Started Jul 16 07:11:03 PM PDT 24
Finished Jul 16 07:11:05 PM PDT 24
Peak memory 205448 kb
Host smart-9d40bffc-ac66-4e3e-869f-0c29750e22ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248012583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.2248012583
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.875440958
Short name T1048
Test name
Test status
Simulation time 11210492 ps
CPU time 0.88 seconds
Started Jul 16 07:11:02 PM PDT 24
Finished Jul 16 07:11:04 PM PDT 24
Peak memory 205376 kb
Host smart-073f5e78-4343-4270-8793-83a7349ea642
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875440958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.875440958
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.3732529426
Short name T1079
Test name
Test status
Simulation time 76687839 ps
CPU time 2.49 seconds
Started Jul 16 07:11:03 PM PDT 24
Finished Jul 16 07:11:08 PM PDT 24
Peak memory 205472 kb
Host smart-b7dbce17-50dd-4b48-a61b-7538e1243313
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732529426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.3732529426
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.4042998959
Short name T1065
Test name
Test status
Simulation time 798145317 ps
CPU time 4.4 seconds
Started Jul 16 07:11:04 PM PDT 24
Finished Jul 16 07:11:11 PM PDT 24
Peak memory 218748 kb
Host smart-c8c6b39d-45f7-415a-a633-fa670245653d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042998959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.4042998959
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.2737720066
Short name T1023
Test name
Test status
Simulation time 672646663 ps
CPU time 4.56 seconds
Started Jul 16 07:11:04 PM PDT 24
Finished Jul 16 07:11:11 PM PDT 24
Peak memory 213972 kb
Host smart-5e69dbe5-a4b3-497c-b735-4e06f51ecc80
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737720066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.2737720066
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1604485340
Short name T1025
Test name
Test status
Simulation time 64069312 ps
CPU time 2.18 seconds
Started Jul 16 07:11:01 PM PDT 24
Finished Jul 16 07:11:03 PM PDT 24
Peak memory 213660 kb
Host smart-251701c8-387f-4df3-9978-458652841889
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604485340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.1604485340
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3071141191
Short name T168
Test name
Test status
Simulation time 1689475761 ps
CPU time 3.7 seconds
Started Jul 16 07:11:09 PM PDT 24
Finished Jul 16 07:11:37 PM PDT 24
Peak memory 213800 kb
Host smart-0fa30337-0d2e-48ec-86c9-f404b447872e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071141191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.3071141191
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.4024194166
Short name T956
Test name
Test status
Simulation time 52908514 ps
CPU time 2.14 seconds
Started Jul 16 07:11:06 PM PDT 24
Finished Jul 16 07:11:15 PM PDT 24
Peak memory 213788 kb
Host smart-d1402911-006e-411c-9a8f-1ac9af763395
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024194166 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.4024194166
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3553696070
Short name T1007
Test name
Test status
Simulation time 42228242 ps
CPU time 1.1 seconds
Started Jul 16 07:11:03 PM PDT 24
Finished Jul 16 07:11:05 PM PDT 24
Peak memory 205440 kb
Host smart-f617120f-b282-45bb-a7c1-c22b2f1658e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553696070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.3553696070
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2784101665
Short name T917
Test name
Test status
Simulation time 15940092 ps
CPU time 0.76 seconds
Started Jul 16 07:11:05 PM PDT 24
Finished Jul 16 07:11:09 PM PDT 24
Peak memory 205392 kb
Host smart-cbb7ac3b-502a-44fe-ace1-1da16933daa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784101665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.2784101665
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.785381431
Short name T135
Test name
Test status
Simulation time 218890691 ps
CPU time 1.47 seconds
Started Jul 16 07:11:10 PM PDT 24
Finished Jul 16 07:11:47 PM PDT 24
Peak memory 205416 kb
Host smart-06d21268-4691-4ed1-92a5-b16132cbe51f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785381431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_sa
me_csr_outstanding.785381431
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.333258650
Short name T1046
Test name
Test status
Simulation time 1122013344 ps
CPU time 3.67 seconds
Started Jul 16 07:11:03 PM PDT 24
Finished Jul 16 07:11:08 PM PDT 24
Peak memory 214060 kb
Host smart-c21d3aad-2796-4423-800d-d71c90072baa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333258650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shado
w_reg_errors.333258650
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2253671845
Short name T994
Test name
Test status
Simulation time 1739975548 ps
CPU time 9.64 seconds
Started Jul 16 07:11:05 PM PDT 24
Finished Jul 16 07:11:19 PM PDT 24
Peak memory 214096 kb
Host smart-57ba96f7-f342-4083-bfbe-533c668330a1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253671845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.2253671845
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.4069459820
Short name T919
Test name
Test status
Simulation time 61267223 ps
CPU time 2.82 seconds
Started Jul 16 07:11:04 PM PDT 24
Finished Jul 16 07:11:10 PM PDT 24
Peak memory 213580 kb
Host smart-d8f7f7f5-31ab-44b7-adcc-8623156984b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069459820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.4069459820
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.3282322000
Short name T930
Test name
Test status
Simulation time 79858511 ps
CPU time 3.38 seconds
Started Jul 16 07:11:05 PM PDT 24
Finished Jul 16 07:11:12 PM PDT 24
Peak memory 213800 kb
Host smart-42465073-47a6-4165-b07c-6df7ab3891e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282322000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.3282322000
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.3796169694
Short name T1040
Test name
Test status
Simulation time 56337372 ps
CPU time 1.74 seconds
Started Jul 16 07:11:05 PM PDT 24
Finished Jul 16 07:11:10 PM PDT 24
Peak memory 213864 kb
Host smart-d47c13cc-8f6d-4eda-904f-9cb0abab1220
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796169694 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.3796169694
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.3543731868
Short name T931
Test name
Test status
Simulation time 31620123 ps
CPU time 1.2 seconds
Started Jul 16 07:11:05 PM PDT 24
Finished Jul 16 07:11:10 PM PDT 24
Peak memory 205708 kb
Host smart-e0b54de7-9d54-4786-87bd-86b2c7bf2491
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543731868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.3543731868
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2994090770
Short name T988
Test name
Test status
Simulation time 39049639 ps
CPU time 0.74 seconds
Started Jul 16 07:11:04 PM PDT 24
Finished Jul 16 07:11:08 PM PDT 24
Peak memory 205320 kb
Host smart-fef2a8af-7607-4ab6-b1c2-998dc24c5cd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994090770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.2994090770
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.1962800870
Short name T1081
Test name
Test status
Simulation time 32981205 ps
CPU time 1.94 seconds
Started Jul 16 07:11:03 PM PDT 24
Finished Jul 16 07:11:07 PM PDT 24
Peak memory 205668 kb
Host smart-5464c044-e848-4206-a512-8c5e21e6ab49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962800870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.1962800870
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1569297558
Short name T1063
Test name
Test status
Simulation time 398442317 ps
CPU time 1.7 seconds
Started Jul 16 07:11:05 PM PDT 24
Finished Jul 16 07:11:11 PM PDT 24
Peak memory 214044 kb
Host smart-562031bb-dee6-4517-b9fb-790414112506
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569297558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.1569297558
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2835655872
Short name T1051
Test name
Test status
Simulation time 43267775 ps
CPU time 1.99 seconds
Started Jul 16 07:11:05 PM PDT 24
Finished Jul 16 07:11:12 PM PDT 24
Peak memory 213768 kb
Host smart-285af4aa-69a2-45ec-bd7b-afff6e9fb31c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835655872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.2835655872
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.1547993180
Short name T401
Test name
Test status
Simulation time 166222118 ps
CPU time 5.32 seconds
Started Jul 16 07:11:03 PM PDT 24
Finished Jul 16 07:11:11 PM PDT 24
Peak memory 205604 kb
Host smart-65812166-d5cb-4d48-9274-00a8c78d9c5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547993180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.1547993180
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.720040502
Short name T1050
Test name
Test status
Simulation time 190253881 ps
CPU time 1.43 seconds
Started Jul 16 07:11:04 PM PDT 24
Finished Jul 16 07:11:07 PM PDT 24
Peak memory 213768 kb
Host smart-c3e7b172-e08e-47ec-996f-8eb32e147332
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720040502 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.720040502
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.3246556028
Short name T178
Test name
Test status
Simulation time 37548359 ps
CPU time 0.89 seconds
Started Jul 16 07:11:06 PM PDT 24
Finished Jul 16 07:11:14 PM PDT 24
Peak memory 205368 kb
Host smart-58c23aeb-00f3-442b-9d10-232cb11cd818
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246556028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.3246556028
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3009627068
Short name T1026
Test name
Test status
Simulation time 16672187 ps
CPU time 0.82 seconds
Started Jul 16 07:11:07 PM PDT 24
Finished Jul 16 07:11:17 PM PDT 24
Peak memory 205380 kb
Host smart-e8aed86b-d242-4bbe-b13a-4ff8d90b27be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009627068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3009627068
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.886069442
Short name T1068
Test name
Test status
Simulation time 117873243 ps
CPU time 1.54 seconds
Started Jul 16 07:11:04 PM PDT 24
Finished Jul 16 07:11:08 PM PDT 24
Peak memory 213744 kb
Host smart-715aee23-f0d8-49d1-9c13-ac8925856f44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886069442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_sa
me_csr_outstanding.886069442
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2781973165
Short name T986
Test name
Test status
Simulation time 144841208 ps
CPU time 1.43 seconds
Started Jul 16 07:11:06 PM PDT 24
Finished Jul 16 07:11:13 PM PDT 24
Peak memory 214096 kb
Host smart-0fd5de48-18c5-4db8-b86b-ffb21dcff37f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781973165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.2781973165
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1193844316
Short name T1034
Test name
Test status
Simulation time 147928753 ps
CPU time 6.56 seconds
Started Jul 16 07:11:05 PM PDT 24
Finished Jul 16 07:11:15 PM PDT 24
Peak memory 214092 kb
Host smart-8d80ac2c-4a77-41b1-9c18-ffdcd910a668
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193844316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.1193844316
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3458831297
Short name T1078
Test name
Test status
Simulation time 198621038 ps
CPU time 3.6 seconds
Started Jul 16 07:11:04 PM PDT 24
Finished Jul 16 07:11:11 PM PDT 24
Peak memory 216844 kb
Host smart-b908b5cd-2cb2-48d3-b35f-bf98f8bd4c2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458831297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.3458831297
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2709456241
Short name T987
Test name
Test status
Simulation time 41807315 ps
CPU time 1.26 seconds
Started Jul 16 07:11:10 PM PDT 24
Finished Jul 16 07:11:47 PM PDT 24
Peak memory 213808 kb
Host smart-1ba67934-da38-4fae-9927-e9a05701ae91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709456241 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.2709456241
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.3225599659
Short name T137
Test name
Test status
Simulation time 95600042 ps
CPU time 1.23 seconds
Started Jul 16 07:11:06 PM PDT 24
Finished Jul 16 07:11:14 PM PDT 24
Peak memory 205548 kb
Host smart-00e89bc3-07b1-4d04-abdf-b3a2a4e25efa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225599659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.3225599659
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2091561256
Short name T1031
Test name
Test status
Simulation time 10777457 ps
CPU time 0.75 seconds
Started Jul 16 07:11:05 PM PDT 24
Finished Jul 16 07:11:10 PM PDT 24
Peak memory 205380 kb
Host smart-4b633adb-f583-455a-9d69-c4a1ae7070ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091561256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2091561256
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2703428043
Short name T944
Test name
Test status
Simulation time 540259949 ps
CPU time 3.66 seconds
Started Jul 16 07:11:11 PM PDT 24
Finished Jul 16 07:11:50 PM PDT 24
Peak memory 205412 kb
Host smart-17f36a9c-088d-4cc7-997a-acdb6d458c7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703428043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.2703428043
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1876288853
Short name T952
Test name
Test status
Simulation time 192049567 ps
CPU time 3.69 seconds
Started Jul 16 07:11:09 PM PDT 24
Finished Jul 16 07:11:30 PM PDT 24
Peak memory 214104 kb
Host smart-fed6dc03-40dc-4e3c-b884-ca5f55df1987
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876288853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.1876288853
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.409493262
Short name T997
Test name
Test status
Simulation time 254740114 ps
CPU time 7.51 seconds
Started Jul 16 07:11:08 PM PDT 24
Finished Jul 16 07:11:31 PM PDT 24
Peak memory 214084 kb
Host smart-5f6eef98-121d-4e80-a9c0-d47ee8a3b844
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409493262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
keymgr_shadow_reg_errors_with_csr_rw.409493262
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.3809485757
Short name T959
Test name
Test status
Simulation time 103152209 ps
CPU time 3.79 seconds
Started Jul 16 07:11:10 PM PDT 24
Finished Jul 16 07:11:43 PM PDT 24
Peak memory 213500 kb
Host smart-7f201be9-0dbf-4d04-9f1a-4ff571ccad29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809485757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.3809485757
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3460373147
Short name T941
Test name
Test status
Simulation time 23396060 ps
CPU time 1.24 seconds
Started Jul 16 07:11:10 PM PDT 24
Finished Jul 16 07:11:40 PM PDT 24
Peak memory 213852 kb
Host smart-fcd7874c-0966-42a0-95d4-33278bf39e99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460373147 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.3460373147
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2584566174
Short name T1062
Test name
Test status
Simulation time 121154290 ps
CPU time 0.98 seconds
Started Jul 16 07:11:10 PM PDT 24
Finished Jul 16 07:11:40 PM PDT 24
Peak memory 205340 kb
Host smart-bd334294-e29c-4957-9d49-d4e7b2f4d750
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584566174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.2584566174
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.627483846
Short name T1077
Test name
Test status
Simulation time 36686010 ps
CPU time 0.72 seconds
Started Jul 16 07:11:05 PM PDT 24
Finished Jul 16 07:11:11 PM PDT 24
Peak memory 205332 kb
Host smart-64363f43-03e2-4367-aeed-a75ab7d11a92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627483846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.627483846
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3101740602
Short name T1015
Test name
Test status
Simulation time 99575786 ps
CPU time 3.74 seconds
Started Jul 16 07:11:06 PM PDT 24
Finished Jul 16 07:11:15 PM PDT 24
Peak memory 205572 kb
Host smart-7c597d39-76e3-43f6-bbad-f79a0886103e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101740602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.3101740602
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2592671111
Short name T1058
Test name
Test status
Simulation time 315897155 ps
CPU time 2.38 seconds
Started Jul 16 07:11:03 PM PDT 24
Finished Jul 16 07:11:07 PM PDT 24
Peak memory 214108 kb
Host smart-5b2c8bb4-5797-48bf-a16b-f4005d5c1121
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592671111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.2592671111
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3351674931
Short name T981
Test name
Test status
Simulation time 357022858 ps
CPU time 10.21 seconds
Started Jul 16 07:11:05 PM PDT 24
Finished Jul 16 07:11:20 PM PDT 24
Peak memory 220588 kb
Host smart-8bc111a4-7585-4e90-ae34-91aa366f8449
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351674931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.3351674931
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.865848930
Short name T964
Test name
Test status
Simulation time 26464099 ps
CPU time 1.62 seconds
Started Jul 16 07:11:05 PM PDT 24
Finished Jul 16 07:11:11 PM PDT 24
Peak memory 213772 kb
Host smart-cd5d196f-3486-41c0-b26c-1d3ac9bbc78f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865848930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.865848930
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.879123189
Short name T1053
Test name
Test status
Simulation time 565451684 ps
CPU time 3.47 seconds
Started Jul 16 07:11:09 PM PDT 24
Finished Jul 16 07:11:27 PM PDT 24
Peak memory 213772 kb
Host smart-1d24e8e4-0051-4213-8a44-0d430da9c9d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879123189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err
.879123189
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.637934455
Short name T971
Test name
Test status
Simulation time 74127428 ps
CPU time 1.41 seconds
Started Jul 16 07:11:14 PM PDT 24
Finished Jul 16 07:12:06 PM PDT 24
Peak memory 221700 kb
Host smart-f99b27e3-4c6d-4d21-98f8-d8f976c44f97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637934455 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.637934455
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3735255992
Short name T947
Test name
Test status
Simulation time 40172333 ps
CPU time 0.87 seconds
Started Jul 16 07:11:06 PM PDT 24
Finished Jul 16 07:11:14 PM PDT 24
Peak memory 205412 kb
Host smart-1dcb14f9-e13e-4190-869e-194b76646bf5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735255992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.3735255992
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3135053892
Short name T954
Test name
Test status
Simulation time 10283461 ps
CPU time 0.71 seconds
Started Jul 16 07:11:09 PM PDT 24
Finished Jul 16 07:11:27 PM PDT 24
Peak memory 205348 kb
Host smart-04bf519c-4c4a-4104-b538-4fa979dbed5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135053892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3135053892
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.685786198
Short name T1016
Test name
Test status
Simulation time 216984156 ps
CPU time 1.32 seconds
Started Jul 16 07:11:11 PM PDT 24
Finished Jul 16 07:11:54 PM PDT 24
Peak memory 205548 kb
Host smart-a50f8337-d54b-46ef-ba81-a619e5fcc3cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685786198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_sa
me_csr_outstanding.685786198
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.598853313
Short name T1037
Test name
Test status
Simulation time 1046178612 ps
CPU time 2.92 seconds
Started Jul 16 07:11:14 PM PDT 24
Finished Jul 16 07:12:07 PM PDT 24
Peak memory 213812 kb
Host smart-42461f5c-9535-46d8-a16d-75eea17e375c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598853313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shado
w_reg_errors.598853313
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3629530081
Short name T113
Test name
Test status
Simulation time 185715921 ps
CPU time 4.28 seconds
Started Jul 16 07:11:07 PM PDT 24
Finished Jul 16 07:11:18 PM PDT 24
Peak memory 214096 kb
Host smart-82c51cff-379f-4f70-8d6c-7490d11a0158
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629530081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3629530081
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1060362633
Short name T1060
Test name
Test status
Simulation time 380557918 ps
CPU time 3.62 seconds
Started Jul 16 07:11:06 PM PDT 24
Finished Jul 16 07:11:17 PM PDT 24
Peak memory 213760 kb
Host smart-2fa48622-e28f-447f-b527-5184319171a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060362633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1060362633
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.1349521603
Short name T152
Test name
Test status
Simulation time 109673430 ps
CPU time 3.34 seconds
Started Jul 16 07:11:10 PM PDT 24
Finished Jul 16 07:11:42 PM PDT 24
Peak memory 213776 kb
Host smart-2d54e5c8-3078-4a03-9f7b-93eb3f90dd60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349521603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.1349521603
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1560843756
Short name T927
Test name
Test status
Simulation time 54520096 ps
CPU time 2.04 seconds
Started Jul 16 07:11:10 PM PDT 24
Finished Jul 16 07:11:41 PM PDT 24
Peak memory 213844 kb
Host smart-56fbac5e-5277-423a-9468-5a2d1b1c6bdb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560843756 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.1560843756
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2730522670
Short name T990
Test name
Test status
Simulation time 25314726 ps
CPU time 1.45 seconds
Started Jul 16 07:11:08 PM PDT 24
Finished Jul 16 07:11:24 PM PDT 24
Peak memory 205508 kb
Host smart-145f1e6a-6bf0-41be-be1a-6ed17f04ac0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730522670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.2730522670
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2200249745
Short name T1009
Test name
Test status
Simulation time 115537349 ps
CPU time 0.69 seconds
Started Jul 16 07:11:10 PM PDT 24
Finished Jul 16 07:11:40 PM PDT 24
Peak memory 205288 kb
Host smart-dd64e6c4-f49d-4904-9ea6-3d3efe5df934
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200249745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2200249745
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1088728171
Short name T1072
Test name
Test status
Simulation time 35127013 ps
CPU time 1.39 seconds
Started Jul 16 07:11:09 PM PDT 24
Finished Jul 16 07:11:25 PM PDT 24
Peak memory 205576 kb
Host smart-6c442ee1-1c3b-4f5c-9cf1-2c15652b5d8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088728171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.1088728171
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.165439246
Short name T1003
Test name
Test status
Simulation time 335709635 ps
CPU time 3.88 seconds
Started Jul 16 07:11:09 PM PDT 24
Finished Jul 16 07:11:31 PM PDT 24
Peak memory 213988 kb
Host smart-d0f93979-751a-4001-9cd2-a0138d02ba73
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165439246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shado
w_reg_errors.165439246
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.1075973580
Short name T1010
Test name
Test status
Simulation time 393951876 ps
CPU time 9.12 seconds
Started Jul 16 07:11:10 PM PDT 24
Finished Jul 16 07:11:43 PM PDT 24
Peak memory 214116 kb
Host smart-7215f959-f676-47d0-87b1-6e943dbcf842
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075973580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.1075973580
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.2873127570
Short name T925
Test name
Test status
Simulation time 47977471 ps
CPU time 1.83 seconds
Started Jul 16 07:11:10 PM PDT 24
Finished Jul 16 07:11:41 PM PDT 24
Peak memory 213668 kb
Host smart-d25e140b-05da-4572-98b0-8609f728d46b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873127570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.2873127570
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1767693109
Short name T1038
Test name
Test status
Simulation time 48780942 ps
CPU time 1.58 seconds
Started Jul 16 07:11:10 PM PDT 24
Finished Jul 16 07:11:41 PM PDT 24
Peak memory 213868 kb
Host smart-5df7beb9-c740-4654-813c-0c41609997d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767693109 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.1767693109
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3834971008
Short name T974
Test name
Test status
Simulation time 49363814 ps
CPU time 1.1 seconds
Started Jul 16 07:11:10 PM PDT 24
Finished Jul 16 07:11:40 PM PDT 24
Peak memory 205568 kb
Host smart-306e30cc-8838-4930-b2aa-78f4cd70c11d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834971008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.3834971008
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.4081176341
Short name T1018
Test name
Test status
Simulation time 43491838 ps
CPU time 0.82 seconds
Started Jul 16 07:11:09 PM PDT 24
Finished Jul 16 07:11:34 PM PDT 24
Peak memory 205360 kb
Host smart-829429df-ba95-464c-bd06-6b7c8d1475fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081176341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.4081176341
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1455281822
Short name T938
Test name
Test status
Simulation time 49475190 ps
CPU time 1.55 seconds
Started Jul 16 07:11:09 PM PDT 24
Finished Jul 16 07:11:28 PM PDT 24
Peak memory 205472 kb
Host smart-2654f6a5-6b6d-40c0-9211-af1047f54206
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455281822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.1455281822
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.145097877
Short name T957
Test name
Test status
Simulation time 606091812 ps
CPU time 2.93 seconds
Started Jul 16 07:11:04 PM PDT 24
Finished Jul 16 07:11:11 PM PDT 24
Peak memory 214092 kb
Host smart-b45c5938-51af-4d7d-9704-5a3b361759aa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145097877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shado
w_reg_errors.145097877
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.4017027665
Short name T119
Test name
Test status
Simulation time 217435219 ps
CPU time 8.94 seconds
Started Jul 16 07:11:10 PM PDT 24
Finished Jul 16 07:11:55 PM PDT 24
Peak memory 214172 kb
Host smart-9633c3c2-bf4b-4e88-82ec-97d13959b354
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017027665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.4017027665
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3176685316
Short name T1030
Test name
Test status
Simulation time 103122142 ps
CPU time 2.04 seconds
Started Jul 16 07:11:09 PM PDT 24
Finished Jul 16 07:11:35 PM PDT 24
Peak memory 215876 kb
Host smart-e31c48c9-be4e-46c0-9567-2d28eede897b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176685316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3176685316
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3385992028
Short name T165
Test name
Test status
Simulation time 241430001 ps
CPU time 2.59 seconds
Started Jul 16 07:11:09 PM PDT 24
Finished Jul 16 07:11:36 PM PDT 24
Peak memory 205608 kb
Host smart-9d32e079-f831-4e3a-af81-e78e3aec7523
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385992028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.3385992028
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3905186498
Short name T1064
Test name
Test status
Simulation time 36868964 ps
CPU time 1.15 seconds
Started Jul 16 07:11:08 PM PDT 24
Finished Jul 16 07:11:22 PM PDT 24
Peak memory 216340 kb
Host smart-1fcd7933-ab78-45b3-9437-ea768bfae52d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905186498 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3905186498
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.126134321
Short name T1054
Test name
Test status
Simulation time 56546440 ps
CPU time 1.57 seconds
Started Jul 16 07:11:03 PM PDT 24
Finished Jul 16 07:11:07 PM PDT 24
Peak memory 205468 kb
Host smart-67988a51-3a81-4a45-9c50-947df992454c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126134321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.126134321
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3371202273
Short name T921
Test name
Test status
Simulation time 35073248 ps
CPU time 0.79 seconds
Started Jul 16 07:11:09 PM PDT 24
Finished Jul 16 07:11:34 PM PDT 24
Peak memory 205368 kb
Host smart-c0b02cb7-babe-4ba2-ad84-7544ce60967c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371202273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.3371202273
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1244518300
Short name T1069
Test name
Test status
Simulation time 213292084 ps
CPU time 1.68 seconds
Started Jul 16 07:11:09 PM PDT 24
Finished Jul 16 07:11:35 PM PDT 24
Peak memory 205584 kb
Host smart-406a20b6-865f-48d3-ab2f-d1cc2f64f4f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244518300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.1244518300
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2199511019
Short name T1061
Test name
Test status
Simulation time 82298128 ps
CPU time 2.26 seconds
Started Jul 16 07:11:09 PM PDT 24
Finished Jul 16 07:11:36 PM PDT 24
Peak memory 213880 kb
Host smart-4ecd01cb-14d1-4043-a456-c2e59288ede1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199511019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.2199511019
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3341738277
Short name T989
Test name
Test status
Simulation time 81513556 ps
CPU time 4.04 seconds
Started Jul 16 07:11:09 PM PDT 24
Finished Jul 16 07:11:27 PM PDT 24
Peak memory 214076 kb
Host smart-49572957-e074-4b7f-ac48-58d1d07142f8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341738277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.3341738277
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.819622274
Short name T975
Test name
Test status
Simulation time 2092634356 ps
CPU time 4.6 seconds
Started Jul 16 07:11:09 PM PDT 24
Finished Jul 16 07:11:38 PM PDT 24
Peak memory 216892 kb
Host smart-165c76c1-2274-4f74-bef6-e45f823ba26b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819622274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.819622274
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.2352984818
Short name T1055
Test name
Test status
Simulation time 401521046 ps
CPU time 4.79 seconds
Started Jul 16 07:11:04 PM PDT 24
Finished Jul 16 07:11:10 PM PDT 24
Peak memory 213784 kb
Host smart-3b3bdb83-25cb-4dc2-a3db-29ea2c7d14fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352984818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.2352984818
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.877337733
Short name T138
Test name
Test status
Simulation time 1980599106 ps
CPU time 16.2 seconds
Started Jul 16 07:10:50 PM PDT 24
Finished Jul 16 07:11:08 PM PDT 24
Peak memory 205600 kb
Host smart-d60a460b-1d38-46d3-aa6c-232a3dad6937
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877337733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.877337733
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.112380774
Short name T942
Test name
Test status
Simulation time 4751446678 ps
CPU time 15.18 seconds
Started Jul 16 07:10:50 PM PDT 24
Finished Jul 16 07:11:07 PM PDT 24
Peak memory 205564 kb
Host smart-c1e46176-db43-4555-bafb-c903b1a1a4fe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112380774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.112380774
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1581498003
Short name T1033
Test name
Test status
Simulation time 31357038 ps
CPU time 1.1 seconds
Started Jul 16 07:10:48 PM PDT 24
Finished Jul 16 07:10:51 PM PDT 24
Peak memory 205568 kb
Host smart-1595d735-0d11-4c1d-9f3f-1d178ab7a76b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581498003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1
581498003
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.782463268
Short name T1014
Test name
Test status
Simulation time 211089724 ps
CPU time 1.78 seconds
Started Jul 16 07:10:46 PM PDT 24
Finished Jul 16 07:10:48 PM PDT 24
Peak memory 213848 kb
Host smart-67b919f2-c332-4c61-8ff6-78487ddb4d1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782463268 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.782463268
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2414862821
Short name T980
Test name
Test status
Simulation time 9155563 ps
CPU time 0.89 seconds
Started Jul 16 07:10:47 PM PDT 24
Finished Jul 16 07:10:48 PM PDT 24
Peak memory 205480 kb
Host smart-6eecc504-457f-4fc9-a1e8-efa503e1c3e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414862821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.2414862821
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.336752818
Short name T1002
Test name
Test status
Simulation time 143194844 ps
CPU time 0.79 seconds
Started Jul 16 07:10:52 PM PDT 24
Finished Jul 16 07:10:56 PM PDT 24
Peak memory 205400 kb
Host smart-aef0b5f2-cdb5-4027-9de7-e81c507cb22f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336752818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.336752818
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.4063964882
Short name T136
Test name
Test status
Simulation time 500351993 ps
CPU time 3.02 seconds
Started Jul 16 07:10:48 PM PDT 24
Finished Jul 16 07:10:52 PM PDT 24
Peak memory 205580 kb
Host smart-5e296b49-39a3-41b0-a735-53e1c6e79f46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063964882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.4063964882
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1591362639
Short name T117
Test name
Test status
Simulation time 154719053 ps
CPU time 1.96 seconds
Started Jul 16 07:10:49 PM PDT 24
Finished Jul 16 07:10:53 PM PDT 24
Peak memory 214100 kb
Host smart-42bb7421-9711-44e7-8505-0258d9939ec2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591362639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.1591362639
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.198125464
Short name T1080
Test name
Test status
Simulation time 650606864 ps
CPU time 19.2 seconds
Started Jul 16 07:10:51 PM PDT 24
Finished Jul 16 07:11:13 PM PDT 24
Peak memory 221232 kb
Host smart-b2116801-7dba-49cc-b4b9-cd828a14be7a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198125464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_shadow_reg_errors_with_csr_rw.198125464
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2395678242
Short name T918
Test name
Test status
Simulation time 93960187 ps
CPU time 2.16 seconds
Started Jul 16 07:10:51 PM PDT 24
Finished Jul 16 07:10:56 PM PDT 24
Peak memory 213868 kb
Host smart-f1500317-4a8c-4fda-9fbd-f6732c724cbf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395678242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.2395678242
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.3698695608
Short name T1032
Test name
Test status
Simulation time 9349549 ps
CPU time 0.71 seconds
Started Jul 16 07:11:05 PM PDT 24
Finished Jul 16 07:11:10 PM PDT 24
Peak memory 205380 kb
Host smart-a4f05812-7c38-4a83-b84e-18d7f07e189c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698695608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.3698695608
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1502676977
Short name T1028
Test name
Test status
Simulation time 13670827 ps
CPU time 0.85 seconds
Started Jul 16 07:11:07 PM PDT 24
Finished Jul 16 07:11:15 PM PDT 24
Peak memory 205360 kb
Host smart-ebece944-135f-4f04-9b3b-74eccde9f280
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502676977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1502676977
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.849321505
Short name T1013
Test name
Test status
Simulation time 30802291 ps
CPU time 0.79 seconds
Started Jul 16 07:11:12 PM PDT 24
Finished Jul 16 07:12:00 PM PDT 24
Peak memory 205340 kb
Host smart-3734fc61-71eb-4fcc-847f-f41ea1bb032a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849321505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.849321505
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2853915670
Short name T929
Test name
Test status
Simulation time 18451047 ps
CPU time 0.73 seconds
Started Jul 16 07:11:11 PM PDT 24
Finished Jul 16 07:11:47 PM PDT 24
Peak memory 205132 kb
Host smart-33a1fe4b-5531-4e3a-8a51-3d95831a320a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853915670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2853915670
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1425909356
Short name T979
Test name
Test status
Simulation time 8792025 ps
CPU time 0.8 seconds
Started Jul 16 07:11:08 PM PDT 24
Finished Jul 16 07:11:21 PM PDT 24
Peak memory 205364 kb
Host smart-4506d4a0-0afa-4b19-972b-b34e64033c76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425909356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.1425909356
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.1526136768
Short name T922
Test name
Test status
Simulation time 10287620 ps
CPU time 0.74 seconds
Started Jul 16 07:11:09 PM PDT 24
Finished Jul 16 07:11:24 PM PDT 24
Peak memory 205292 kb
Host smart-164ee9e2-ef3a-4489-970a-ad92d7f06c7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526136768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.1526136768
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1077466986
Short name T1039
Test name
Test status
Simulation time 16865447 ps
CPU time 0.78 seconds
Started Jul 16 07:11:18 PM PDT 24
Finished Jul 16 07:12:18 PM PDT 24
Peak memory 205368 kb
Host smart-27f13ae2-40e4-49b6-81fb-17e58b1177b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077466986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.1077466986
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.4186704892
Short name T958
Test name
Test status
Simulation time 8750841 ps
CPU time 0.7 seconds
Started Jul 16 07:11:17 PM PDT 24
Finished Jul 16 07:12:17 PM PDT 24
Peak memory 205376 kb
Host smart-c6a60985-a981-400f-a84a-56b98cd0918e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186704892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.4186704892
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1736140718
Short name T984
Test name
Test status
Simulation time 12024085 ps
CPU time 0.72 seconds
Started Jul 16 07:11:18 PM PDT 24
Finished Jul 16 07:12:19 PM PDT 24
Peak memory 205260 kb
Host smart-e9a410b1-6cc6-432c-839c-9ccd18875596
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736140718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.1736140718
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2059582136
Short name T999
Test name
Test status
Simulation time 8529483 ps
CPU time 0.71 seconds
Started Jul 16 07:11:21 PM PDT 24
Finished Jul 16 07:12:35 PM PDT 24
Peak memory 205372 kb
Host smart-8fa93033-add4-4c52-bfe3-3d0b110d3bc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059582136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.2059582136
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3122396911
Short name T153
Test name
Test status
Simulation time 513378112 ps
CPU time 10.73 seconds
Started Jul 16 07:10:52 PM PDT 24
Finished Jul 16 07:11:06 PM PDT 24
Peak memory 205636 kb
Host smart-17f23715-f5b1-49c9-9f4a-6ca31380b300
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122396911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.3
122396911
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2372014701
Short name T982
Test name
Test status
Simulation time 132990450 ps
CPU time 6.4 seconds
Started Jul 16 07:10:51 PM PDT 24
Finished Jul 16 07:11:01 PM PDT 24
Peak memory 205540 kb
Host smart-7bfd675a-52d1-4846-9677-0a1b7538b108
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372014701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2
372014701
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2199956405
Short name T1019
Test name
Test status
Simulation time 37866879 ps
CPU time 1.56 seconds
Started Jul 16 07:10:49 PM PDT 24
Finished Jul 16 07:10:52 PM PDT 24
Peak memory 205552 kb
Host smart-b5bcb953-cf13-4faf-883d-4d44940740b5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199956405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.2
199956405
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.448994557
Short name T928
Test name
Test status
Simulation time 99680384 ps
CPU time 1.92 seconds
Started Jul 16 07:10:48 PM PDT 24
Finished Jul 16 07:10:51 PM PDT 24
Peak memory 213996 kb
Host smart-1ea6d1fc-f523-4071-abbb-8b4e0452ce80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448994557 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.448994557
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1064603072
Short name T1082
Test name
Test status
Simulation time 17993555 ps
CPU time 1.31 seconds
Started Jul 16 07:10:45 PM PDT 24
Finished Jul 16 07:10:47 PM PDT 24
Peak memory 205432 kb
Host smart-8cf56898-b168-4fce-8ea6-6c3db17f1dd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064603072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.1064603072
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1503255714
Short name T1041
Test name
Test status
Simulation time 36105641 ps
CPU time 0.72 seconds
Started Jul 16 07:10:52 PM PDT 24
Finished Jul 16 07:10:56 PM PDT 24
Peak memory 205324 kb
Host smart-3732f9a4-cf01-4388-a9ee-a52f7e7a4672
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503255714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.1503255714
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.492956720
Short name T1001
Test name
Test status
Simulation time 66703997 ps
CPU time 1.29 seconds
Started Jul 16 07:10:52 PM PDT 24
Finished Jul 16 07:10:56 PM PDT 24
Peak memory 205592 kb
Host smart-51c9476e-3435-4861-b39f-2545332a6976
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492956720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sam
e_csr_outstanding.492956720
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1454499365
Short name T950
Test name
Test status
Simulation time 213999665 ps
CPU time 3.7 seconds
Started Jul 16 07:10:48 PM PDT 24
Finished Jul 16 07:10:53 PM PDT 24
Peak memory 214020 kb
Host smart-c55425c1-a7c0-47fc-a516-7664538de5ff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454499365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.1454499365
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.3105176504
Short name T976
Test name
Test status
Simulation time 948220407 ps
CPU time 5.94 seconds
Started Jul 16 07:10:48 PM PDT 24
Finished Jul 16 07:10:55 PM PDT 24
Peak memory 213928 kb
Host smart-6057cd72-fe45-4d7f-b8c5-a0eb2f35a64a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105176504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.3105176504
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3107523143
Short name T1059
Test name
Test status
Simulation time 23389675 ps
CPU time 1.47 seconds
Started Jul 16 07:10:53 PM PDT 24
Finished Jul 16 07:10:57 PM PDT 24
Peak memory 213776 kb
Host smart-bef13382-b4c6-4fa1-b0c1-938c4918d5f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107523143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.3107523143
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.4268092651
Short name T159
Test name
Test status
Simulation time 101898225 ps
CPU time 4.49 seconds
Started Jul 16 07:10:52 PM PDT 24
Finished Jul 16 07:11:00 PM PDT 24
Peak memory 213788 kb
Host smart-2b93e079-609d-4812-b706-cf177c57e32e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268092651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.4268092651
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.4280990079
Short name T924
Test name
Test status
Simulation time 39322229 ps
CPU time 0.7 seconds
Started Jul 16 07:11:21 PM PDT 24
Finished Jul 16 07:12:34 PM PDT 24
Peak memory 205312 kb
Host smart-df07dbbb-5804-47c0-b41f-f83502765862
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280990079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.4280990079
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.1757378259
Short name T934
Test name
Test status
Simulation time 10148389 ps
CPU time 0.82 seconds
Started Jul 16 07:11:20 PM PDT 24
Finished Jul 16 07:12:29 PM PDT 24
Peak memory 205348 kb
Host smart-3d5b893b-be81-44f1-9531-28d47b255e63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757378259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.1757378259
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.4158015011
Short name T1036
Test name
Test status
Simulation time 70444264 ps
CPU time 0.72 seconds
Started Jul 16 07:11:19 PM PDT 24
Finished Jul 16 07:12:26 PM PDT 24
Peak memory 205392 kb
Host smart-eab85d2f-ab9a-40c1-b6e2-68823f3b0187
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158015011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.4158015011
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3660432473
Short name T1008
Test name
Test status
Simulation time 7884999 ps
CPU time 0.7 seconds
Started Jul 16 07:11:18 PM PDT 24
Finished Jul 16 07:12:19 PM PDT 24
Peak memory 205260 kb
Host smart-02aef781-89c2-408e-9677-91a69770a3d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660432473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3660432473
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.873132344
Short name T1029
Test name
Test status
Simulation time 12165298 ps
CPU time 0.84 seconds
Started Jul 16 07:11:18 PM PDT 24
Finished Jul 16 07:12:19 PM PDT 24
Peak memory 205272 kb
Host smart-495e374d-9237-43c6-a5df-04e88de9b4ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873132344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.873132344
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.2393518289
Short name T926
Test name
Test status
Simulation time 13230976 ps
CPU time 0.82 seconds
Started Jul 16 07:11:21 PM PDT 24
Finished Jul 16 07:12:35 PM PDT 24
Peak memory 205292 kb
Host smart-a49a7f33-9fbe-4625-9387-6b086968b233
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393518289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.2393518289
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1023193050
Short name T963
Test name
Test status
Simulation time 26235591 ps
CPU time 0.73 seconds
Started Jul 16 07:11:24 PM PDT 24
Finished Jul 16 07:12:48 PM PDT 24
Peak memory 205392 kb
Host smart-a34a2d90-df78-4947-9bd5-7f969101370d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023193050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.1023193050
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.3127833298
Short name T993
Test name
Test status
Simulation time 69022040 ps
CPU time 0.82 seconds
Started Jul 16 07:11:17 PM PDT 24
Finished Jul 16 07:12:17 PM PDT 24
Peak memory 205292 kb
Host smart-b2b14bea-fa35-4d67-b360-4828cbd8fb0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127833298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.3127833298
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.241987945
Short name T965
Test name
Test status
Simulation time 12028117 ps
CPU time 0.7 seconds
Started Jul 16 07:11:16 PM PDT 24
Finished Jul 16 07:12:16 PM PDT 24
Peak memory 205400 kb
Host smart-80cb24ab-f0a4-40ed-9d11-33464a990558
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241987945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.241987945
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2906631800
Short name T1073
Test name
Test status
Simulation time 18099078 ps
CPU time 0.83 seconds
Started Jul 16 07:11:17 PM PDT 24
Finished Jul 16 07:12:17 PM PDT 24
Peak memory 205308 kb
Host smart-dc677636-cf7e-4e92-a67d-b1d9020b39ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906631800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2906631800
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2292838390
Short name T977
Test name
Test status
Simulation time 380848060 ps
CPU time 3.92 seconds
Started Jul 16 07:10:49 PM PDT 24
Finished Jul 16 07:10:55 PM PDT 24
Peak memory 205652 kb
Host smart-61e82579-a1ec-4f58-a3f4-01054b40307e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292838390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.2
292838390
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1522609257
Short name T1057
Test name
Test status
Simulation time 533667493 ps
CPU time 6.44 seconds
Started Jul 16 07:10:52 PM PDT 24
Finished Jul 16 07:11:01 PM PDT 24
Peak memory 205452 kb
Host smart-384f6655-95f9-433d-b286-4d401fd00c10
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522609257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.1
522609257
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1070164381
Short name T1066
Test name
Test status
Simulation time 29092130 ps
CPU time 1.04 seconds
Started Jul 16 07:10:52 PM PDT 24
Finished Jul 16 07:10:56 PM PDT 24
Peak memory 205400 kb
Host smart-45543d5c-c477-44b6-935c-fd0d304efcd6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070164381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.1
070164381
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.1799939902
Short name T985
Test name
Test status
Simulation time 48821829 ps
CPU time 1.11 seconds
Started Jul 16 07:10:48 PM PDT 24
Finished Jul 16 07:10:51 PM PDT 24
Peak memory 205588 kb
Host smart-f21aaf87-d22d-4acb-aec6-c3d55db2a12f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799939902 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.1799939902
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1603873853
Short name T1005
Test name
Test status
Simulation time 31134650 ps
CPU time 1.29 seconds
Started Jul 16 07:10:50 PM PDT 24
Finished Jul 16 07:10:53 PM PDT 24
Peak memory 205488 kb
Host smart-6d4105ec-4905-48e0-819b-d2635ccddeb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603873853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.1603873853
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3630915506
Short name T920
Test name
Test status
Simulation time 10210390 ps
CPU time 0.74 seconds
Started Jul 16 07:10:49 PM PDT 24
Finished Jul 16 07:10:51 PM PDT 24
Peak memory 205336 kb
Host smart-92e1e5e2-ecb3-4953-b19b-e81c30d48c47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630915506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.3630915506
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1356292957
Short name T961
Test name
Test status
Simulation time 77010749 ps
CPU time 1.37 seconds
Started Jul 16 07:10:53 PM PDT 24
Finished Jul 16 07:10:57 PM PDT 24
Peak memory 205488 kb
Host smart-fb333eaf-aef4-4e63-ba46-bac9461bfbee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356292957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.1356292957
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1708201968
Short name T1021
Test name
Test status
Simulation time 190782432 ps
CPU time 2.88 seconds
Started Jul 16 07:10:48 PM PDT 24
Finished Jul 16 07:10:52 PM PDT 24
Peak memory 213980 kb
Host smart-03886ef3-a0ee-4b4d-af33-3e3ae3fbfa5c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708201968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1708201968
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2175633417
Short name T973
Test name
Test status
Simulation time 417592224 ps
CPU time 14.03 seconds
Started Jul 16 07:10:49 PM PDT 24
Finished Jul 16 07:11:05 PM PDT 24
Peak memory 214068 kb
Host smart-f87ac319-1ea6-49cb-81bd-8172c34750e2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175633417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.2175633417
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.2531579808
Short name T995
Test name
Test status
Simulation time 1174628332 ps
CPU time 5.01 seconds
Started Jul 16 07:10:52 PM PDT 24
Finished Jul 16 07:11:00 PM PDT 24
Peak memory 213812 kb
Host smart-c5c88663-5bfc-438e-a42b-d6d6e6260829
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531579808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.2531579808
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3281832402
Short name T992
Test name
Test status
Simulation time 21246160 ps
CPU time 0.72 seconds
Started Jul 16 07:11:18 PM PDT 24
Finished Jul 16 07:12:19 PM PDT 24
Peak memory 205240 kb
Host smart-a4c6a7c1-5b4b-40b5-92b3-9ac0d305d0f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281832402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.3281832402
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3188517088
Short name T936
Test name
Test status
Simulation time 14452224 ps
CPU time 0.71 seconds
Started Jul 16 07:11:21 PM PDT 24
Finished Jul 16 07:12:35 PM PDT 24
Peak memory 205324 kb
Host smart-ec03bd2b-de81-4420-808d-03a88fd95e2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188517088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.3188517088
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.4123643952
Short name T1004
Test name
Test status
Simulation time 47946010 ps
CPU time 0.84 seconds
Started Jul 16 07:11:21 PM PDT 24
Finished Jul 16 07:12:35 PM PDT 24
Peak memory 205364 kb
Host smart-15e98998-4b71-425d-b2ba-05d7f6f46d8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123643952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.4123643952
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.3067717210
Short name T967
Test name
Test status
Simulation time 8425727 ps
CPU time 0.73 seconds
Started Jul 16 07:11:22 PM PDT 24
Finished Jul 16 07:12:36 PM PDT 24
Peak memory 205276 kb
Host smart-00dbd826-67b9-4eff-b4ea-3c53470fd993
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067717210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.3067717210
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.675321522
Short name T968
Test name
Test status
Simulation time 29390265 ps
CPU time 0.71 seconds
Started Jul 16 07:11:21 PM PDT 24
Finished Jul 16 07:12:35 PM PDT 24
Peak memory 205388 kb
Host smart-b9b31ba2-53b2-495e-a843-471e4d6bae1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675321522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.675321522
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3510345025
Short name T983
Test name
Test status
Simulation time 11752425 ps
CPU time 0.7 seconds
Started Jul 16 07:11:16 PM PDT 24
Finished Jul 16 07:12:16 PM PDT 24
Peak memory 205368 kb
Host smart-e1a72caa-54ba-46e5-866e-c9cf598ffbd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510345025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.3510345025
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2179457329
Short name T1076
Test name
Test status
Simulation time 11022685 ps
CPU time 0.7 seconds
Started Jul 16 07:11:18 PM PDT 24
Finished Jul 16 07:12:18 PM PDT 24
Peak memory 205396 kb
Host smart-3adb66d6-62b7-4fce-94a7-dc9f4b0eecb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179457329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.2179457329
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.2911898326
Short name T916
Test name
Test status
Simulation time 38292339 ps
CPU time 0.77 seconds
Started Jul 16 07:11:21 PM PDT 24
Finished Jul 16 07:12:34 PM PDT 24
Peak memory 205392 kb
Host smart-64913ae7-c150-4736-ab44-f7c3af431055
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911898326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.2911898326
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2312250524
Short name T937
Test name
Test status
Simulation time 15193601 ps
CPU time 0.72 seconds
Started Jul 16 07:11:17 PM PDT 24
Finished Jul 16 07:12:17 PM PDT 24
Peak memory 205340 kb
Host smart-c8fa92ae-5dd1-47b5-bddd-e25ab4c420b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312250524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.2312250524
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.3914515737
Short name T1044
Test name
Test status
Simulation time 13404011 ps
CPU time 0.74 seconds
Started Jul 16 07:11:19 PM PDT 24
Finished Jul 16 07:12:26 PM PDT 24
Peak memory 205380 kb
Host smart-90de7219-daa9-412d-812f-9996cf8e059f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914515737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.3914515737
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3336141059
Short name T933
Test name
Test status
Simulation time 89228094 ps
CPU time 1.5 seconds
Started Jul 16 07:10:50 PM PDT 24
Finished Jul 16 07:10:54 PM PDT 24
Peak memory 213852 kb
Host smart-0ef80425-772e-4057-9c4b-f8df106116cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336141059 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3336141059
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.1938595933
Short name T998
Test name
Test status
Simulation time 11692330 ps
CPU time 0.98 seconds
Started Jul 16 07:10:51 PM PDT 24
Finished Jul 16 07:10:54 PM PDT 24
Peak memory 205384 kb
Host smart-be590079-6b3f-46d5-9a41-638b73d7fa50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938595933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.1938595933
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.2775869760
Short name T969
Test name
Test status
Simulation time 82070471 ps
CPU time 0.74 seconds
Started Jul 16 07:10:50 PM PDT 24
Finished Jul 16 07:10:53 PM PDT 24
Peak memory 205304 kb
Host smart-f65a895e-504c-4912-84de-631ee58e4ee3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775869760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.2775869760
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3121282428
Short name T943
Test name
Test status
Simulation time 445318910 ps
CPU time 3.47 seconds
Started Jul 16 07:10:51 PM PDT 24
Finished Jul 16 07:10:58 PM PDT 24
Peak memory 205576 kb
Host smart-ee405321-622a-4b65-82a1-c1c121da529a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121282428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.3121282428
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.2306873806
Short name T940
Test name
Test status
Simulation time 139715567 ps
CPU time 1.55 seconds
Started Jul 16 07:10:50 PM PDT 24
Finished Jul 16 07:10:53 PM PDT 24
Peak memory 214176 kb
Host smart-f8210fd1-7a71-46d4-99a0-9e40928846d1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306873806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.2306873806
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2308017025
Short name T114
Test name
Test status
Simulation time 1208515389 ps
CPU time 11.05 seconds
Started Jul 16 07:10:48 PM PDT 24
Finished Jul 16 07:11:00 PM PDT 24
Peak memory 220264 kb
Host smart-8748e32c-7fff-48a1-9052-340b230cb5fe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308017025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.2308017025
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.938256299
Short name T1084
Test name
Test status
Simulation time 382254219 ps
CPU time 2.75 seconds
Started Jul 16 07:10:50 PM PDT 24
Finished Jul 16 07:10:55 PM PDT 24
Peak memory 216744 kb
Host smart-022dbf4f-a41b-43c1-bbd4-a8f496f59e6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938256299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.938256299
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.609624210
Short name T158
Test name
Test status
Simulation time 33311530 ps
CPU time 1.2 seconds
Started Jul 16 07:10:52 PM PDT 24
Finished Jul 16 07:10:56 PM PDT 24
Peak memory 213752 kb
Host smart-689fd430-f18c-4df9-b26a-ab75ed0bbb5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609624210 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.609624210
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1623057034
Short name T198
Test name
Test status
Simulation time 60452097 ps
CPU time 0.86 seconds
Started Jul 16 07:10:52 PM PDT 24
Finished Jul 16 07:10:56 PM PDT 24
Peak memory 205508 kb
Host smart-3dcdddf2-2d5a-4eb9-8ae7-0333b6a0a959
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623057034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1623057034
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2384380838
Short name T1035
Test name
Test status
Simulation time 25897859 ps
CPU time 0.77 seconds
Started Jul 16 07:10:52 PM PDT 24
Finished Jul 16 07:10:55 PM PDT 24
Peak memory 205324 kb
Host smart-7775d1de-0f9f-43e8-ac3f-982d911efda2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384380838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.2384380838
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.3340694091
Short name T932
Test name
Test status
Simulation time 42729770 ps
CPU time 1.55 seconds
Started Jul 16 07:10:51 PM PDT 24
Finished Jul 16 07:10:55 PM PDT 24
Peak memory 205572 kb
Host smart-9857c8b4-8352-4f27-a392-a84357c6f263
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340694091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.3340694091
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3491286383
Short name T1006
Test name
Test status
Simulation time 339952072 ps
CPU time 2.56 seconds
Started Jul 16 07:10:50 PM PDT 24
Finished Jul 16 07:10:54 PM PDT 24
Peak memory 214028 kb
Host smart-da19d086-db3c-4f7d-a15a-4a883083ca97
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491286383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.3491286383
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.796326322
Short name T121
Test name
Test status
Simulation time 341202647 ps
CPU time 4.3 seconds
Started Jul 16 07:10:51 PM PDT 24
Finished Jul 16 07:10:58 PM PDT 24
Peak memory 214064 kb
Host smart-7392ae20-6860-46a8-8995-e9b0c8bdb7b2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796326322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_shadow_reg_errors_with_csr_rw.796326322
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.1877405689
Short name T962
Test name
Test status
Simulation time 22230537 ps
CPU time 1.39 seconds
Started Jul 16 07:10:48 PM PDT 24
Finished Jul 16 07:10:51 PM PDT 24
Peak memory 213732 kb
Host smart-7102d5a2-f16a-453d-afad-bc9d54e75d81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877405689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.1877405689
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.1047349447
Short name T179
Test name
Test status
Simulation time 55089233 ps
CPU time 1.44 seconds
Started Jul 16 07:11:04 PM PDT 24
Finished Jul 16 07:11:08 PM PDT 24
Peak memory 205724 kb
Host smart-f8c2a091-af0d-45da-bb03-31a77ad4e928
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047349447 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.1047349447
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.158375236
Short name T1074
Test name
Test status
Simulation time 27549896 ps
CPU time 1.14 seconds
Started Jul 16 07:10:52 PM PDT 24
Finished Jul 16 07:10:56 PM PDT 24
Peak memory 205492 kb
Host smart-127c643e-94f8-4ce4-8419-943fbe313aa0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158375236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.158375236
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.1531830261
Short name T923
Test name
Test status
Simulation time 44258955 ps
CPU time 0.7 seconds
Started Jul 16 07:10:51 PM PDT 24
Finished Jul 16 07:10:54 PM PDT 24
Peak memory 205292 kb
Host smart-c1d73792-381d-426c-b9c3-6e35a887711a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531830261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.1531830261
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2644395581
Short name T1071
Test name
Test status
Simulation time 53766758 ps
CPU time 1.46 seconds
Started Jul 16 07:10:50 PM PDT 24
Finished Jul 16 07:10:54 PM PDT 24
Peak memory 205576 kb
Host smart-f4708931-4f49-48b1-ada7-020f8291bbce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644395581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.2644395581
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.710303829
Short name T966
Test name
Test status
Simulation time 185792005 ps
CPU time 3.16 seconds
Started Jul 16 07:10:52 PM PDT 24
Finished Jul 16 07:10:58 PM PDT 24
Peak memory 214140 kb
Host smart-8d3a96c1-fe54-4eca-a3a3-af48f9a55c9e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710303829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow
_reg_errors.710303829
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.521416536
Short name T960
Test name
Test status
Simulation time 153205623 ps
CPU time 8.02 seconds
Started Jul 16 07:10:51 PM PDT 24
Finished Jul 16 07:11:02 PM PDT 24
Peak memory 220244 kb
Host smart-a21f7566-0fe0-4aaf-b49b-ac110683a72e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521416536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_shadow_reg_errors_with_csr_rw.521416536
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1805156938
Short name T1022
Test name
Test status
Simulation time 32586357 ps
CPU time 2.29 seconds
Started Jul 16 07:10:50 PM PDT 24
Finished Jul 16 07:10:55 PM PDT 24
Peak memory 213828 kb
Host smart-5d18d89e-c0c1-4ab4-8df0-d897a047d2b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805156938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.1805156938
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2530947324
Short name T1070
Test name
Test status
Simulation time 112730717 ps
CPU time 1.4 seconds
Started Jul 16 07:11:05 PM PDT 24
Finished Jul 16 07:11:11 PM PDT 24
Peak memory 205520 kb
Host smart-a522378a-c201-4bb9-941a-165842ecefeb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530947324 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.2530947324
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.715899463
Short name T1056
Test name
Test status
Simulation time 15374373 ps
CPU time 1.12 seconds
Started Jul 16 07:11:04 PM PDT 24
Finished Jul 16 07:11:07 PM PDT 24
Peak memory 205548 kb
Host smart-dd7ee8db-5c4b-4584-a2e1-91c3d9e7287a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715899463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.715899463
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1925877576
Short name T1083
Test name
Test status
Simulation time 57070292 ps
CPU time 0.82 seconds
Started Jul 16 07:11:04 PM PDT 24
Finished Jul 16 07:11:08 PM PDT 24
Peak memory 205400 kb
Host smart-c396ba74-c14b-45cc-8773-22897fe6a14c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925877576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.1925877576
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3630223889
Short name T951
Test name
Test status
Simulation time 145006433 ps
CPU time 2.08 seconds
Started Jul 16 07:11:06 PM PDT 24
Finished Jul 16 07:11:14 PM PDT 24
Peak memory 205496 kb
Host smart-e974e283-b6db-4812-a5fe-d17974b11042
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630223889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.3630223889
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.3631268816
Short name T122
Test name
Test status
Simulation time 266235560 ps
CPU time 7.57 seconds
Started Jul 16 07:11:05 PM PDT 24
Finished Jul 16 07:11:18 PM PDT 24
Peak memory 222180 kb
Host smart-549fac75-7761-42e4-be7c-9a274e28ec85
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631268816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.3631268816
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.2473015847
Short name T1027
Test name
Test status
Simulation time 116791902 ps
CPU time 1.78 seconds
Started Jul 16 07:11:03 PM PDT 24
Finished Jul 16 07:11:06 PM PDT 24
Peak memory 214672 kb
Host smart-361f5a6f-7ff1-4d51-8754-7fa683eac10a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473015847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.2473015847
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.138261601
Short name T156
Test name
Test status
Simulation time 265573298 ps
CPU time 3.65 seconds
Started Jul 16 07:11:04 PM PDT 24
Finished Jul 16 07:11:12 PM PDT 24
Peak memory 205832 kb
Host smart-8b50635c-993d-40b8-a30b-3b2c9e391959
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138261601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.
138261601
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2580282299
Short name T1047
Test name
Test status
Simulation time 134341688 ps
CPU time 1.66 seconds
Started Jul 16 07:11:04 PM PDT 24
Finished Jul 16 07:11:09 PM PDT 24
Peak memory 213752 kb
Host smart-f488eeb5-3379-49c5-8427-ffaa39ccf501
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580282299 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.2580282299
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.320857302
Short name T1075
Test name
Test status
Simulation time 21009792 ps
CPU time 1.26 seconds
Started Jul 16 07:11:08 PM PDT 24
Finished Jul 16 07:11:20 PM PDT 24
Peak memory 205472 kb
Host smart-acb32f98-c7ea-4ec5-924a-18384b343dca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320857302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.320857302
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.835871943
Short name T1017
Test name
Test status
Simulation time 39449431 ps
CPU time 0.72 seconds
Started Jul 16 07:11:05 PM PDT 24
Finished Jul 16 07:11:10 PM PDT 24
Peak memory 205400 kb
Host smart-3ec29558-d03c-4b9c-99e5-3a709469cbb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835871943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.835871943
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.3462718938
Short name T996
Test name
Test status
Simulation time 126849619 ps
CPU time 2.3 seconds
Started Jul 16 07:11:14 PM PDT 24
Finished Jul 16 07:12:07 PM PDT 24
Peak memory 205548 kb
Host smart-29d0b724-5cd8-4957-a33f-270102b2d392
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462718938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.3462718938
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3386353649
Short name T120
Test name
Test status
Simulation time 696364526 ps
CPU time 3.08 seconds
Started Jul 16 07:11:05 PM PDT 24
Finished Jul 16 07:11:12 PM PDT 24
Peak memory 214112 kb
Host smart-7df66ce1-82aa-4ce5-ac7e-3db9bc6c3db0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386353649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.3386353649
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2941886417
Short name T118
Test name
Test status
Simulation time 210214729 ps
CPU time 5.48 seconds
Started Jul 16 07:11:03 PM PDT 24
Finished Jul 16 07:11:10 PM PDT 24
Peak memory 214116 kb
Host smart-678b7afb-7950-4403-8077-4de652fffde4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941886417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.2941886417
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.1247511477
Short name T935
Test name
Test status
Simulation time 39149300 ps
CPU time 1.79 seconds
Started Jul 16 07:11:04 PM PDT 24
Finished Jul 16 07:11:09 PM PDT 24
Peak memory 213580 kb
Host smart-0425fbaf-70a4-46ae-ae1a-c85d70d9c151
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247511477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.1247511477
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.2912913016
Short name T662
Test name
Test status
Simulation time 13523287 ps
CPU time 0.91 seconds
Started Jul 16 07:56:43 PM PDT 24
Finished Jul 16 07:56:46 PM PDT 24
Peak memory 206036 kb
Host smart-50bb67a9-7a29-4feb-b87f-8d48f0fd9c80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912913016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.2912913016
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.459562408
Short name T21
Test name
Test status
Simulation time 576257295 ps
CPU time 2.66 seconds
Started Jul 16 07:56:40 PM PDT 24
Finished Jul 16 07:56:44 PM PDT 24
Peak memory 216872 kb
Host smart-182bc544-a79d-4139-b8fa-41d4232de2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459562408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.459562408
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.4087727648
Short name T80
Test name
Test status
Simulation time 147945168 ps
CPU time 2.26 seconds
Started Jul 16 07:56:33 PM PDT 24
Finished Jul 16 07:56:36 PM PDT 24
Peak memory 208128 kb
Host smart-f119e02c-a65f-42c0-a7f8-6be9c4e5552b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087727648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.4087727648
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.4078700496
Short name T630
Test name
Test status
Simulation time 79415696 ps
CPU time 3.51 seconds
Started Jul 16 07:56:41 PM PDT 24
Finished Jul 16 07:56:46 PM PDT 24
Peak memory 214356 kb
Host smart-5b054893-a3f9-400d-8009-d30e5fd38c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078700496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.4078700496
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.3775317773
Short name T408
Test name
Test status
Simulation time 195701343 ps
CPU time 4 seconds
Started Jul 16 07:56:39 PM PDT 24
Finished Jul 16 07:56:44 PM PDT 24
Peak memory 206172 kb
Host smart-0cd6946e-0129-41fd-9755-a1b4a7fb47d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775317773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3775317773
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.1374417901
Short name T699
Test name
Test status
Simulation time 63300946 ps
CPU time 3.69 seconds
Started Jul 16 07:56:39 PM PDT 24
Finished Jul 16 07:56:44 PM PDT 24
Peak memory 207916 kb
Host smart-dfc3666e-7303-4c7f-a385-083ccaa9e332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374417901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.1374417901
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.4264900401
Short name T283
Test name
Test status
Simulation time 96165241 ps
CPU time 4.45 seconds
Started Jul 16 07:56:28 PM PDT 24
Finished Jul 16 07:56:34 PM PDT 24
Peak memory 222404 kb
Host smart-32c5ff4f-9bc2-423f-81a7-d89823780231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264900401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.4264900401
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.3207004001
Short name T661
Test name
Test status
Simulation time 78096380 ps
CPU time 2.83 seconds
Started Jul 16 07:56:25 PM PDT 24
Finished Jul 16 07:56:30 PM PDT 24
Peak memory 206776 kb
Host smart-bc7a87ae-5cb1-4f15-9169-baf295f9c1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207004001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.3207004001
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.2970501407
Short name T338
Test name
Test status
Simulation time 694098115 ps
CPU time 5.89 seconds
Started Jul 16 07:56:27 PM PDT 24
Finished Jul 16 07:56:35 PM PDT 24
Peak memory 208184 kb
Host smart-9267e02a-17c2-47d9-8178-96940d0437e6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970501407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.2970501407
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.1482384059
Short name T841
Test name
Test status
Simulation time 930666706 ps
CPU time 7.21 seconds
Started Jul 16 07:56:29 PM PDT 24
Finished Jul 16 07:56:38 PM PDT 24
Peak memory 208564 kb
Host smart-eb9d9c7d-506f-4d9a-b3e6-3d6f00b5eac6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482384059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.1482384059
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.2939383866
Short name T352
Test name
Test status
Simulation time 1240892917 ps
CPU time 8.53 seconds
Started Jul 16 07:56:24 PM PDT 24
Finished Jul 16 07:56:35 PM PDT 24
Peak memory 208856 kb
Host smart-79add97f-b25f-4bd6-9f40-acea2ce0b07d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939383866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.2939383866
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.1071819892
Short name T387
Test name
Test status
Simulation time 196977766 ps
CPU time 3.48 seconds
Started Jul 16 07:56:41 PM PDT 24
Finished Jul 16 07:56:46 PM PDT 24
Peak memory 207292 kb
Host smart-c7ab3c45-8748-496a-96e2-fca303825ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071819892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.1071819892
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.4023250325
Short name T483
Test name
Test status
Simulation time 61973870 ps
CPU time 2.83 seconds
Started Jul 16 07:56:28 PM PDT 24
Finished Jul 16 07:56:33 PM PDT 24
Peak memory 208516 kb
Host smart-8c5e9971-daab-4318-8203-549899997a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023250325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.4023250325
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.1273331963
Short name T874
Test name
Test status
Simulation time 419475697 ps
CPU time 5.09 seconds
Started Jul 16 07:56:42 PM PDT 24
Finished Jul 16 07:56:48 PM PDT 24
Peak memory 210172 kb
Host smart-86cbd75e-7416-4530-8e69-01cf9afec701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273331963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.1273331963
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.310149473
Short name T713
Test name
Test status
Simulation time 45649910 ps
CPU time 2.21 seconds
Started Jul 16 07:56:40 PM PDT 24
Finished Jul 16 07:56:43 PM PDT 24
Peak memory 210068 kb
Host smart-e2c007bd-c642-4eb5-8fc9-38e8d6a6bd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310149473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.310149473
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.457790653
Short name T464
Test name
Test status
Simulation time 15149995 ps
CPU time 0.69 seconds
Started Jul 16 07:56:45 PM PDT 24
Finished Jul 16 07:56:49 PM PDT 24
Peak memory 206008 kb
Host smart-cd381760-3a70-4575-894b-b1477727165d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457790653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.457790653
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.622926503
Short name T30
Test name
Test status
Simulation time 129734853 ps
CPU time 3.51 seconds
Started Jul 16 07:56:44 PM PDT 24
Finished Jul 16 07:56:49 PM PDT 24
Peak memory 210392 kb
Host smart-56721baf-e847-4eb4-bf0c-739387b92037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622926503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.622926503
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.2448414762
Short name T523
Test name
Test status
Simulation time 116729879 ps
CPU time 4.32 seconds
Started Jul 16 07:56:40 PM PDT 24
Finished Jul 16 07:56:46 PM PDT 24
Peak memory 208332 kb
Host smart-9294d8f2-50f8-45b3-a7d4-ac5d33f16253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448414762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.2448414762
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.2154286885
Short name T840
Test name
Test status
Simulation time 85595566 ps
CPU time 3.06 seconds
Started Jul 16 07:56:48 PM PDT 24
Finished Jul 16 07:56:56 PM PDT 24
Peak memory 222336 kb
Host smart-8271d0bf-5f14-43eb-868a-8cf75496cf1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154286885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.2154286885
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1094218703
Short name T685
Test name
Test status
Simulation time 59041283 ps
CPU time 2.68 seconds
Started Jul 16 07:56:43 PM PDT 24
Finished Jul 16 07:56:47 PM PDT 24
Peak memory 219736 kb
Host smart-1a6fa146-b70c-42ad-88ba-e196e1946a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094218703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1094218703
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.1940799224
Short name T651
Test name
Test status
Simulation time 167754435 ps
CPU time 5.52 seconds
Started Jul 16 07:56:40 PM PDT 24
Finished Jul 16 07:56:46 PM PDT 24
Peak memory 214336 kb
Host smart-ddfc0d1e-6a1b-4728-979b-f80abd472b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940799224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1940799224
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload.1103819836
Short name T323
Test name
Test status
Simulation time 550721363 ps
CPU time 4.17 seconds
Started Jul 16 07:56:39 PM PDT 24
Finished Jul 16 07:56:44 PM PDT 24
Peak memory 208404 kb
Host smart-170acb97-de8d-409c-bcb1-d17b20f75e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103819836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.1103819836
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.4181666519
Short name T832
Test name
Test status
Simulation time 61986162 ps
CPU time 2.56 seconds
Started Jul 16 07:56:40 PM PDT 24
Finished Jul 16 07:56:44 PM PDT 24
Peak memory 208212 kb
Host smart-88f8d2a8-3ebf-42dc-b987-f29453ad4e17
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181666519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.4181666519
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.2694787749
Short name T504
Test name
Test status
Simulation time 190930675 ps
CPU time 2.68 seconds
Started Jul 16 07:56:44 PM PDT 24
Finished Jul 16 07:56:49 PM PDT 24
Peak memory 206924 kb
Host smart-e95d430d-3f6a-43c5-9478-b929963fa0db
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694787749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.2694787749
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.3332320891
Short name T683
Test name
Test status
Simulation time 107256162 ps
CPU time 2.47 seconds
Started Jul 16 07:56:42 PM PDT 24
Finished Jul 16 07:56:45 PM PDT 24
Peak memory 206840 kb
Host smart-91d69b5f-547a-44f8-b4a9-fd816b37b61f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332320891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.3332320891
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.701395657
Short name T279
Test name
Test status
Simulation time 1334889032 ps
CPU time 6.29 seconds
Started Jul 16 07:56:44 PM PDT 24
Finished Jul 16 07:56:52 PM PDT 24
Peak memory 220736 kb
Host smart-0358776d-cc82-4fce-935b-63eea839e6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701395657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.701395657
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.4214426576
Short name T548
Test name
Test status
Simulation time 75114014 ps
CPU time 1.62 seconds
Started Jul 16 07:56:44 PM PDT 24
Finished Jul 16 07:56:48 PM PDT 24
Peak memory 206768 kb
Host smart-821d30e0-f43a-4c1f-9c1e-5e7736401d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214426576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.4214426576
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.4275271258
Short name T605
Test name
Test status
Simulation time 552309707 ps
CPU time 5.38 seconds
Started Jul 16 07:56:44 PM PDT 24
Finished Jul 16 07:56:52 PM PDT 24
Peak memory 222432 kb
Host smart-796463f8-9204-459e-b263-fc0e691936de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275271258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.4275271258
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.3487397864
Short name T852
Test name
Test status
Simulation time 35493905 ps
CPU time 0.7 seconds
Started Jul 16 07:57:05 PM PDT 24
Finished Jul 16 07:57:07 PM PDT 24
Peak memory 205956 kb
Host smart-16e1324b-e9e8-49a6-88ae-0bffcc0bc325
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487397864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.3487397864
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.375069428
Short name T76
Test name
Test status
Simulation time 45966991 ps
CPU time 1.4 seconds
Started Jul 16 07:56:55 PM PDT 24
Finished Jul 16 07:56:58 PM PDT 24
Peak memory 214716 kb
Host smart-a58b9f46-6bea-4bc8-8da9-f7ecdbba7c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375069428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.375069428
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.1981730123
Short name T757
Test name
Test status
Simulation time 117746260 ps
CPU time 2.08 seconds
Started Jul 16 07:57:02 PM PDT 24
Finished Jul 16 07:57:05 PM PDT 24
Peak memory 207016 kb
Host smart-1f65f24e-0dec-4e33-b015-0b3f055ff260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981730123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.1981730123
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.2757169906
Short name T877
Test name
Test status
Simulation time 1931284118 ps
CPU time 56.82 seconds
Started Jul 16 07:57:03 PM PDT 24
Finished Jul 16 07:58:01 PM PDT 24
Peak memory 222392 kb
Host smart-4ae9e2b8-d61e-4954-89b8-52c5dee1e02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757169906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.2757169906
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.2014796387
Short name T616
Test name
Test status
Simulation time 140940380 ps
CPU time 4.6 seconds
Started Jul 16 07:57:03 PM PDT 24
Finished Jul 16 07:57:09 PM PDT 24
Peak memory 214336 kb
Host smart-108abf16-b841-4a32-8dad-2165d0a556ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014796387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.2014796387
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.3766994389
Short name T93
Test name
Test status
Simulation time 1815594962 ps
CPU time 16.13 seconds
Started Jul 16 07:57:02 PM PDT 24
Finished Jul 16 07:57:19 PM PDT 24
Peak memory 214264 kb
Host smart-521c1d49-953c-400f-a65d-e19e90f5ab1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766994389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3766994389
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.3218847067
Short name T826
Test name
Test status
Simulation time 6037029644 ps
CPU time 29.68 seconds
Started Jul 16 07:57:03 PM PDT 24
Finished Jul 16 07:57:34 PM PDT 24
Peak memory 208068 kb
Host smart-0196b513-47b9-45a6-a554-9a4d5d7d015a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218847067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.3218847067
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.248514139
Short name T317
Test name
Test status
Simulation time 82441415 ps
CPU time 3.96 seconds
Started Jul 16 07:57:03 PM PDT 24
Finished Jul 16 07:57:08 PM PDT 24
Peak memory 208540 kb
Host smart-62be44e7-1bfc-4bc3-84db-98a3e50f6d51
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248514139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.248514139
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.2244061081
Short name T871
Test name
Test status
Simulation time 92755545 ps
CPU time 3.16 seconds
Started Jul 16 07:57:05 PM PDT 24
Finished Jul 16 07:57:10 PM PDT 24
Peak memory 206728 kb
Host smart-a8822f4c-5f68-4123-9b90-e4126d5f0dbb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244061081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.2244061081
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.1651218398
Short name T497
Test name
Test status
Simulation time 588832602 ps
CPU time 3.65 seconds
Started Jul 16 07:56:53 PM PDT 24
Finished Jul 16 07:56:59 PM PDT 24
Peak memory 206896 kb
Host smart-bc40e4cf-d580-40ec-97e4-831e00301b05
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651218398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.1651218398
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.443390009
Short name T914
Test name
Test status
Simulation time 231808668 ps
CPU time 2.76 seconds
Started Jul 16 07:57:05 PM PDT 24
Finished Jul 16 07:57:10 PM PDT 24
Peak memory 207972 kb
Host smart-96a95c9c-3a71-4012-bbd6-bd09484b41cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443390009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.443390009
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.80639291
Short name T438
Test name
Test status
Simulation time 2705168905 ps
CPU time 40.23 seconds
Started Jul 16 07:57:02 PM PDT 24
Finished Jul 16 07:57:43 PM PDT 24
Peak memory 208764 kb
Host smart-7d54ebbb-136c-4ee3-a15e-b34150f64186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80639291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.80639291
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.1316407032
Short name T799
Test name
Test status
Simulation time 261405374 ps
CPU time 7.44 seconds
Started Jul 16 07:57:03 PM PDT 24
Finished Jul 16 07:57:12 PM PDT 24
Peak memory 222500 kb
Host smart-d2a0f220-c8ad-456c-902c-e0be354af23b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316407032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1316407032
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.293617292
Short name T620
Test name
Test status
Simulation time 1839375308 ps
CPU time 19.35 seconds
Started Jul 16 07:57:09 PM PDT 24
Finished Jul 16 07:57:29 PM PDT 24
Peak memory 221432 kb
Host smart-12a86027-ce83-4c6d-b55a-7ccd23154d85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293617292 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.293617292
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.2211345054
Short name T766
Test name
Test status
Simulation time 492782476 ps
CPU time 5.16 seconds
Started Jul 16 07:57:04 PM PDT 24
Finished Jul 16 07:57:10 PM PDT 24
Peak memory 214276 kb
Host smart-99084305-f14c-4740-93b7-c49e6c918212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211345054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.2211345054
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.3211717666
Short name T868
Test name
Test status
Simulation time 304750336 ps
CPU time 2.58 seconds
Started Jul 16 07:56:53 PM PDT 24
Finished Jul 16 07:56:58 PM PDT 24
Peak memory 210336 kb
Host smart-4ad05269-b11b-457f-9acf-7270ffffcc06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211717666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.3211717666
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.3464956932
Short name T590
Test name
Test status
Simulation time 16167774 ps
CPU time 0.95 seconds
Started Jul 16 07:57:05 PM PDT 24
Finished Jul 16 07:57:07 PM PDT 24
Peak memory 206104 kb
Host smart-69978d32-2d07-4543-ba92-b370b9198988
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464956932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.3464956932
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.2522621450
Short name T345
Test name
Test status
Simulation time 33349604 ps
CPU time 2.13 seconds
Started Jul 16 07:57:02 PM PDT 24
Finished Jul 16 07:57:05 PM PDT 24
Peak memory 209212 kb
Host smart-69b70744-106f-46bc-9ae1-de4dd86f638c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522621450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.2522621450
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.4158166484
Short name T98
Test name
Test status
Simulation time 150656972 ps
CPU time 2.2 seconds
Started Jul 16 07:57:09 PM PDT 24
Finished Jul 16 07:57:13 PM PDT 24
Peak memory 222448 kb
Host smart-33ab39f2-bf88-4040-8a30-0a4b1eec9f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158166484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.4158166484
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.3109058892
Short name T567
Test name
Test status
Simulation time 371349108 ps
CPU time 3.96 seconds
Started Jul 16 07:57:09 PM PDT 24
Finished Jul 16 07:57:14 PM PDT 24
Peak memory 217900 kb
Host smart-16f97683-ce79-4064-a6f7-454155e86154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109058892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.3109058892
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.1555065877
Short name T695
Test name
Test status
Simulation time 156093414 ps
CPU time 6.34 seconds
Started Jul 16 07:57:09 PM PDT 24
Finished Jul 16 07:57:16 PM PDT 24
Peak memory 210476 kb
Host smart-c20dc2fc-eda4-4f29-9744-3cf24ba56def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555065877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.1555065877
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.1979908173
Short name T291
Test name
Test status
Simulation time 67048344 ps
CPU time 3.38 seconds
Started Jul 16 07:57:09 PM PDT 24
Finished Jul 16 07:57:13 PM PDT 24
Peak memory 208872 kb
Host smart-03168fb1-661f-4da2-9dcf-7c21b6f84bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979908173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1979908173
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.3894715309
Short name T739
Test name
Test status
Simulation time 3200835100 ps
CPU time 42.14 seconds
Started Jul 16 07:57:05 PM PDT 24
Finished Jul 16 07:57:48 PM PDT 24
Peak memory 208364 kb
Host smart-76a1b9de-4925-4d2c-91c4-9c32013998b2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894715309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3894715309
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.4140837320
Short name T368
Test name
Test status
Simulation time 138621153 ps
CPU time 5.1 seconds
Started Jul 16 07:57:03 PM PDT 24
Finished Jul 16 07:57:09 PM PDT 24
Peak memory 208076 kb
Host smart-c6b5ab87-c428-43a1-9d0d-b7f822a0313e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140837320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.4140837320
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.3067639021
Short name T718
Test name
Test status
Simulation time 1218292368 ps
CPU time 41.05 seconds
Started Jul 16 07:57:03 PM PDT 24
Finished Jul 16 07:57:45 PM PDT 24
Peak memory 209128 kb
Host smart-253ed83c-004e-4f52-8943-4a0c6d707965
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067639021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.3067639021
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.2477084149
Short name T763
Test name
Test status
Simulation time 39933713 ps
CPU time 2.22 seconds
Started Jul 16 07:57:04 PM PDT 24
Finished Jul 16 07:57:08 PM PDT 24
Peak memory 209280 kb
Host smart-762e116c-e72d-4aff-afbd-a56c29d38e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477084149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.2477084149
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.3634111300
Short name T406
Test name
Test status
Simulation time 265616835 ps
CPU time 5.29 seconds
Started Jul 16 07:57:09 PM PDT 24
Finished Jul 16 07:57:15 PM PDT 24
Peak memory 208552 kb
Host smart-f4543c37-32c9-4679-8c0f-af1cb640082f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634111300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3634111300
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.3788425876
Short name T244
Test name
Test status
Simulation time 2806999168 ps
CPU time 31.76 seconds
Started Jul 16 07:57:05 PM PDT 24
Finished Jul 16 07:57:39 PM PDT 24
Peak memory 222552 kb
Host smart-1dd517cb-8dc1-4cbc-975b-eb3db456801d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788425876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3788425876
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.1644397618
Short name T857
Test name
Test status
Simulation time 4187593862 ps
CPU time 10.2 seconds
Started Jul 16 07:57:03 PM PDT 24
Finished Jul 16 07:57:15 PM PDT 24
Peak memory 222656 kb
Host smart-51711182-04ad-4ad7-94f1-8f9b01e37d1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644397618 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.1644397618
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.1369395043
Short name T899
Test name
Test status
Simulation time 671834580 ps
CPU time 8.15 seconds
Started Jul 16 07:57:09 PM PDT 24
Finished Jul 16 07:57:18 PM PDT 24
Peak memory 208280 kb
Host smart-c5e168ca-7a5d-426f-8967-c339f651c672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369395043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.1369395043
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.2821507116
Short name T194
Test name
Test status
Simulation time 1255060891 ps
CPU time 6.09 seconds
Started Jul 16 07:57:05 PM PDT 24
Finished Jul 16 07:57:13 PM PDT 24
Peak memory 210536 kb
Host smart-ba19e2fc-400e-4be5-92c4-18e2e030f1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821507116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.2821507116
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.2979138691
Short name T859
Test name
Test status
Simulation time 1880745230 ps
CPU time 48.85 seconds
Started Jul 16 07:57:09 PM PDT 24
Finished Jul 16 07:57:58 PM PDT 24
Peak memory 215328 kb
Host smart-ef3451f4-b7b2-46cd-9254-fcbb0d662eee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2979138691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.2979138691
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.3014473481
Short name T606
Test name
Test status
Simulation time 367812253 ps
CPU time 1.98 seconds
Started Jul 16 07:57:20 PM PDT 24
Finished Jul 16 07:57:23 PM PDT 24
Peak memory 218256 kb
Host smart-9fcd796e-5b72-476c-aefb-fb512279048f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014473481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.3014473481
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.3467569691
Short name T391
Test name
Test status
Simulation time 44965408 ps
CPU time 2.19 seconds
Started Jul 16 07:57:09 PM PDT 24
Finished Jul 16 07:57:12 PM PDT 24
Peak memory 208816 kb
Host smart-d9410ece-b719-4a3d-9d9f-365fae2e52ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467569691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.3467569691
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.959929681
Short name T100
Test name
Test status
Simulation time 338933994 ps
CPU time 3.65 seconds
Started Jul 16 07:57:09 PM PDT 24
Finished Jul 16 07:57:14 PM PDT 24
Peak memory 210204 kb
Host smart-c3fd3dba-7c79-4b40-b0d9-41b8216cb437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959929681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.959929681
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.1704487529
Short name T720
Test name
Test status
Simulation time 46583629 ps
CPU time 2.87 seconds
Started Jul 16 07:57:09 PM PDT 24
Finished Jul 16 07:57:13 PM PDT 24
Peak memory 215352 kb
Host smart-1d3788b0-e30e-416f-9c45-3338206e69a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704487529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1704487529
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.4063492766
Short name T822
Test name
Test status
Simulation time 203715086 ps
CPU time 4.27 seconds
Started Jul 16 07:57:08 PM PDT 24
Finished Jul 16 07:57:13 PM PDT 24
Peak memory 215968 kb
Host smart-bee00e72-a851-46a2-a013-3723287fe660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063492766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.4063492766
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.2321423191
Short name T252
Test name
Test status
Simulation time 2409765463 ps
CPU time 6.79 seconds
Started Jul 16 07:57:08 PM PDT 24
Finished Jul 16 07:57:15 PM PDT 24
Peak memory 214476 kb
Host smart-3fe14ecc-93e6-4c89-b869-bc9031b5cd4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321423191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.2321423191
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.1191048332
Short name T777
Test name
Test status
Simulation time 197555318 ps
CPU time 5.53 seconds
Started Jul 16 07:57:04 PM PDT 24
Finished Jul 16 07:57:12 PM PDT 24
Peak memory 207800 kb
Host smart-023cb7e7-f764-451e-b383-254a5e68df39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191048332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.1191048332
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.796994015
Short name T550
Test name
Test status
Simulation time 116902408 ps
CPU time 4.84 seconds
Started Jul 16 07:57:05 PM PDT 24
Finished Jul 16 07:57:11 PM PDT 24
Peak memory 208692 kb
Host smart-90090fd1-1213-4028-bf82-d21ee3887157
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796994015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.796994015
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.3867664100
Short name T453
Test name
Test status
Simulation time 112494261 ps
CPU time 4.58 seconds
Started Jul 16 07:57:05 PM PDT 24
Finished Jul 16 07:57:11 PM PDT 24
Peak memory 207112 kb
Host smart-cea76b06-a0e0-4cee-ae07-0dd26a1bbcd0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867664100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.3867664100
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.532265025
Short name T692
Test name
Test status
Simulation time 122456638 ps
CPU time 4.97 seconds
Started Jul 16 07:57:09 PM PDT 24
Finished Jul 16 07:57:15 PM PDT 24
Peak memory 206524 kb
Host smart-1b8f3477-7ae6-4371-a10d-3bc98ff5a8f0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532265025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.532265025
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.1955346469
Short name T694
Test name
Test status
Simulation time 130703213 ps
CPU time 2.17 seconds
Started Jul 16 07:57:19 PM PDT 24
Finished Jul 16 07:57:22 PM PDT 24
Peak memory 208132 kb
Host smart-4b0d2548-2778-4d07-a725-9a25fd5eb4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955346469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.1955346469
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.2234255988
Short name T724
Test name
Test status
Simulation time 76765093 ps
CPU time 2.07 seconds
Started Jul 16 07:56:59 PM PDT 24
Finished Jul 16 07:57:02 PM PDT 24
Peak memory 206944 kb
Host smart-32ba1783-7765-4701-9cdc-ea94d7f51663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234255988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.2234255988
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.2057013112
Short name T81
Test name
Test status
Simulation time 522622726 ps
CPU time 13.6 seconds
Started Jul 16 07:57:22 PM PDT 24
Finished Jul 16 07:57:37 PM PDT 24
Peak memory 214324 kb
Host smart-321deed8-db7b-4c66-9624-694cf6fd1110
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057013112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.2057013112
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.3701809982
Short name T459
Test name
Test status
Simulation time 343909789 ps
CPU time 8.78 seconds
Started Jul 16 07:57:09 PM PDT 24
Finished Jul 16 07:57:19 PM PDT 24
Peak memory 208468 kb
Host smart-7067f336-72b3-4288-a2db-c89dc24abeb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701809982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.3701809982
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.106164191
Short name T628
Test name
Test status
Simulation time 60680057 ps
CPU time 2.32 seconds
Started Jul 16 07:57:17 PM PDT 24
Finished Jul 16 07:57:20 PM PDT 24
Peak memory 210936 kb
Host smart-111de012-0d86-45f1-9300-e80cc1b3be30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106164191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.106164191
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.4243189094
Short name T660
Test name
Test status
Simulation time 18057180 ps
CPU time 0.89 seconds
Started Jul 16 07:57:21 PM PDT 24
Finished Jul 16 07:57:23 PM PDT 24
Peak memory 205992 kb
Host smart-656f7d59-38e9-4ae9-9b30-1875ef383de7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243189094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.4243189094
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.2787562408
Short name T415
Test name
Test status
Simulation time 65945602 ps
CPU time 4.13 seconds
Started Jul 16 07:57:22 PM PDT 24
Finished Jul 16 07:57:27 PM PDT 24
Peak memory 215164 kb
Host smart-4a0bd00a-2889-4e1d-beda-2f7596ebb114
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2787562408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.2787562408
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.1213851174
Short name T814
Test name
Test status
Simulation time 494658562 ps
CPU time 2.62 seconds
Started Jul 16 07:57:23 PM PDT 24
Finished Jul 16 07:57:26 PM PDT 24
Peak memory 219388 kb
Host smart-1177ee11-4382-4c4e-9292-55e5e5a90941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213851174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.1213851174
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3406901994
Short name T597
Test name
Test status
Simulation time 245293489 ps
CPU time 2.84 seconds
Started Jul 16 07:57:18 PM PDT 24
Finished Jul 16 07:57:22 PM PDT 24
Peak memory 209460 kb
Host smart-d1ffd3c7-98b0-4937-90a1-ed6316e42b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406901994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3406901994
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.1086668251
Short name T771
Test name
Test status
Simulation time 235370649 ps
CPU time 3.37 seconds
Started Jul 16 07:57:23 PM PDT 24
Finished Jul 16 07:57:27 PM PDT 24
Peak memory 214340 kb
Host smart-d4cbbb62-57ce-4a81-ae41-9ac787efbfcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086668251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1086668251
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sideload.2973101898
Short name T803
Test name
Test status
Simulation time 281974908 ps
CPU time 6.2 seconds
Started Jul 16 07:57:19 PM PDT 24
Finished Jul 16 07:57:26 PM PDT 24
Peak memory 208792 kb
Host smart-060805e7-84d3-4954-b0e7-492655ad3f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973101898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.2973101898
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.3551484683
Short name T439
Test name
Test status
Simulation time 96916085 ps
CPU time 2.12 seconds
Started Jul 16 07:57:24 PM PDT 24
Finished Jul 16 07:57:27 PM PDT 24
Peak memory 208640 kb
Host smart-557b6e74-a7bb-4667-a035-5d6fda81d3d4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551484683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3551484683
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.2521698957
Short name T796
Test name
Test status
Simulation time 36552569 ps
CPU time 1.82 seconds
Started Jul 16 07:57:20 PM PDT 24
Finished Jul 16 07:57:22 PM PDT 24
Peak memory 207000 kb
Host smart-517a4888-072a-4725-a84a-e7d9a6a613e6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521698957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.2521698957
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.2393828785
Short name T714
Test name
Test status
Simulation time 182358970 ps
CPU time 4.16 seconds
Started Jul 16 07:57:19 PM PDT 24
Finished Jul 16 07:57:25 PM PDT 24
Peak memory 208680 kb
Host smart-e4e553cd-fcdc-4112-8928-504eaa50d3dd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393828785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.2393828785
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.3565563969
Short name T214
Test name
Test status
Simulation time 79819518 ps
CPU time 1.71 seconds
Started Jul 16 07:57:19 PM PDT 24
Finished Jul 16 07:57:21 PM PDT 24
Peak memory 207388 kb
Host smart-a893e4c3-872a-4fc3-a928-39421cf917ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565563969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.3565563969
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.2670883260
Short name T446
Test name
Test status
Simulation time 88076964 ps
CPU time 1.65 seconds
Started Jul 16 07:57:21 PM PDT 24
Finished Jul 16 07:57:24 PM PDT 24
Peak memory 206932 kb
Host smart-47a05029-26d5-4a07-b8b3-5a5e98e89a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670883260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.2670883260
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.2691568038
Short name T850
Test name
Test status
Simulation time 671131468 ps
CPU time 21.68 seconds
Started Jul 16 07:57:19 PM PDT 24
Finished Jul 16 07:57:42 PM PDT 24
Peak memory 222664 kb
Host smart-7d09b699-6a0e-4716-a9f5-e391cda69ca5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691568038 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.2691568038
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.2250130202
Short name T735
Test name
Test status
Simulation time 98734177 ps
CPU time 2.24 seconds
Started Jul 16 07:57:21 PM PDT 24
Finished Jul 16 07:57:24 PM PDT 24
Peak memory 206960 kb
Host smart-28c9b2f4-f238-4d4c-a656-96579bcfbbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250130202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2250130202
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.13098127
Short name T493
Test name
Test status
Simulation time 30277696 ps
CPU time 1.68 seconds
Started Jul 16 07:57:19 PM PDT 24
Finished Jul 16 07:57:22 PM PDT 24
Peak memory 209948 kb
Host smart-9fd4b05d-c079-47ec-aa93-c05e1cd3370c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13098127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.13098127
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.3041806977
Short name T617
Test name
Test status
Simulation time 16803899 ps
CPU time 0.95 seconds
Started Jul 16 07:57:37 PM PDT 24
Finished Jul 16 07:57:39 PM PDT 24
Peak memory 206224 kb
Host smart-5904dfc6-c60e-493d-b8ee-7d024daab8b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041806977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.3041806977
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.2298343334
Short name T827
Test name
Test status
Simulation time 749182286 ps
CPU time 40.13 seconds
Started Jul 16 07:57:22 PM PDT 24
Finished Jul 16 07:58:03 PM PDT 24
Peak memory 215752 kb
Host smart-6db6c9ec-1721-4b49-95ee-227f746cb334
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2298343334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2298343334
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.2240369398
Short name T815
Test name
Test status
Simulation time 99637190 ps
CPU time 1.42 seconds
Started Jul 16 07:57:37 PM PDT 24
Finished Jul 16 07:57:40 PM PDT 24
Peak memory 214324 kb
Host smart-17f4a5b0-9857-45a7-89b5-f9d9abc5af42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240369398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.2240369398
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.1981527778
Short name T847
Test name
Test status
Simulation time 32654556 ps
CPU time 1.92 seconds
Started Jul 16 07:57:18 PM PDT 24
Finished Jul 16 07:57:21 PM PDT 24
Peak memory 207616 kb
Host smart-8ca5544a-976f-49f3-887b-5ef1bd921815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981527778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1981527778
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.891785074
Short name T663
Test name
Test status
Simulation time 299134284 ps
CPU time 6.04 seconds
Started Jul 16 07:57:44 PM PDT 24
Finished Jul 16 07:57:54 PM PDT 24
Peak memory 214312 kb
Host smart-6a8938e6-23a4-43a4-b3a9-1755b473623f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891785074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.891785074
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.1884488704
Short name T260
Test name
Test status
Simulation time 164310862 ps
CPU time 5.41 seconds
Started Jul 16 07:57:39 PM PDT 24
Finished Jul 16 07:57:47 PM PDT 24
Peak memory 220900 kb
Host smart-feef816b-8a46-492b-81ee-164919396768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884488704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.1884488704
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.4129214281
Short name T622
Test name
Test status
Simulation time 154079089 ps
CPU time 2.16 seconds
Started Jul 16 07:57:22 PM PDT 24
Finished Jul 16 07:57:26 PM PDT 24
Peak memory 208616 kb
Host smart-fcd6b3ae-8589-469c-ba52-bac046ded34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129214281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.4129214281
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.2950161037
Short name T272
Test name
Test status
Simulation time 2856737833 ps
CPU time 6.48 seconds
Started Jul 16 07:57:22 PM PDT 24
Finished Jul 16 07:57:30 PM PDT 24
Peak memory 207380 kb
Host smart-6f2f797c-c73c-4488-a010-178341d5dedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950161037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.2950161037
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.414911995
Short name T672
Test name
Test status
Simulation time 114575687 ps
CPU time 3.56 seconds
Started Jul 16 07:57:21 PM PDT 24
Finished Jul 16 07:57:26 PM PDT 24
Peak memory 206976 kb
Host smart-a04910c1-6a24-496a-aab5-b1ebaab06273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414911995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.414911995
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.352603239
Short name T582
Test name
Test status
Simulation time 225587492 ps
CPU time 5.03 seconds
Started Jul 16 07:57:19 PM PDT 24
Finished Jul 16 07:57:25 PM PDT 24
Peak memory 209056 kb
Host smart-de7fce88-a935-4c6b-922d-caf674dbea41
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352603239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.352603239
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.3389369028
Short name T835
Test name
Test status
Simulation time 68389992 ps
CPU time 3.45 seconds
Started Jul 16 07:57:19 PM PDT 24
Finished Jul 16 07:57:24 PM PDT 24
Peak memory 208668 kb
Host smart-29a8650a-fd56-437c-99f7-0d6768c05106
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389369028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.3389369028
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.1250284375
Short name T602
Test name
Test status
Simulation time 70794263 ps
CPU time 3.29 seconds
Started Jul 16 07:57:23 PM PDT 24
Finished Jul 16 07:57:27 PM PDT 24
Peak memory 207788 kb
Host smart-4490d2db-e1b2-4274-b305-7e06605c89ac
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250284375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.1250284375
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.4188430401
Short name T221
Test name
Test status
Simulation time 104625374 ps
CPU time 2.8 seconds
Started Jul 16 07:57:39 PM PDT 24
Finished Jul 16 07:57:44 PM PDT 24
Peak memory 208400 kb
Host smart-15476527-6a07-4ec0-a7cb-4926e3108616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188430401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.4188430401
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.872931516
Short name T751
Test name
Test status
Simulation time 148430280 ps
CPU time 3.81 seconds
Started Jul 16 07:57:22 PM PDT 24
Finished Jul 16 07:57:27 PM PDT 24
Peak memory 208456 kb
Host smart-7fb41005-82d9-487b-b955-3aa16c8efcee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872931516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.872931516
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.1546969335
Short name T385
Test name
Test status
Simulation time 631111000 ps
CPU time 24.96 seconds
Started Jul 16 07:57:52 PM PDT 24
Finished Jul 16 07:58:22 PM PDT 24
Peak memory 221980 kb
Host smart-becf7791-eac0-4d2e-9f5a-9689bdf2df58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546969335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.1546969335
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.2072362585
Short name T83
Test name
Test status
Simulation time 1256956616 ps
CPU time 12.28 seconds
Started Jul 16 07:57:46 PM PDT 24
Finished Jul 16 07:58:03 PM PDT 24
Peak memory 219720 kb
Host smart-be895455-4987-4d7b-a9f0-96ae0c4ebc7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072362585 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.2072362585
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.960778312
Short name T288
Test name
Test status
Simulation time 972886132 ps
CPU time 6.06 seconds
Started Jul 16 07:57:37 PM PDT 24
Finished Jul 16 07:57:44 PM PDT 24
Peak memory 214324 kb
Host smart-6ca69775-0d2b-4caf-8f8a-7cdde8dad369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960778312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.960778312
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.1808769747
Short name T770
Test name
Test status
Simulation time 85256960 ps
CPU time 1.87 seconds
Started Jul 16 07:57:41 PM PDT 24
Finished Jul 16 07:57:46 PM PDT 24
Peak memory 210244 kb
Host smart-9c6638af-18a7-4d9e-ab79-b11406b56c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808769747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1808769747
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.3526987912
Short name T722
Test name
Test status
Simulation time 20468139 ps
CPU time 0.75 seconds
Started Jul 16 07:57:41 PM PDT 24
Finished Jul 16 07:57:46 PM PDT 24
Peak memory 205968 kb
Host smart-fb2b357f-a8a9-4616-8d02-dfcc137c7672
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526987912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.3526987912
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.1607672424
Short name T424
Test name
Test status
Simulation time 267509975 ps
CPU time 2.62 seconds
Started Jul 16 07:57:39 PM PDT 24
Finished Jul 16 07:57:42 PM PDT 24
Peak memory 214504 kb
Host smart-c1c521d5-b42d-4107-a456-549cca9750f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1607672424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.1607672424
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.3129489110
Short name T22
Test name
Test status
Simulation time 76735395 ps
CPU time 3.11 seconds
Started Jul 16 07:57:45 PM PDT 24
Finished Jul 16 07:57:52 PM PDT 24
Peak memory 221744 kb
Host smart-f7f7224f-6527-4c43-b9f5-29a21c95b7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129489110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.3129489110
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.3720267081
Short name T192
Test name
Test status
Simulation time 48618095 ps
CPU time 3.3 seconds
Started Jul 16 07:57:39 PM PDT 24
Finished Jul 16 07:57:43 PM PDT 24
Peak memory 209920 kb
Host smart-2ec90167-cabb-43af-a335-1d69d4767a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720267081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.3720267081
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.1028824830
Short name T600
Test name
Test status
Simulation time 209120724 ps
CPU time 7.06 seconds
Started Jul 16 07:57:41 PM PDT 24
Finished Jul 16 07:57:51 PM PDT 24
Peak memory 214308 kb
Host smart-ad1051fa-4cb0-4a91-ae61-0a418f2990e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028824830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.1028824830
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.1542945918
Short name T277
Test name
Test status
Simulation time 97148835 ps
CPU time 2.3 seconds
Started Jul 16 07:57:43 PM PDT 24
Finished Jul 16 07:57:49 PM PDT 24
Peak memory 214496 kb
Host smart-212d9ddb-0839-423f-b3d6-58de04d4af98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542945918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.1542945918
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.190779533
Short name T307
Test name
Test status
Simulation time 105549704 ps
CPU time 4.7 seconds
Started Jul 16 07:57:44 PM PDT 24
Finished Jul 16 07:57:54 PM PDT 24
Peak memory 210344 kb
Host smart-b9c93f4e-a889-4663-83e8-69a13baa9a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190779533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.190779533
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.2413430006
Short name T707
Test name
Test status
Simulation time 3728921035 ps
CPU time 9.15 seconds
Started Jul 16 07:57:46 PM PDT 24
Finished Jul 16 07:58:00 PM PDT 24
Peak memory 214364 kb
Host smart-21e2fe9e-43a3-44a9-8d35-5157486b2976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413430006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.2413430006
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.3560054492
Short name T478
Test name
Test status
Simulation time 1206048055 ps
CPU time 3.8 seconds
Started Jul 16 07:57:41 PM PDT 24
Finished Jul 16 07:57:48 PM PDT 24
Peak memory 206984 kb
Host smart-1bda538f-ee74-4973-aac3-7105e27b857f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560054492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.3560054492
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.3829154073
Short name T327
Test name
Test status
Simulation time 906150028 ps
CPU time 6.56 seconds
Started Jul 16 07:57:40 PM PDT 24
Finished Jul 16 07:57:48 PM PDT 24
Peak memory 208064 kb
Host smart-0e209c27-764c-46bc-9d79-201f548b4d15
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829154073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.3829154073
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.2434226154
Short name T741
Test name
Test status
Simulation time 378911767 ps
CPU time 7.66 seconds
Started Jul 16 07:57:39 PM PDT 24
Finished Jul 16 07:57:48 PM PDT 24
Peak memory 208824 kb
Host smart-860c1eb3-1f71-45ac-83e4-5ebbf4dfe3dd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434226154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2434226154
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.1577442599
Short name T204
Test name
Test status
Simulation time 2583147354 ps
CPU time 18.03 seconds
Started Jul 16 07:57:39 PM PDT 24
Finished Jul 16 07:57:58 PM PDT 24
Peak memory 208288 kb
Host smart-c4eec6c1-3c2c-41a9-8f6e-cb0649d09f9d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577442599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.1577442599
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.2812828625
Short name T519
Test name
Test status
Simulation time 61420823 ps
CPU time 2.25 seconds
Started Jul 16 07:57:41 PM PDT 24
Finished Jul 16 07:57:47 PM PDT 24
Peak memory 208296 kb
Host smart-010f02b5-4e52-4d4d-8f08-e1c6926c9915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812828625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2812828625
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.3299935152
Short name T678
Test name
Test status
Simulation time 211803238 ps
CPU time 4.42 seconds
Started Jul 16 07:57:41 PM PDT 24
Finished Jul 16 07:57:49 PM PDT 24
Peak memory 207872 kb
Host smart-2e2dbbdd-e612-4b6e-9f9e-dfd8194f9377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299935152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.3299935152
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.1248482184
Short name T238
Test name
Test status
Simulation time 3294308800 ps
CPU time 101.31 seconds
Started Jul 16 07:57:41 PM PDT 24
Finished Jul 16 07:59:26 PM PDT 24
Peak memory 222556 kb
Host smart-cf8a6d71-9373-42ec-99f0-0fe38514da95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248482184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.1248482184
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.2743238961
Short name T43
Test name
Test status
Simulation time 59251607 ps
CPU time 1.34 seconds
Started Jul 16 07:57:39 PM PDT 24
Finished Jul 16 07:57:42 PM PDT 24
Peak memory 209824 kb
Host smart-ce4d9f7c-8bae-403f-b1c1-6e7c5b505d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743238961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.2743238961
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.242972366
Short name T748
Test name
Test status
Simulation time 30942510 ps
CPU time 0.74 seconds
Started Jul 16 07:57:41 PM PDT 24
Finished Jul 16 07:57:45 PM PDT 24
Peak memory 206000 kb
Host smart-f64550a5-58bd-49cf-b9c7-3f0c8cb9f27b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242972366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.242972366
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.934460079
Short name T131
Test name
Test status
Simulation time 94483315 ps
CPU time 3.59 seconds
Started Jul 16 07:57:41 PM PDT 24
Finished Jul 16 07:57:49 PM PDT 24
Peak memory 215584 kb
Host smart-a19964c1-4775-4d54-855d-bc22cb296ad3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=934460079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.934460079
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.503045443
Short name T11
Test name
Test status
Simulation time 174088011 ps
CPU time 4.56 seconds
Started Jul 16 07:57:41 PM PDT 24
Finished Jul 16 07:57:48 PM PDT 24
Peak memory 222020 kb
Host smart-64e48b00-e532-4ede-bb87-860b29231d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503045443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.503045443
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.3426458508
Short name T535
Test name
Test status
Simulation time 236473592 ps
CPU time 1.8 seconds
Started Jul 16 07:57:46 PM PDT 24
Finished Jul 16 07:57:53 PM PDT 24
Peak memory 207100 kb
Host smart-9a99b546-5701-4b04-8a0a-2d8aadfaacc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426458508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.3426458508
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.802829643
Short name T105
Test name
Test status
Simulation time 2220410038 ps
CPU time 5.29 seconds
Started Jul 16 07:57:40 PM PDT 24
Finished Jul 16 07:57:48 PM PDT 24
Peak memory 214428 kb
Host smart-ab05c775-ee55-4c35-bcb3-4e56e20b1bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802829643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.802829643
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.2627670195
Short name T417
Test name
Test status
Simulation time 387422764 ps
CPU time 2.13 seconds
Started Jul 16 07:57:42 PM PDT 24
Finished Jul 16 07:57:48 PM PDT 24
Peak memory 214236 kb
Host smart-560fdaab-fcc5-4afd-b988-7334dbb5b010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627670195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.2627670195
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.2469701026
Short name T647
Test name
Test status
Simulation time 267271653 ps
CPU time 3.03 seconds
Started Jul 16 07:57:37 PM PDT 24
Finished Jul 16 07:57:41 PM PDT 24
Peak memory 222520 kb
Host smart-b50b155e-72fb-41b4-854e-6faa16a46d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469701026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.2469701026
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_sideload.1613530674
Short name T350
Test name
Test status
Simulation time 145787716 ps
CPU time 3.72 seconds
Started Jul 16 07:57:40 PM PDT 24
Finished Jul 16 07:57:45 PM PDT 24
Peak memory 208844 kb
Host smart-70612316-58b9-4fcf-9e1d-7eb9ec006a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613530674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.1613530674
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.3586796892
Short name T885
Test name
Test status
Simulation time 771325338 ps
CPU time 8.78 seconds
Started Jul 16 07:57:41 PM PDT 24
Finished Jul 16 07:57:53 PM PDT 24
Peak memory 208768 kb
Host smart-7eaf76af-82db-4350-bbf0-c85417194bd8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586796892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.3586796892
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.3406481062
Short name T646
Test name
Test status
Simulation time 78889286 ps
CPU time 3.05 seconds
Started Jul 16 07:57:41 PM PDT 24
Finished Jul 16 07:57:48 PM PDT 24
Peak memory 206928 kb
Host smart-2173bbbe-3cf7-4e17-8e28-862496b84f70
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406481062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3406481062
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.3421564439
Short name T912
Test name
Test status
Simulation time 221820701 ps
CPU time 6.24 seconds
Started Jul 16 07:57:40 PM PDT 24
Finished Jul 16 07:57:49 PM PDT 24
Peak memory 207092 kb
Host smart-6d2abbb6-2cfc-43d4-bd37-0f430d5db549
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421564439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.3421564439
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.1553486037
Short name T434
Test name
Test status
Simulation time 392007089 ps
CPU time 1.88 seconds
Started Jul 16 07:57:40 PM PDT 24
Finished Jul 16 07:57:43 PM PDT 24
Peak memory 207624 kb
Host smart-fb680a84-a792-4deb-990b-0694abe3dbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553486037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.1553486037
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.4282339687
Short name T607
Test name
Test status
Simulation time 158157170 ps
CPU time 3.49 seconds
Started Jul 16 07:57:39 PM PDT 24
Finished Jul 16 07:57:44 PM PDT 24
Peak memory 208512 kb
Host smart-ffd58ab2-e2c3-4578-aa13-eec8473df44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282339687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.4282339687
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.4013624425
Short name T341
Test name
Test status
Simulation time 515577227 ps
CPU time 10.54 seconds
Started Jul 16 07:57:39 PM PDT 24
Finished Jul 16 07:57:52 PM PDT 24
Peak memory 209096 kb
Host smart-a7071f66-2a5d-4912-965f-00f08f94cd05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013624425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.4013624425
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.3589097631
Short name T892
Test name
Test status
Simulation time 254367355 ps
CPU time 2.93 seconds
Started Jul 16 07:57:37 PM PDT 24
Finished Jul 16 07:57:41 PM PDT 24
Peak memory 210336 kb
Host smart-f4f00448-67ef-426a-a48a-a25bb80c519e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589097631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.3589097631
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.3193088813
Short name T634
Test name
Test status
Simulation time 23680209 ps
CPU time 0.92 seconds
Started Jul 16 07:57:47 PM PDT 24
Finished Jul 16 07:57:54 PM PDT 24
Peak memory 206000 kb
Host smart-5d64ea62-83e1-40a4-940e-0a20bf5414d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193088813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.3193088813
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.4041585315
Short name T88
Test name
Test status
Simulation time 46877645 ps
CPU time 3.16 seconds
Started Jul 16 07:57:46 PM PDT 24
Finished Jul 16 07:57:54 PM PDT 24
Peak memory 214252 kb
Host smart-852c5ac9-3f01-41fc-9cd3-4d4dca493f24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4041585315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.4041585315
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.4200270225
Short name T539
Test name
Test status
Simulation time 88221215 ps
CPU time 3.04 seconds
Started Jul 16 07:57:40 PM PDT 24
Finished Jul 16 07:57:45 PM PDT 24
Peak memory 214712 kb
Host smart-61c96c61-2eb8-4758-986d-d204c60fdaaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200270225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.4200270225
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.835473939
Short name T697
Test name
Test status
Simulation time 54577157 ps
CPU time 2.82 seconds
Started Jul 16 07:57:41 PM PDT 24
Finished Jul 16 07:57:48 PM PDT 24
Peak memory 218260 kb
Host smart-c76bb444-89fb-4c5e-ac4b-c89806fbd685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835473939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.835473939
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.688099312
Short name T205
Test name
Test status
Simulation time 336729583 ps
CPU time 3.23 seconds
Started Jul 16 07:57:41 PM PDT 24
Finished Jul 16 07:57:48 PM PDT 24
Peak memory 214324 kb
Host smart-8f9439d5-269b-4e95-8ef5-e2b7605d7703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688099312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.688099312
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.3481253721
Short name T562
Test name
Test status
Simulation time 156877127 ps
CPU time 2.22 seconds
Started Jul 16 07:57:41 PM PDT 24
Finished Jul 16 07:57:48 PM PDT 24
Peak memory 214244 kb
Host smart-6e5c0626-83ef-4d8d-a2fe-b2d58fe37b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481253721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.3481253721
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.4190782141
Short name T915
Test name
Test status
Simulation time 165057563 ps
CPU time 5.06 seconds
Started Jul 16 07:57:42 PM PDT 24
Finished Jul 16 07:57:51 PM PDT 24
Peak memory 215260 kb
Host smart-1d54b8af-86c9-4073-a7fe-5411089693ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190782141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.4190782141
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.2403087699
Short name T527
Test name
Test status
Simulation time 55506269 ps
CPU time 3.57 seconds
Started Jul 16 07:57:41 PM PDT 24
Finished Jul 16 07:57:48 PM PDT 24
Peak memory 207896 kb
Host smart-0530a815-a48b-41dd-b99b-7cbc67fa4391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403087699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.2403087699
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.632790784
Short name T456
Test name
Test status
Simulation time 398266838 ps
CPU time 3.84 seconds
Started Jul 16 07:57:40 PM PDT 24
Finished Jul 16 07:57:47 PM PDT 24
Peak memory 206992 kb
Host smart-82d56f3f-edbc-4780-9003-2c489262c254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632790784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.632790784
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.1414035189
Short name T502
Test name
Test status
Simulation time 38899221 ps
CPU time 2.34 seconds
Started Jul 16 07:57:48 PM PDT 24
Finished Jul 16 07:57:56 PM PDT 24
Peak memory 207004 kb
Host smart-91a2a3e6-9433-4927-bdd3-5f9f8982df44
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414035189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.1414035189
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.3209583139
Short name T510
Test name
Test status
Simulation time 671759680 ps
CPU time 7.21 seconds
Started Jul 16 07:57:42 PM PDT 24
Finished Jul 16 07:57:54 PM PDT 24
Peak memory 206976 kb
Host smart-a138fe56-874c-4603-91cd-26d645c7752e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209583139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.3209583139
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.1905670368
Short name T40
Test name
Test status
Simulation time 2634383830 ps
CPU time 18.39 seconds
Started Jul 16 07:57:40 PM PDT 24
Finished Jul 16 07:58:02 PM PDT 24
Peak memory 208864 kb
Host smart-56ef89fd-8e31-4749-9bac-4ebb4036f98f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905670368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.1905670368
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.1661683408
Short name T87
Test name
Test status
Simulation time 139202551 ps
CPU time 2.68 seconds
Started Jul 16 07:57:41 PM PDT 24
Finished Jul 16 07:57:48 PM PDT 24
Peak memory 207276 kb
Host smart-98bc317a-f689-4567-b3b6-0bbddf33666f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661683408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.1661683408
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2690706528
Short name T725
Test name
Test status
Simulation time 46990619 ps
CPU time 2.07 seconds
Started Jul 16 07:57:40 PM PDT 24
Finished Jul 16 07:57:45 PM PDT 24
Peak memory 208616 kb
Host smart-b8808e2b-934a-4937-8074-17eeeb519355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690706528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2690706528
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.2399204195
Short name T362
Test name
Test status
Simulation time 3486663292 ps
CPU time 33.7 seconds
Started Jul 16 07:57:42 PM PDT 24
Finished Jul 16 07:58:20 PM PDT 24
Peak memory 216504 kb
Host smart-7e3a9f0e-99ed-4f01-81d0-8bb377622620
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399204195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.2399204195
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.3825372613
Short name T759
Test name
Test status
Simulation time 433341313 ps
CPU time 3.45 seconds
Started Jul 16 07:57:48 PM PDT 24
Finished Jul 16 07:57:58 PM PDT 24
Peak memory 207576 kb
Host smart-0a7cf3ef-dc81-42e4-87c4-26bbfff4c440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825372613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.3825372613
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.1438734298
Short name T6
Test name
Test status
Simulation time 218125116 ps
CPU time 2.16 seconds
Started Jul 16 07:57:41 PM PDT 24
Finished Jul 16 07:57:46 PM PDT 24
Peak memory 210476 kb
Host smart-f1b233bb-b6a6-44c6-9b28-46c12387a704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438734298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1438734298
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.249708319
Short name T521
Test name
Test status
Simulation time 15335494 ps
CPU time 0.81 seconds
Started Jul 16 07:57:51 PM PDT 24
Finished Jul 16 07:57:58 PM PDT 24
Peak memory 205972 kb
Host smart-7ac6761e-7729-44ad-9d61-8f8219927bec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249708319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.249708319
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.4203463187
Short name T134
Test name
Test status
Simulation time 1495812434 ps
CPU time 11.46 seconds
Started Jul 16 07:57:49 PM PDT 24
Finished Jul 16 07:58:07 PM PDT 24
Peak memory 214320 kb
Host smart-369323c7-ff18-4c3c-abe3-7799c2f3211b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4203463187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.4203463187
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.1277527152
Short name T422
Test name
Test status
Simulation time 58956302 ps
CPU time 2.7 seconds
Started Jul 16 07:57:48 PM PDT 24
Finished Jul 16 07:57:57 PM PDT 24
Peak memory 208532 kb
Host smart-2247e3a2-7232-4534-85bc-0eeed3fb6672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277527152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.1277527152
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.3257989915
Short name T101
Test name
Test status
Simulation time 108324098 ps
CPU time 2.19 seconds
Started Jul 16 07:57:40 PM PDT 24
Finished Jul 16 07:57:45 PM PDT 24
Peak memory 209536 kb
Host smart-f2b511ce-9ece-4e3c-9394-2099e3812c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257989915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.3257989915
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.66189873
Short name T805
Test name
Test status
Simulation time 313551078 ps
CPU time 4.86 seconds
Started Jul 16 07:57:41 PM PDT 24
Finished Jul 16 07:57:50 PM PDT 24
Peak memory 222320 kb
Host smart-7d65057a-d231-4544-9838-6abdf24c088e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66189873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.66189873
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.501359318
Short name T717
Test name
Test status
Simulation time 273349280 ps
CPU time 3.36 seconds
Started Jul 16 07:57:39 PM PDT 24
Finished Jul 16 07:57:43 PM PDT 24
Peak memory 219260 kb
Host smart-616a3ccb-d4b7-434e-a9ac-c073adb027fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501359318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.501359318
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.2259279936
Short name T295
Test name
Test status
Simulation time 2157184537 ps
CPU time 21.37 seconds
Started Jul 16 07:57:49 PM PDT 24
Finished Jul 16 07:58:17 PM PDT 24
Peak memory 214408 kb
Host smart-df202fed-f5ab-48b6-b2d0-07f0137f0bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259279936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.2259279936
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.2752146279
Short name T853
Test name
Test status
Simulation time 47794998 ps
CPU time 2.6 seconds
Started Jul 16 07:57:49 PM PDT 24
Finished Jul 16 07:57:58 PM PDT 24
Peak memory 208668 kb
Host smart-50b23e31-66cb-4118-bba5-6a9f29ae0424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752146279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.2752146279
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.2128080811
Short name T816
Test name
Test status
Simulation time 640740270 ps
CPU time 3.77 seconds
Started Jul 16 07:57:39 PM PDT 24
Finished Jul 16 07:57:45 PM PDT 24
Peak memory 206752 kb
Host smart-89260004-a7e8-45cd-8f21-b93dac4cf0fd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128080811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.2128080811
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.2406301274
Short name T560
Test name
Test status
Simulation time 84473819 ps
CPU time 2.49 seconds
Started Jul 16 07:57:40 PM PDT 24
Finished Jul 16 07:57:45 PM PDT 24
Peak memory 206940 kb
Host smart-f66fb020-c5ea-425b-a543-a00c9f3ed3e9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406301274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.2406301274
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.321275501
Short name T627
Test name
Test status
Simulation time 57920032 ps
CPU time 2.86 seconds
Started Jul 16 07:57:47 PM PDT 24
Finished Jul 16 07:57:57 PM PDT 24
Peak memory 208892 kb
Host smart-37d74b54-8e7a-45ec-9c01-471a367a3c9e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321275501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.321275501
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.848811667
Short name T473
Test name
Test status
Simulation time 52742427 ps
CPU time 1.94 seconds
Started Jul 16 07:57:47 PM PDT 24
Finished Jul 16 07:57:56 PM PDT 24
Peak memory 215876 kb
Host smart-f9a859c9-dfa6-43d1-9677-35e293295e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848811667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.848811667
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.3444911259
Short name T448
Test name
Test status
Simulation time 100975633 ps
CPU time 3.17 seconds
Started Jul 16 07:57:41 PM PDT 24
Finished Jul 16 07:57:49 PM PDT 24
Peak memory 206784 kb
Host smart-f8efac09-ba6c-4e72-80fc-684a045cff52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444911259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.3444911259
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.3312696003
Short name T335
Test name
Test status
Simulation time 359141837 ps
CPU time 5.52 seconds
Started Jul 16 07:57:46 PM PDT 24
Finished Jul 16 07:57:57 PM PDT 24
Peak memory 218472 kb
Host smart-9b41e191-7f60-4916-a19b-15798faabf33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312696003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.3312696003
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.2955342565
Short name T514
Test name
Test status
Simulation time 55221872 ps
CPU time 2.74 seconds
Started Jul 16 07:57:48 PM PDT 24
Finished Jul 16 07:57:57 PM PDT 24
Peak memory 210212 kb
Host smart-f0f6d97b-887a-42ab-bc7e-e591017ff1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955342565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.2955342565
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.2455285108
Short name T897
Test name
Test status
Simulation time 23802093 ps
CPU time 0.76 seconds
Started Jul 16 07:57:51 PM PDT 24
Finished Jul 16 07:57:58 PM PDT 24
Peak memory 205940 kb
Host smart-d4df260d-23f9-4742-abbb-196dd2907f92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455285108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.2455285108
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.3355763593
Short name T806
Test name
Test status
Simulation time 106050281 ps
CPU time 3.21 seconds
Started Jul 16 07:57:51 PM PDT 24
Finished Jul 16 07:58:00 PM PDT 24
Peak memory 218488 kb
Host smart-33491f86-68db-4f6f-ad20-912b95150b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355763593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.3355763593
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.1293990626
Short name T303
Test name
Test status
Simulation time 149406108 ps
CPU time 2.46 seconds
Started Jul 16 07:57:47 PM PDT 24
Finished Jul 16 07:57:56 PM PDT 24
Peak memory 214228 kb
Host smart-978276f3-c005-40bc-abaf-fa554b3b935b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293990626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.1293990626
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.2899030478
Short name T347
Test name
Test status
Simulation time 530231502 ps
CPU time 3.71 seconds
Started Jul 16 07:57:50 PM PDT 24
Finished Jul 16 07:58:00 PM PDT 24
Peak memory 214284 kb
Host smart-6a02b9d3-a7a5-46bf-8f70-dee224b6a712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899030478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.2899030478
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.2635562379
Short name T72
Test name
Test status
Simulation time 189687964 ps
CPU time 3.29 seconds
Started Jul 16 07:57:49 PM PDT 24
Finished Jul 16 07:57:59 PM PDT 24
Peak memory 208868 kb
Host smart-3c6b9f82-5e1a-45a7-a2f2-1818b14b6122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635562379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.2635562379
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.2860999578
Short name T18
Test name
Test status
Simulation time 338431034 ps
CPU time 4.64 seconds
Started Jul 16 07:57:45 PM PDT 24
Finished Jul 16 07:57:55 PM PDT 24
Peak memory 218392 kb
Host smart-6f71df16-f3ae-456d-a688-98f47501f551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860999578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.2860999578
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.830677419
Short name T793
Test name
Test status
Simulation time 1252596180 ps
CPU time 3.72 seconds
Started Jul 16 07:57:51 PM PDT 24
Finished Jul 16 07:58:01 PM PDT 24
Peak memory 206840 kb
Host smart-d6e83999-67d6-40fd-9550-6585e36cf96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830677419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.830677419
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.325745369
Short name T679
Test name
Test status
Simulation time 88894434 ps
CPU time 3.84 seconds
Started Jul 16 07:57:49 PM PDT 24
Finished Jul 16 07:57:59 PM PDT 24
Peak memory 208612 kb
Host smart-b2214e85-8416-47bc-950f-7ba37a7a4b58
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325745369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.325745369
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.2359974391
Short name T687
Test name
Test status
Simulation time 184714877 ps
CPU time 2.59 seconds
Started Jul 16 07:57:51 PM PDT 24
Finished Jul 16 07:57:59 PM PDT 24
Peak memory 208800 kb
Host smart-1bff0e4f-609a-4079-9ef1-bd0bb6a1f62b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359974391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.2359974391
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.1492409738
Short name T86
Test name
Test status
Simulation time 1523964426 ps
CPU time 7.04 seconds
Started Jul 16 07:57:50 PM PDT 24
Finished Jul 16 07:58:04 PM PDT 24
Peak memory 208672 kb
Host smart-ef99e7dc-e194-40cf-a971-7a55c8904131
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492409738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.1492409738
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.2608721554
Short name T314
Test name
Test status
Simulation time 30869106 ps
CPU time 2.29 seconds
Started Jul 16 07:57:50 PM PDT 24
Finished Jul 16 07:57:58 PM PDT 24
Peak memory 214440 kb
Host smart-01b07fa5-049c-4425-80ed-b221dac8b7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608721554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2608721554
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.3693514518
Short name T614
Test name
Test status
Simulation time 652126791 ps
CPU time 5.56 seconds
Started Jul 16 07:57:46 PM PDT 24
Finished Jul 16 07:57:58 PM PDT 24
Peak memory 208660 kb
Host smart-bd11a651-f266-4a55-9599-23660812ee14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693514518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.3693514518
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.177265140
Short name T208
Test name
Test status
Simulation time 127915387 ps
CPU time 5.6 seconds
Started Jul 16 07:57:49 PM PDT 24
Finished Jul 16 07:58:01 PM PDT 24
Peak memory 208952 kb
Host smart-01382d74-0ba7-40eb-8c25-91dab7c2c129
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177265140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.177265140
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.3004046559
Short name T667
Test name
Test status
Simulation time 1205693868 ps
CPU time 5.11 seconds
Started Jul 16 07:57:51 PM PDT 24
Finished Jul 16 07:58:02 PM PDT 24
Peak memory 209212 kb
Host smart-557989a7-19a9-48b5-a5bc-437bafc704ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004046559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3004046559
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.848780917
Short name T691
Test name
Test status
Simulation time 304603910 ps
CPU time 1.95 seconds
Started Jul 16 07:57:54 PM PDT 24
Finished Jul 16 07:58:01 PM PDT 24
Peak memory 209808 kb
Host smart-0e996446-fc84-4e52-a166-a185cd4a18d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848780917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.848780917
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.768947958
Short name T501
Test name
Test status
Simulation time 52216010 ps
CPU time 0.77 seconds
Started Jul 16 07:56:55 PM PDT 24
Finished Jul 16 07:56:58 PM PDT 24
Peak memory 205904 kb
Host smart-8039bbe4-8bb5-4c5b-8f7c-8a95b64b6009
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768947958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.768947958
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.3016624204
Short name T10
Test name
Test status
Simulation time 113695863 ps
CPU time 5.21 seconds
Started Jul 16 07:56:48 PM PDT 24
Finished Jul 16 07:56:57 PM PDT 24
Peak memory 222832 kb
Host smart-45ed5a05-f9cf-4336-af92-b06c6b37c419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016624204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.3016624204
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.115581598
Short name T273
Test name
Test status
Simulation time 241590768 ps
CPU time 2.61 seconds
Started Jul 16 07:56:46 PM PDT 24
Finished Jul 16 07:56:52 PM PDT 24
Peak memory 214308 kb
Host smart-9afa5e16-2cac-412f-82f3-5af1c4b24703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115581598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.115581598
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.4193688778
Short name T108
Test name
Test status
Simulation time 655858708 ps
CPU time 5 seconds
Started Jul 16 07:56:44 PM PDT 24
Finished Jul 16 07:56:51 PM PDT 24
Peak memory 214348 kb
Host smart-71f814c6-7e7f-4e98-9a67-e54651de71a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193688778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.4193688778
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.3823617172
Short name T903
Test name
Test status
Simulation time 61188969 ps
CPU time 2.34 seconds
Started Jul 16 07:56:45 PM PDT 24
Finished Jul 16 07:56:52 PM PDT 24
Peak memory 221612 kb
Host smart-651a2218-b4be-4595-9a24-538b18e20162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823617172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.3823617172
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.293742533
Short name T301
Test name
Test status
Simulation time 54541194 ps
CPU time 2.87 seconds
Started Jul 16 07:56:45 PM PDT 24
Finished Jul 16 07:56:52 PM PDT 24
Peak memory 222384 kb
Host smart-090f0365-fe9d-4d78-beba-fff05553e474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293742533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.293742533
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.3770773945
Short name T328
Test name
Test status
Simulation time 71681072 ps
CPU time 3.31 seconds
Started Jul 16 07:56:46 PM PDT 24
Finished Jul 16 07:56:53 PM PDT 24
Peak memory 209308 kb
Host smart-7da094c5-a3cb-4681-a487-8f1b569cba53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770773945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3770773945
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sideload.3499208569
Short name T370
Test name
Test status
Simulation time 169896334 ps
CPU time 2.77 seconds
Started Jul 16 07:56:46 PM PDT 24
Finished Jul 16 07:56:53 PM PDT 24
Peak memory 206904 kb
Host smart-9ad4cca0-13f1-492a-ae7f-7d2d5329c4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499208569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3499208569
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.332756764
Short name T543
Test name
Test status
Simulation time 24095325 ps
CPU time 1.83 seconds
Started Jul 16 07:56:46 PM PDT 24
Finished Jul 16 07:56:51 PM PDT 24
Peak memory 206876 kb
Host smart-2cde3d86-5a0f-4dca-821f-f732c54bcbfa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332756764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.332756764
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.2248009903
Short name T571
Test name
Test status
Simulation time 1636210556 ps
CPU time 10.85 seconds
Started Jul 16 07:56:45 PM PDT 24
Finished Jul 16 07:56:59 PM PDT 24
Peak memory 208172 kb
Host smart-1aaf6696-d34a-4e32-a030-d1b2ac873c2e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248009903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.2248009903
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.1535938508
Short name T2
Test name
Test status
Simulation time 45848266 ps
CPU time 1.83 seconds
Started Jul 16 07:56:47 PM PDT 24
Finished Jul 16 07:56:54 PM PDT 24
Peak memory 207748 kb
Host smart-34ca2f55-7096-4547-98ed-64f0b2cdd03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535938508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.1535938508
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.3057981562
Short name T906
Test name
Test status
Simulation time 1313377089 ps
CPU time 3.21 seconds
Started Jul 16 07:56:45 PM PDT 24
Finished Jul 16 07:56:52 PM PDT 24
Peak memory 208480 kb
Host smart-ee39da7f-6872-4bf5-b1d0-462911c33d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057981562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.3057981562
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.1308129715
Short name T206
Test name
Test status
Simulation time 4004620383 ps
CPU time 69.08 seconds
Started Jul 16 07:56:47 PM PDT 24
Finished Jul 16 07:58:01 PM PDT 24
Peak memory 216904 kb
Host smart-51ccc156-64a0-49df-8fde-49de18dd7afc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308129715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.1308129715
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.1918517346
Short name T304
Test name
Test status
Simulation time 1847543820 ps
CPU time 5.31 seconds
Started Jul 16 07:56:46 PM PDT 24
Finished Jul 16 07:56:56 PM PDT 24
Peak memory 207916 kb
Host smart-f0af62aa-0b73-4175-b601-10d157291911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918517346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.1918517346
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.1951808848
Short name T397
Test name
Test status
Simulation time 101766230 ps
CPU time 3.69 seconds
Started Jul 16 07:56:47 PM PDT 24
Finished Jul 16 07:56:55 PM PDT 24
Peak memory 209908 kb
Host smart-5d6d20fa-c419-42d1-badc-8c8f23859fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951808848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.1951808848
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.2493670904
Short name T16
Test name
Test status
Simulation time 32137352 ps
CPU time 0.96 seconds
Started Jul 16 07:57:40 PM PDT 24
Finished Jul 16 07:57:43 PM PDT 24
Peak memory 206144 kb
Host smart-51610c7b-efba-4bda-9fd5-db927c031160
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493670904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.2493670904
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.3457914247
Short name T267
Test name
Test status
Simulation time 46141549 ps
CPU time 3.46 seconds
Started Jul 16 07:57:54 PM PDT 24
Finished Jul 16 07:58:02 PM PDT 24
Peak memory 214316 kb
Host smart-799c6345-9cce-49cc-bf76-638a2e38296e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3457914247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.3457914247
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.3720407951
Short name T75
Test name
Test status
Simulation time 174087849 ps
CPU time 1.98 seconds
Started Jul 16 07:57:52 PM PDT 24
Finished Jul 16 07:57:59 PM PDT 24
Peak memory 208692 kb
Host smart-952da102-2d82-4568-b037-433939b64691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720407951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3720407951
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.943738785
Short name T664
Test name
Test status
Simulation time 684647681 ps
CPU time 5.99 seconds
Started Jul 16 07:57:52 PM PDT 24
Finished Jul 16 07:58:03 PM PDT 24
Peak memory 219468 kb
Host smart-2460412a-6af0-4837-88f3-28c1027db786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943738785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.943738785
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.57040073
Short name T696
Test name
Test status
Simulation time 38299149 ps
CPU time 2.08 seconds
Started Jul 16 07:57:41 PM PDT 24
Finished Jul 16 07:57:48 PM PDT 24
Peak memory 214304 kb
Host smart-5862b1ed-1fe7-492f-8878-bb7138a9104b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57040073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.57040073
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.3156383192
Short name T737
Test name
Test status
Simulation time 184111552 ps
CPU time 4.16 seconds
Started Jul 16 07:57:36 PM PDT 24
Finished Jul 16 07:57:41 PM PDT 24
Peak memory 214348 kb
Host smart-295a3a75-2c4f-4686-baf2-60d7ea53ba7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156383192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3156383192
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.1393430441
Short name T305
Test name
Test status
Simulation time 2266928757 ps
CPU time 7.5 seconds
Started Jul 16 07:57:50 PM PDT 24
Finished Jul 16 07:58:03 PM PDT 24
Peak memory 208904 kb
Host smart-9c117fbb-7d39-47ca-ad4f-007508600ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393430441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1393430441
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.278353024
Short name T784
Test name
Test status
Simulation time 174621555 ps
CPU time 6.95 seconds
Started Jul 16 07:57:51 PM PDT 24
Finished Jul 16 07:58:04 PM PDT 24
Peak memory 208988 kb
Host smart-3716d48d-53ee-4c15-a930-0cbc1db9f2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278353024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.278353024
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.4185795456
Short name T587
Test name
Test status
Simulation time 275086607 ps
CPU time 3.81 seconds
Started Jul 16 07:57:51 PM PDT 24
Finished Jul 16 07:58:01 PM PDT 24
Peak memory 206888 kb
Host smart-2f46e4a4-8ab5-44c7-8045-930266fe0fc7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185795456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.4185795456
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.740336806
Short name T873
Test name
Test status
Simulation time 728431916 ps
CPU time 6.16 seconds
Started Jul 16 07:57:49 PM PDT 24
Finished Jul 16 07:58:02 PM PDT 24
Peak memory 208820 kb
Host smart-e6307bfd-9029-4b83-9a17-efb572cba5c0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740336806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.740336806
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.3385695467
Short name T711
Test name
Test status
Simulation time 758089243 ps
CPU time 4.58 seconds
Started Jul 16 07:57:49 PM PDT 24
Finished Jul 16 07:58:00 PM PDT 24
Peak memory 206764 kb
Host smart-40709daa-3b5b-4c11-a0ed-c61fce9fb88a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385695467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.3385695467
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.3579297368
Short name T872
Test name
Test status
Simulation time 140063990 ps
CPU time 2.75 seconds
Started Jul 16 07:57:40 PM PDT 24
Finished Jul 16 07:57:46 PM PDT 24
Peak memory 218348 kb
Host smart-9b05d2eb-ede7-47e8-9e53-737827f3f0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579297368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3579297368
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.897189827
Short name T845
Test name
Test status
Simulation time 67299176 ps
CPU time 3.15 seconds
Started Jul 16 07:57:50 PM PDT 24
Finished Jul 16 07:57:59 PM PDT 24
Peak memory 208596 kb
Host smart-577e1f2d-a5af-4e23-8d0d-a736903b14db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897189827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.897189827
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.2557481127
Short name T682
Test name
Test status
Simulation time 434084582 ps
CPU time 3.95 seconds
Started Jul 16 07:57:53 PM PDT 24
Finished Jul 16 07:58:03 PM PDT 24
Peak memory 208064 kb
Host smart-482036b4-7ecd-43c9-8c09-808efd6594b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557481127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.2557481127
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.2941526337
Short name T511
Test name
Test status
Simulation time 127176770 ps
CPU time 4.9 seconds
Started Jul 16 07:57:41 PM PDT 24
Finished Jul 16 07:57:50 PM PDT 24
Peak memory 211028 kb
Host smart-1435e8e7-5cbe-4a1a-8eed-31ab5194a9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941526337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.2941526337
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.409787698
Short name T570
Test name
Test status
Simulation time 12869697 ps
CPU time 0.79 seconds
Started Jul 16 07:57:54 PM PDT 24
Finished Jul 16 07:58:00 PM PDT 24
Peak memory 205980 kb
Host smart-8f923f4b-abfd-4df2-991f-df3f957a5929
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409787698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.409787698
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.601567805
Short name T414
Test name
Test status
Simulation time 113719636 ps
CPU time 3.48 seconds
Started Jul 16 07:57:46 PM PDT 24
Finished Jul 16 07:57:54 PM PDT 24
Peak memory 214236 kb
Host smart-4a3a4f7c-c1a7-4ba4-874b-dbe52210da38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=601567805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.601567805
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.23904464
Short name T37
Test name
Test status
Simulation time 64170548 ps
CPU time 2.09 seconds
Started Jul 16 07:57:57 PM PDT 24
Finished Jul 16 07:58:04 PM PDT 24
Peak memory 222848 kb
Host smart-2b0de7f6-912e-4252-aa25-fedd53ea3233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23904464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.23904464
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.4118813415
Short name T686
Test name
Test status
Simulation time 81861018 ps
CPU time 1.7 seconds
Started Jul 16 07:57:45 PM PDT 24
Finished Jul 16 07:57:51 PM PDT 24
Peak memory 207080 kb
Host smart-46eb4589-ca4f-43db-a6cf-77a74848c5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118813415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.4118813415
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2465119811
Short name T276
Test name
Test status
Simulation time 1034507930 ps
CPU time 3.43 seconds
Started Jul 16 07:57:55 PM PDT 24
Finished Jul 16 07:58:03 PM PDT 24
Peak memory 214344 kb
Host smart-8a9ae5a0-f034-4a13-b64a-975634d2f4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465119811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2465119811
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.347782952
Short name T530
Test name
Test status
Simulation time 362139806 ps
CPU time 2.38 seconds
Started Jul 16 07:57:45 PM PDT 24
Finished Jul 16 07:57:52 PM PDT 24
Peak memory 209480 kb
Host smart-6c912dab-6695-46d6-99dd-1cb17653fe17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347782952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.347782952
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.2631666486
Short name T760
Test name
Test status
Simulation time 248107902 ps
CPU time 2.91 seconds
Started Jul 16 07:57:46 PM PDT 24
Finished Jul 16 07:57:55 PM PDT 24
Peak memory 207792 kb
Host smart-d195760a-8bcb-4068-872f-bb52382e9c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631666486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.2631666486
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.897181239
Short name T443
Test name
Test status
Simulation time 57449621 ps
CPU time 1.68 seconds
Started Jul 16 07:57:40 PM PDT 24
Finished Jul 16 07:57:44 PM PDT 24
Peak memory 206744 kb
Host smart-9e874890-d5d9-4fdd-83dc-49f2d7d0f9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897181239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.897181239
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.2923455426
Short name T487
Test name
Test status
Simulation time 451212384 ps
CPU time 11.38 seconds
Started Jul 16 07:57:42 PM PDT 24
Finished Jul 16 07:57:57 PM PDT 24
Peak memory 208108 kb
Host smart-53a3c088-4b4e-48e4-8191-48b4a2492df5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923455426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.2923455426
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.3062348268
Short name T565
Test name
Test status
Simulation time 348133780 ps
CPU time 5.22 seconds
Started Jul 16 07:57:41 PM PDT 24
Finished Jul 16 07:57:50 PM PDT 24
Peak memory 208284 kb
Host smart-7817f7b9-bc9d-49b3-b176-58573640c01a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062348268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.3062348268
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.2002637524
Short name T904
Test name
Test status
Simulation time 173599141 ps
CPU time 4.3 seconds
Started Jul 16 07:57:41 PM PDT 24
Finished Jul 16 07:57:49 PM PDT 24
Peak memory 207068 kb
Host smart-2ca2f938-47ca-4565-9c9c-efd243fcf8ac
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002637524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.2002637524
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.1555242846
Short name T359
Test name
Test status
Simulation time 324668759 ps
CPU time 3.9 seconds
Started Jul 16 07:57:54 PM PDT 24
Finished Jul 16 07:58:03 PM PDT 24
Peak memory 218460 kb
Host smart-a38566f7-7297-418d-8339-72b5744d96ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555242846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.1555242846
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.3607438896
Short name T5
Test name
Test status
Simulation time 47978069 ps
CPU time 2.51 seconds
Started Jul 16 07:57:47 PM PDT 24
Finished Jul 16 07:57:55 PM PDT 24
Peak memory 208840 kb
Host smart-dd8b513c-ab17-4273-9bd6-20f95db46d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607438896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3607438896
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.1181756506
Short name T344
Test name
Test status
Simulation time 195967482 ps
CPU time 9.55 seconds
Started Jul 16 07:58:05 PM PDT 24
Finished Jul 16 07:58:22 PM PDT 24
Peak memory 216648 kb
Host smart-ff2c03c7-1b72-499b-92dd-2cc8a082208d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181756506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.1181756506
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.3867336437
Short name T418
Test name
Test status
Simulation time 206265312 ps
CPU time 6.26 seconds
Started Jul 16 07:57:54 PM PDT 24
Finished Jul 16 07:58:05 PM PDT 24
Peak memory 209864 kb
Host smart-25a6d873-5d15-4d83-adab-efdfff332f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867336437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.3867336437
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.3466411791
Short name T656
Test name
Test status
Simulation time 185538615 ps
CPU time 1.71 seconds
Started Jul 16 07:57:57 PM PDT 24
Finished Jul 16 07:58:04 PM PDT 24
Peak memory 210044 kb
Host smart-af95c12d-02fe-4f7f-aeb5-e0f3a1ff47c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466411791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.3466411791
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.4238330986
Short name T533
Test name
Test status
Simulation time 52902967 ps
CPU time 0.9 seconds
Started Jul 16 07:58:05 PM PDT 24
Finished Jul 16 07:58:13 PM PDT 24
Peak memory 206104 kb
Host smart-9f5c7b28-9188-42fe-ab14-10429e463156
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238330986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.4238330986
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.2456343855
Short name T419
Test name
Test status
Simulation time 150531760 ps
CPU time 7.59 seconds
Started Jul 16 07:58:01 PM PDT 24
Finished Jul 16 07:58:16 PM PDT 24
Peak memory 214812 kb
Host smart-73540610-4b5f-4519-9bf7-b799d1106b7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2456343855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.2456343855
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.317620036
Short name T680
Test name
Test status
Simulation time 893078936 ps
CPU time 6.44 seconds
Started Jul 16 07:57:59 PM PDT 24
Finished Jul 16 07:58:11 PM PDT 24
Peak memory 218412 kb
Host smart-93ab7bfb-7fb0-4196-ab5f-08e292195600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317620036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.317620036
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.3023186927
Short name T902
Test name
Test status
Simulation time 110925575 ps
CPU time 2.02 seconds
Started Jul 16 07:58:04 PM PDT 24
Finished Jul 16 07:58:13 PM PDT 24
Peak memory 207236 kb
Host smart-fe3bd941-9e07-49e3-81a5-9e155d582b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023186927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.3023186927
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.2521654375
Short name T24
Test name
Test status
Simulation time 4869217960 ps
CPU time 26.21 seconds
Started Jul 16 07:57:59 PM PDT 24
Finished Jul 16 07:58:31 PM PDT 24
Peak memory 214344 kb
Host smart-9fadc598-4d1f-4739-ac23-1d0c217380ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521654375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.2521654375
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.3694263669
Short name T592
Test name
Test status
Simulation time 76858765 ps
CPU time 3.52 seconds
Started Jul 16 07:57:59 PM PDT 24
Finished Jul 16 07:58:08 PM PDT 24
Peak memory 214228 kb
Host smart-56a52ab8-bcc9-421d-b1c1-0f13921d6748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694263669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.3694263669
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.652601844
Short name T808
Test name
Test status
Simulation time 292630637 ps
CPU time 2.5 seconds
Started Jul 16 07:57:54 PM PDT 24
Finished Jul 16 07:58:01 PM PDT 24
Peak memory 214316 kb
Host smart-4d6ed38f-0dbb-4ad4-992b-5e544924ae8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652601844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.652601844
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.79395151
Short name T381
Test name
Test status
Simulation time 118179483 ps
CPU time 2.96 seconds
Started Jul 16 07:57:56 PM PDT 24
Finished Jul 16 07:58:04 PM PDT 24
Peak memory 219068 kb
Host smart-09cb2066-96c4-48be-b694-085a9b01632c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79395151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.79395151
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.1150568900
Short name T733
Test name
Test status
Simulation time 184834081 ps
CPU time 2.72 seconds
Started Jul 16 07:57:57 PM PDT 24
Finished Jul 16 07:58:04 PM PDT 24
Peak memory 206912 kb
Host smart-4df9379e-9aa1-4ee7-ba7c-797d0b387da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150568900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1150568900
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.1369290671
Short name T591
Test name
Test status
Simulation time 384140616 ps
CPU time 12.79 seconds
Started Jul 16 07:58:05 PM PDT 24
Finished Jul 16 07:58:25 PM PDT 24
Peak memory 208248 kb
Host smart-f4f706fb-a3f1-48ef-9b80-ae5c165af33b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369290671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1369290671
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.3431461897
Short name T715
Test name
Test status
Simulation time 56386108 ps
CPU time 3.13 seconds
Started Jul 16 07:58:05 PM PDT 24
Finished Jul 16 07:58:15 PM PDT 24
Peak memory 208780 kb
Host smart-3b766abe-c80e-4ef9-8e7d-c860a90a87bd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431461897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.3431461897
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.2118590294
Short name T89
Test name
Test status
Simulation time 601366472 ps
CPU time 3.18 seconds
Started Jul 16 07:57:52 PM PDT 24
Finished Jul 16 07:58:00 PM PDT 24
Peak memory 209020 kb
Host smart-ea734024-0a0f-4d40-9dcf-74938414e59b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118590294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.2118590294
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.2343086679
Short name T658
Test name
Test status
Simulation time 211658099 ps
CPU time 3.31 seconds
Started Jul 16 07:57:59 PM PDT 24
Finished Jul 16 07:58:08 PM PDT 24
Peak memory 216128 kb
Host smart-1c3f4058-9d69-4ca2-a40e-f1f76a6c106f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343086679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.2343086679
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.1988690216
Short name T410
Test name
Test status
Simulation time 108501198 ps
CPU time 3.15 seconds
Started Jul 16 07:57:56 PM PDT 24
Finished Jul 16 07:58:04 PM PDT 24
Peak memory 208528 kb
Host smart-dd395061-6e66-42a3-96e1-e71d2d0bf537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988690216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.1988690216
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.1224416531
Short name T299
Test name
Test status
Simulation time 324068125 ps
CPU time 8.08 seconds
Started Jul 16 07:58:05 PM PDT 24
Finished Jul 16 07:58:20 PM PDT 24
Peak memory 222428 kb
Host smart-a1d1435f-c543-463e-ab85-58550f1ce605
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224416531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.1224416531
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.610530257
Short name T189
Test name
Test status
Simulation time 140323951 ps
CPU time 3.89 seconds
Started Jul 16 07:57:56 PM PDT 24
Finished Jul 16 07:58:05 PM PDT 24
Peak memory 207772 kb
Host smart-690ba762-7a9a-4756-adaf-2509cfe79ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610530257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.610530257
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.3325548365
Short name T61
Test name
Test status
Simulation time 70592011 ps
CPU time 2.62 seconds
Started Jul 16 07:58:06 PM PDT 24
Finished Jul 16 07:58:16 PM PDT 24
Peak memory 210000 kb
Host smart-1e7066ce-f3d8-47e0-b0f4-1d9840fc88fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325548365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3325548365
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.700127761
Short name T898
Test name
Test status
Simulation time 44686287 ps
CPU time 0.74 seconds
Started Jul 16 07:58:00 PM PDT 24
Finished Jul 16 07:58:08 PM PDT 24
Peak memory 206048 kb
Host smart-7f6c7614-2c1b-4ecd-9133-06d77b6c8171
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700127761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.700127761
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.293245254
Short name T829
Test name
Test status
Simulation time 241959793 ps
CPU time 6.9 seconds
Started Jul 16 07:57:59 PM PDT 24
Finished Jul 16 07:58:12 PM PDT 24
Peak memory 215432 kb
Host smart-1fb43344-badb-4fb8-baab-d31b023be6e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=293245254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.293245254
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.1190768273
Short name T409
Test name
Test status
Simulation time 30321777 ps
CPU time 1.98 seconds
Started Jul 16 07:57:56 PM PDT 24
Finished Jul 16 07:58:03 PM PDT 24
Peak memory 207632 kb
Host smart-e89e9a1c-c6de-4c34-ab9c-ad5b2f709fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190768273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.1190768273
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.3936116362
Short name T536
Test name
Test status
Simulation time 434829651 ps
CPU time 3.43 seconds
Started Jul 16 07:57:58 PM PDT 24
Finished Jul 16 07:58:07 PM PDT 24
Peak memory 214544 kb
Host smart-e9d30559-9be1-4c45-a91b-c4c92ac1d0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936116362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3936116362
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.1796466413
Short name T346
Test name
Test status
Simulation time 37016353 ps
CPU time 2.14 seconds
Started Jul 16 07:58:02 PM PDT 24
Finished Jul 16 07:58:11 PM PDT 24
Peak memory 214276 kb
Host smart-84bdd947-36c8-446e-90d9-3433d58a8e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796466413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1796466413
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.135424191
Short name T843
Test name
Test status
Simulation time 66773626 ps
CPU time 1.65 seconds
Started Jul 16 07:58:02 PM PDT 24
Finished Jul 16 07:58:11 PM PDT 24
Peak memory 214300 kb
Host smart-670a3c6d-c773-423f-be1f-98c6ca5f954d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135424191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.135424191
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.180388272
Short name T183
Test name
Test status
Simulation time 567166209 ps
CPU time 5.24 seconds
Started Jul 16 07:58:05 PM PDT 24
Finished Jul 16 07:58:18 PM PDT 24
Peak memory 214336 kb
Host smart-61cd2bdc-39ed-4d7f-a59e-1f9f21d59054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180388272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.180388272
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.2818414801
Short name T688
Test name
Test status
Simulation time 133656242 ps
CPU time 2.44 seconds
Started Jul 16 07:58:05 PM PDT 24
Finished Jul 16 07:58:14 PM PDT 24
Peak memory 206912 kb
Host smart-b13db417-5b6f-4699-bfae-694dfe30afc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818414801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.2818414801
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.456053698
Short name T522
Test name
Test status
Simulation time 627310368 ps
CPU time 5.49 seconds
Started Jul 16 07:57:55 PM PDT 24
Finished Jul 16 07:58:05 PM PDT 24
Peak memory 206920 kb
Host smart-76f96df4-1cf6-49dc-b433-e49bde909827
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456053698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.456053698
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.1007027853
Short name T677
Test name
Test status
Simulation time 133715272 ps
CPU time 2.68 seconds
Started Jul 16 07:57:53 PM PDT 24
Finished Jul 16 07:58:01 PM PDT 24
Peak memory 208784 kb
Host smart-f4d32ced-9678-41a8-b96d-505a864c36ce
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007027853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.1007027853
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.570200430
Short name T383
Test name
Test status
Simulation time 291894234 ps
CPU time 3.54 seconds
Started Jul 16 07:58:02 PM PDT 24
Finished Jul 16 07:58:12 PM PDT 24
Peak memory 208632 kb
Host smart-723c600b-82f2-4ba1-93ae-afb7eb74c958
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570200430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.570200430
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.2268023951
Short name T336
Test name
Test status
Simulation time 156210800 ps
CPU time 4.28 seconds
Started Jul 16 07:57:57 PM PDT 24
Finished Jul 16 07:58:05 PM PDT 24
Peak memory 218412 kb
Host smart-c7f21685-710e-4e60-a586-91e88f0627ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268023951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2268023951
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.450891874
Short name T460
Test name
Test status
Simulation time 50288957 ps
CPU time 2.55 seconds
Started Jul 16 07:57:57 PM PDT 24
Finished Jul 16 07:58:03 PM PDT 24
Peak memory 206740 kb
Host smart-b9d5c47f-5750-4ed7-aaf3-576a66bf8891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450891874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.450891874
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.2006911814
Short name T762
Test name
Test status
Simulation time 575275623 ps
CPU time 17.16 seconds
Started Jul 16 07:58:02 PM PDT 24
Finished Jul 16 07:58:26 PM PDT 24
Peak memory 215144 kb
Host smart-bbc311ef-24ab-44c8-9081-1354c3156c7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006911814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.2006911814
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.3112626016
Short name T124
Test name
Test status
Simulation time 3779271872 ps
CPU time 13 seconds
Started Jul 16 07:57:59 PM PDT 24
Finished Jul 16 07:58:19 PM PDT 24
Peak memory 220636 kb
Host smart-51b93575-e82f-4ddc-9c0d-a75fd7af816a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112626016 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.3112626016
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.4141516502
Short name T355
Test name
Test status
Simulation time 100418197 ps
CPU time 4.83 seconds
Started Jul 16 07:57:57 PM PDT 24
Finished Jul 16 07:58:06 PM PDT 24
Peak memory 209536 kb
Host smart-e468a3b3-5b53-4527-994b-f3bff53e02b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141516502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.4141516502
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.2769752386
Short name T171
Test name
Test status
Simulation time 352194648 ps
CPU time 3.03 seconds
Started Jul 16 07:58:01 PM PDT 24
Finished Jul 16 07:58:12 PM PDT 24
Peak memory 209912 kb
Host smart-759cde15-6387-42b0-bc66-49fbff7a6d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769752386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.2769752386
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.2351329285
Short name T589
Test name
Test status
Simulation time 10451640 ps
CPU time 0.86 seconds
Started Jul 16 07:58:00 PM PDT 24
Finished Jul 16 07:58:08 PM PDT 24
Peak memory 205920 kb
Host smart-69220b1d-821c-4fec-b456-d10d230704c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351329285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.2351329285
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.2858067061
Short name T20
Test name
Test status
Simulation time 88777755 ps
CPU time 1.74 seconds
Started Jul 16 07:58:02 PM PDT 24
Finished Jul 16 07:58:11 PM PDT 24
Peak memory 216740 kb
Host smart-71b29883-5cba-4a21-9ad0-eba7dc5aeff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858067061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.2858067061
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.1161071580
Short name T516
Test name
Test status
Simulation time 247030499 ps
CPU time 2.32 seconds
Started Jul 16 07:58:04 PM PDT 24
Finished Jul 16 07:58:13 PM PDT 24
Peak memory 209528 kb
Host smart-a2a938bb-c43b-4b5f-9273-71fa84ee8414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161071580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.1161071580
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.3582963834
Short name T374
Test name
Test status
Simulation time 355231236 ps
CPU time 3.62 seconds
Started Jul 16 07:58:03 PM PDT 24
Finished Jul 16 07:58:14 PM PDT 24
Peak memory 214352 kb
Host smart-4cac1d6e-3ada-46e0-a5ba-ea523051fa23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582963834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.3582963834
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.1722833293
Short name T297
Test name
Test status
Simulation time 106580876 ps
CPU time 1.5 seconds
Started Jul 16 07:58:02 PM PDT 24
Finished Jul 16 07:58:10 PM PDT 24
Peak memory 214264 kb
Host smart-d1a92df5-52b7-450e-bab6-2146027e6eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722833293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.1722833293
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.1357370634
Short name T182
Test name
Test status
Simulation time 144154696 ps
CPU time 3.07 seconds
Started Jul 16 07:58:04 PM PDT 24
Finished Jul 16 07:58:15 PM PDT 24
Peak memory 214192 kb
Host smart-e066dbe7-18ae-4e27-98a3-1825e2ebee25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357370634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.1357370634
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.3056396161
Short name T821
Test name
Test status
Simulation time 3518388810 ps
CPU time 23.36 seconds
Started Jul 16 07:57:59 PM PDT 24
Finished Jul 16 07:58:28 PM PDT 24
Peak memory 208416 kb
Host smart-c8078f21-dee3-43fd-9aeb-d34be05cb82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056396161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.3056396161
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.155829188
Short name T547
Test name
Test status
Simulation time 287648424 ps
CPU time 4.53 seconds
Started Jul 16 07:58:08 PM PDT 24
Finished Jul 16 07:58:18 PM PDT 24
Peak memory 206904 kb
Host smart-104fce02-c6a6-4257-8848-917ef0a1ada0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155829188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.155829188
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.38554973
Short name T744
Test name
Test status
Simulation time 324460277 ps
CPU time 6.47 seconds
Started Jul 16 07:58:06 PM PDT 24
Finished Jul 16 07:58:19 PM PDT 24
Peak memory 208040 kb
Host smart-0545636f-e909-43fe-8d94-15504d49f571
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38554973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.38554973
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.847960442
Short name T494
Test name
Test status
Simulation time 348618898 ps
CPU time 6.96 seconds
Started Jul 16 07:58:06 PM PDT 24
Finished Jul 16 07:58:20 PM PDT 24
Peak memory 209040 kb
Host smart-c255d37f-7d36-4171-aef5-21512219dcb6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847960442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.847960442
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.2241644923
Short name T266
Test name
Test status
Simulation time 1217756318 ps
CPU time 3.82 seconds
Started Jul 16 07:58:05 PM PDT 24
Finished Jul 16 07:58:16 PM PDT 24
Peak memory 208880 kb
Host smart-ec6237f3-2c98-40c2-b353-509d788cdfe4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241644923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.2241644923
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.409342168
Short name T704
Test name
Test status
Simulation time 43349113 ps
CPU time 2.48 seconds
Started Jul 16 07:58:01 PM PDT 24
Finished Jul 16 07:58:11 PM PDT 24
Peak memory 208656 kb
Host smart-5870ccd4-2446-46ab-ba96-df985d85d2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409342168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.409342168
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.3282545898
Short name T894
Test name
Test status
Simulation time 158506526 ps
CPU time 2.46 seconds
Started Jul 16 07:57:58 PM PDT 24
Finished Jul 16 07:58:06 PM PDT 24
Peak memory 208552 kb
Host smart-ae553bc0-55c1-4a31-aab2-01ac92a657d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282545898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.3282545898
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.113008773
Short name T176
Test name
Test status
Simulation time 10697221328 ps
CPU time 23.58 seconds
Started Jul 16 07:58:00 PM PDT 24
Finished Jul 16 07:58:30 PM PDT 24
Peak memory 223496 kb
Host smart-8242b230-7f02-48fe-8138-49e5a383120a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113008773 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.113008773
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.613802011
Short name T369
Test name
Test status
Simulation time 74879270 ps
CPU time 3.39 seconds
Started Jul 16 07:58:00 PM PDT 24
Finished Jul 16 07:58:10 PM PDT 24
Peak memory 207652 kb
Host smart-e22b4b7b-5834-4acc-ac93-b555ee276736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613802011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.613802011
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.3198824845
Short name T127
Test name
Test status
Simulation time 167413980 ps
CPU time 2.17 seconds
Started Jul 16 07:58:04 PM PDT 24
Finished Jul 16 07:58:13 PM PDT 24
Peak memory 210364 kb
Host smart-d156054e-168e-4ee5-9401-f31b8c319a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198824845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3198824845
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.3844186702
Short name T811
Test name
Test status
Simulation time 18179618 ps
CPU time 0.97 seconds
Started Jul 16 07:58:03 PM PDT 24
Finished Jul 16 07:58:12 PM PDT 24
Peak memory 206128 kb
Host smart-2b7cb5ac-9a65-4bf7-9a61-3dad072bfd01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844186702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.3844186702
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.3493974689
Short name T416
Test name
Test status
Simulation time 107989668 ps
CPU time 3.89 seconds
Started Jul 16 07:58:01 PM PDT 24
Finished Jul 16 07:58:12 PM PDT 24
Peak memory 215368 kb
Host smart-732102bc-a5af-45b6-8006-89abb71f7220
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3493974689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.3493974689
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.2912143118
Short name T838
Test name
Test status
Simulation time 41826851 ps
CPU time 2.18 seconds
Started Jul 16 07:58:04 PM PDT 24
Finished Jul 16 07:58:14 PM PDT 24
Peak memory 214164 kb
Host smart-d16eefb7-b05d-4972-a56d-6a470a16a277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912143118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.2912143118
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.752594200
Short name T546
Test name
Test status
Simulation time 162643525 ps
CPU time 4.34 seconds
Started Jul 16 07:58:08 PM PDT 24
Finished Jul 16 07:58:18 PM PDT 24
Peak memory 208388 kb
Host smart-d1497f0a-2fc6-4de5-a02d-7462107d24fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752594200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.752594200
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.693188304
Short name T465
Test name
Test status
Simulation time 96905596 ps
CPU time 4.16 seconds
Started Jul 16 07:58:08 PM PDT 24
Finished Jul 16 07:58:19 PM PDT 24
Peak memory 214360 kb
Host smart-7b102d0b-cad1-47b3-b1fa-d966a37c4f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693188304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.693188304
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.3935769925
Short name T54
Test name
Test status
Simulation time 176440823 ps
CPU time 6.13 seconds
Started Jul 16 07:58:01 PM PDT 24
Finished Jul 16 07:58:15 PM PDT 24
Peak memory 214324 kb
Host smart-b0333796-6f3d-4980-850f-8e710b5f11cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935769925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.3935769925
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.2349157773
Short name T740
Test name
Test status
Simulation time 129593721 ps
CPU time 5.7 seconds
Started Jul 16 07:57:58 PM PDT 24
Finished Jul 16 07:58:08 PM PDT 24
Peak memory 222484 kb
Host smart-72f427b9-0915-40c9-8843-0bc104160fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349157773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.2349157773
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.2546541183
Short name T181
Test name
Test status
Simulation time 46414057 ps
CPU time 3.25 seconds
Started Jul 16 07:57:59 PM PDT 24
Finished Jul 16 07:58:08 PM PDT 24
Peak memory 207984 kb
Host smart-89eb3aa1-4788-4640-9824-36867138b6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546541183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.2546541183
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.2244539286
Short name T756
Test name
Test status
Simulation time 116102620 ps
CPU time 3.79 seconds
Started Jul 16 07:58:00 PM PDT 24
Finished Jul 16 07:58:10 PM PDT 24
Peak memory 206812 kb
Host smart-5cb29826-707e-4efe-b799-4fdcd6796a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244539286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.2244539286
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.3838885852
Short name T512
Test name
Test status
Simulation time 1980105732 ps
CPU time 11.64 seconds
Started Jul 16 07:58:00 PM PDT 24
Finished Jul 16 07:58:19 PM PDT 24
Peak memory 208164 kb
Host smart-33397f35-9d62-47be-84ef-09cdd0188596
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838885852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3838885852
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2853238181
Short name T474
Test name
Test status
Simulation time 148716899 ps
CPU time 3.28 seconds
Started Jul 16 07:57:59 PM PDT 24
Finished Jul 16 07:58:08 PM PDT 24
Peak memory 208472 kb
Host smart-95376b87-0415-478d-9afd-8e063a3f35a5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853238181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2853238181
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1794955519
Short name T861
Test name
Test status
Simulation time 172967047 ps
CPU time 5.29 seconds
Started Jul 16 07:58:01 PM PDT 24
Finished Jul 16 07:58:13 PM PDT 24
Peak memory 208940 kb
Host smart-12874b45-cec7-4384-8585-12e821af7a64
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794955519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1794955519
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.1646089078
Short name T457
Test name
Test status
Simulation time 5582100660 ps
CPU time 18.93 seconds
Started Jul 16 07:58:03 PM PDT 24
Finished Jul 16 07:58:29 PM PDT 24
Peak memory 208668 kb
Host smart-c3560d6a-6196-4424-b36f-d9afce37e90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646089078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.1646089078
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.2682426574
Short name T524
Test name
Test status
Simulation time 489244623 ps
CPU time 4.87 seconds
Started Jul 16 07:57:59 PM PDT 24
Finished Jul 16 07:58:10 PM PDT 24
Peak memory 207032 kb
Host smart-245fa3a6-1571-4f88-9708-ecc8c0c03c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682426574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.2682426574
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.1390746369
Short name T870
Test name
Test status
Simulation time 3020603775 ps
CPU time 30.76 seconds
Started Jul 16 07:58:01 PM PDT 24
Finished Jul 16 07:58:39 PM PDT 24
Peak memory 220324 kb
Host smart-964047e5-a129-4c1c-a365-f0ee96de9f80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390746369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.1390746369
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.1126877936
Short name T128
Test name
Test status
Simulation time 2884761228 ps
CPU time 19.58 seconds
Started Jul 16 07:58:01 PM PDT 24
Finished Jul 16 07:58:28 PM PDT 24
Peak memory 222780 kb
Host smart-1fee85dc-c857-4ff4-893f-0ebae61c0235
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126877936 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.1126877936
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.3172323560
Short name T469
Test name
Test status
Simulation time 464325133 ps
CPU time 4.45 seconds
Started Jul 16 07:58:08 PM PDT 24
Finished Jul 16 07:58:18 PM PDT 24
Peak memory 207588 kb
Host smart-eae674b0-0c65-4d01-84bf-f9a2f9feb3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172323560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.3172323560
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.1858647184
Short name T400
Test name
Test status
Simulation time 51059621 ps
CPU time 1.73 seconds
Started Jul 16 07:58:00 PM PDT 24
Finished Jul 16 07:58:08 PM PDT 24
Peak memory 210324 kb
Host smart-9ea541f4-5dcf-4276-905c-49939030c99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858647184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.1858647184
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.4134164536
Short name T568
Test name
Test status
Simulation time 16707649 ps
CPU time 1.02 seconds
Started Jul 16 07:57:56 PM PDT 24
Finished Jul 16 07:58:01 PM PDT 24
Peak memory 206024 kb
Host smart-dd99d7d5-500a-4f36-a7a7-f72eefdcad4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134164536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.4134164536
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.1639760815
Short name T46
Test name
Test status
Simulation time 292807392 ps
CPU time 2.41 seconds
Started Jul 16 07:58:09 PM PDT 24
Finished Jul 16 07:58:17 PM PDT 24
Peak memory 218804 kb
Host smart-ac32662a-a82b-4ee0-8904-f17498274d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639760815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.1639760815
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.1019328580
Short name T761
Test name
Test status
Simulation time 194804000 ps
CPU time 1.62 seconds
Started Jul 16 07:58:09 PM PDT 24
Finished Jul 16 07:58:17 PM PDT 24
Peak memory 209216 kb
Host smart-c52f08af-a085-42bd-8725-09df39485930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019328580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.1019328580
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.283493142
Short name T25
Test name
Test status
Simulation time 202306565 ps
CPU time 5.13 seconds
Started Jul 16 07:58:09 PM PDT 24
Finished Jul 16 07:58:20 PM PDT 24
Peak memory 214292 kb
Host smart-7f697419-aeea-47b5-9993-9e06e557d46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283493142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.283493142
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.3204539907
Short name T60
Test name
Test status
Simulation time 110610934 ps
CPU time 3.16 seconds
Started Jul 16 07:57:56 PM PDT 24
Finished Jul 16 07:58:03 PM PDT 24
Peak memory 220708 kb
Host smart-459f9d1f-f963-4801-b18d-52e21bc25234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204539907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.3204539907
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_random.1110285058
Short name T471
Test name
Test status
Simulation time 2204727720 ps
CPU time 30.42 seconds
Started Jul 16 07:58:01 PM PDT 24
Finished Jul 16 07:58:37 PM PDT 24
Peak memory 214140 kb
Host smart-a194253c-00a3-4920-adb7-a7eee328bd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110285058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.1110285058
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.2405038502
Short name T286
Test name
Test status
Simulation time 8918637622 ps
CPU time 43.6 seconds
Started Jul 16 07:58:09 PM PDT 24
Finished Jul 16 07:58:59 PM PDT 24
Peak memory 208672 kb
Host smart-b8ccf047-3925-4dfa-9f8f-4f4a2abebf87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405038502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.2405038502
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2918285036
Short name T292
Test name
Test status
Simulation time 150169703 ps
CPU time 4.49 seconds
Started Jul 16 07:58:06 PM PDT 24
Finished Jul 16 07:58:17 PM PDT 24
Peak memory 208612 kb
Host smart-d7960ec1-b63c-4264-a5ab-56811e154009
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918285036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2918285036
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.57741594
Short name T865
Test name
Test status
Simulation time 76239538 ps
CPU time 3.38 seconds
Started Jul 16 07:58:01 PM PDT 24
Finished Jul 16 07:58:11 PM PDT 24
Peak memory 207036 kb
Host smart-7d135121-018f-4588-a6d4-55cce3a5c48b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57741594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.57741594
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.2516157103
Short name T481
Test name
Test status
Simulation time 81918511 ps
CPU time 1.9 seconds
Started Jul 16 07:58:09 PM PDT 24
Finished Jul 16 07:58:17 PM PDT 24
Peak memory 207008 kb
Host smart-92df2148-bf47-4f09-a77a-04b48a140559
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516157103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.2516157103
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.2464490730
Short name T631
Test name
Test status
Simulation time 286080556 ps
CPU time 2.56 seconds
Started Jul 16 07:58:03 PM PDT 24
Finished Jul 16 07:58:13 PM PDT 24
Peak memory 214280 kb
Host smart-c147815f-c8d8-483c-959d-cb97507186fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464490730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.2464490730
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.1980450373
Short name T407
Test name
Test status
Simulation time 70094607 ps
CPU time 2.47 seconds
Started Jul 16 07:58:09 PM PDT 24
Finished Jul 16 07:58:17 PM PDT 24
Peak memory 208496 kb
Host smart-f29f985e-915a-4eee-a7d0-0c737725b1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980450373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.1980450373
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.1011545520
Short name T509
Test name
Test status
Simulation time 164788153 ps
CPU time 4.65 seconds
Started Jul 16 07:58:02 PM PDT 24
Finished Jul 16 07:58:14 PM PDT 24
Peak memory 220572 kb
Host smart-a2e17ae9-27ff-4f10-81e7-37716350a363
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011545520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.1011545520
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.2378927051
Short name T710
Test name
Test status
Simulation time 1050000972 ps
CPU time 26.07 seconds
Started Jul 16 07:57:59 PM PDT 24
Finished Jul 16 07:58:31 PM PDT 24
Peak memory 214336 kb
Host smart-76a78162-da62-48ad-8576-ac93fec227d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378927051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.2378927051
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2924526816
Short name T217
Test name
Test status
Simulation time 57097370 ps
CPU time 2.19 seconds
Started Jul 16 07:58:03 PM PDT 24
Finished Jul 16 07:58:13 PM PDT 24
Peak memory 209700 kb
Host smart-982ce512-116f-4ba1-a137-b109509616ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924526816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2924526816
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.217464466
Short name T831
Test name
Test status
Simulation time 23939998 ps
CPU time 1.02 seconds
Started Jul 16 07:57:59 PM PDT 24
Finished Jul 16 07:58:07 PM PDT 24
Peak memory 206116 kb
Host smart-1a94d71f-be29-4c15-9b80-f4a41b5c183a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217464466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.217464466
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.741539577
Short name T429
Test name
Test status
Simulation time 2503532309 ps
CPU time 127.65 seconds
Started Jul 16 07:58:00 PM PDT 24
Finished Jul 16 08:00:15 PM PDT 24
Peak memory 214444 kb
Host smart-c67a9127-20f9-4da9-8fe1-670635323ede
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=741539577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.741539577
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.2053986794
Short name T294
Test name
Test status
Simulation time 248062064 ps
CPU time 3.8 seconds
Started Jul 16 07:57:59 PM PDT 24
Finished Jul 16 07:58:09 PM PDT 24
Peak memory 221852 kb
Host smart-3573abf1-0c1b-4408-ae60-93bac20a8dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053986794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.2053986794
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.3191698371
Short name T79
Test name
Test status
Simulation time 253501078 ps
CPU time 3.03 seconds
Started Jul 16 07:58:04 PM PDT 24
Finished Jul 16 07:58:15 PM PDT 24
Peak memory 218308 kb
Host smart-02069279-faa4-4e42-b55a-538a053f88e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191698371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3191698371
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.28927341
Short name T96
Test name
Test status
Simulation time 308993115 ps
CPU time 3.72 seconds
Started Jul 16 07:58:03 PM PDT 24
Finished Jul 16 07:58:14 PM PDT 24
Peak memory 214280 kb
Host smart-58d4e14c-73cd-4f1c-bf53-e31e5e7884e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28927341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.28927341
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.3214103681
Short name T373
Test name
Test status
Simulation time 269275615 ps
CPU time 7.29 seconds
Started Jul 16 07:58:01 PM PDT 24
Finished Jul 16 07:58:14 PM PDT 24
Peak memory 222636 kb
Host smart-fce606d4-52cc-4390-a058-ef67eebe895b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214103681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.3214103681
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.1943384950
Short name T142
Test name
Test status
Simulation time 131330538 ps
CPU time 3.76 seconds
Started Jul 16 07:58:01 PM PDT 24
Finished Jul 16 07:58:11 PM PDT 24
Peak memory 218464 kb
Host smart-b07d1509-441f-4eea-9d2f-c3936d5bc4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943384950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1943384950
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.2117188780
Short name T581
Test name
Test status
Simulation time 129477762 ps
CPU time 4.42 seconds
Started Jul 16 07:58:04 PM PDT 24
Finished Jul 16 07:58:15 PM PDT 24
Peak memory 210040 kb
Host smart-b198048a-f57e-49f7-992f-e0a6a869f45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117188780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.2117188780
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.1758170008
Short name T405
Test name
Test status
Simulation time 54847520 ps
CPU time 2.56 seconds
Started Jul 16 07:58:03 PM PDT 24
Finished Jul 16 07:58:14 PM PDT 24
Peak memory 208432 kb
Host smart-576c8b8e-a0b3-4eef-a16e-7b66a6ba6f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758170008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.1758170008
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.2043627724
Short name T256
Test name
Test status
Simulation time 155177419 ps
CPU time 2.69 seconds
Started Jul 16 07:58:04 PM PDT 24
Finished Jul 16 07:58:14 PM PDT 24
Peak memory 206720 kb
Host smart-53c6e819-3a83-4b8f-9736-8663040a449c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043627724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2043627724
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.3813725754
Short name T800
Test name
Test status
Simulation time 105123941 ps
CPU time 3.48 seconds
Started Jul 16 07:57:59 PM PDT 24
Finished Jul 16 07:58:08 PM PDT 24
Peak memory 208568 kb
Host smart-02104387-2895-4e5c-a5c4-363c3fb27c88
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813725754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.3813725754
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.3975657833
Short name T615
Test name
Test status
Simulation time 181970963 ps
CPU time 4.1 seconds
Started Jul 16 07:58:01 PM PDT 24
Finished Jul 16 07:58:11 PM PDT 24
Peak memory 208408 kb
Host smart-ee66ef1d-da05-4d92-91b7-6a5dc1dfcd7e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975657833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.3975657833
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.2813711782
Short name T635
Test name
Test status
Simulation time 159717968 ps
CPU time 3.17 seconds
Started Jul 16 07:58:02 PM PDT 24
Finished Jul 16 07:58:12 PM PDT 24
Peak memory 208920 kb
Host smart-edcc72dc-67a3-45b7-a96a-99456ac8c1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813711782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.2813711782
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.724772230
Short name T544
Test name
Test status
Simulation time 1390236169 ps
CPU time 4.3 seconds
Started Jul 16 07:57:55 PM PDT 24
Finished Jul 16 07:58:04 PM PDT 24
Peak memory 208552 kb
Host smart-a6d4fb94-8308-4be2-93d8-d4474d1fff01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724772230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.724772230
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.182669398
Short name T139
Test name
Test status
Simulation time 418842055 ps
CPU time 6.17 seconds
Started Jul 16 07:58:00 PM PDT 24
Finished Jul 16 07:58:13 PM PDT 24
Peak memory 208796 kb
Host smart-485ec55f-e87e-4f41-aa4e-a90629af51f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182669398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.182669398
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.1875565987
Short name T767
Test name
Test status
Simulation time 234238076 ps
CPU time 2.11 seconds
Started Jul 16 07:58:00 PM PDT 24
Finished Jul 16 07:58:09 PM PDT 24
Peak memory 210020 kb
Host smart-6b95db04-7569-4c35-b466-967dbdf59e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875565987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.1875565987
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.1673488049
Short name T466
Test name
Test status
Simulation time 76788600 ps
CPU time 0.84 seconds
Started Jul 16 07:58:16 PM PDT 24
Finished Jul 16 07:58:20 PM PDT 24
Peak memory 205980 kb
Host smart-1109a796-f142-4aad-bf42-48511b3a3053
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673488049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.1673488049
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.492483314
Short name T250
Test name
Test status
Simulation time 90655490 ps
CPU time 5.05 seconds
Started Jul 16 07:58:07 PM PDT 24
Finished Jul 16 07:58:19 PM PDT 24
Peak memory 214328 kb
Host smart-658f9438-d8ab-4adf-897e-239163e9c0e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=492483314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.492483314
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.3973889253
Short name T632
Test name
Test status
Simulation time 24580044 ps
CPU time 1.48 seconds
Started Jul 16 07:58:12 PM PDT 24
Finished Jul 16 07:58:19 PM PDT 24
Peak memory 208856 kb
Host smart-074ea87b-08d5-4084-8139-95613dd466ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973889253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.3973889253
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.3246153019
Short name T743
Test name
Test status
Simulation time 76260444 ps
CPU time 2.13 seconds
Started Jul 16 07:58:09 PM PDT 24
Finished Jul 16 07:58:18 PM PDT 24
Peak memory 208928 kb
Host smart-3dc9fee4-2a1e-46c8-b200-ed403aeadc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246153019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.3246153019
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.3162827794
Short name T311
Test name
Test status
Simulation time 456770858 ps
CPU time 4.48 seconds
Started Jul 16 07:58:17 PM PDT 24
Finished Jul 16 07:58:25 PM PDT 24
Peak memory 220588 kb
Host smart-2a3c924d-5458-4c33-97a0-69253a960a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162827794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.3162827794
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.3942153845
Short name T689
Test name
Test status
Simulation time 81444451 ps
CPU time 1.63 seconds
Started Jul 16 07:58:24 PM PDT 24
Finished Jul 16 07:58:28 PM PDT 24
Peak memory 214352 kb
Host smart-65894037-aabb-4e7f-9e6e-1dbd32c005e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942153845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.3942153845
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.3930719158
Short name T552
Test name
Test status
Simulation time 31781016 ps
CPU time 2.36 seconds
Started Jul 16 07:58:08 PM PDT 24
Finished Jul 16 07:58:16 PM PDT 24
Peak memory 214312 kb
Host smart-e296ce85-8ba1-4221-a720-d0ec773c6649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930719158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.3930719158
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.2928830963
Short name T358
Test name
Test status
Simulation time 944225175 ps
CPU time 3.89 seconds
Started Jul 16 07:58:07 PM PDT 24
Finished Jul 16 07:58:18 PM PDT 24
Peak memory 208148 kb
Host smart-a07fd4e6-b6da-4290-915a-d9fbdd79edcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928830963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.2928830963
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.780283254
Short name T690
Test name
Test status
Simulation time 488259068 ps
CPU time 11.97 seconds
Started Jul 16 07:58:02 PM PDT 24
Finished Jul 16 07:58:21 PM PDT 24
Peak memory 208244 kb
Host smart-91e295ca-59d7-40e4-bcb4-9482f9c3c4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780283254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.780283254
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.3530163288
Short name T506
Test name
Test status
Simulation time 328207371 ps
CPU time 3.38 seconds
Started Jul 16 07:58:11 PM PDT 24
Finished Jul 16 07:58:20 PM PDT 24
Peak memory 206800 kb
Host smart-cc319c55-1c2b-44c3-8895-20cdcf990c92
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530163288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3530163288
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.100332023
Short name T817
Test name
Test status
Simulation time 25796349 ps
CPU time 2.03 seconds
Started Jul 16 07:57:59 PM PDT 24
Finished Jul 16 07:58:08 PM PDT 24
Peak memory 208744 kb
Host smart-eaaf82ee-8e1c-42c0-a43a-840740373eee
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100332023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.100332023
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.2491523700
Short name T363
Test name
Test status
Simulation time 1224587707 ps
CPU time 6.4 seconds
Started Jul 16 07:58:07 PM PDT 24
Finished Jul 16 07:58:20 PM PDT 24
Peak memory 208776 kb
Host smart-54fdcf8d-53d5-4880-adb0-e2a0d3c18474
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491523700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.2491523700
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.4265742263
Short name T195
Test name
Test status
Simulation time 214502873 ps
CPU time 2.29 seconds
Started Jul 16 07:58:08 PM PDT 24
Finished Jul 16 07:58:17 PM PDT 24
Peak memory 207572 kb
Host smart-f90a23e5-2f22-470d-aaf9-f51a4bb0791a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265742263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.4265742263
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.1636245287
Short name T554
Test name
Test status
Simulation time 119465303 ps
CPU time 2.66 seconds
Started Jul 16 07:57:59 PM PDT 24
Finished Jul 16 07:58:07 PM PDT 24
Peak memory 208552 kb
Host smart-a96da977-1a92-47ab-aa8e-2413c434a3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636245287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.1636245287
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.1589300407
Short name T508
Test name
Test status
Simulation time 68094485 ps
CPU time 3.24 seconds
Started Jul 16 07:58:17 PM PDT 24
Finished Jul 16 07:58:24 PM PDT 24
Peak memory 208288 kb
Host smart-45551c59-5269-449b-9b6e-a3ee271eca63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589300407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.1589300407
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.1661016
Short name T555
Test name
Test status
Simulation time 1405135807 ps
CPU time 6.69 seconds
Started Jul 16 07:58:18 PM PDT 24
Finished Jul 16 07:58:28 PM PDT 24
Peak memory 208348 kb
Host smart-bcecb887-aeb3-4fea-aae8-a67e2a23c0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1661016
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.3421532350
Short name T900
Test name
Test status
Simulation time 84791450 ps
CPU time 3.13 seconds
Started Jul 16 07:58:12 PM PDT 24
Finished Jul 16 07:58:21 PM PDT 24
Peak memory 210340 kb
Host smart-f6a4fc6d-4867-4592-bd17-7da58a6c4f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421532350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.3421532350
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.1477135080
Short name T742
Test name
Test status
Simulation time 10952160 ps
CPU time 0.73 seconds
Started Jul 16 07:58:09 PM PDT 24
Finished Jul 16 07:58:16 PM PDT 24
Peak memory 205904 kb
Host smart-7ae1b42d-3846-484e-bda8-2a1a4b38a067
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477135080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1477135080
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.2668482302
Short name T830
Test name
Test status
Simulation time 209545424 ps
CPU time 4.16 seconds
Started Jul 16 07:58:13 PM PDT 24
Finished Jul 16 07:58:22 PM PDT 24
Peak memory 209072 kb
Host smart-2d622791-0cee-4b40-b7c0-44f3c09e4757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668482302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.2668482302
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.2760978987
Short name T500
Test name
Test status
Simulation time 128118357 ps
CPU time 2.72 seconds
Started Jul 16 07:58:13 PM PDT 24
Finished Jul 16 07:58:20 PM PDT 24
Peak memory 215016 kb
Host smart-b56dd661-2e0e-4f72-b20f-bbc53bd8c2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760978987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.2760978987
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.721610922
Short name T375
Test name
Test status
Simulation time 58745852 ps
CPU time 2.83 seconds
Started Jul 16 07:58:12 PM PDT 24
Finished Jul 16 07:58:20 PM PDT 24
Peak memory 222324 kb
Host smart-75cd14b6-3876-4efe-8a30-785139facc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721610922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.721610922
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.2777587863
Short name T911
Test name
Test status
Simulation time 34057456 ps
CPU time 2.55 seconds
Started Jul 16 07:58:08 PM PDT 24
Finished Jul 16 07:58:17 PM PDT 24
Peak memory 209136 kb
Host smart-eec40df5-a2a5-4103-b734-5897babac6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777587863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2777587863
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.1575786651
Short name T339
Test name
Test status
Simulation time 338318412 ps
CPU time 5.07 seconds
Started Jul 16 07:58:10 PM PDT 24
Finished Jul 16 07:58:21 PM PDT 24
Peak memory 214296 kb
Host smart-6095493c-32d6-4081-8d20-5f7e02c78eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575786651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1575786651
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.1283986630
Short name T655
Test name
Test status
Simulation time 34209046 ps
CPU time 1.94 seconds
Started Jul 16 07:58:10 PM PDT 24
Finished Jul 16 07:58:18 PM PDT 24
Peak memory 208056 kb
Host smart-9d1701b8-5d21-453d-b135-b019da4be936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283986630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.1283986630
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.42900593
Short name T598
Test name
Test status
Simulation time 71644687 ps
CPU time 1.77 seconds
Started Jul 16 07:58:08 PM PDT 24
Finished Jul 16 07:58:17 PM PDT 24
Peak memory 206860 kb
Host smart-4f84e71a-ef51-4e80-b0fe-49c6dbe38165
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42900593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.42900593
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.2527475637
Short name T452
Test name
Test status
Simulation time 940566648 ps
CPU time 5.74 seconds
Started Jul 16 07:58:14 PM PDT 24
Finished Jul 16 07:58:24 PM PDT 24
Peak memory 207076 kb
Host smart-40765c6e-c47b-4d9a-97fe-7e710e3fe6ae
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527475637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.2527475637
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.2319819083
Short name T755
Test name
Test status
Simulation time 182877934 ps
CPU time 4.1 seconds
Started Jul 16 07:58:10 PM PDT 24
Finished Jul 16 07:58:20 PM PDT 24
Peak memory 208728 kb
Host smart-3fa56e90-2d31-46bc-a819-eaf64df83363
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319819083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.2319819083
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.4185847809
Short name T254
Test name
Test status
Simulation time 88125062 ps
CPU time 3.24 seconds
Started Jul 16 07:58:10 PM PDT 24
Finished Jul 16 07:58:19 PM PDT 24
Peak memory 218468 kb
Host smart-d9367237-e9c1-4572-8d17-250fe2f128dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185847809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.4185847809
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.1505755680
Short name T752
Test name
Test status
Simulation time 304940521 ps
CPU time 4.86 seconds
Started Jul 16 07:58:08 PM PDT 24
Finished Jul 16 07:58:20 PM PDT 24
Peak memory 208472 kb
Host smart-4900acd8-e478-4701-8e9e-851fde6b6d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505755680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.1505755680
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.4051939775
Short name T758
Test name
Test status
Simulation time 14632184734 ps
CPU time 94.53 seconds
Started Jul 16 07:58:16 PM PDT 24
Finished Jul 16 07:59:54 PM PDT 24
Peak memory 218240 kb
Host smart-712b14a4-7779-4c12-b6b8-293572902adf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051939775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.4051939775
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.3265080909
Short name T85
Test name
Test status
Simulation time 230079455 ps
CPU time 14.14 seconds
Started Jul 16 07:58:09 PM PDT 24
Finished Jul 16 07:58:29 PM PDT 24
Peak memory 222532 kb
Host smart-a57089cb-2458-4c05-a315-e46c4e3701c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265080909 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.3265080909
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.1220547741
Short name T579
Test name
Test status
Simulation time 203628859 ps
CPU time 7.49 seconds
Started Jul 16 07:58:16 PM PDT 24
Finished Jul 16 07:58:28 PM PDT 24
Peak memory 208764 kb
Host smart-feb9217c-2dc7-4121-ad9a-a8f05df16c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220547741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.1220547741
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.2938982028
Short name T398
Test name
Test status
Simulation time 3072464244 ps
CPU time 16.69 seconds
Started Jul 16 07:58:08 PM PDT 24
Finished Jul 16 07:58:32 PM PDT 24
Peak memory 211388 kb
Host smart-4748131a-a625-4858-a6fd-7eca042127ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938982028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.2938982028
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.4037908390
Short name T436
Test name
Test status
Simulation time 14512334 ps
CPU time 0.75 seconds
Started Jul 16 07:56:44 PM PDT 24
Finished Jul 16 07:56:47 PM PDT 24
Peak memory 206060 kb
Host smart-aeeb927c-7a73-4d56-b8d9-be07a0c66ca0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037908390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.4037908390
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.786273599
Short name T293
Test name
Test status
Simulation time 36427925 ps
CPU time 2.84 seconds
Started Jul 16 07:56:55 PM PDT 24
Finished Jul 16 07:57:00 PM PDT 24
Peak memory 214240 kb
Host smart-3f1bce5e-531d-414e-a3e8-cae970394b83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=786273599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.786273599
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.2753746156
Short name T529
Test name
Test status
Simulation time 215265970 ps
CPU time 3.68 seconds
Started Jul 16 07:56:49 PM PDT 24
Finished Jul 16 07:56:57 PM PDT 24
Peak memory 210284 kb
Host smart-3a2fe3f4-97a6-484b-af09-98b05a6ea7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753746156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.2753746156
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.4005651949
Short name T274
Test name
Test status
Simulation time 112040667 ps
CPU time 1.94 seconds
Started Jul 16 07:56:46 PM PDT 24
Finished Jul 16 07:56:52 PM PDT 24
Peak memory 214328 kb
Host smart-2e41346d-4e0a-4143-8235-232096badfdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005651949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.4005651949
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.4049516681
Short name T26
Test name
Test status
Simulation time 197385060 ps
CPU time 3.22 seconds
Started Jul 16 07:56:57 PM PDT 24
Finished Jul 16 07:57:02 PM PDT 24
Peak memory 214324 kb
Host smart-4a9a99ec-5e03-45da-9c58-5f52478ae402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049516681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.4049516681
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.3515658189
Short name T322
Test name
Test status
Simulation time 117369197 ps
CPU time 5.12 seconds
Started Jul 16 07:56:57 PM PDT 24
Finished Jul 16 07:57:04 PM PDT 24
Peak memory 208584 kb
Host smart-d4ba72d4-437c-4a8c-801c-f0bb5f1d2bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515658189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.3515658189
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.4225610560
Short name T14
Test name
Test status
Simulation time 931719337 ps
CPU time 23.23 seconds
Started Jul 16 07:56:43 PM PDT 24
Finished Jul 16 07:57:08 PM PDT 24
Peak memory 231292 kb
Host smart-f27771a2-b9d1-4599-a761-e9a210a7126a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225610560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.4225610560
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.1562309290
Short name T812
Test name
Test status
Simulation time 1506622651 ps
CPU time 10.06 seconds
Started Jul 16 07:56:57 PM PDT 24
Finished Jul 16 07:57:09 PM PDT 24
Peak memory 208016 kb
Host smart-e342f4f6-5a6c-4caf-943a-436f870abe27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562309290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.1562309290
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.1110009322
Short name T610
Test name
Test status
Simulation time 201525297 ps
CPU time 2.62 seconds
Started Jul 16 07:56:47 PM PDT 24
Finished Jul 16 07:56:54 PM PDT 24
Peak memory 207004 kb
Host smart-d1895638-5f1a-4f34-bf51-c5619d5969c0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110009322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.1110009322
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.3388247193
Short name T673
Test name
Test status
Simulation time 67628660 ps
CPU time 3 seconds
Started Jul 16 07:56:49 PM PDT 24
Finished Jul 16 07:56:57 PM PDT 24
Peak memory 206928 kb
Host smart-3e41b136-0ba4-420e-b48c-59164317d91a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388247193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.3388247193
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.1536868259
Short name T750
Test name
Test status
Simulation time 37986142 ps
CPU time 2.71 seconds
Started Jul 16 07:56:49 PM PDT 24
Finished Jul 16 07:56:56 PM PDT 24
Peak memory 208576 kb
Host smart-8ea1931c-c02a-4951-a2c9-84c28da4fbc2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536868259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.1536868259
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.2325529144
Short name T765
Test name
Test status
Simulation time 58263082 ps
CPU time 2.97 seconds
Started Jul 16 07:56:44 PM PDT 24
Finished Jul 16 07:56:50 PM PDT 24
Peak memory 208788 kb
Host smart-396993a3-66cb-4cba-9798-ecf361c77e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325529144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.2325529144
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.516370842
Short name T878
Test name
Test status
Simulation time 46810485 ps
CPU time 1.91 seconds
Started Jul 16 07:56:55 PM PDT 24
Finished Jul 16 07:56:59 PM PDT 24
Peak memory 208560 kb
Host smart-e672009e-89c6-4de2-840a-65cf82ddd11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516370842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.516370842
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.413775270
Short name T82
Test name
Test status
Simulation time 34186380 ps
CPU time 1.93 seconds
Started Jul 16 07:56:42 PM PDT 24
Finished Jul 16 07:56:45 PM PDT 24
Peak memory 207212 kb
Host smart-98cbf27c-df80-4d7a-8f20-3c320a863767
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413775270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.413775270
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.2532460419
Short name T239
Test name
Test status
Simulation time 656293466 ps
CPU time 15.21 seconds
Started Jul 16 07:56:44 PM PDT 24
Finished Jul 16 07:57:01 PM PDT 24
Peak memory 222744 kb
Host smart-54b26cba-f5ae-450a-b25d-2891b2e625fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532460419 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.2532460419
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.868169573
Short name T708
Test name
Test status
Simulation time 418370551 ps
CPU time 4.54 seconds
Started Jul 16 07:56:46 PM PDT 24
Finished Jul 16 07:56:54 PM PDT 24
Peak memory 208244 kb
Host smart-88fff462-4cd5-4816-8068-b9b1515103e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868169573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.868169573
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.331592202
Short name T433
Test name
Test status
Simulation time 21611230 ps
CPU time 0.98 seconds
Started Jul 16 07:58:11 PM PDT 24
Finished Jul 16 07:58:17 PM PDT 24
Peak memory 206104 kb
Host smart-572aaa46-5934-4bcd-918f-f7870e24189d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331592202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.331592202
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.354015609
Short name T823
Test name
Test status
Simulation time 48737472 ps
CPU time 2.16 seconds
Started Jul 16 07:58:09 PM PDT 24
Finished Jul 16 07:58:17 PM PDT 24
Peak memory 214360 kb
Host smart-a0a464a7-a0d0-4015-bdf1-377845292ef3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=354015609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.354015609
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.2628656459
Short name T35
Test name
Test status
Simulation time 156001632 ps
CPU time 4.28 seconds
Started Jul 16 07:58:18 PM PDT 24
Finished Jul 16 07:58:25 PM PDT 24
Peak memory 218300 kb
Host smart-8f55bebd-e035-44e5-b9c6-7d5743eee686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628656459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.2628656459
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.3372216909
Short name T532
Test name
Test status
Simulation time 141429483 ps
CPU time 4.51 seconds
Started Jul 16 07:58:12 PM PDT 24
Finished Jul 16 07:58:22 PM PDT 24
Peak memory 207212 kb
Host smart-d516e5c3-bffb-48f5-9488-2edbc6939357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372216909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.3372216909
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.3707126423
Short name T42
Test name
Test status
Simulation time 96724981 ps
CPU time 2.07 seconds
Started Jul 16 07:58:12 PM PDT 24
Finished Jul 16 07:58:19 PM PDT 24
Peak memory 206744 kb
Host smart-564b59a2-72d3-4272-a036-648b67e55679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707126423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.3707126423
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.1974728471
Short name T583
Test name
Test status
Simulation time 492074779 ps
CPU time 3.55 seconds
Started Jul 16 07:58:12 PM PDT 24
Finished Jul 16 07:58:20 PM PDT 24
Peak memory 220952 kb
Host smart-b6e12f20-0fbc-4910-9382-eab73086a6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974728471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.1974728471
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_random.2771782071
Short name T559
Test name
Test status
Simulation time 620783656 ps
CPU time 6.87 seconds
Started Jul 16 07:58:18 PM PDT 24
Finished Jul 16 07:58:28 PM PDT 24
Peak memory 208032 kb
Host smart-91cfbc5e-7fe6-4088-8ecc-4b674bfc94de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771782071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.2771782071
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.110961515
Short name T186
Test name
Test status
Simulation time 23773168 ps
CPU time 1.95 seconds
Started Jul 16 07:58:09 PM PDT 24
Finished Jul 16 07:58:17 PM PDT 24
Peak memory 207460 kb
Host smart-de4f03ce-3acc-4a1b-ac9c-f4d31563b04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110961515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.110961515
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.2252867824
Short name T839
Test name
Test status
Simulation time 232284507 ps
CPU time 6.12 seconds
Started Jul 16 07:58:15 PM PDT 24
Finished Jul 16 07:58:25 PM PDT 24
Peak memory 208652 kb
Host smart-3f5314bb-561f-466c-b96c-2babb63dbcb7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252867824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2252867824
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.305400489
Short name T910
Test name
Test status
Simulation time 48606317 ps
CPU time 1.96 seconds
Started Jul 16 07:58:13 PM PDT 24
Finished Jul 16 07:58:20 PM PDT 24
Peak memory 208568 kb
Host smart-47190a89-53a6-4dc0-8799-4be0c5ba4e6c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305400489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.305400489
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.1303892570
Short name T619
Test name
Test status
Simulation time 188089882 ps
CPU time 2.63 seconds
Started Jul 16 07:58:09 PM PDT 24
Finished Jul 16 07:58:19 PM PDT 24
Peak memory 208632 kb
Host smart-372f18f9-cd61-4f60-b8fe-381554bd6d1f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303892570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.1303892570
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.748162521
Short name T129
Test name
Test status
Simulation time 5527145298 ps
CPU time 10.26 seconds
Started Jul 16 07:58:10 PM PDT 24
Finished Jul 16 07:58:26 PM PDT 24
Peak memory 209396 kb
Host smart-49a50848-406b-49eb-bfb7-39e7e9a21cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748162521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.748162521
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.2552688464
Short name T909
Test name
Test status
Simulation time 1733817780 ps
CPU time 22.04 seconds
Started Jul 16 07:58:07 PM PDT 24
Finished Jul 16 07:58:36 PM PDT 24
Peak memory 207840 kb
Host smart-8648ff71-d44a-4eaf-9627-0b83eec3c91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552688464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.2552688464
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.154612850
Short name T209
Test name
Test status
Simulation time 8188754037 ps
CPU time 56.31 seconds
Started Jul 16 07:58:16 PM PDT 24
Finished Jul 16 07:59:17 PM PDT 24
Peak memory 222616 kb
Host smart-54cdc4dc-985e-43d5-95d6-95046f96fb1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154612850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.154612850
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.2991428977
Short name T768
Test name
Test status
Simulation time 2184903411 ps
CPU time 22.11 seconds
Started Jul 16 07:58:13 PM PDT 24
Finished Jul 16 07:58:40 PM PDT 24
Peak memory 222652 kb
Host smart-1048e498-56ef-4c54-9c9f-1cd1b344f8e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991428977 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.2991428977
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.158354981
Short name T542
Test name
Test status
Simulation time 1156153293 ps
CPU time 7.49 seconds
Started Jul 16 07:58:17 PM PDT 24
Finished Jul 16 07:58:28 PM PDT 24
Peak memory 218384 kb
Host smart-3000e604-7516-469c-b4af-5e669059c9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158354981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.158354981
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.1787411464
Short name T213
Test name
Test status
Simulation time 172513412 ps
CPU time 2.28 seconds
Started Jul 16 07:58:16 PM PDT 24
Finished Jul 16 07:58:22 PM PDT 24
Peak memory 209960 kb
Host smart-61db4bbd-d49b-4428-81a4-061373d595cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787411464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.1787411464
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.2063429048
Short name T470
Test name
Test status
Simulation time 62879527 ps
CPU time 0.92 seconds
Started Jul 16 07:58:15 PM PDT 24
Finished Jul 16 07:58:21 PM PDT 24
Peak memory 206132 kb
Host smart-969182eb-e005-4bee-bf17-cffaaa5b619a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063429048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.2063429048
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.2586743269
Short name T73
Test name
Test status
Simulation time 74972238 ps
CPU time 2.46 seconds
Started Jul 16 07:58:24 PM PDT 24
Finished Jul 16 07:58:29 PM PDT 24
Peak memory 221132 kb
Host smart-8e935abc-4bd6-4b21-9e48-a36eab9277a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586743269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.2586743269
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.2968138293
Short name T623
Test name
Test status
Simulation time 670198010 ps
CPU time 16.94 seconds
Started Jul 16 07:58:19 PM PDT 24
Finished Jul 16 07:58:39 PM PDT 24
Peak memory 209856 kb
Host smart-7b37e828-f445-4429-b1b9-9b3d77a00aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968138293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.2968138293
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.1660061524
Short name T888
Test name
Test status
Simulation time 84786838 ps
CPU time 2.66 seconds
Started Jul 16 07:58:16 PM PDT 24
Finished Jul 16 07:58:22 PM PDT 24
Peak memory 214388 kb
Host smart-66978eb9-39ef-4f94-960c-1b2ed52fa669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660061524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.1660061524
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.165980955
Short name T313
Test name
Test status
Simulation time 153612370 ps
CPU time 2.26 seconds
Started Jul 16 07:58:16 PM PDT 24
Finished Jul 16 07:58:22 PM PDT 24
Peak memory 214272 kb
Host smart-7235fc2b-9276-496f-8174-ed6c641ea22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165980955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.165980955
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.424509248
Short name T819
Test name
Test status
Simulation time 220035329 ps
CPU time 2.79 seconds
Started Jul 16 07:58:17 PM PDT 24
Finished Jul 16 07:58:23 PM PDT 24
Peak memory 220076 kb
Host smart-f3295bf6-6d85-451e-aa34-0b7b02ca6c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424509248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.424509248
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.2404058356
Short name T361
Test name
Test status
Simulation time 1382473582 ps
CPU time 11.79 seconds
Started Jul 16 07:58:09 PM PDT 24
Finished Jul 16 07:58:27 PM PDT 24
Peak memory 218284 kb
Host smart-3b55c757-450c-4468-ae0f-b642ecd1e45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404058356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.2404058356
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.4007655661
Short name T609
Test name
Test status
Simulation time 287306707 ps
CPU time 6.45 seconds
Started Jul 16 07:58:08 PM PDT 24
Finished Jul 16 07:58:21 PM PDT 24
Peak memory 207100 kb
Host smart-27e3d9d1-0fe7-4176-afec-8956a02bf5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007655661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.4007655661
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.2818118080
Short name T879
Test name
Test status
Simulation time 2454285997 ps
CPU time 19.13 seconds
Started Jul 16 07:58:10 PM PDT 24
Finished Jul 16 07:58:35 PM PDT 24
Peak memory 208376 kb
Host smart-6ea36dd2-bb60-463d-8200-ae00942b3d43
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818118080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.2818118080
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.4053514586
Short name T842
Test name
Test status
Simulation time 62967815 ps
CPU time 2.31 seconds
Started Jul 16 07:58:13 PM PDT 24
Finished Jul 16 07:58:20 PM PDT 24
Peak memory 206656 kb
Host smart-b5e5ae7e-f6fd-4bd4-ad81-7a7e3674ffda
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053514586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.4053514586
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.1689021358
Short name T836
Test name
Test status
Simulation time 115230296 ps
CPU time 2.93 seconds
Started Jul 16 07:58:27 PM PDT 24
Finished Jul 16 07:58:31 PM PDT 24
Peak memory 208344 kb
Host smart-55db37da-e357-4ed3-aca8-c369202d847b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689021358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.1689021358
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.1895423254
Short name T734
Test name
Test status
Simulation time 134802985 ps
CPU time 2.07 seconds
Started Jul 16 07:58:17 PM PDT 24
Finished Jul 16 07:58:23 PM PDT 24
Peak memory 207032 kb
Host smart-8fd0e4f6-196d-4401-ad56-018aae72bb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895423254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1895423254
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.909062352
Short name T848
Test name
Test status
Simulation time 321576597 ps
CPU time 2.56 seconds
Started Jul 16 07:58:10 PM PDT 24
Finished Jul 16 07:58:19 PM PDT 24
Peak memory 206860 kb
Host smart-eb442bfd-fd85-42f7-9665-d956d190cdff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909062352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.909062352
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.3880233731
Short name T719
Test name
Test status
Simulation time 3873794077 ps
CPU time 39.23 seconds
Started Jul 16 07:58:24 PM PDT 24
Finished Jul 16 07:59:06 PM PDT 24
Peak memory 222564 kb
Host smart-8a0f933d-b126-4799-b831-61a773927eb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880233731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.3880233731
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.2843138493
Short name T356
Test name
Test status
Simulation time 576134370 ps
CPU time 9.16 seconds
Started Jul 16 07:58:16 PM PDT 24
Finished Jul 16 07:58:29 PM PDT 24
Peak memory 209404 kb
Host smart-a7bed29d-648c-43be-a3f1-a74a652d1f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843138493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2843138493
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.745244085
Short name T676
Test name
Test status
Simulation time 102485618 ps
CPU time 1.91 seconds
Started Jul 16 07:58:24 PM PDT 24
Finished Jul 16 07:58:28 PM PDT 24
Peak memory 209844 kb
Host smart-5675cb85-f796-4f7f-9040-4199707fe223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745244085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.745244085
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.4180951676
Short name T437
Test name
Test status
Simulation time 16888957 ps
CPU time 0.78 seconds
Started Jul 16 07:58:26 PM PDT 24
Finished Jul 16 07:58:29 PM PDT 24
Peak memory 206000 kb
Host smart-3431b3aa-a044-46f5-b71c-4b58c75e9181
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180951676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.4180951676
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.899979413
Short name T262
Test name
Test status
Simulation time 474621462 ps
CPU time 8.5 seconds
Started Jul 16 07:58:26 PM PDT 24
Finished Jul 16 07:58:37 PM PDT 24
Peak memory 215608 kb
Host smart-1644dbb0-cdbc-43a7-8f4d-c3bd68eedb12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=899979413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.899979413
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.1164069368
Short name T150
Test name
Test status
Simulation time 177432834 ps
CPU time 4.83 seconds
Started Jul 16 07:58:25 PM PDT 24
Finished Jul 16 07:58:32 PM PDT 24
Peak memory 218068 kb
Host smart-8b5afb24-6c2b-40f4-b598-5489b512b8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164069368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.1164069368
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.2206021755
Short name T371
Test name
Test status
Simulation time 61847947 ps
CPU time 1.93 seconds
Started Jul 16 07:58:23 PM PDT 24
Finished Jul 16 07:58:26 PM PDT 24
Peak memory 207276 kb
Host smart-f65911a2-8cdc-415d-b5ad-5cdee8bcecd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206021755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.2206021755
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.3266292346
Short name T503
Test name
Test status
Simulation time 208770246 ps
CPU time 4.81 seconds
Started Jul 16 07:58:23 PM PDT 24
Finished Jul 16 07:58:29 PM PDT 24
Peak memory 209796 kb
Host smart-a02a9aa3-e129-4c9c-969e-ad17255b1664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266292346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3266292346
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.3229236829
Short name T785
Test name
Test status
Simulation time 175932592 ps
CPU time 2.71 seconds
Started Jul 16 07:58:24 PM PDT 24
Finished Jul 16 07:58:30 PM PDT 24
Peak memory 220284 kb
Host smart-bb0eafe0-0490-4d93-b425-676da917da84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229236829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.3229236829
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.470033598
Short name T64
Test name
Test status
Simulation time 163380108 ps
CPU time 3.62 seconds
Started Jul 16 07:58:22 PM PDT 24
Finished Jul 16 07:58:27 PM PDT 24
Peak memory 222388 kb
Host smart-96a44e94-37e6-478b-bcd1-c0bf3f6222c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470033598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.470033598
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.1960035694
Short name T525
Test name
Test status
Simulation time 220440608 ps
CPU time 4.77 seconds
Started Jul 16 07:58:21 PM PDT 24
Finished Jul 16 07:58:27 PM PDT 24
Peak memory 218260 kb
Host smart-f52fc969-0822-47c8-849a-deba2949ad1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960035694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.1960035694
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.2804148671
Short name T706
Test name
Test status
Simulation time 325697576 ps
CPU time 3.87 seconds
Started Jul 16 07:58:19 PM PDT 24
Finished Jul 16 07:58:26 PM PDT 24
Peak memory 209024 kb
Host smart-946d7036-e899-4985-bfa0-920d4c3d35e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804148671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.2804148671
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.1790687156
Short name T561
Test name
Test status
Simulation time 232330016 ps
CPU time 2.93 seconds
Started Jul 16 07:58:17 PM PDT 24
Finished Jul 16 07:58:24 PM PDT 24
Peak memory 206656 kb
Host smart-b9c429f2-cc89-4877-8f46-2432011f7e5c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790687156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.1790687156
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.1930681206
Short name T659
Test name
Test status
Simulation time 688057328 ps
CPU time 3 seconds
Started Jul 16 07:58:24 PM PDT 24
Finished Jul 16 07:58:29 PM PDT 24
Peak memory 206904 kb
Host smart-aaa5a947-666e-4e3b-9422-1260db7b3e91
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930681206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.1930681206
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.2537226817
Short name T280
Test name
Test status
Simulation time 2433484731 ps
CPU time 25.54 seconds
Started Jul 16 07:58:24 PM PDT 24
Finished Jul 16 07:58:52 PM PDT 24
Peak memory 209228 kb
Host smart-3066e052-cb13-4dff-9d8d-b6b26cc3e8e2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537226817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.2537226817
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.3178221349
Short name T518
Test name
Test status
Simulation time 45396856 ps
CPU time 1.87 seconds
Started Jul 16 07:58:22 PM PDT 24
Finished Jul 16 07:58:25 PM PDT 24
Peak memory 207396 kb
Host smart-f115c15f-a23c-4e32-909b-070cd56d87aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178221349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.3178221349
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.310139052
Short name T876
Test name
Test status
Simulation time 134947860 ps
CPU time 3.08 seconds
Started Jul 16 07:58:19 PM PDT 24
Finished Jul 16 07:58:25 PM PDT 24
Peak memory 206896 kb
Host smart-347efe98-ad67-4862-ae16-5fafe07b2369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310139052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.310139052
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.771139933
Short name T864
Test name
Test status
Simulation time 2573228432 ps
CPU time 42.49 seconds
Started Jul 16 07:58:22 PM PDT 24
Finished Jul 16 07:59:06 PM PDT 24
Peak memory 214404 kb
Host smart-b19ce9ce-1a9b-4004-a8b5-854443fb3ebe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771139933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.771139933
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.1940996440
Short name T74
Test name
Test status
Simulation time 718969872 ps
CPU time 28 seconds
Started Jul 16 07:58:39 PM PDT 24
Finished Jul 16 07:59:08 PM PDT 24
Peak memory 222648 kb
Host smart-b26c3280-a757-42a9-a1ee-fd48e9dac65c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940996440 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.1940996440
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.616690193
Short name T325
Test name
Test status
Simulation time 138255602 ps
CPU time 5.11 seconds
Started Jul 16 07:58:22 PM PDT 24
Finished Jul 16 07:58:29 PM PDT 24
Peak memory 207376 kb
Host smart-f1d70b9d-9f8c-4a49-9706-b31d9859904d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616690193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.616690193
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.1116050704
Short name T170
Test name
Test status
Simulation time 98798186 ps
CPU time 3.63 seconds
Started Jul 16 07:58:26 PM PDT 24
Finished Jul 16 07:58:32 PM PDT 24
Peak memory 210720 kb
Host smart-338240ac-2098-43f3-9009-f1b73f807169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116050704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.1116050704
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.3930898083
Short name T807
Test name
Test status
Simulation time 23952265 ps
CPU time 0.88 seconds
Started Jul 16 07:58:25 PM PDT 24
Finished Jul 16 07:58:28 PM PDT 24
Peak memory 206028 kb
Host smart-6b37df5f-c14b-4987-bcfe-02d7690e39eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930898083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.3930898083
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.3037444978
Short name T366
Test name
Test status
Simulation time 97411049 ps
CPU time 4.37 seconds
Started Jul 16 07:58:25 PM PDT 24
Finished Jul 16 07:58:32 PM PDT 24
Peak memory 214328 kb
Host smart-bed06525-21d1-49fb-a616-d9c570ae2480
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3037444978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.3037444978
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.762551770
Short name T9
Test name
Test status
Simulation time 148988830 ps
CPU time 3.6 seconds
Started Jul 16 07:58:26 PM PDT 24
Finished Jul 16 07:58:32 PM PDT 24
Peak memory 210196 kb
Host smart-224e59d9-8e72-4e25-8591-47287dc3f78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762551770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.762551770
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.50356517
Short name T372
Test name
Test status
Simulation time 24270623 ps
CPU time 1.63 seconds
Started Jul 16 07:58:24 PM PDT 24
Finished Jul 16 07:58:29 PM PDT 24
Peak memory 208412 kb
Host smart-f3bf8d54-6346-4a0a-87f2-04535950d57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50356517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.50356517
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.2854616856
Short name T764
Test name
Test status
Simulation time 171317813 ps
CPU time 2.51 seconds
Started Jul 16 07:58:24 PM PDT 24
Finished Jul 16 07:58:29 PM PDT 24
Peak memory 214252 kb
Host smart-8b65afb7-8340-413c-aa40-064916f0f242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854616856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.2854616856
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.2885392452
Short name T234
Test name
Test status
Simulation time 542210019 ps
CPU time 3.16 seconds
Started Jul 16 07:58:21 PM PDT 24
Finished Jul 16 07:58:26 PM PDT 24
Peak memory 214348 kb
Host smart-567d18fb-782f-4cab-89ad-0b6da40f7f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885392452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.2885392452
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.34343746
Short name T393
Test name
Test status
Simulation time 255537570 ps
CPU time 4.87 seconds
Started Jul 16 07:58:22 PM PDT 24
Finished Jul 16 07:58:28 PM PDT 24
Peak memory 209356 kb
Host smart-84d0aa65-d67b-4b10-88c6-e77606d61586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34343746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.34343746
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.3518401890
Short name T712
Test name
Test status
Simulation time 619980168 ps
CPU time 5.19 seconds
Started Jul 16 07:58:20 PM PDT 24
Finished Jul 16 07:58:27 PM PDT 24
Peak memory 206900 kb
Host smart-e16baaa7-27b8-45fb-ac65-5a8ec4c32b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518401890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.3518401890
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.2108208615
Short name T284
Test name
Test status
Simulation time 78923495 ps
CPU time 3.87 seconds
Started Jul 16 07:58:27 PM PDT 24
Finished Jul 16 07:58:32 PM PDT 24
Peak memory 208736 kb
Host smart-18ede5f5-bfad-44c6-aa8a-e58fa16410bd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108208615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.2108208615
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.667894378
Short name T330
Test name
Test status
Simulation time 3887817552 ps
CPU time 15.18 seconds
Started Jul 16 07:58:21 PM PDT 24
Finished Jul 16 07:58:38 PM PDT 24
Peak memory 208452 kb
Host smart-e57fde10-a598-4043-acd3-3ddc4f9af98f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667894378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.667894378
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.3528793690
Short name T190
Test name
Test status
Simulation time 27494660 ps
CPU time 2.15 seconds
Started Jul 16 07:58:21 PM PDT 24
Finished Jul 16 07:58:25 PM PDT 24
Peak memory 208768 kb
Host smart-427bdac3-1a72-4d0c-aa9f-1192549edfd4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528793690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.3528793690
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.1641205735
Short name T306
Test name
Test status
Simulation time 272834386 ps
CPU time 2.03 seconds
Started Jul 16 07:58:23 PM PDT 24
Finished Jul 16 07:58:26 PM PDT 24
Peak memory 208148 kb
Host smart-fbe7584a-4d35-40fd-8a85-738480cf8c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641205735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1641205735
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.1219938446
Short name T890
Test name
Test status
Simulation time 186614632 ps
CPU time 4.36 seconds
Started Jul 16 07:58:22 PM PDT 24
Finished Jul 16 07:58:28 PM PDT 24
Peak memory 208008 kb
Host smart-89229853-330d-4d0c-af7f-1611e84f54f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219938446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.1219938446
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.1298354034
Short name T249
Test name
Test status
Simulation time 640943607 ps
CPU time 32.6 seconds
Started Jul 16 07:58:29 PM PDT 24
Finished Jul 16 07:59:03 PM PDT 24
Peak memory 222604 kb
Host smart-5fc310eb-32fa-45d0-9fd4-0984031f654c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298354034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1298354034
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.2167755729
Short name T580
Test name
Test status
Simulation time 210809068 ps
CPU time 5.11 seconds
Started Jul 16 07:58:20 PM PDT 24
Finished Jul 16 07:58:27 PM PDT 24
Peak memory 218284 kb
Host smart-7b127c55-eee7-4573-9269-db173a6bccf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167755729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.2167755729
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.3157352545
Short name T49
Test name
Test status
Simulation time 55014691 ps
CPU time 2.27 seconds
Started Jul 16 07:58:21 PM PDT 24
Finished Jul 16 07:58:25 PM PDT 24
Peak memory 210544 kb
Host smart-2e64232f-f58f-4374-b259-a02cbee18766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157352545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.3157352545
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.291348903
Short name T574
Test name
Test status
Simulation time 81331471 ps
CPU time 0.86 seconds
Started Jul 16 07:58:40 PM PDT 24
Finished Jul 16 07:58:42 PM PDT 24
Peak memory 206000 kb
Host smart-0fdf2e35-ba1c-4584-8273-655194748502
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291348903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.291348903
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.304245955
Short name T316
Test name
Test status
Simulation time 456312100 ps
CPU time 12.29 seconds
Started Jul 16 07:58:47 PM PDT 24
Finished Jul 16 07:59:02 PM PDT 24
Peak memory 215488 kb
Host smart-86e92310-644e-405c-bb0d-194882e0c744
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=304245955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.304245955
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.299109200
Short name T810
Test name
Test status
Simulation time 116805487 ps
CPU time 1.98 seconds
Started Jul 16 07:58:41 PM PDT 24
Finished Jul 16 07:58:44 PM PDT 24
Peak memory 208188 kb
Host smart-6a01a3ad-9e2f-413b-828d-1f693248d7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299109200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.299109200
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.1841296102
Short name T392
Test name
Test status
Simulation time 410854631 ps
CPU time 4.01 seconds
Started Jul 16 07:58:42 PM PDT 24
Finished Jul 16 07:58:47 PM PDT 24
Peak memory 222496 kb
Host smart-161a20ff-c5ec-4adb-ab69-595725dc6fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841296102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.1841296102
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.857638887
Short name T769
Test name
Test status
Simulation time 207009423 ps
CPU time 3.07 seconds
Started Jul 16 07:58:41 PM PDT 24
Finished Jul 16 07:58:45 PM PDT 24
Peak memory 214212 kb
Host smart-515ae7ea-1aeb-4d93-aee5-4a1ea7224271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857638887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.857638887
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.3990080712
Short name T278
Test name
Test status
Simulation time 47588273 ps
CPU time 3.18 seconds
Started Jul 16 07:58:45 PM PDT 24
Finished Jul 16 07:58:50 PM PDT 24
Peak memory 220040 kb
Host smart-976337cc-971d-4531-92d0-c116853381ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990080712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3990080712
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.4153418583
Short name T538
Test name
Test status
Simulation time 107799672 ps
CPU time 3.88 seconds
Started Jul 16 07:58:44 PM PDT 24
Finished Jul 16 07:58:50 PM PDT 24
Peak memory 209860 kb
Host smart-008e5f29-b0eb-4c7f-b2af-1848a7023e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153418583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.4153418583
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.1290783723
Short name T575
Test name
Test status
Simulation time 403837359 ps
CPU time 5.7 seconds
Started Jul 16 07:58:25 PM PDT 24
Finished Jul 16 07:58:33 PM PDT 24
Peak memory 206896 kb
Host smart-940234b0-6157-47d7-9e27-e45ff8db2a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290783723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.1290783723
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.2270546689
Short name T794
Test name
Test status
Simulation time 6527138591 ps
CPU time 63.69 seconds
Started Jul 16 07:58:44 PM PDT 24
Finished Jul 16 07:59:49 PM PDT 24
Peak memory 208584 kb
Host smart-8b343b9f-fbbb-4f17-8404-438ee8cf0f0e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270546689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.2270546689
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.898914366
Short name T880
Test name
Test status
Simulation time 148396955 ps
CPU time 3.51 seconds
Started Jul 16 07:58:48 PM PDT 24
Finished Jul 16 07:58:54 PM PDT 24
Peak memory 208928 kb
Host smart-b1d37b48-9576-45c8-9690-5d098279e169
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898914366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.898914366
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.4194831694
Short name T558
Test name
Test status
Simulation time 125653979 ps
CPU time 3.33 seconds
Started Jul 16 07:58:48 PM PDT 24
Finished Jul 16 07:58:54 PM PDT 24
Peak memory 208912 kb
Host smart-2ef07856-bb46-431e-92b1-85fbed5b778c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194831694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.4194831694
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.67685790
Short name T540
Test name
Test status
Simulation time 93775689 ps
CPU time 2.48 seconds
Started Jul 16 07:58:45 PM PDT 24
Finished Jul 16 07:58:50 PM PDT 24
Peak memory 209268 kb
Host smart-97b9b742-3b97-4d88-aafa-5531433740f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67685790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.67685790
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.37683347
Short name T801
Test name
Test status
Simulation time 102173338 ps
CPU time 2.78 seconds
Started Jul 16 07:58:26 PM PDT 24
Finished Jul 16 07:58:31 PM PDT 24
Peak memory 206764 kb
Host smart-03fcfe5c-5492-4999-b165-901db0f728cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37683347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.37683347
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.2962637808
Short name T360
Test name
Test status
Simulation time 748662515 ps
CPU time 29.84 seconds
Started Jul 16 07:58:50 PM PDT 24
Finished Jul 16 07:59:21 PM PDT 24
Peak memory 222408 kb
Host smart-06cf9600-ce70-4832-9207-7e0c6fffc301
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962637808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.2962637808
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.672897759
Short name T809
Test name
Test status
Simulation time 383314459 ps
CPU time 15.66 seconds
Started Jul 16 07:58:44 PM PDT 24
Finished Jul 16 07:59:02 PM PDT 24
Peak memory 222656 kb
Host smart-2d95ffb6-e06e-4fdf-a25e-ee1a491aefbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672897759 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.672897759
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.401234385
Short name T791
Test name
Test status
Simulation time 112970629 ps
CPU time 3.82 seconds
Started Jul 16 07:58:47 PM PDT 24
Finished Jul 16 07:58:53 PM PDT 24
Peak memory 207368 kb
Host smart-c94750fe-0096-457b-96c8-4758209a6070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401234385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.401234385
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.261815255
Short name T404
Test name
Test status
Simulation time 153161182 ps
CPU time 2.24 seconds
Started Jul 16 07:58:50 PM PDT 24
Finished Jul 16 07:58:54 PM PDT 24
Peak memory 209944 kb
Host smart-213d1c1f-f93a-4be9-8508-3337ff4bc191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261815255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.261815255
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.2074676373
Short name T595
Test name
Test status
Simulation time 119864208 ps
CPU time 0.98 seconds
Started Jul 16 07:58:44 PM PDT 24
Finished Jul 16 07:58:47 PM PDT 24
Peak memory 206092 kb
Host smart-5673287d-107c-4275-b1cf-1cc993464d3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074676373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.2074676373
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.3750437200
Short name T379
Test name
Test status
Simulation time 445285788 ps
CPU time 5.6 seconds
Started Jul 16 07:58:45 PM PDT 24
Finished Jul 16 07:58:52 PM PDT 24
Peak memory 214696 kb
Host smart-52401b9d-366a-4b9c-85a7-2041a5fe7080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750437200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.3750437200
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.883291510
Short name T480
Test name
Test status
Simulation time 38915781 ps
CPU time 1.57 seconds
Started Jul 16 07:58:50 PM PDT 24
Finished Jul 16 07:58:53 PM PDT 24
Peak memory 207548 kb
Host smart-e6e4a14e-bf35-40b6-909b-419b98051dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883291510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.883291510
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1945450685
Short name T332
Test name
Test status
Simulation time 100907244 ps
CPU time 3.44 seconds
Started Jul 16 07:58:46 PM PDT 24
Finished Jul 16 07:58:53 PM PDT 24
Peak memory 214324 kb
Host smart-2c4148cd-1f5f-4f22-92a3-a8a6af390fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945450685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1945450685
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.3802784114
Short name T541
Test name
Test status
Simulation time 635685564 ps
CPU time 2.88 seconds
Started Jul 16 07:58:44 PM PDT 24
Finished Jul 16 07:58:48 PM PDT 24
Peak memory 207376 kb
Host smart-3ae20ead-ce67-4561-89d2-2451bb968dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802784114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.3802784114
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.3627924694
Short name T173
Test name
Test status
Simulation time 275723628 ps
CPU time 3.03 seconds
Started Jul 16 07:58:45 PM PDT 24
Finished Jul 16 07:58:50 PM PDT 24
Peak memory 210408 kb
Host smart-a3641bad-afec-4d57-8f7a-d0ea821aa07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627924694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.3627924694
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.1987085945
Short name T681
Test name
Test status
Simulation time 1479077947 ps
CPU time 5.84 seconds
Started Jul 16 07:58:46 PM PDT 24
Finished Jul 16 07:58:55 PM PDT 24
Peak memory 209748 kb
Host smart-dc314201-b4fa-4d52-8dbc-1e3096100732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987085945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1987085945
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.2940603775
Short name T638
Test name
Test status
Simulation time 49097210 ps
CPU time 2.65 seconds
Started Jul 16 07:58:43 PM PDT 24
Finished Jul 16 07:58:46 PM PDT 24
Peak memory 206780 kb
Host smart-e9c73189-78cc-4d64-81f4-cca022d8fe57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940603775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2940603775
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.3938400659
Short name T782
Test name
Test status
Simulation time 6210044098 ps
CPU time 45.69 seconds
Started Jul 16 07:58:44 PM PDT 24
Finished Jul 16 07:59:31 PM PDT 24
Peak memory 208388 kb
Host smart-1b480dce-df33-4cd0-afcc-ecbd9d239c8c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938400659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.3938400659
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.1431485762
Short name T586
Test name
Test status
Simulation time 83340595 ps
CPU time 2.02 seconds
Started Jul 16 07:58:45 PM PDT 24
Finished Jul 16 07:58:50 PM PDT 24
Peak memory 208940 kb
Host smart-7e617bc9-271e-4204-a8c2-18ce603e5caf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431485762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.1431485762
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.2280005390
Short name T572
Test name
Test status
Simulation time 246807998 ps
CPU time 3.19 seconds
Started Jul 16 07:58:40 PM PDT 24
Finished Jul 16 07:58:44 PM PDT 24
Peak memory 206984 kb
Host smart-56f61087-3511-4aea-8fc1-42095e7acb90
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280005390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.2280005390
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.1426391246
Short name T268
Test name
Test status
Simulation time 36491813 ps
CPU time 2.2 seconds
Started Jul 16 07:58:51 PM PDT 24
Finished Jul 16 07:58:54 PM PDT 24
Peak memory 208140 kb
Host smart-187eb168-6509-4a29-94e7-3d6f0af49e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426391246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.1426391246
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.1758532176
Short name T451
Test name
Test status
Simulation time 75862411 ps
CPU time 1.87 seconds
Started Jul 16 07:58:44 PM PDT 24
Finished Jul 16 07:58:48 PM PDT 24
Peak memory 206968 kb
Host smart-d39140d4-c885-46be-80f1-f26e603c026c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758532176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1758532176
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.3145572563
Short name T896
Test name
Test status
Simulation time 959806293 ps
CPU time 9.96 seconds
Started Jul 16 07:58:45 PM PDT 24
Finished Jul 16 07:58:58 PM PDT 24
Peak memory 222640 kb
Host smart-8e5d28b4-88d8-4850-8963-4c0d9ddbe46c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145572563 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.3145572563
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.561334982
Short name T640
Test name
Test status
Simulation time 246506531 ps
CPU time 5.28 seconds
Started Jul 16 07:58:46 PM PDT 24
Finished Jul 16 07:58:54 PM PDT 24
Peak memory 210372 kb
Host smart-d4c50db5-50cd-4db2-a076-b57e2387109f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561334982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.561334982
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2443942466
Short name T671
Test name
Test status
Simulation time 117174742 ps
CPU time 1.9 seconds
Started Jul 16 07:58:50 PM PDT 24
Finished Jul 16 07:58:53 PM PDT 24
Peak memory 209708 kb
Host smart-aeb75b60-dbe7-4e71-ae12-a6f165cfcb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443942466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2443942466
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.1030063675
Short name T732
Test name
Test status
Simulation time 15132246 ps
CPU time 0.73 seconds
Started Jul 16 07:58:45 PM PDT 24
Finished Jul 16 07:58:49 PM PDT 24
Peak memory 205968 kb
Host smart-ef2924d7-6089-47f9-8385-f72d8c40ec08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030063675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.1030063675
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.1726045496
Short name T251
Test name
Test status
Simulation time 6655019235 ps
CPU time 91.08 seconds
Started Jul 16 07:58:46 PM PDT 24
Finished Jul 16 08:00:20 PM PDT 24
Peak memory 215288 kb
Host smart-30b1f84a-f858-46cf-9009-2aa8fc13a198
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1726045496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.1726045496
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.960696762
Short name T804
Test name
Test status
Simulation time 88349772 ps
CPU time 3.89 seconds
Started Jul 16 07:58:44 PM PDT 24
Finished Jul 16 07:58:50 PM PDT 24
Peak memory 209744 kb
Host smart-5f807f0c-9941-43f8-a1c6-3b7382220506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960696762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.960696762
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.731496110
Short name T200
Test name
Test status
Simulation time 198086138 ps
CPU time 2.98 seconds
Started Jul 16 07:58:45 PM PDT 24
Finished Jul 16 07:58:51 PM PDT 24
Peak memory 208232 kb
Host smart-1c401286-b888-4da5-856c-b15dca084fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731496110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.731496110
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.967192849
Short name T27
Test name
Test status
Simulation time 250785320 ps
CPU time 5.31 seconds
Started Jul 16 07:58:45 PM PDT 24
Finished Jul 16 07:58:54 PM PDT 24
Peak memory 222404 kb
Host smart-dcaccfee-8522-4708-a1b0-d29a6ae77ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967192849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.967192849
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.2003775612
Short name T68
Test name
Test status
Simulation time 96337251 ps
CPU time 4.94 seconds
Started Jul 16 07:58:48 PM PDT 24
Finished Jul 16 07:58:55 PM PDT 24
Peak memory 209396 kb
Host smart-9d05b9e4-2108-42f8-b433-b74fc95fa7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003775612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.2003775612
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.3805512187
Short name T553
Test name
Test status
Simulation time 794480399 ps
CPU time 24.5 seconds
Started Jul 16 07:58:46 PM PDT 24
Finished Jul 16 07:59:14 PM PDT 24
Peak memory 220312 kb
Host smart-a8b73c63-4624-459b-9a5f-770530de4745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805512187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.3805512187
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.4082465861
Short name T613
Test name
Test status
Simulation time 89127494 ps
CPU time 2.7 seconds
Started Jul 16 07:58:44 PM PDT 24
Finished Jul 16 07:58:49 PM PDT 24
Peak memory 207292 kb
Host smart-7e2c6467-f555-4578-9f56-e7ab448fef6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082465861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.4082465861
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.137174166
Short name T642
Test name
Test status
Simulation time 98005143 ps
CPU time 4.16 seconds
Started Jul 16 07:58:42 PM PDT 24
Finished Jul 16 07:58:47 PM PDT 24
Peak memory 206960 kb
Host smart-586c0df3-f1fc-476c-975a-922cfd5dfbc7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137174166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.137174166
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.4073881994
Short name T364
Test name
Test status
Simulation time 68737521 ps
CPU time 2.69 seconds
Started Jul 16 07:58:45 PM PDT 24
Finished Jul 16 07:58:51 PM PDT 24
Peak memory 208892 kb
Host smart-27d94c9c-a7e6-44bd-bca1-7b7e326f3545
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073881994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.4073881994
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.1365905660
Short name T458
Test name
Test status
Simulation time 405157736 ps
CPU time 5.81 seconds
Started Jul 16 07:58:41 PM PDT 24
Finished Jul 16 07:58:48 PM PDT 24
Peak memory 207872 kb
Host smart-1b1485ba-a56f-4243-8516-bd1ce0dddd2c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365905660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.1365905660
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.3710900513
Short name T484
Test name
Test status
Simulation time 3191252697 ps
CPU time 15.4 seconds
Started Jul 16 07:58:48 PM PDT 24
Finished Jul 16 07:59:06 PM PDT 24
Peak memory 214388 kb
Host smart-d4090ee6-8a7f-4e81-bc7e-853bbe2b53b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710900513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.3710900513
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.3571069487
Short name T604
Test name
Test status
Simulation time 356480814 ps
CPU time 3.64 seconds
Started Jul 16 07:58:44 PM PDT 24
Finished Jul 16 07:58:49 PM PDT 24
Peak memory 208460 kb
Host smart-4e4c1ed2-d24e-41a9-9c8e-fff3d54d8cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571069487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.3571069487
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.847634329
Short name T232
Test name
Test status
Simulation time 4167889393 ps
CPU time 32.28 seconds
Started Jul 16 07:58:42 PM PDT 24
Finished Jul 16 07:59:15 PM PDT 24
Peak memory 220548 kb
Host smart-6d361c40-19cd-47a8-acc6-644dadf2f88d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847634329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.847634329
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.2857335772
Short name T849
Test name
Test status
Simulation time 446939981 ps
CPU time 13 seconds
Started Jul 16 07:58:45 PM PDT 24
Finished Jul 16 07:59:01 PM PDT 24
Peak memory 222548 kb
Host smart-2adee3d7-9a36-4257-b3ca-331e4c1ca600
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857335772 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.2857335772
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.75724504
Short name T825
Test name
Test status
Simulation time 84463896 ps
CPU time 3.61 seconds
Started Jul 16 07:58:47 PM PDT 24
Finished Jul 16 07:58:54 PM PDT 24
Peak memory 214332 kb
Host smart-849c0714-4e98-4a1b-8697-233a83541063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75724504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.75724504
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.3791751018
Short name T790
Test name
Test status
Simulation time 62812643 ps
CPU time 2.79 seconds
Started Jul 16 07:58:44 PM PDT 24
Finished Jul 16 07:58:49 PM PDT 24
Peak memory 210008 kb
Host smart-a39ec506-1a42-4b16-aa6f-6fe44b76eb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791751018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.3791751018
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.2254436753
Short name T729
Test name
Test status
Simulation time 42996646 ps
CPU time 0.73 seconds
Started Jul 16 07:58:46 PM PDT 24
Finished Jul 16 07:58:50 PM PDT 24
Peak memory 205940 kb
Host smart-c222bb21-4699-4df0-a45c-392f0ca8dfa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254436753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.2254436753
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2046991418
Short name T721
Test name
Test status
Simulation time 296925811 ps
CPU time 3.34 seconds
Started Jul 16 07:58:46 PM PDT 24
Finished Jul 16 07:58:53 PM PDT 24
Peak memory 206728 kb
Host smart-54e091d7-bcfe-48ed-b695-d79dff62b492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046991418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2046991418
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.2602835802
Short name T77
Test name
Test status
Simulation time 856373366 ps
CPU time 8.77 seconds
Started Jul 16 07:58:45 PM PDT 24
Finished Jul 16 07:58:57 PM PDT 24
Peak memory 209352 kb
Host smart-de5d0180-ffe3-45e6-b435-87ca520bd2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602835802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.2602835802
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.757672598
Short name T106
Test name
Test status
Simulation time 183803581 ps
CPU time 3.28 seconds
Started Jul 16 07:58:42 PM PDT 24
Finished Jul 16 07:58:46 PM PDT 24
Peak memory 208788 kb
Host smart-b5ac463f-bf9a-42a4-b0b6-d33003d02710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757672598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.757672598
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.2151095161
Short name T776
Test name
Test status
Simulation time 87076121 ps
CPU time 2.86 seconds
Started Jul 16 07:58:49 PM PDT 24
Finished Jul 16 07:58:54 PM PDT 24
Peak memory 214204 kb
Host smart-d3ab7864-46f3-4a95-b595-04ee93641103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151095161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.2151095161
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.3695699218
Short name T65
Test name
Test status
Simulation time 83458542 ps
CPU time 3.13 seconds
Started Jul 16 07:58:43 PM PDT 24
Finished Jul 16 07:58:47 PM PDT 24
Peak memory 216000 kb
Host smart-6a388116-28a1-42bc-b728-b13a8b3d3938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695699218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3695699218
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.2322882835
Short name T255
Test name
Test status
Simulation time 1593311962 ps
CPU time 7.87 seconds
Started Jul 16 07:58:44 PM PDT 24
Finished Jul 16 07:58:54 PM PDT 24
Peak memory 208456 kb
Host smart-cbf3dc37-15d2-45c7-834a-ac73b5d68abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322882835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2322882835
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.551617190
Short name T624
Test name
Test status
Simulation time 38179251 ps
CPU time 2.26 seconds
Started Jul 16 07:58:45 PM PDT 24
Finished Jul 16 07:58:50 PM PDT 24
Peak memory 206972 kb
Host smart-ca623f53-9dd5-4dd3-bd66-989d61fd5941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551617190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.551617190
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.4212480995
Short name T545
Test name
Test status
Simulation time 210990246 ps
CPU time 6.19 seconds
Started Jul 16 07:58:42 PM PDT 24
Finished Jul 16 07:58:49 PM PDT 24
Peak memory 208628 kb
Host smart-74c870f9-eb54-4ad6-9776-3e7e9a97282c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212480995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.4212480995
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.1802283836
Short name T287
Test name
Test status
Simulation time 3200448585 ps
CPU time 40.07 seconds
Started Jul 16 07:58:41 PM PDT 24
Finished Jul 16 07:59:22 PM PDT 24
Peak memory 209012 kb
Host smart-72e67151-40ad-4961-bae0-06756a397805
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802283836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.1802283836
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.2188914192
Short name T648
Test name
Test status
Simulation time 1982822578 ps
CPU time 14.56 seconds
Started Jul 16 07:58:49 PM PDT 24
Finished Jul 16 07:59:05 PM PDT 24
Peak memory 206920 kb
Host smart-533bacda-49d1-4ef3-8454-ab1f7be6fcb9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188914192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.2188914192
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.2270387465
Short name T884
Test name
Test status
Simulation time 156432279 ps
CPU time 1.82 seconds
Started Jul 16 07:58:44 PM PDT 24
Finished Jul 16 07:58:49 PM PDT 24
Peak memory 208740 kb
Host smart-1ee4bef2-3153-4d86-afac-b32ec098eb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270387465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.2270387465
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.3227598322
Short name T772
Test name
Test status
Simulation time 127863826 ps
CPU time 3.09 seconds
Started Jul 16 07:58:44 PM PDT 24
Finished Jul 16 07:58:49 PM PDT 24
Peak memory 208836 kb
Host smart-33d3b372-2cfa-44ae-83d1-12f35b500f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227598322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.3227598322
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.247145206
Short name T749
Test name
Test status
Simulation time 39735449 ps
CPU time 0.78 seconds
Started Jul 16 07:58:44 PM PDT 24
Finished Jul 16 07:58:46 PM PDT 24
Peak memory 206008 kb
Host smart-3b7d7a53-29d1-402b-b888-35f8f0e826f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247145206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.247145206
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.2773008864
Short name T395
Test name
Test status
Simulation time 142946959 ps
CPU time 4.1 seconds
Started Jul 16 07:58:45 PM PDT 24
Finished Jul 16 07:58:51 PM PDT 24
Peak memory 207476 kb
Host smart-d576ae88-bc53-44f1-83b7-03c632d10810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773008864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.2773008864
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1323141584
Short name T727
Test name
Test status
Simulation time 17386699 ps
CPU time 0.78 seconds
Started Jul 16 07:58:54 PM PDT 24
Finished Jul 16 07:58:56 PM PDT 24
Peak memory 206080 kb
Host smart-21d497df-e8ff-4afa-a875-db4ad8988bf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323141584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1323141584
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.3696701193
Short name T151
Test name
Test status
Simulation time 33764936 ps
CPU time 2.59 seconds
Started Jul 16 07:58:51 PM PDT 24
Finished Jul 16 07:58:54 PM PDT 24
Peak memory 213868 kb
Host smart-21f77183-1698-4f27-9b7e-f7d903b16e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696701193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.3696701193
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.1440193293
Short name T180
Test name
Test status
Simulation time 396106877 ps
CPU time 1.57 seconds
Started Jul 16 07:58:54 PM PDT 24
Finished Jul 16 07:58:57 PM PDT 24
Peak memory 207648 kb
Host smart-6c64acb4-93e5-484c-bec0-f090e8a12e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440193293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.1440193293
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.3982896693
Short name T285
Test name
Test status
Simulation time 42354645 ps
CPU time 2.2 seconds
Started Jul 16 07:58:57 PM PDT 24
Finished Jul 16 07:59:02 PM PDT 24
Peak memory 209136 kb
Host smart-bd7f83ce-259b-4929-a6c6-8ea56e5828ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982896693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.3982896693
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.3592301105
Short name T215
Test name
Test status
Simulation time 54277106 ps
CPU time 3.1 seconds
Started Jul 16 07:58:58 PM PDT 24
Finished Jul 16 07:59:04 PM PDT 24
Peak memory 220616 kb
Host smart-df4d4272-e7d7-4cd3-b2c0-f80ee85b97ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592301105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.3592301105
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.2421840184
Short name T788
Test name
Test status
Simulation time 216711288 ps
CPU time 2.62 seconds
Started Jul 16 07:58:52 PM PDT 24
Finished Jul 16 07:58:55 PM PDT 24
Peak memory 210576 kb
Host smart-0bf4b8b4-51fc-4b3b-9d67-28ab846d1d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421840184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.2421840184
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.2446114042
Short name T573
Test name
Test status
Simulation time 1028571905 ps
CPU time 8.98 seconds
Started Jul 16 07:58:54 PM PDT 24
Finished Jul 16 07:59:05 PM PDT 24
Peak memory 222504 kb
Host smart-898cae8d-5207-4ce1-a30b-7c0174ca81fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446114042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.2446114042
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.3180202889
Short name T492
Test name
Test status
Simulation time 39602247 ps
CPU time 2.75 seconds
Started Jul 16 07:58:56 PM PDT 24
Finished Jul 16 07:59:03 PM PDT 24
Peak memory 209036 kb
Host smart-adc434a2-67b5-44f4-84b5-39d4045f72c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180202889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.3180202889
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2238012581
Short name T754
Test name
Test status
Simulation time 87254757 ps
CPU time 4.58 seconds
Started Jul 16 07:58:59 PM PDT 24
Finished Jul 16 07:59:08 PM PDT 24
Peak memory 208848 kb
Host smart-4d5bd87c-0ce2-4a30-a48f-aea2a68c8b28
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238012581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2238012581
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.3581794573
Short name T797
Test name
Test status
Simulation time 213061134 ps
CPU time 3.72 seconds
Started Jul 16 07:58:52 PM PDT 24
Finished Jul 16 07:58:57 PM PDT 24
Peak memory 207852 kb
Host smart-cc0b883a-ebb3-4cb6-aea8-6486e3e16b8d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581794573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.3581794573
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.610039027
Short name T730
Test name
Test status
Simulation time 41176322 ps
CPU time 2.38 seconds
Started Jul 16 07:58:54 PM PDT 24
Finished Jul 16 07:58:58 PM PDT 24
Peak memory 208096 kb
Host smart-bc2b5338-4085-4075-8129-ea9fb713d74d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610039027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.610039027
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.1302353472
Short name T891
Test name
Test status
Simulation time 360259638 ps
CPU time 3.73 seconds
Started Jul 16 07:58:53 PM PDT 24
Finished Jul 16 07:58:58 PM PDT 24
Peak memory 214416 kb
Host smart-e575142c-7122-43b2-be57-869d6f5b6caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302353472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.1302353472
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.3362035255
Short name T187
Test name
Test status
Simulation time 36282739 ps
CPU time 2.2 seconds
Started Jul 16 07:58:56 PM PDT 24
Finished Jul 16 07:59:02 PM PDT 24
Peak memory 208280 kb
Host smart-376f048f-4d52-4b7f-8c34-52bb18760be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362035255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.3362035255
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.273792680
Short name T705
Test name
Test status
Simulation time 200991862 ps
CPU time 6 seconds
Started Jul 16 07:58:53 PM PDT 24
Finished Jul 16 07:59:01 PM PDT 24
Peak memory 207060 kb
Host smart-4eb3e8a8-5d56-4662-8ef0-f1382b2fff81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273792680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.273792680
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.2756540005
Short name T126
Test name
Test status
Simulation time 183665973 ps
CPU time 10.34 seconds
Started Jul 16 07:58:54 PM PDT 24
Finished Jul 16 07:59:05 PM PDT 24
Peak memory 222720 kb
Host smart-a6aa9dfa-93fd-4208-b00c-d601bc8d6e26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756540005 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.2756540005
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.3923460511
Short name T612
Test name
Test status
Simulation time 618608266 ps
CPU time 7.64 seconds
Started Jul 16 07:58:50 PM PDT 24
Finished Jul 16 07:58:59 PM PDT 24
Peak memory 218432 kb
Host smart-b164e2f9-15ab-4d77-a576-a6c2a112774a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923460511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.3923460511
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.4070629926
Short name T403
Test name
Test status
Simulation time 521722383 ps
CPU time 3.7 seconds
Started Jul 16 07:58:54 PM PDT 24
Finished Jul 16 07:58:59 PM PDT 24
Peak memory 210036 kb
Host smart-00546913-bb33-4d4c-b4ce-4b16d6ee0a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070629926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.4070629926
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.14172890
Short name T450
Test name
Test status
Simulation time 12170589 ps
CPU time 0.77 seconds
Started Jul 16 07:58:58 PM PDT 24
Finished Jul 16 07:59:04 PM PDT 24
Peak memory 205992 kb
Host smart-cc13c97b-5556-4125-b16e-9e1366393b94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14172890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.14172890
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.206050098
Short name T34
Test name
Test status
Simulation time 315085902 ps
CPU time 2.48 seconds
Started Jul 16 07:58:56 PM PDT 24
Finished Jul 16 07:59:02 PM PDT 24
Peak memory 209804 kb
Host smart-6144c2c1-7ea9-4d47-bf07-cd6edddb1101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206050098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.206050098
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.3618924862
Short name T534
Test name
Test status
Simulation time 978476850 ps
CPU time 14.01 seconds
Started Jul 16 07:58:56 PM PDT 24
Finished Jul 16 07:59:14 PM PDT 24
Peak memory 209596 kb
Host smart-3fc5542b-ee2b-4286-ba65-17a99a2745a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618924862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.3618924862
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.2864387825
Short name T107
Test name
Test status
Simulation time 1205849264 ps
CPU time 6.22 seconds
Started Jul 16 07:58:55 PM PDT 24
Finished Jul 16 07:59:03 PM PDT 24
Peak memory 209552 kb
Host smart-01a98d61-6cb3-41ef-a5d4-c1da5d5f9fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864387825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.2864387825
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.2685189490
Short name T802
Test name
Test status
Simulation time 31578497 ps
CPU time 1.94 seconds
Started Jul 16 07:58:56 PM PDT 24
Finished Jul 16 07:58:59 PM PDT 24
Peak memory 214216 kb
Host smart-939810ac-19c6-4a08-a62c-f6f87685642a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685189490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2685189490
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.239526221
Short name T701
Test name
Test status
Simulation time 72895230 ps
CPU time 5.47 seconds
Started Jul 16 07:58:54 PM PDT 24
Finished Jul 16 07:59:00 PM PDT 24
Peak memory 222632 kb
Host smart-788f73b2-3f41-416f-af90-7f377d45ca8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239526221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.239526221
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.1996070386
Short name T798
Test name
Test status
Simulation time 94357142 ps
CPU time 4.25 seconds
Started Jul 16 07:58:56 PM PDT 24
Finished Jul 16 07:59:01 PM PDT 24
Peak memory 207428 kb
Host smart-8d17b4c1-67df-4872-8c2b-b8bbb9afbadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996070386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.1996070386
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.899590847
Short name T463
Test name
Test status
Simulation time 81346678 ps
CPU time 3.48 seconds
Started Jul 16 07:58:58 PM PDT 24
Finished Jul 16 07:59:07 PM PDT 24
Peak memory 208680 kb
Host smart-1a8d75c6-66d1-424b-8099-1c9b49788bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899590847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.899590847
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.2820990850
Short name T202
Test name
Test status
Simulation time 4589170210 ps
CPU time 14.38 seconds
Started Jul 16 07:58:59 PM PDT 24
Finished Jul 16 07:59:18 PM PDT 24
Peak memory 206968 kb
Host smart-41df358f-2e93-4db1-bad0-31597be2b51e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820990850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.2820990850
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.3195724510
Short name T265
Test name
Test status
Simulation time 91958923 ps
CPU time 2.68 seconds
Started Jul 16 07:58:54 PM PDT 24
Finished Jul 16 07:58:58 PM PDT 24
Peak memory 207300 kb
Host smart-b25998ce-a6a3-456d-8aea-0b80b464cf45
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195724510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.3195724510
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.2645772480
Short name T703
Test name
Test status
Simulation time 778013771 ps
CPU time 6.2 seconds
Started Jul 16 07:58:58 PM PDT 24
Finished Jul 16 07:59:09 PM PDT 24
Peak memory 208696 kb
Host smart-404895ff-f5e3-4165-8ff9-26653b79485f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645772480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.2645772480
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.429761476
Short name T611
Test name
Test status
Simulation time 29509251 ps
CPU time 1.77 seconds
Started Jul 16 07:58:54 PM PDT 24
Finished Jul 16 07:58:57 PM PDT 24
Peak memory 207924 kb
Host smart-830723ba-6195-41ca-ac10-79fe0585c9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429761476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.429761476
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.479817942
Short name T432
Test name
Test status
Simulation time 208877859 ps
CPU time 3.36 seconds
Started Jul 16 07:58:54 PM PDT 24
Finished Jul 16 07:58:59 PM PDT 24
Peak memory 208404 kb
Host smart-13ca0268-3401-40e1-9dd7-1b1d8a7ba870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479817942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.479817942
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.213554034
Short name T247
Test name
Test status
Simulation time 1292206679 ps
CPU time 19.39 seconds
Started Jul 16 07:58:54 PM PDT 24
Finished Jul 16 07:59:14 PM PDT 24
Peak memory 222604 kb
Host smart-90ac6293-5061-46c2-ae1d-37ed06c17be0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213554034 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.213554034
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.154140082
Short name T308
Test name
Test status
Simulation time 67922316 ps
CPU time 2.64 seconds
Started Jul 16 07:58:56 PM PDT 24
Finished Jul 16 07:59:00 PM PDT 24
Peak memory 208240 kb
Host smart-c81dbc72-2569-4939-8cf9-a9f2b9e5b8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154140082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.154140082
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.647740121
Short name T629
Test name
Test status
Simulation time 44788205 ps
CPU time 0.72 seconds
Started Jul 16 07:56:46 PM PDT 24
Finished Jul 16 07:56:51 PM PDT 24
Peak memory 205968 kb
Host smart-b0ad8fac-d212-4cc2-8111-b0791fe2e010
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647740121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.647740121
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.3508344097
Short name T513
Test name
Test status
Simulation time 18159630 ps
CPU time 1.51 seconds
Started Jul 16 07:56:46 PM PDT 24
Finished Jul 16 07:56:51 PM PDT 24
Peak memory 207580 kb
Host smart-d11a8544-69d7-4a2b-96a6-c79fa1027736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508344097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.3508344097
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.1758156024
Short name T348
Test name
Test status
Simulation time 66508159 ps
CPU time 3.05 seconds
Started Jul 16 07:56:45 PM PDT 24
Finished Jul 16 07:56:52 PM PDT 24
Peak memory 214280 kb
Host smart-64dc08d1-1fd9-4853-9a03-6e240a6e8e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758156024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.1758156024
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_random.529370228
Short name T594
Test name
Test status
Simulation time 642899458 ps
CPU time 7.97 seconds
Started Jul 16 07:56:43 PM PDT 24
Finished Jul 16 07:56:53 PM PDT 24
Peak memory 214320 kb
Host smart-6ffdfada-d968-484d-a472-92283b7a7d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529370228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.529370228
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.1018908979
Short name T13
Test name
Test status
Simulation time 439119391 ps
CPU time 10.51 seconds
Started Jul 16 07:56:46 PM PDT 24
Finished Jul 16 07:57:01 PM PDT 24
Peak memory 237260 kb
Host smart-d6a50481-0e3f-4d0f-bb50-a50c416d44b5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018908979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.1018908979
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.3066263555
Short name T219
Test name
Test status
Simulation time 124836548 ps
CPU time 2.9 seconds
Started Jul 16 07:56:41 PM PDT 24
Finished Jul 16 07:56:45 PM PDT 24
Peak memory 206872 kb
Host smart-6e78fe53-9ae8-4654-8503-1e9c00b577a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066263555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.3066263555
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.362785237
Short name T482
Test name
Test status
Simulation time 46132450 ps
CPU time 1.78 seconds
Started Jul 16 07:56:44 PM PDT 24
Finished Jul 16 07:56:48 PM PDT 24
Peak memory 207228 kb
Host smart-cab8dc41-ea5e-449f-9716-1189d60dfce4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362785237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.362785237
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.812287977
Short name T564
Test name
Test status
Simulation time 260150486 ps
CPU time 2.36 seconds
Started Jul 16 07:56:44 PM PDT 24
Finished Jul 16 07:56:49 PM PDT 24
Peak memory 206932 kb
Host smart-b4b9a526-49bf-4b3a-9215-18db60899f29
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812287977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.812287977
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.1450135768
Short name T783
Test name
Test status
Simulation time 263215898 ps
CPU time 5.29 seconds
Started Jul 16 07:56:45 PM PDT 24
Finished Jul 16 07:56:53 PM PDT 24
Peak memory 208836 kb
Host smart-2d42516b-f047-4d4d-bcd4-0e6f751547cf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450135768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.1450135768
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.4076260328
Short name T315
Test name
Test status
Simulation time 83655113 ps
CPU time 4.13 seconds
Started Jul 16 07:56:48 PM PDT 24
Finished Jul 16 07:56:56 PM PDT 24
Peak memory 209660 kb
Host smart-dbb54cf4-9a60-42c5-b903-08a78d0f46a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076260328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.4076260328
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.2791846948
Short name T828
Test name
Test status
Simulation time 305544231 ps
CPU time 2.49 seconds
Started Jul 16 07:56:44 PM PDT 24
Finished Jul 16 07:56:50 PM PDT 24
Peak memory 206816 kb
Host smart-3bcd0120-036b-4fa2-af02-342202c10a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791846948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.2791846948
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.4117122930
Short name T228
Test name
Test status
Simulation time 9382315676 ps
CPU time 110.64 seconds
Started Jul 16 07:56:47 PM PDT 24
Finished Jul 16 07:58:41 PM PDT 24
Peak memory 222536 kb
Host smart-50b272d5-586e-491b-96bc-5842c856e985
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117122930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.4117122930
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.2059102333
Short name T388
Test name
Test status
Simulation time 172997628 ps
CPU time 3.95 seconds
Started Jul 16 07:56:46 PM PDT 24
Finished Jul 16 07:56:54 PM PDT 24
Peak memory 214344 kb
Host smart-13c335e6-9f2a-42e2-a9ac-7fe3289f9fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059102333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.2059102333
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.3723933386
Short name T174
Test name
Test status
Simulation time 366442872 ps
CPU time 1.84 seconds
Started Jul 16 07:56:45 PM PDT 24
Finished Jul 16 07:56:51 PM PDT 24
Peak memory 209480 kb
Host smart-d03d5430-8264-4d43-9115-9cb71614fb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723933386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.3723933386
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.895019731
Short name T745
Test name
Test status
Simulation time 15141236 ps
CPU time 0.97 seconds
Started Jul 16 07:58:58 PM PDT 24
Finished Jul 16 07:59:03 PM PDT 24
Peak memory 206060 kb
Host smart-9cb427bc-fc5a-47e5-991b-03e1c76acdb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895019731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.895019731
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.4036245667
Short name T354
Test name
Test status
Simulation time 916882922 ps
CPU time 12.38 seconds
Started Jul 16 07:58:55 PM PDT 24
Finished Jul 16 07:59:09 PM PDT 24
Peak memory 215340 kb
Host smart-7a43ff55-f846-4640-83ba-7261d11f249d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4036245667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.4036245667
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.2226874165
Short name T226
Test name
Test status
Simulation time 197905547 ps
CPU time 4.33 seconds
Started Jul 16 07:58:58 PM PDT 24
Finished Jul 16 07:59:06 PM PDT 24
Peak memory 222364 kb
Host smart-954b46e4-9beb-4df2-bb7a-e2010e1db516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226874165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.2226874165
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.1096105336
Short name T551
Test name
Test status
Simulation time 46858726 ps
CPU time 2.46 seconds
Started Jul 16 07:58:57 PM PDT 24
Finished Jul 16 07:59:03 PM PDT 24
Peak memory 207664 kb
Host smart-1a4f7155-1a5c-4e6c-93dc-86d893023523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096105336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.1096105336
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.3845808412
Short name T224
Test name
Test status
Simulation time 179918095 ps
CPU time 4.32 seconds
Started Jul 16 07:58:58 PM PDT 24
Finished Jul 16 07:59:06 PM PDT 24
Peak memory 214364 kb
Host smart-ef58b789-3e7c-4203-be8d-8734aa962e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845808412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.3845808412
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.1674489031
Short name T377
Test name
Test status
Simulation time 373158605 ps
CPU time 3.28 seconds
Started Jul 16 07:58:56 PM PDT 24
Finished Jul 16 07:59:02 PM PDT 24
Peak memory 214240 kb
Host smart-9a39625d-9b00-4dc9-9f95-c2f1485a2bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674489031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.1674489031
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.819881130
Short name T235
Test name
Test status
Simulation time 373966371 ps
CPU time 3.04 seconds
Started Jul 16 07:59:01 PM PDT 24
Finished Jul 16 07:59:07 PM PDT 24
Peak memory 216624 kb
Host smart-ce247406-aef6-46ef-9a34-ad791a9fcc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819881130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.819881130
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.1679986819
Short name T498
Test name
Test status
Simulation time 178026348 ps
CPU time 7.32 seconds
Started Jul 16 07:59:01 PM PDT 24
Finished Jul 16 07:59:12 PM PDT 24
Peak memory 209388 kb
Host smart-4e118c7a-9463-4523-91e5-2f5348281794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679986819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1679986819
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.769950319
Short name T454
Test name
Test status
Simulation time 2096652747 ps
CPU time 14.06 seconds
Started Jul 16 07:58:57 PM PDT 24
Finished Jul 16 07:59:14 PM PDT 24
Peak memory 208564 kb
Host smart-152ea3dc-aae0-4ee8-9108-1ac90a9d46fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769950319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.769950319
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.3209073483
Short name T445
Test name
Test status
Simulation time 55170994 ps
CPU time 3.05 seconds
Started Jul 16 07:59:01 PM PDT 24
Finished Jul 16 07:59:07 PM PDT 24
Peak memory 208604 kb
Host smart-df2ed4e8-b4f0-4334-8af1-66f2fc2b23ee
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209073483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.3209073483
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.2565774927
Short name T654
Test name
Test status
Simulation time 187073086 ps
CPU time 4.18 seconds
Started Jul 16 07:58:55 PM PDT 24
Finished Jul 16 07:59:00 PM PDT 24
Peak memory 208968 kb
Host smart-d715aad8-2e5c-49c7-9ffa-86ccd10fc709
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565774927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.2565774927
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.924844965
Short name T907
Test name
Test status
Simulation time 32333413 ps
CPU time 2.19 seconds
Started Jul 16 07:58:53 PM PDT 24
Finished Jul 16 07:58:57 PM PDT 24
Peak memory 206948 kb
Host smart-2f05fe4a-9888-4d30-a615-44be9e974312
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924844965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.924844965
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.598031022
Short name T220
Test name
Test status
Simulation time 31991841 ps
CPU time 2.03 seconds
Started Jul 16 07:58:58 PM PDT 24
Finished Jul 16 07:59:04 PM PDT 24
Peak memory 209464 kb
Host smart-eff3537c-5e43-4861-ad95-faeeba527e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598031022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.598031022
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.330116683
Short name T444
Test name
Test status
Simulation time 550459409 ps
CPU time 3.78 seconds
Started Jul 16 07:58:58 PM PDT 24
Finished Jul 16 07:59:06 PM PDT 24
Peak memory 208660 kb
Host smart-89540e43-7179-4b49-9bfa-37be0b366b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330116683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.330116683
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.2040966212
Short name T856
Test name
Test status
Simulation time 2836423242 ps
CPU time 39.94 seconds
Started Jul 16 07:58:56 PM PDT 24
Finished Jul 16 07:59:39 PM PDT 24
Peak memory 222556 kb
Host smart-917b3b0e-1665-4030-9abb-fca81ed3003a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040966212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.2040966212
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.1947050265
Short name T578
Test name
Test status
Simulation time 1277438672 ps
CPU time 15.08 seconds
Started Jul 16 07:58:58 PM PDT 24
Finished Jul 16 07:59:17 PM PDT 24
Peak memory 220600 kb
Host smart-3424c410-9777-44c0-a522-a07605ee9891
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947050265 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.1947050265
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.452274439
Short name T289
Test name
Test status
Simulation time 55602367 ps
CPU time 2.35 seconds
Started Jul 16 07:58:56 PM PDT 24
Finished Jul 16 07:59:02 PM PDT 24
Peak memory 207940 kb
Host smart-0d03b170-ebf4-4a82-9fc8-41a464792f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452274439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.452274439
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.2177307740
Short name T66
Test name
Test status
Simulation time 7876301567 ps
CPU time 12.63 seconds
Started Jul 16 07:58:55 PM PDT 24
Finished Jul 16 07:59:09 PM PDT 24
Peak memory 211576 kb
Host smart-cd64bf94-8735-4933-9914-2edc35fddb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177307740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.2177307740
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.411965891
Short name T472
Test name
Test status
Simulation time 44566476 ps
CPU time 0.72 seconds
Started Jul 16 07:59:00 PM PDT 24
Finished Jul 16 07:59:04 PM PDT 24
Peak memory 205960 kb
Host smart-76fa09ef-d6d9-4237-9a7c-db419aa2c713
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411965891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.411965891
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.755594262
Short name T913
Test name
Test status
Simulation time 95994689 ps
CPU time 2.66 seconds
Started Jul 16 07:58:57 PM PDT 24
Finished Jul 16 07:59:03 PM PDT 24
Peak memory 222696 kb
Host smart-4ead9ac1-b51f-4f49-9b35-fab8f4f0f9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755594262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.755594262
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.1419865632
Short name T333
Test name
Test status
Simulation time 100217070 ps
CPU time 2.79 seconds
Started Jul 16 08:00:56 PM PDT 24
Finished Jul 16 08:01:00 PM PDT 24
Peak memory 214324 kb
Host smart-4d4d638b-c7de-4652-bd23-18f720e28423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419865632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.1419865632
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.2959539358
Short name T669
Test name
Test status
Simulation time 656256179 ps
CPU time 5.04 seconds
Started Jul 16 07:58:58 PM PDT 24
Finished Jul 16 07:59:08 PM PDT 24
Peak memory 214356 kb
Host smart-190175a6-03ff-4c63-abc6-8690f8af4e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959539358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.2959539358
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.2156622184
Short name T298
Test name
Test status
Simulation time 664782557 ps
CPU time 3.29 seconds
Started Jul 16 07:58:56 PM PDT 24
Finished Jul 16 07:59:03 PM PDT 24
Peak memory 214624 kb
Host smart-952ef1c3-41a1-4309-b3ba-18858ed64048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156622184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.2156622184
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.4245943225
Short name T246
Test name
Test status
Simulation time 480832165 ps
CPU time 8.97 seconds
Started Jul 16 07:58:57 PM PDT 24
Finished Jul 16 07:59:10 PM PDT 24
Peak memory 209348 kb
Host smart-659daceb-4d98-4647-91a8-57f9147406fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245943225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.4245943225
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.2041117063
Short name T92
Test name
Test status
Simulation time 1192057995 ps
CPU time 6.97 seconds
Started Jul 16 07:59:01 PM PDT 24
Finished Jul 16 07:59:11 PM PDT 24
Peak memory 209444 kb
Host smart-ef05d09a-9cd7-4a2f-b47c-5ca16ca7942f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041117063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.2041117063
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.1467057236
Short name T386
Test name
Test status
Simulation time 185242427 ps
CPU time 2.61 seconds
Started Jul 16 07:58:56 PM PDT 24
Finished Jul 16 07:59:01 PM PDT 24
Peak memory 208112 kb
Host smart-96ce94d9-791d-4059-8704-29d2c3f3b486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467057236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.1467057236
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.3469630769
Short name T728
Test name
Test status
Simulation time 525365311 ps
CPU time 4.14 seconds
Started Jul 16 07:58:57 PM PDT 24
Finished Jul 16 07:59:04 PM PDT 24
Peak memory 206856 kb
Host smart-d3719f3f-599f-4822-94ce-4769103de823
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469630769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.3469630769
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.4130886810
Short name T490
Test name
Test status
Simulation time 488033691 ps
CPU time 3.96 seconds
Started Jul 16 07:58:56 PM PDT 24
Finished Jul 16 07:59:02 PM PDT 24
Peak memory 206972 kb
Host smart-e59c4a8a-8852-4737-83e1-d7ee5956e257
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130886810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.4130886810
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.1059549822
Short name T753
Test name
Test status
Simulation time 3969959876 ps
CPU time 27.76 seconds
Started Jul 16 07:58:57 PM PDT 24
Finished Jul 16 07:59:28 PM PDT 24
Peak memory 209076 kb
Host smart-523ea8b7-bb57-4398-808c-9eb375d17791
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059549822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.1059549822
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.748736792
Short name T389
Test name
Test status
Simulation time 34186245 ps
CPU time 2.37 seconds
Started Jul 16 07:59:01 PM PDT 24
Finished Jul 16 07:59:07 PM PDT 24
Peak memory 216216 kb
Host smart-31799899-781e-44e5-b218-727c79f0b0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748736792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.748736792
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.2577436954
Short name T665
Test name
Test status
Simulation time 822168352 ps
CPU time 5.94 seconds
Started Jul 16 07:58:58 PM PDT 24
Finished Jul 16 07:59:08 PM PDT 24
Peak memory 208200 kb
Host smart-44bae99b-93b0-4db6-8665-fc5609fdc8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577436954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.2577436954
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.3639049982
Short name T243
Test name
Test status
Simulation time 580535760 ps
CPU time 3.96 seconds
Started Jul 16 07:58:58 PM PDT 24
Finished Jul 16 07:59:07 PM PDT 24
Peak memory 219524 kb
Host smart-d2df6c29-fde0-4ed2-9446-af10d790ce23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639049982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.3639049982
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.3148089886
Short name T342
Test name
Test status
Simulation time 63037504 ps
CPU time 2.5 seconds
Started Jul 16 07:58:57 PM PDT 24
Finished Jul 16 07:59:03 PM PDT 24
Peak memory 207496 kb
Host smart-8a299887-2c97-43d8-9a10-7f6e806b3440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148089886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.3148089886
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.582760864
Short name T608
Test name
Test status
Simulation time 24470334 ps
CPU time 1.65 seconds
Started Jul 16 07:59:00 PM PDT 24
Finished Jul 16 07:59:05 PM PDT 24
Peak memory 209740 kb
Host smart-7b8d4cbb-efe6-4581-8e33-74858c5af3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582760864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.582760864
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.4134891004
Short name T431
Test name
Test status
Simulation time 138522812 ps
CPU time 0.76 seconds
Started Jul 16 07:58:58 PM PDT 24
Finished Jul 16 07:59:02 PM PDT 24
Peak memory 206016 kb
Host smart-7b371401-0bdc-4c76-92ee-4cba2f767cf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134891004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.4134891004
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.3514152264
Short name T269
Test name
Test status
Simulation time 344832197 ps
CPU time 2.93 seconds
Started Jul 16 07:59:04 PM PDT 24
Finished Jul 16 07:59:08 PM PDT 24
Peak memory 214328 kb
Host smart-c585e999-0386-41ac-9baf-be6b161864ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3514152264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.3514152264
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.156968852
Short name T855
Test name
Test status
Simulation time 27543190 ps
CPU time 1.85 seconds
Started Jul 16 07:59:01 PM PDT 24
Finished Jul 16 07:59:06 PM PDT 24
Peak memory 210080 kb
Host smart-a37e348d-5081-4588-a696-2ba9aca621f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156968852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.156968852
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.2362679912
Short name T69
Test name
Test status
Simulation time 114545491 ps
CPU time 2.87 seconds
Started Jul 16 07:59:00 PM PDT 24
Finished Jul 16 07:59:07 PM PDT 24
Peak memory 209144 kb
Host smart-eec0dc86-0755-4504-a335-8a772e1323ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362679912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.2362679912
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.1355356629
Short name T104
Test name
Test status
Simulation time 1926770689 ps
CPU time 24.9 seconds
Started Jul 16 07:58:58 PM PDT 24
Finished Jul 16 07:59:27 PM PDT 24
Peak memory 209612 kb
Host smart-54b14b9d-abde-4e7a-832d-0d146faefdad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355356629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.1355356629
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.3659642742
Short name T863
Test name
Test status
Simulation time 139592885 ps
CPU time 2.57 seconds
Started Jul 16 07:58:57 PM PDT 24
Finished Jul 16 07:59:04 PM PDT 24
Peak memory 214280 kb
Host smart-f7cc01e5-c659-41bc-a8c1-dc0704eab81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659642742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.3659642742
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.3766336526
Short name T225
Test name
Test status
Simulation time 116613377 ps
CPU time 3.53 seconds
Started Jul 16 07:58:58 PM PDT 24
Finished Jul 16 07:59:06 PM PDT 24
Peak memory 209084 kb
Host smart-a1eaf3bd-683a-4161-bf97-2a49a32db4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766336526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.3766336526
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2286062434
Short name T778
Test name
Test status
Simulation time 109340795 ps
CPU time 2.97 seconds
Started Jul 16 07:59:01 PM PDT 24
Finished Jul 16 07:59:07 PM PDT 24
Peak memory 208296 kb
Host smart-4ab6e326-41c4-4168-8214-dfc97d6e0e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286062434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2286062434
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.2361099960
Short name T188
Test name
Test status
Simulation time 1356963366 ps
CPU time 30.52 seconds
Started Jul 16 07:58:56 PM PDT 24
Finished Jul 16 07:59:29 PM PDT 24
Peak memory 208328 kb
Host smart-1411f146-2f9d-4814-ae79-57b88955f11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361099960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.2361099960
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3372278535
Short name T887
Test name
Test status
Simulation time 55620194 ps
CPU time 2.89 seconds
Started Jul 16 07:58:58 PM PDT 24
Finished Jul 16 07:59:06 PM PDT 24
Peak memory 208068 kb
Host smart-c3d9d1ff-95ba-4a76-ba2d-b881bce8220c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372278535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3372278535
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.399953071
Short name T860
Test name
Test status
Simulation time 418210656 ps
CPU time 3.65 seconds
Started Jul 16 07:58:58 PM PDT 24
Finished Jul 16 07:59:07 PM PDT 24
Peak memory 208832 kb
Host smart-216bb576-8011-4d45-b5a1-278262a0fda9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399953071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.399953071
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.3049201162
Short name T411
Test name
Test status
Simulation time 126982681 ps
CPU time 3.29 seconds
Started Jul 16 07:58:58 PM PDT 24
Finished Jul 16 07:59:06 PM PDT 24
Peak memory 206956 kb
Host smart-28350cc1-51e0-40b1-b626-06e358cc094f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049201162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3049201162
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.3412178601
Short name T854
Test name
Test status
Simulation time 113560643 ps
CPU time 1.62 seconds
Started Jul 16 07:59:00 PM PDT 24
Finished Jul 16 07:59:05 PM PDT 24
Peak memory 208136 kb
Host smart-85f1ca85-1eaf-4e75-ab16-15cb527d8960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412178601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.3412178601
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.186549586
Short name T588
Test name
Test status
Simulation time 79222357 ps
CPU time 1.66 seconds
Started Jul 16 07:58:58 PM PDT 24
Finished Jul 16 07:59:04 PM PDT 24
Peak memory 206920 kb
Host smart-c0bc569b-a0fe-4847-85d2-b6ec03d5d3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186549586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.186549586
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.2114376197
Short name T324
Test name
Test status
Simulation time 520798736 ps
CPU time 21.51 seconds
Started Jul 16 07:58:58 PM PDT 24
Finished Jul 16 07:59:23 PM PDT 24
Peak memory 215112 kb
Host smart-a801daee-6bcd-4c34-aad9-73d1ff2c8bc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114376197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.2114376197
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.1939018454
Short name T637
Test name
Test status
Simulation time 28725304 ps
CPU time 2.13 seconds
Started Jul 16 07:58:58 PM PDT 24
Finished Jul 16 07:59:03 PM PDT 24
Peak memory 207540 kb
Host smart-b3ad93a2-08e1-4d26-bbb0-99afdd91a66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939018454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.1939018454
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.1513524582
Short name T399
Test name
Test status
Simulation time 109766955 ps
CPU time 2.81 seconds
Started Jul 16 07:59:01 PM PDT 24
Finished Jul 16 07:59:07 PM PDT 24
Peak memory 210572 kb
Host smart-24e49580-4fb1-40a8-88a0-d3bf502c9852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513524582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.1513524582
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.1091584405
Short name T746
Test name
Test status
Simulation time 8405073 ps
CPU time 0.8 seconds
Started Jul 16 07:59:09 PM PDT 24
Finished Jul 16 07:59:13 PM PDT 24
Peak memory 206012 kb
Host smart-6055da50-7bba-4ddc-8b69-e963ca080aa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091584405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.1091584405
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.814272448
Short name T271
Test name
Test status
Simulation time 125251346 ps
CPU time 3.65 seconds
Started Jul 16 07:58:56 PM PDT 24
Finished Jul 16 07:59:03 PM PDT 24
Peak memory 215072 kb
Host smart-71a9aaa8-a69a-412e-a8fc-1a5fdbd562ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=814272448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.814272448
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.2907145178
Short name T858
Test name
Test status
Simulation time 67880047 ps
CPU time 2.97 seconds
Started Jul 16 07:59:10 PM PDT 24
Finished Jul 16 07:59:17 PM PDT 24
Peak memory 208664 kb
Host smart-86198095-45fa-428f-ac18-2dbf82153b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907145178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.2907145178
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.3706492243
Short name T78
Test name
Test status
Simulation time 25037690 ps
CPU time 1.99 seconds
Started Jul 16 07:58:58 PM PDT 24
Finished Jul 16 07:59:04 PM PDT 24
Peak memory 207720 kb
Host smart-c1f59268-773a-47fe-aded-2d1c7fb84329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706492243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.3706492243
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.3928908476
Short name T795
Test name
Test status
Simulation time 122857283 ps
CPU time 2.73 seconds
Started Jul 16 07:59:11 PM PDT 24
Finished Jul 16 07:59:19 PM PDT 24
Peak memory 214420 kb
Host smart-4cf783ff-b178-412a-ac49-8f4fa152fdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928908476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.3928908476
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.2749049612
Short name T698
Test name
Test status
Simulation time 194081970 ps
CPU time 3.36 seconds
Started Jul 16 07:59:13 PM PDT 24
Finished Jul 16 07:59:22 PM PDT 24
Peak memory 214256 kb
Host smart-2be894fa-df17-43ff-b3b8-a4dbb299072d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749049612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.2749049612
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.2144255150
Short name T8
Test name
Test status
Simulation time 380398179 ps
CPU time 3.19 seconds
Started Jul 16 07:59:12 PM PDT 24
Finished Jul 16 07:59:21 PM PDT 24
Peak memory 214300 kb
Host smart-b51f41da-2e1f-4a8e-b0e3-f72b7efc5ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144255150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.2144255150
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.2478102276
Short name T218
Test name
Test status
Simulation time 40741787 ps
CPU time 2.83 seconds
Started Jul 16 07:58:56 PM PDT 24
Finished Jul 16 07:59:02 PM PDT 24
Peak memory 218012 kb
Host smart-d260bb2c-894e-461a-b407-f2d2184e13df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478102276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.2478102276
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.1217493308
Short name T709
Test name
Test status
Simulation time 221631671 ps
CPU time 6.66 seconds
Started Jul 16 07:58:57 PM PDT 24
Finished Jul 16 07:59:07 PM PDT 24
Peak memory 208656 kb
Host smart-4814dd2f-bc3f-460f-a1f4-8a9e3776c23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217493308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.1217493308
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.2237752569
Short name T867
Test name
Test status
Simulation time 40666525 ps
CPU time 2.08 seconds
Started Jul 16 07:58:57 PM PDT 24
Finished Jul 16 07:59:03 PM PDT 24
Peak memory 207704 kb
Host smart-218e1a31-bc26-41d4-87dd-1b88b2b48a66
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237752569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2237752569
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.2566275737
Short name T390
Test name
Test status
Simulation time 75090477 ps
CPU time 1.96 seconds
Started Jul 16 07:58:58 PM PDT 24
Finished Jul 16 07:59:04 PM PDT 24
Peak memory 206940 kb
Host smart-4a72f2aa-e270-41cf-9c8c-7c7492e25eb4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566275737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.2566275737
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.4159023227
Short name T537
Test name
Test status
Simulation time 114118369 ps
CPU time 4.27 seconds
Started Jul 16 07:58:56 PM PDT 24
Finished Jul 16 07:59:04 PM PDT 24
Peak memory 206856 kb
Host smart-c40d001d-5ba2-4f08-b2dd-55e29b1b3625
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159023227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.4159023227
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.988386152
Short name T645
Test name
Test status
Simulation time 294042410 ps
CPU time 3.37 seconds
Started Jul 16 07:59:08 PM PDT 24
Finished Jul 16 07:59:14 PM PDT 24
Peak memory 210436 kb
Host smart-ba20e2f0-b5c1-4ab9-9bc6-1671a9a5297e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988386152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.988386152
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.2776589739
Short name T486
Test name
Test status
Simulation time 369442384 ps
CPU time 3.57 seconds
Started Jul 16 07:58:58 PM PDT 24
Finished Jul 16 07:59:06 PM PDT 24
Peak memory 208424 kb
Host smart-864df696-f5a5-496c-94f0-3f1ae7904ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776589739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.2776589739
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.148353291
Short name T319
Test name
Test status
Simulation time 561892239 ps
CPU time 20.28 seconds
Started Jul 16 07:59:07 PM PDT 24
Finished Jul 16 07:59:30 PM PDT 24
Peak memory 220064 kb
Host smart-9b85f813-fed1-4ff3-9e71-f11ec4bd9040
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148353291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.148353291
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.999549993
Short name T175
Test name
Test status
Simulation time 576742362 ps
CPU time 20.41 seconds
Started Jul 16 07:59:08 PM PDT 24
Finished Jul 16 07:59:31 PM PDT 24
Peak memory 222732 kb
Host smart-02e3d361-419d-4bb5-ab46-468fe6342dc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999549993 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.999549993
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.1110176935
Short name T485
Test name
Test status
Simulation time 102759292 ps
CPU time 3.65 seconds
Started Jul 16 07:59:06 PM PDT 24
Finished Jul 16 07:59:12 PM PDT 24
Peak memory 207260 kb
Host smart-c09c2ad1-e1dc-4092-9b53-aafed3941a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110176935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.1110176935
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.3457136207
Short name T833
Test name
Test status
Simulation time 421057150 ps
CPU time 2.93 seconds
Started Jul 16 07:59:11 PM PDT 24
Finished Jul 16 07:59:17 PM PDT 24
Peak memory 210888 kb
Host smart-f532b594-3ee2-4ec2-8e54-a905e5c249ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457136207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.3457136207
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.3654542508
Short name T1
Test name
Test status
Simulation time 14235687 ps
CPU time 0.77 seconds
Started Jul 16 07:59:08 PM PDT 24
Finished Jul 16 07:59:11 PM PDT 24
Peak memory 206000 kb
Host smart-7b529279-db31-44cc-a011-98b33dd64180
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654542508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.3654542508
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.774714301
Short name T29
Test name
Test status
Simulation time 2817605573 ps
CPU time 6 seconds
Started Jul 16 07:59:12 PM PDT 24
Finished Jul 16 07:59:23 PM PDT 24
Peak memory 222948 kb
Host smart-b8b65d84-4631-403b-a00e-99953f743e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774714301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.774714301
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.2705945122
Short name T505
Test name
Test status
Simulation time 20000232 ps
CPU time 1.88 seconds
Started Jul 16 07:59:12 PM PDT 24
Finished Jul 16 07:59:19 PM PDT 24
Peak memory 207788 kb
Host smart-725d60ed-6ca9-46f5-8f05-dca59ffa4911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705945122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.2705945122
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.2677396573
Short name T549
Test name
Test status
Simulation time 117923368 ps
CPU time 3.25 seconds
Started Jul 16 07:59:08 PM PDT 24
Finished Jul 16 07:59:14 PM PDT 24
Peak memory 214280 kb
Host smart-0f177abf-6666-4f65-8e3b-213c6f50b6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677396573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.2677396573
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_random.918936976
Short name T626
Test name
Test status
Simulation time 296629380 ps
CPU time 8.58 seconds
Started Jul 16 07:59:07 PM PDT 24
Finished Jul 16 07:59:17 PM PDT 24
Peak memory 209976 kb
Host smart-e5a2630b-ec5a-4e6e-937f-2bced3e8e1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918936976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.918936976
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.1519051289
Short name T515
Test name
Test status
Simulation time 170463733 ps
CPU time 3.87 seconds
Started Jul 16 07:59:10 PM PDT 24
Finished Jul 16 07:59:17 PM PDT 24
Peak memory 206836 kb
Host smart-910361af-e54c-4da3-9142-cbd2e67afdf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519051289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.1519051289
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.498827012
Short name T773
Test name
Test status
Simulation time 231006675 ps
CPU time 3.28 seconds
Started Jul 16 07:59:12 PM PDT 24
Finished Jul 16 07:59:20 PM PDT 24
Peak memory 208640 kb
Host smart-07668c7b-1408-4433-95fd-ac51b96d605f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498827012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.498827012
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3811389144
Short name T203
Test name
Test status
Simulation time 190903626 ps
CPU time 5.92 seconds
Started Jul 16 07:59:08 PM PDT 24
Finished Jul 16 07:59:17 PM PDT 24
Peak memory 208048 kb
Host smart-84c9ce96-210e-4e81-aed6-e08a7c2698c5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811389144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3811389144
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.2137591160
Short name T716
Test name
Test status
Simulation time 171431901 ps
CPU time 3.02 seconds
Started Jul 16 07:59:15 PM PDT 24
Finished Jul 16 07:59:23 PM PDT 24
Peak memory 207488 kb
Host smart-1195133b-3826-4ff3-b49f-74b1958403a4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137591160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.2137591160
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.2287856355
Short name T675
Test name
Test status
Simulation time 706275600 ps
CPU time 2.42 seconds
Started Jul 16 07:59:09 PM PDT 24
Finished Jul 16 07:59:15 PM PDT 24
Peak memory 209256 kb
Host smart-fbe6018d-c54e-42ac-b9b7-ddd275daaf11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287856355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.2287856355
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3344852860
Short name T531
Test name
Test status
Simulation time 109588866 ps
CPU time 3.03 seconds
Started Jul 16 08:01:51 PM PDT 24
Finished Jul 16 08:01:55 PM PDT 24
Peak memory 208684 kb
Host smart-83378363-4700-4b1e-977d-b66a4195134e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344852860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3344852860
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.2358572769
Short name T520
Test name
Test status
Simulation time 254635059 ps
CPU time 5.7 seconds
Started Jul 16 07:59:14 PM PDT 24
Finished Jul 16 07:59:26 PM PDT 24
Peak memory 209012 kb
Host smart-5e405639-8dd0-49b3-8a66-da25d3644c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358572769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.2358572769
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.3119913835
Short name T893
Test name
Test status
Simulation time 54222985 ps
CPU time 1.63 seconds
Started Jul 16 07:59:10 PM PDT 24
Finished Jul 16 07:59:15 PM PDT 24
Peak memory 209988 kb
Host smart-61224aa4-5e71-416e-9a85-8ceb066be205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119913835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.3119913835
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.1224643241
Short name T435
Test name
Test status
Simulation time 77551344 ps
CPU time 1.06 seconds
Started Jul 16 07:59:08 PM PDT 24
Finished Jul 16 07:59:12 PM PDT 24
Peak memory 206280 kb
Host smart-a778bc32-b93f-478a-a265-5209e7895902
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224643241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.1224643241
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.3108880112
Short name T263
Test name
Test status
Simulation time 110730428 ps
CPU time 3.99 seconds
Started Jul 16 07:59:12 PM PDT 24
Finished Jul 16 07:59:21 PM PDT 24
Peak memory 214304 kb
Host smart-78a3c8cd-e13a-417e-b25a-b48153fee3cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3108880112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.3108880112
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.2755391734
Short name T468
Test name
Test status
Simulation time 90528601 ps
CPU time 2.08 seconds
Started Jul 16 07:59:11 PM PDT 24
Finished Jul 16 07:59:18 PM PDT 24
Peak memory 207196 kb
Host smart-855c1432-6b7b-4b8d-aab2-6f0e3a0d3af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755391734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2755391734
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.791040338
Short name T97
Test name
Test status
Simulation time 26276551 ps
CPU time 2.07 seconds
Started Jul 16 07:59:13 PM PDT 24
Finished Jul 16 07:59:21 PM PDT 24
Peak memory 214416 kb
Host smart-baa53c6a-c6ba-4545-91c8-dc6a719aa027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791040338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.791040338
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.3920239392
Short name T649
Test name
Test status
Simulation time 646773703 ps
CPU time 7.48 seconds
Started Jul 16 07:59:10 PM PDT 24
Finished Jul 16 07:59:20 PM PDT 24
Peak memory 222448 kb
Host smart-76c12e90-d378-447b-946f-ce794c8a85f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920239392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.3920239392
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.242990590
Short name T644
Test name
Test status
Simulation time 225663071 ps
CPU time 3.59 seconds
Started Jul 16 07:59:10 PM PDT 24
Finished Jul 16 07:59:16 PM PDT 24
Peak memory 208372 kb
Host smart-dfbd5d21-b5dd-43f5-9f80-abfcc0d22f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242990590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.242990590
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.4114357979
Short name T621
Test name
Test status
Simulation time 4327883276 ps
CPU time 84.11 seconds
Started Jul 16 07:59:10 PM PDT 24
Finished Jul 16 08:00:36 PM PDT 24
Peak memory 209572 kb
Host smart-42d45531-9a84-4100-b0ac-ed1b438e3f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114357979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.4114357979
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.1803151872
Short name T491
Test name
Test status
Simulation time 22984389 ps
CPU time 1.78 seconds
Started Jul 16 07:59:05 PM PDT 24
Finished Jul 16 07:59:08 PM PDT 24
Peak memory 206968 kb
Host smart-619ef06c-e711-4e3d-974a-93de4c4f9d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803151872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1803151872
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.545253163
Short name T886
Test name
Test status
Simulation time 3699160980 ps
CPU time 21.58 seconds
Started Jul 16 07:59:14 PM PDT 24
Finished Jul 16 07:59:41 PM PDT 24
Peak memory 208308 kb
Host smart-4e9d01ee-edd0-454e-af0d-cd27a3b76e36
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545253163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.545253163
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.117940354
Short name T639
Test name
Test status
Simulation time 80973424 ps
CPU time 3.1 seconds
Started Jul 16 07:59:10 PM PDT 24
Finished Jul 16 07:59:16 PM PDT 24
Peak memory 206796 kb
Host smart-b79636c3-ff93-444f-bb43-89fbd5e98df8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117940354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.117940354
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.1971928581
Short name T668
Test name
Test status
Simulation time 662578280 ps
CPU time 2.81 seconds
Started Jul 16 07:59:10 PM PDT 24
Finished Jul 16 07:59:16 PM PDT 24
Peak memory 208484 kb
Host smart-897903e4-6890-4423-875c-b2fcb57a8c37
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971928581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.1971928581
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.627385972
Short name T302
Test name
Test status
Simulation time 19581332 ps
CPU time 1.66 seconds
Started Jul 16 07:59:08 PM PDT 24
Finished Jul 16 07:59:12 PM PDT 24
Peak memory 209272 kb
Host smart-b0aa0aab-e6d5-4435-ad6e-0f197f56049b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627385972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.627385972
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.845132066
Short name T883
Test name
Test status
Simulation time 205202016 ps
CPU time 2.32 seconds
Started Jul 16 07:59:08 PM PDT 24
Finished Jul 16 07:59:13 PM PDT 24
Peak memory 207084 kb
Host smart-6c16b96b-4da6-48c1-b029-f002a190fba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845132066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.845132066
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.1779676632
Short name T593
Test name
Test status
Simulation time 455943238 ps
CPU time 4.9 seconds
Started Jul 16 07:59:06 PM PDT 24
Finished Jul 16 07:59:13 PM PDT 24
Peak memory 208708 kb
Host smart-20a6aa53-11b8-412b-8d29-299964ea5b48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779676632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.1779676632
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3014246693
Short name T875
Test name
Test status
Simulation time 223911842 ps
CPU time 5.36 seconds
Started Jul 16 07:59:12 PM PDT 24
Finished Jul 16 07:59:23 PM PDT 24
Peak memory 207768 kb
Host smart-95ef5565-60e3-42e6-af3b-263d5dafadfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014246693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3014246693
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.1266389419
Short name T895
Test name
Test status
Simulation time 36208351 ps
CPU time 2.13 seconds
Started Jul 16 07:59:14 PM PDT 24
Finished Jul 16 07:59:22 PM PDT 24
Peak memory 209600 kb
Host smart-cb8f0818-4e17-4562-8713-51d9166863cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266389419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.1266389419
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.385436223
Short name T449
Test name
Test status
Simulation time 20779197 ps
CPU time 0.74 seconds
Started Jul 16 07:59:11 PM PDT 24
Finished Jul 16 07:59:15 PM PDT 24
Peak memory 205984 kb
Host smart-0a953ed7-6c6f-4387-bc2a-f93793bd60b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385436223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.385436223
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.858801051
Short name T428
Test name
Test status
Simulation time 500089453 ps
CPU time 9.15 seconds
Started Jul 16 07:59:11 PM PDT 24
Finished Jul 16 07:59:25 PM PDT 24
Peak memory 215720 kb
Host smart-eed30bfd-aec0-44c0-8d97-ddaa8d874912
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=858801051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.858801051
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.2181722252
Short name T44
Test name
Test status
Simulation time 432811544 ps
CPU time 10.55 seconds
Started Jul 16 07:59:06 PM PDT 24
Finished Jul 16 07:59:18 PM PDT 24
Peak memory 219740 kb
Host smart-5f18f689-f9e3-44d5-9363-7f67e1aff178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181722252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2181722252
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.1078592764
Short name T53
Test name
Test status
Simulation time 118530502 ps
CPU time 3.54 seconds
Started Jul 16 07:59:11 PM PDT 24
Finished Jul 16 07:59:18 PM PDT 24
Peak memory 218212 kb
Host smart-fee6368c-46b5-4703-b2e9-d6546b9310f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078592764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.1078592764
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.2786816356
Short name T275
Test name
Test status
Simulation time 676853947 ps
CPU time 4.21 seconds
Started Jul 16 07:59:08 PM PDT 24
Finished Jul 16 07:59:15 PM PDT 24
Peak memory 221252 kb
Host smart-480349a1-739e-444d-b174-ae23d1deb3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786816356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.2786816356
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.1753137709
Short name T230
Test name
Test status
Simulation time 209259473 ps
CPU time 3.5 seconds
Started Jul 16 07:59:11 PM PDT 24
Finished Jul 16 07:59:18 PM PDT 24
Peak memory 220228 kb
Host smart-c276801c-8401-482e-ba73-3d43f18a2d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753137709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.1753137709
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.2256882375
Short name T343
Test name
Test status
Simulation time 99851703 ps
CPU time 4.84 seconds
Started Jul 16 07:59:12 PM PDT 24
Finished Jul 16 07:59:21 PM PDT 24
Peak memory 214272 kb
Host smart-3aed86a6-3422-4868-862b-283d5d9dc485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256882375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.2256882375
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.3454105957
Short name T577
Test name
Test status
Simulation time 1764136332 ps
CPU time 8.43 seconds
Started Jul 16 07:59:11 PM PDT 24
Finished Jul 16 07:59:23 PM PDT 24
Peak memory 206780 kb
Host smart-b5cdbbfd-4723-4e2f-a8b8-45ef4331e20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454105957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.3454105957
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.3723055715
Short name T496
Test name
Test status
Simulation time 308188580 ps
CPU time 1.87 seconds
Started Jul 16 07:59:09 PM PDT 24
Finished Jul 16 07:59:14 PM PDT 24
Peak memory 206932 kb
Host smart-1e6a81c9-781d-44c4-9cd4-f6f42d38131f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723055715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.3723055715
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1822051940
Short name T211
Test name
Test status
Simulation time 116723423 ps
CPU time 3.58 seconds
Started Jul 16 07:59:12 PM PDT 24
Finished Jul 16 07:59:21 PM PDT 24
Peak memory 208116 kb
Host smart-7f656faf-4ec6-408e-ae22-4aba6adbca2e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822051940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1822051940
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.3712642504
Short name T455
Test name
Test status
Simulation time 141239638 ps
CPU time 4.22 seconds
Started Jul 16 07:59:12 PM PDT 24
Finished Jul 16 07:59:21 PM PDT 24
Peak memory 206752 kb
Host smart-d0cc7b86-e6c4-45fa-9be9-a15e2ff37854
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712642504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.3712642504
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.3092095530
Short name T528
Test name
Test status
Simulation time 171141950 ps
CPU time 2.62 seconds
Started Jul 16 07:59:08 PM PDT 24
Finished Jul 16 07:59:14 PM PDT 24
Peak memory 214296 kb
Host smart-703289a5-ed94-417d-b698-a493bd1c260c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092095530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.3092095530
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.2677602266
Short name T196
Test name
Test status
Simulation time 39600074 ps
CPU time 1.75 seconds
Started Jul 16 07:59:14 PM PDT 24
Finished Jul 16 07:59:21 PM PDT 24
Peak memory 207080 kb
Host smart-a246bcaf-b0e4-4cec-952e-6815b3e3ba60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677602266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.2677602266
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.2862205883
Short name T290
Test name
Test status
Simulation time 285312142 ps
CPU time 6.5 seconds
Started Jul 16 07:59:07 PM PDT 24
Finished Jul 16 07:59:16 PM PDT 24
Peak memory 207612 kb
Host smart-25d3a736-d356-4deb-95f9-db0dbecf5b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862205883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.2862205883
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.2531614229
Short name T62
Test name
Test status
Simulation time 143320612 ps
CPU time 2 seconds
Started Jul 16 07:59:14 PM PDT 24
Finished Jul 16 07:59:22 PM PDT 24
Peak memory 209692 kb
Host smart-d107d2c5-fb14-4646-9361-9b9492578313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531614229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.2531614229
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.3287623305
Short name T442
Test name
Test status
Simulation time 81852053 ps
CPU time 0.75 seconds
Started Jul 16 07:59:11 PM PDT 24
Finished Jul 16 07:59:17 PM PDT 24
Peak memory 205992 kb
Host smart-b8e06cdc-2306-4509-a128-3f18bad52b86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287623305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.3287623305
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.1663847443
Short name T851
Test name
Test status
Simulation time 8860293851 ps
CPU time 95.04 seconds
Started Jul 16 07:59:13 PM PDT 24
Finished Jul 16 08:00:54 PM PDT 24
Peak memory 220188 kb
Host smart-bbdbec7e-43dc-40a9-8a86-fb95c974a73b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1663847443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.1663847443
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.3594522646
Short name T820
Test name
Test status
Simulation time 207038514 ps
CPU time 6.9 seconds
Started Jul 16 07:59:09 PM PDT 24
Finished Jul 16 07:59:18 PM PDT 24
Peak memory 220632 kb
Host smart-ec418dad-dd36-438a-baee-61a61b89fda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594522646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.3594522646
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.3642644768
Short name T70
Test name
Test status
Simulation time 187129755 ps
CPU time 5.06 seconds
Started Jul 16 07:59:14 PM PDT 24
Finished Jul 16 07:59:25 PM PDT 24
Peak memory 219776 kb
Host smart-c00752d5-7114-4cf0-bfa2-2a53ce3a7fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642644768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3642644768
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.3133315456
Short name T110
Test name
Test status
Simulation time 528381414 ps
CPU time 8.02 seconds
Started Jul 16 07:59:17 PM PDT 24
Finished Jul 16 07:59:29 PM PDT 24
Peak memory 214340 kb
Host smart-61128938-3344-4d9e-ac44-e677cfd4f084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133315456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.3133315456
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.219401450
Short name T376
Test name
Test status
Simulation time 33246646 ps
CPU time 2.5 seconds
Started Jul 16 07:59:11 PM PDT 24
Finished Jul 16 07:59:19 PM PDT 24
Peak memory 214212 kb
Host smart-2a3bff68-30f6-4e16-ba29-6d95bc0c58f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219401450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.219401450
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.3009432396
Short name T56
Test name
Test status
Simulation time 110301189 ps
CPU time 3.51 seconds
Started Jul 16 07:59:13 PM PDT 24
Finished Jul 16 07:59:22 PM PDT 24
Peak memory 219812 kb
Host smart-4955f397-6d4d-45ff-8688-86e0af3a7a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009432396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.3009432396
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.1462389157
Short name T526
Test name
Test status
Simulation time 522767168 ps
CPU time 6.71 seconds
Started Jul 16 07:59:11 PM PDT 24
Finished Jul 16 07:59:22 PM PDT 24
Peak memory 214336 kb
Host smart-b0c0bffb-a0e7-4f5b-b148-9e165e9c81ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462389157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1462389157
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1554032999
Short name T321
Test name
Test status
Simulation time 109006268 ps
CPU time 3.93 seconds
Started Jul 16 07:59:14 PM PDT 24
Finished Jul 16 07:59:23 PM PDT 24
Peak memory 208808 kb
Host smart-252fa933-807f-43e7-b2e5-04bf8cde8216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554032999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1554032999
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.2439458615
Short name T193
Test name
Test status
Simulation time 428373658 ps
CPU time 3.5 seconds
Started Jul 16 07:59:15 PM PDT 24
Finished Jul 16 07:59:24 PM PDT 24
Peak memory 207360 kb
Host smart-421dda3f-2173-4787-83cf-41a1d31dbfe9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439458615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.2439458615
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.4229384398
Short name T652
Test name
Test status
Simulation time 93828429 ps
CPU time 1.77 seconds
Started Jul 16 07:59:12 PM PDT 24
Finished Jul 16 07:59:20 PM PDT 24
Peak memory 206948 kb
Host smart-a7bc1217-d917-4574-b27d-a38e691f3d64
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229384398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.4229384398
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.4224253756
Short name T212
Test name
Test status
Simulation time 247575277 ps
CPU time 2.86 seconds
Started Jul 16 07:59:12 PM PDT 24
Finished Jul 16 07:59:21 PM PDT 24
Peak memory 208084 kb
Host smart-7f4998cb-9462-4569-8156-9b4ee2052741
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224253756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.4224253756
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.2128149242
Short name T394
Test name
Test status
Simulation time 396456223 ps
CPU time 4.47 seconds
Started Jul 16 07:59:13 PM PDT 24
Finished Jul 16 07:59:23 PM PDT 24
Peak memory 208176 kb
Host smart-ee9cace6-5451-45b0-a616-4ddba60d5539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128149242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.2128149242
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.1059993673
Short name T666
Test name
Test status
Simulation time 66925710 ps
CPU time 2.26 seconds
Started Jul 16 07:59:13 PM PDT 24
Finished Jul 16 07:59:21 PM PDT 24
Peak memory 208440 kb
Host smart-9147821d-cea2-4f00-aebd-25aba35905b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059993673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.1059993673
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.1283280026
Short name T625
Test name
Test status
Simulation time 3281182383 ps
CPU time 32.75 seconds
Started Jul 16 07:59:13 PM PDT 24
Finished Jul 16 07:59:52 PM PDT 24
Peak memory 210388 kb
Host smart-a24c3c27-6426-440f-9c22-006050f69994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283280026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.1283280026
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2147514412
Short name T402
Test name
Test status
Simulation time 50274614 ps
CPU time 2.23 seconds
Started Jul 16 07:59:12 PM PDT 24
Finished Jul 16 07:59:20 PM PDT 24
Peak memory 210180 kb
Host smart-640f36e7-553b-4d19-9010-47b27182f5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147514412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2147514412
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.4125341853
Short name T780
Test name
Test status
Simulation time 7935646 ps
CPU time 0.77 seconds
Started Jul 16 07:59:15 PM PDT 24
Finished Jul 16 07:59:21 PM PDT 24
Peak memory 205976 kb
Host smart-1d7ad843-35c8-425f-82bf-792ea2a1e479
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125341853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.4125341853
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.918941540
Short name T427
Test name
Test status
Simulation time 144972971 ps
CPU time 2.77 seconds
Started Jul 16 07:59:16 PM PDT 24
Finished Jul 16 07:59:24 PM PDT 24
Peak memory 214748 kb
Host smart-f22482e3-ac18-4b2d-b6b1-65e6298c35be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=918941540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.918941540
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.4136404171
Short name T837
Test name
Test status
Simulation time 104170372 ps
CPU time 2.32 seconds
Started Jul 16 07:59:10 PM PDT 24
Finished Jul 16 07:59:16 PM PDT 24
Peak memory 209284 kb
Host smart-b33ac5e5-a1e7-4b71-9f6b-abd3a9ea6e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136404171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.4136404171
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.705274211
Short name T240
Test name
Test status
Simulation time 288745180 ps
CPU time 3.64 seconds
Started Jul 16 07:59:20 PM PDT 24
Finished Jul 16 07:59:26 PM PDT 24
Peak memory 220000 kb
Host smart-9f377c9d-4837-450b-b2c4-f38cc28d6084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705274211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.705274211
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.2698225870
Short name T300
Test name
Test status
Simulation time 705824384 ps
CPU time 8.87 seconds
Started Jul 16 07:59:17 PM PDT 24
Finished Jul 16 07:59:31 PM PDT 24
Peak memory 218156 kb
Host smart-b2bc9c8c-e72a-4465-9ab5-8f4fad351836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698225870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.2698225870
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.4048994624
Short name T670
Test name
Test status
Simulation time 48508425 ps
CPU time 2.77 seconds
Started Jul 16 07:59:12 PM PDT 24
Finished Jul 16 07:59:20 PM PDT 24
Peak memory 208612 kb
Host smart-22f1233f-f491-4d6d-8182-1d964193746f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048994624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.4048994624
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.3548047550
Short name T792
Test name
Test status
Simulation time 207743718 ps
CPU time 2.94 seconds
Started Jul 16 07:59:14 PM PDT 24
Finished Jul 16 07:59:23 PM PDT 24
Peak memory 208868 kb
Host smart-de15fff1-4ff8-48c2-8469-b2d36e899ae4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548047550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.3548047550
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.2236718570
Short name T507
Test name
Test status
Simulation time 95744341 ps
CPU time 2.65 seconds
Started Jul 16 07:59:16 PM PDT 24
Finished Jul 16 07:59:24 PM PDT 24
Peak memory 206996 kb
Host smart-5e1f03a7-0442-4713-84fb-171a0d579004
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236718570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.2236718570
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.2825232458
Short name T19
Test name
Test status
Simulation time 88893686 ps
CPU time 3.47 seconds
Started Jul 16 07:59:17 PM PDT 24
Finished Jul 16 07:59:25 PM PDT 24
Peak memory 206956 kb
Host smart-df07f58f-7f3e-44c0-b5d1-027ffc0e86b5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825232458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.2825232458
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.999650043
Short name T476
Test name
Test status
Simulation time 374700627 ps
CPU time 2.93 seconds
Started Jul 16 07:59:11 PM PDT 24
Finished Jul 16 07:59:19 PM PDT 24
Peak memory 208984 kb
Host smart-927c0630-c373-4940-8bee-47c3adfca420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999650043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.999650043
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.612638623
Short name T566
Test name
Test status
Simulation time 32808213 ps
CPU time 2.27 seconds
Started Jul 16 07:59:09 PM PDT 24
Finished Jul 16 07:59:14 PM PDT 24
Peak memory 208592 kb
Host smart-465f68b5-3bf7-473f-be35-39bec800b190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612638623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.612638623
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.540654844
Short name T636
Test name
Test status
Simulation time 48880941 ps
CPU time 2.99 seconds
Started Jul 16 07:59:22 PM PDT 24
Finished Jul 16 07:59:27 PM PDT 24
Peak memory 209532 kb
Host smart-983f2567-87c0-4175-98aa-6ce63c4b5b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540654844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.540654844
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1476606053
Short name T67
Test name
Test status
Simulation time 58804041 ps
CPU time 2.78 seconds
Started Jul 16 07:59:16 PM PDT 24
Finished Jul 16 07:59:24 PM PDT 24
Peak memory 210260 kb
Host smart-0518f7d4-43b9-46e3-bf37-0e45cfb517b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476606053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1476606053
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.3488652957
Short name T738
Test name
Test status
Simulation time 16612752 ps
CPU time 0.79 seconds
Started Jul 16 07:59:13 PM PDT 24
Finished Jul 16 07:59:19 PM PDT 24
Peak memory 205972 kb
Host smart-57811b3e-0628-42e4-83b8-900ce9bd39e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488652957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.3488652957
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.3951383313
Short name T702
Test name
Test status
Simulation time 132294851 ps
CPU time 3 seconds
Started Jul 16 07:59:07 PM PDT 24
Finished Jul 16 07:59:11 PM PDT 24
Peak memory 208612 kb
Host smart-90c4320d-59fe-4b92-b69f-3d56241ac4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951383313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.3951383313
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.71455759
Short name T191
Test name
Test status
Simulation time 63386623 ps
CPU time 2.83 seconds
Started Jul 16 07:59:22 PM PDT 24
Finished Jul 16 07:59:26 PM PDT 24
Peak memory 214320 kb
Host smart-6acf75f1-7342-4494-928c-062c0b816d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71455759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.71455759
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1517968983
Short name T109
Test name
Test status
Simulation time 1194008062 ps
CPU time 4.9 seconds
Started Jul 16 07:59:14 PM PDT 24
Finished Jul 16 07:59:25 PM PDT 24
Peak memory 214340 kb
Host smart-53840d8a-3225-4da2-8e48-7481ceec3d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517968983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1517968983
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.1036046617
Short name T90
Test name
Test status
Simulation time 362888510 ps
CPU time 4.61 seconds
Started Jul 16 07:59:12 PM PDT 24
Finished Jul 16 07:59:22 PM PDT 24
Peak memory 214256 kb
Host smart-2c0a1baa-b5a4-473e-8899-2c892f80436f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036046617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.1036046617
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_random.2849217999
Short name T775
Test name
Test status
Simulation time 232384830 ps
CPU time 3.97 seconds
Started Jul 16 07:59:15 PM PDT 24
Finished Jul 16 07:59:24 PM PDT 24
Peak memory 218292 kb
Host smart-bc55053d-4b97-443b-bc84-e735087fa5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849217999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.2849217999
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.3792060642
Short name T813
Test name
Test status
Simulation time 1445654781 ps
CPU time 4.93 seconds
Started Jul 16 07:59:14 PM PDT 24
Finished Jul 16 07:59:24 PM PDT 24
Peak memory 208552 kb
Host smart-b72cfdf1-7a54-4f29-b8d7-3020706ba446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792060642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.3792060642
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.3316109852
Short name T684
Test name
Test status
Simulation time 132927410 ps
CPU time 4.16 seconds
Started Jul 16 07:59:21 PM PDT 24
Finished Jul 16 07:59:27 PM PDT 24
Peak memory 207336 kb
Host smart-09e08b70-ac42-44d9-91f3-d8734941fe00
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316109852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.3316109852
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.1966490702
Short name T380
Test name
Test status
Simulation time 92117350 ps
CPU time 1.92 seconds
Started Jul 16 07:59:21 PM PDT 24
Finished Jul 16 07:59:25 PM PDT 24
Peak memory 208660 kb
Host smart-2c0e53fe-4bcb-42cf-9bbd-b0f4748cfaec
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966490702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.1966490702
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.1673188873
Short name T489
Test name
Test status
Simulation time 53288748 ps
CPU time 2.75 seconds
Started Jul 16 07:59:22 PM PDT 24
Finished Jul 16 07:59:26 PM PDT 24
Peak memory 208552 kb
Host smart-76de0778-868f-455c-82da-59c2ddd1c6e6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673188873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.1673188873
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.4017284226
Short name T603
Test name
Test status
Simulation time 24800353 ps
CPU time 1.34 seconds
Started Jul 16 07:59:11 PM PDT 24
Finished Jul 16 07:59:16 PM PDT 24
Peak memory 207200 kb
Host smart-ab864084-e8b4-412e-8e0d-fa951eb90762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017284226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.4017284226
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.3282232017
Short name T475
Test name
Test status
Simulation time 37659729 ps
CPU time 2.32 seconds
Started Jul 16 07:59:16 PM PDT 24
Finished Jul 16 07:59:23 PM PDT 24
Peak memory 208528 kb
Host smart-37d7fefb-88d7-48bc-9c90-1cf84480b2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282232017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.3282232017
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.3019389450
Short name T140
Test name
Test status
Simulation time 1567624042 ps
CPU time 21.47 seconds
Started Jul 16 07:59:12 PM PDT 24
Finished Jul 16 07:59:39 PM PDT 24
Peak memory 215784 kb
Host smart-ef216fbd-1037-41a5-b44e-a0c96006b50d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019389450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.3019389450
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.1589524076
Short name T844
Test name
Test status
Simulation time 211452472 ps
CPU time 2.18 seconds
Started Jul 16 07:59:15 PM PDT 24
Finished Jul 16 07:59:23 PM PDT 24
Peak memory 208344 kb
Host smart-1d17c361-a536-43aa-8d76-2cdded056dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589524076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1589524076
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.901019852
Short name T199
Test name
Test status
Simulation time 210910158 ps
CPU time 2.42 seconds
Started Jul 16 07:59:15 PM PDT 24
Finished Jul 16 07:59:23 PM PDT 24
Peak memory 210180 kb
Host smart-eebc85db-c151-449b-8521-c121572db16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901019852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.901019852
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.1778642170
Short name T557
Test name
Test status
Simulation time 11042282 ps
CPU time 0.83 seconds
Started Jul 16 07:56:51 PM PDT 24
Finished Jul 16 07:56:55 PM PDT 24
Peak memory 206024 kb
Host smart-134d2d0c-78d8-43c9-970e-55a0b9fd6ca5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778642170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.1778642170
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.3143293854
Short name T296
Test name
Test status
Simulation time 286316973 ps
CPU time 3.62 seconds
Started Jul 16 07:56:49 PM PDT 24
Finished Jul 16 07:56:57 PM PDT 24
Peak memory 214384 kb
Host smart-c64e345b-5b12-4a6b-bb65-6f3e28da4de4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3143293854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.3143293854
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.3335608948
Short name T146
Test name
Test status
Simulation time 317778554 ps
CPU time 3.09 seconds
Started Jul 16 07:56:49 PM PDT 24
Finished Jul 16 07:56:57 PM PDT 24
Peak memory 218316 kb
Host smart-23868c1b-de87-44aa-9e43-aef7a22160bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335608948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.3335608948
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.382781099
Short name T731
Test name
Test status
Simulation time 79111057 ps
CPU time 1.99 seconds
Started Jul 16 07:56:50 PM PDT 24
Finished Jul 16 07:56:56 PM PDT 24
Peak memory 209444 kb
Host smart-472171aa-a3bb-4326-bf36-5fa4d47de291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382781099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.382781099
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.1633111228
Short name T310
Test name
Test status
Simulation time 114003949 ps
CPU time 4.74 seconds
Started Jul 16 07:56:49 PM PDT 24
Finished Jul 16 07:56:58 PM PDT 24
Peak memory 214344 kb
Host smart-72e78a17-8ed2-4dd8-bf38-5ee8426397ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633111228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.1633111228
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.221293539
Short name T185
Test name
Test status
Simulation time 183297444 ps
CPU time 2.9 seconds
Started Jul 16 07:56:50 PM PDT 24
Finished Jul 16 07:56:57 PM PDT 24
Peak memory 220972 kb
Host smart-3830f353-cd61-408d-8939-3b3e7ee1af1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221293539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.221293539
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.4075731500
Short name T318
Test name
Test status
Simulation time 42324224 ps
CPU time 3.18 seconds
Started Jul 16 07:56:50 PM PDT 24
Finished Jul 16 07:56:57 PM PDT 24
Peak memory 210364 kb
Host smart-cbabfdb0-6232-4648-b7fe-51b97e01a55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075731500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.4075731500
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.1218683851
Short name T576
Test name
Test status
Simulation time 760140978 ps
CPU time 6.46 seconds
Started Jul 16 07:56:49 PM PDT 24
Finished Jul 16 07:57:00 PM PDT 24
Peak memory 208196 kb
Host smart-79935646-300a-4807-9e3a-b9c0430c032f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218683851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.1218683851
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.1191834433
Short name T197
Test name
Test status
Simulation time 158580844 ps
CPU time 5.06 seconds
Started Jul 16 07:56:48 PM PDT 24
Finished Jul 16 07:56:57 PM PDT 24
Peak memory 208072 kb
Host smart-d088685e-0342-439a-85fb-3ddedf574500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191834433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.1191834433
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.2770645308
Short name T264
Test name
Test status
Simulation time 105385824 ps
CPU time 2.79 seconds
Started Jul 16 07:56:50 PM PDT 24
Finished Jul 16 07:56:57 PM PDT 24
Peak memory 207244 kb
Host smart-08b9035e-d7a6-42e9-a863-f29125d74f9e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770645308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2770645308
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.2714351417
Short name T357
Test name
Test status
Simulation time 141059469 ps
CPU time 4.87 seconds
Started Jul 16 07:56:48 PM PDT 24
Finished Jul 16 07:56:57 PM PDT 24
Peak memory 208464 kb
Host smart-a59165eb-00b8-4a6b-b940-687371251d52
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714351417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2714351417
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.1444314782
Short name T866
Test name
Test status
Simulation time 1042026473 ps
CPU time 5.62 seconds
Started Jul 16 07:56:49 PM PDT 24
Finished Jul 16 07:56:59 PM PDT 24
Peak memory 207952 kb
Host smart-f4937539-1f31-46e4-a735-2c7ac5a52af9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444314782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.1444314782
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.2145400333
Short name T882
Test name
Test status
Simulation time 1064329455 ps
CPU time 29.56 seconds
Started Jul 16 07:56:49 PM PDT 24
Finished Jul 16 07:57:23 PM PDT 24
Peak memory 209036 kb
Host smart-29beb03e-d0b3-41ef-bbbd-34c773b1c54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145400333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.2145400333
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.1690714577
Short name T584
Test name
Test status
Simulation time 122279995 ps
CPU time 4.42 seconds
Started Jul 16 07:56:46 PM PDT 24
Finished Jul 16 07:56:54 PM PDT 24
Peak memory 207884 kb
Host smart-240ec537-332f-4cca-8bf8-1d3f3b53b1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690714577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.1690714577
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.1849225132
Short name T227
Test name
Test status
Simulation time 148988708 ps
CPU time 5.27 seconds
Started Jul 16 07:56:49 PM PDT 24
Finished Jul 16 07:56:59 PM PDT 24
Peak memory 220144 kb
Host smart-40b7c439-4fe4-4602-827f-a2001745ece5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849225132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.1849225132
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.485779493
Short name T281
Test name
Test status
Simulation time 345151435 ps
CPU time 8.79 seconds
Started Jul 16 07:56:50 PM PDT 24
Finished Jul 16 07:57:03 PM PDT 24
Peak memory 218728 kb
Host smart-36008ba1-0b3b-4f79-b256-4bf49ef0a234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485779493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.485779493
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.2491095486
Short name T736
Test name
Test status
Simulation time 101606176 ps
CPU time 1.51 seconds
Started Jul 16 07:56:55 PM PDT 24
Finished Jul 16 07:56:59 PM PDT 24
Peak memory 209940 kb
Host smart-9b6c770a-71bb-4b74-b370-9d3c4352c379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491095486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.2491095486
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.3936082603
Short name T517
Test name
Test status
Simulation time 17522288 ps
CPU time 0.94 seconds
Started Jul 16 07:56:46 PM PDT 24
Finished Jul 16 07:56:51 PM PDT 24
Peak memory 206104 kb
Host smart-18818674-14fb-4627-b2a8-4616ec965a01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936082603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.3936082603
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.4180946230
Short name T365
Test name
Test status
Simulation time 3810287044 ps
CPU time 99.1 seconds
Started Jul 16 07:56:45 PM PDT 24
Finished Jul 16 07:58:28 PM PDT 24
Peak memory 215936 kb
Host smart-11a7a5d0-8016-4717-a479-745a5a9141dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4180946230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.4180946230
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.2580286365
Short name T862
Test name
Test status
Simulation time 20212827 ps
CPU time 1.61 seconds
Started Jul 16 07:56:41 PM PDT 24
Finished Jul 16 07:56:44 PM PDT 24
Peak memory 207816 kb
Host smart-08c634ec-5c79-489d-bf4c-0f607771e0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580286365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.2580286365
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.38386626
Short name T653
Test name
Test status
Simulation time 94347604 ps
CPU time 4 seconds
Started Jul 16 07:56:41 PM PDT 24
Finished Jul 16 07:56:46 PM PDT 24
Peak memory 214368 kb
Host smart-b4046e7d-447d-43d9-8d8b-b25b644f293b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38386626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.38386626
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.1291084414
Short name T331
Test name
Test status
Simulation time 158793959 ps
CPU time 4.96 seconds
Started Jul 16 07:56:47 PM PDT 24
Finished Jul 16 07:56:56 PM PDT 24
Peak memory 214264 kb
Host smart-603fc1fd-8565-45d1-b3c8-544e865ce8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291084414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.1291084414
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.2190501219
Short name T569
Test name
Test status
Simulation time 78727791 ps
CPU time 2.73 seconds
Started Jul 16 07:56:44 PM PDT 24
Finished Jul 16 07:56:49 PM PDT 24
Peak memory 208604 kb
Host smart-3757cc8b-6344-4689-8bb2-79e76e3723ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190501219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.2190501219
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.3456372660
Short name T674
Test name
Test status
Simulation time 1090158013 ps
CPU time 11.27 seconds
Started Jul 16 07:56:42 PM PDT 24
Finished Jul 16 07:56:54 PM PDT 24
Peak memory 208816 kb
Host smart-7fa8fea8-a1b5-44ca-8f80-164b7530594e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456372660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.3456372660
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.654368372
Short name T412
Test name
Test status
Simulation time 280107070 ps
CPU time 2.69 seconds
Started Jul 16 07:56:51 PM PDT 24
Finished Jul 16 07:56:57 PM PDT 24
Peak memory 207260 kb
Host smart-92d3719e-b25c-4bc0-9e0f-f897899ed4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654368372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.654368372
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.261639111
Short name T723
Test name
Test status
Simulation time 1511887896 ps
CPU time 49.09 seconds
Started Jul 16 07:56:50 PM PDT 24
Finished Jul 16 07:57:43 PM PDT 24
Peak memory 208576 kb
Host smart-b1c3e03b-869f-4ec8-b8ba-abe7b0ff46c2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261639111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.261639111
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.2105141954
Short name T786
Test name
Test status
Simulation time 5417224518 ps
CPU time 42.18 seconds
Started Jul 16 07:56:49 PM PDT 24
Finished Jul 16 07:57:35 PM PDT 24
Peak memory 207424 kb
Host smart-a5b0f168-6540-4977-ab6c-be684f246e8b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105141954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.2105141954
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.1959182542
Short name T601
Test name
Test status
Simulation time 190774561 ps
CPU time 2.21 seconds
Started Jul 16 07:56:45 PM PDT 24
Finished Jul 16 07:56:51 PM PDT 24
Peak memory 218372 kb
Host smart-fd663621-7964-45f6-9355-7142bea2dd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959182542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.1959182542
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.1341873483
Short name T643
Test name
Test status
Simulation time 270959628 ps
CPU time 2.84 seconds
Started Jul 16 07:56:50 PM PDT 24
Finished Jul 16 07:56:57 PM PDT 24
Peak memory 206912 kb
Host smart-7532ae82-52c0-45b2-a779-23f5190fafee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341873483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.1341873483
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.515297925
Short name T210
Test name
Test status
Simulation time 6784609199 ps
CPU time 61.6 seconds
Started Jul 16 07:56:43 PM PDT 24
Finished Jul 16 07:57:46 PM PDT 24
Peak memory 216548 kb
Host smart-922964a2-6375-4099-91e6-98e92041f2b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515297925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.515297925
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.4260072313
Short name T177
Test name
Test status
Simulation time 455859389 ps
CPU time 8.42 seconds
Started Jul 16 07:56:43 PM PDT 24
Finished Jul 16 07:56:54 PM PDT 24
Peak memory 219196 kb
Host smart-1e0b0ecb-a426-4f94-91cc-1aa522bc5a80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260072313 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.4260072313
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.1075878647
Short name T869
Test name
Test status
Simulation time 1922249711 ps
CPU time 43.87 seconds
Started Jul 16 07:56:42 PM PDT 24
Finished Jul 16 07:57:27 PM PDT 24
Peak memory 218204 kb
Host smart-5da5faf0-4122-4d97-9f3e-ca9bc4f07178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075878647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.1075878647
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.2274682307
Short name T779
Test name
Test status
Simulation time 173089873 ps
CPU time 3.8 seconds
Started Jul 16 07:56:41 PM PDT 24
Finished Jul 16 07:56:46 PM PDT 24
Peak memory 210292 kb
Host smart-08f1fd04-6621-49d6-a05b-5c7e88458e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274682307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.2274682307
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.1731530343
Short name T447
Test name
Test status
Simulation time 109021898 ps
CPU time 0.78 seconds
Started Jul 16 07:57:01 PM PDT 24
Finished Jul 16 07:57:03 PM PDT 24
Peak memory 205988 kb
Host smart-2a45be99-a4f0-4166-ab7e-9483c7390a77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731530343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.1731530343
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.4254741886
Short name T426
Test name
Test status
Simulation time 49395243 ps
CPU time 3.51 seconds
Started Jul 16 07:56:45 PM PDT 24
Finished Jul 16 07:56:51 PM PDT 24
Peak memory 215292 kb
Host smart-8390618a-79f8-41b1-93ca-458cb5bac82b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4254741886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.4254741886
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.2387465066
Short name T781
Test name
Test status
Simulation time 81134676 ps
CPU time 2.38 seconds
Started Jul 16 07:56:46 PM PDT 24
Finished Jul 16 07:56:52 PM PDT 24
Peak memory 209416 kb
Host smart-9fa21367-b9c2-4e5a-b6cd-df5d0c2b6b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387465066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2387465066
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.2816925140
Short name T693
Test name
Test status
Simulation time 61329732 ps
CPU time 2.38 seconds
Started Jul 16 07:56:53 PM PDT 24
Finished Jul 16 07:56:58 PM PDT 24
Peak memory 214444 kb
Host smart-6fc41871-3377-4880-a562-7a89acc2cfe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816925140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.2816925140
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.1963724611
Short name T774
Test name
Test status
Simulation time 27982118 ps
CPU time 2.1 seconds
Started Jul 16 07:57:01 PM PDT 24
Finished Jul 16 07:57:05 PM PDT 24
Peak memory 214268 kb
Host smart-d7cf7a3b-cd47-40f4-869e-0f3d2998a0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963724611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.1963724611
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.2219856466
Short name T618
Test name
Test status
Simulation time 84122076 ps
CPU time 3.05 seconds
Started Jul 16 07:57:11 PM PDT 24
Finished Jul 16 07:57:15 PM PDT 24
Peak memory 214264 kb
Host smart-f53f93f6-74e6-4eb4-b02b-dfc4834a7d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219856466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.2219856466
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.218764803
Short name T282
Test name
Test status
Simulation time 902497757 ps
CPU time 6.92 seconds
Started Jul 16 07:56:45 PM PDT 24
Finished Jul 16 07:56:55 PM PDT 24
Peak memory 218456 kb
Host smart-a57136d0-5a42-40c5-873b-42c94b94aad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218764803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.218764803
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.3893537520
Short name T700
Test name
Test status
Simulation time 128938582 ps
CPU time 2.57 seconds
Started Jul 16 07:56:45 PM PDT 24
Finished Jul 16 07:56:50 PM PDT 24
Peak memory 207320 kb
Host smart-f67999c2-954b-4b3b-a2e9-27b6566c28b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893537520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.3893537520
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.1818217405
Short name T441
Test name
Test status
Simulation time 5653863489 ps
CPU time 34.71 seconds
Started Jul 16 07:56:47 PM PDT 24
Finished Jul 16 07:57:26 PM PDT 24
Peak memory 209088 kb
Host smart-0379e3fe-8c8f-4895-ac3d-1b2da986b9f9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818217405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.1818217405
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.512161473
Short name T633
Test name
Test status
Simulation time 60445083 ps
CPU time 2.72 seconds
Started Jul 16 07:56:48 PM PDT 24
Finished Jul 16 07:56:55 PM PDT 24
Peak memory 208708 kb
Host smart-bf3e7294-a48f-4764-9ab0-1ab8f4321e8c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512161473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.512161473
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.316617103
Short name T556
Test name
Test status
Simulation time 330442755 ps
CPU time 4.31 seconds
Started Jul 16 07:56:47 PM PDT 24
Finished Jul 16 07:56:55 PM PDT 24
Peak memory 208660 kb
Host smart-e4d71738-f53f-4890-8792-05f820654e29
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316617103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.316617103
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.27802028
Short name T479
Test name
Test status
Simulation time 894894019 ps
CPU time 2.99 seconds
Started Jul 16 07:57:05 PM PDT 24
Finished Jul 16 07:57:10 PM PDT 24
Peak memory 207820 kb
Host smart-6ce02527-2c4a-4481-8bbe-fdfb38c4c999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27802028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.27802028
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.2795718830
Short name T901
Test name
Test status
Simulation time 67629955 ps
CPU time 1.67 seconds
Started Jul 16 07:56:47 PM PDT 24
Finished Jul 16 07:56:53 PM PDT 24
Peak memory 207212 kb
Host smart-19ed6c06-4b96-44a9-babc-952d5feb7780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795718830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.2795718830
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.3401153541
Short name T71
Test name
Test status
Simulation time 852931703 ps
CPU time 7.8 seconds
Started Jul 16 07:56:56 PM PDT 24
Finished Jul 16 07:57:05 PM PDT 24
Peak memory 216704 kb
Host smart-4a17937e-c0fd-4fd2-9324-74a29df9c24e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401153541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.3401153541
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.2631972700
Short name T125
Test name
Test status
Simulation time 325323143 ps
CPU time 14.28 seconds
Started Jul 16 07:57:12 PM PDT 24
Finished Jul 16 07:57:28 PM PDT 24
Peak memory 222640 kb
Host smart-036fee4d-d33e-45a7-80f9-a920c39666b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631972700 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.2631972700
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2598075780
Short name T834
Test name
Test status
Simulation time 81638969 ps
CPU time 3 seconds
Started Jul 16 07:56:54 PM PDT 24
Finished Jul 16 07:56:59 PM PDT 24
Peak memory 207656 kb
Host smart-313132ff-b7ca-4eab-96b3-fadc3997ceb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598075780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2598075780
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3933410388
Short name T396
Test name
Test status
Simulation time 32775462 ps
CPU time 1.5 seconds
Started Jul 16 07:56:54 PM PDT 24
Finished Jul 16 07:56:58 PM PDT 24
Peak memory 210012 kb
Host smart-42366579-6db7-400b-8e38-21c2ea689013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933410388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3933410388
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.4266688309
Short name T216
Test name
Test status
Simulation time 14603931 ps
CPU time 0.9 seconds
Started Jul 16 07:57:12 PM PDT 24
Finished Jul 16 07:57:14 PM PDT 24
Peak memory 206104 kb
Host smart-abb1b35a-0436-402a-94db-a3b98c78fa9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266688309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.4266688309
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.2331630328
Short name T413
Test name
Test status
Simulation time 283197883 ps
CPU time 14.14 seconds
Started Jul 16 07:56:58 PM PDT 24
Finished Jul 16 07:57:14 PM PDT 24
Peak memory 214328 kb
Host smart-8e39b3d5-3e26-4937-938e-1e3881747c7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2331630328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.2331630328
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.578109739
Short name T84
Test name
Test status
Simulation time 365191659 ps
CPU time 8.64 seconds
Started Jul 16 07:57:04 PM PDT 24
Finished Jul 16 07:57:15 PM PDT 24
Peak memory 208760 kb
Host smart-7598043f-ac4e-4c95-b119-3c6070774a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578109739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.578109739
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.3589867866
Short name T641
Test name
Test status
Simulation time 145561033 ps
CPU time 5.57 seconds
Started Jul 16 07:57:12 PM PDT 24
Finished Jul 16 07:57:18 PM PDT 24
Peak memory 208468 kb
Host smart-5b4ebbbe-a68e-4cfe-ac73-83197f68dd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589867866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.3589867866
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.4246019176
Short name T726
Test name
Test status
Simulation time 107914432 ps
CPU time 3.6 seconds
Started Jul 16 07:57:12 PM PDT 24
Finished Jul 16 07:57:17 PM PDT 24
Peak memory 214324 kb
Host smart-5dd54134-9274-4a30-b307-c5a4bb7b202e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246019176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.4246019176
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.2106012393
Short name T461
Test name
Test status
Simulation time 63564261 ps
CPU time 2.6 seconds
Started Jul 16 07:56:58 PM PDT 24
Finished Jul 16 07:57:02 PM PDT 24
Peak memory 210080 kb
Host smart-513674f1-51c5-4213-993c-10a3bd5bca3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106012393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2106012393
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.2214010117
Short name T824
Test name
Test status
Simulation time 36029452 ps
CPU time 2.63 seconds
Started Jul 16 07:56:54 PM PDT 24
Finished Jul 16 07:56:59 PM PDT 24
Peak memory 208768 kb
Host smart-322d6ff6-adb6-4920-bc09-f4f200a4cc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214010117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.2214010117
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.323080778
Short name T38
Test name
Test status
Simulation time 940042201 ps
CPU time 4.17 seconds
Started Jul 16 07:56:54 PM PDT 24
Finished Jul 16 07:57:00 PM PDT 24
Peak memory 208844 kb
Host smart-51a20208-53f1-46c6-a7e4-419161aafd63
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323080778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.323080778
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.693383522
Short name T326
Test name
Test status
Simulation time 107496480 ps
CPU time 4.47 seconds
Started Jul 16 07:57:03 PM PDT 24
Finished Jul 16 07:57:09 PM PDT 24
Peak memory 208860 kb
Host smart-ab89cf51-5091-4060-99c4-6376406f3c57
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693383522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.693383522
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.2138406153
Short name T563
Test name
Test status
Simulation time 1854696202 ps
CPU time 56.71 seconds
Started Jul 16 07:57:02 PM PDT 24
Finished Jul 16 07:58:00 PM PDT 24
Peak memory 208352 kb
Host smart-bb95a61e-887a-4711-82bf-c2f44ff1db0d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138406153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.2138406153
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.572652161
Short name T787
Test name
Test status
Simulation time 102130628 ps
CPU time 2.93 seconds
Started Jul 16 07:56:54 PM PDT 24
Finished Jul 16 07:56:59 PM PDT 24
Peak memory 207644 kb
Host smart-2e01c452-e685-4440-ac44-afa1358baaa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572652161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.572652161
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.3463245935
Short name T495
Test name
Test status
Simulation time 306415369 ps
CPU time 3.42 seconds
Started Jul 16 07:57:11 PM PDT 24
Finished Jul 16 07:57:16 PM PDT 24
Peak memory 208404 kb
Host smart-69758542-da8f-49c5-980e-4fd122cf903a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463245935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3463245935
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.3779724784
Short name T585
Test name
Test status
Simulation time 43239328 ps
CPU time 0.88 seconds
Started Jul 16 07:57:04 PM PDT 24
Finished Jul 16 07:57:06 PM PDT 24
Peak memory 206012 kb
Host smart-af8231d2-e579-44a7-a681-46c6817d6890
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779724784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.3779724784
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.3235922345
Short name T908
Test name
Test status
Simulation time 378115385 ps
CPU time 9 seconds
Started Jul 16 07:56:55 PM PDT 24
Finished Jul 16 07:57:06 PM PDT 24
Peak memory 208592 kb
Host smart-7bfa3121-bbc0-40fc-a232-74571f0ba4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235922345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.3235922345
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.1360085113
Short name T599
Test name
Test status
Simulation time 57442497 ps
CPU time 2.68 seconds
Started Jul 16 07:56:54 PM PDT 24
Finished Jul 16 07:56:59 PM PDT 24
Peak memory 210072 kb
Host smart-6410cf76-f5be-4b86-aa36-840ac322851f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360085113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.1360085113
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.518912571
Short name T499
Test name
Test status
Simulation time 15535364 ps
CPU time 0.73 seconds
Started Jul 16 07:57:11 PM PDT 24
Finished Jul 16 07:57:13 PM PDT 24
Peak memory 205960 kb
Host smart-9375c157-203e-40c2-b4fc-610b12782475
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518912571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.518912571
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.3348834324
Short name T420
Test name
Test status
Simulation time 2653743280 ps
CPU time 80.53 seconds
Started Jul 16 07:57:04 PM PDT 24
Finished Jul 16 07:58:26 PM PDT 24
Peak memory 214380 kb
Host smart-c28ebc5a-9622-493b-afbf-6d9f4409cef0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3348834324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3348834324
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.854523552
Short name T657
Test name
Test status
Simulation time 3202512843 ps
CPU time 21.26 seconds
Started Jul 16 07:56:54 PM PDT 24
Finished Jul 16 07:57:18 PM PDT 24
Peak memory 218144 kb
Host smart-73c95f60-3736-4041-b4b4-d1a0e774abb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854523552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.854523552
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.1315386190
Short name T650
Test name
Test status
Simulation time 276366983 ps
CPU time 2.43 seconds
Started Jul 16 07:57:01 PM PDT 24
Finished Jul 16 07:57:04 PM PDT 24
Peak memory 222520 kb
Host smart-93d4c1c2-02cb-4bfa-a426-978cad33c573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315386190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.1315386190
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.2920811722
Short name T258
Test name
Test status
Simulation time 213068658 ps
CPU time 2.3 seconds
Started Jul 16 07:56:56 PM PDT 24
Finished Jul 16 07:57:00 PM PDT 24
Peak memory 222492 kb
Host smart-7282616f-6daa-4d00-8a55-fe2dba6cc125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920811722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.2920811722
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.821384514
Short name T236
Test name
Test status
Simulation time 73084179 ps
CPU time 3.25 seconds
Started Jul 16 07:56:56 PM PDT 24
Finished Jul 16 07:57:01 PM PDT 24
Peak memory 210040 kb
Host smart-d6cdc517-05b5-41b9-b130-0adb92d90708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821384514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.821384514
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.2855646238
Short name T846
Test name
Test status
Simulation time 1915645462 ps
CPU time 24.28 seconds
Started Jul 16 07:57:03 PM PDT 24
Finished Jul 16 07:57:28 PM PDT 24
Peak memory 219556 kb
Host smart-8f1be4e2-716c-4e90-be5d-3c4995cb5c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855646238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2855646238
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.1585552362
Short name T596
Test name
Test status
Simulation time 89586649 ps
CPU time 1.95 seconds
Started Jul 16 07:57:12 PM PDT 24
Finished Jul 16 07:57:15 PM PDT 24
Peak memory 208624 kb
Host smart-60477aa1-5e02-4855-a532-395edf607efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585552362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1585552362
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.622956668
Short name T488
Test name
Test status
Simulation time 53050555 ps
CPU time 2.87 seconds
Started Jul 16 07:56:57 PM PDT 24
Finished Jul 16 07:57:01 PM PDT 24
Peak memory 207064 kb
Host smart-b9095902-460e-44dc-91b5-3bff9a8e85ed
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622956668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.622956668
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.2975886748
Short name T789
Test name
Test status
Simulation time 49345584 ps
CPU time 2.05 seconds
Started Jul 16 07:56:53 PM PDT 24
Finished Jul 16 07:56:57 PM PDT 24
Peak memory 208868 kb
Host smart-c2c55159-6431-4945-aa9b-4f23a7d8da6a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975886748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2975886748
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.735474588
Short name T477
Test name
Test status
Simulation time 52506299 ps
CPU time 2.69 seconds
Started Jul 16 07:57:11 PM PDT 24
Finished Jul 16 07:57:15 PM PDT 24
Peak memory 208640 kb
Host smart-899f0a1a-e640-4934-ab50-f0279b836c2c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735474588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.735474588
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.3029199370
Short name T905
Test name
Test status
Simulation time 788762125 ps
CPU time 9.29 seconds
Started Jul 16 07:56:53 PM PDT 24
Finished Jul 16 07:57:05 PM PDT 24
Peak memory 208356 kb
Host smart-125d6f69-b1bf-4a92-8758-947912306a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029199370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.3029199370
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.2929856282
Short name T440
Test name
Test status
Simulation time 325298786 ps
CPU time 3.81 seconds
Started Jul 16 07:56:55 PM PDT 24
Finished Jul 16 07:57:01 PM PDT 24
Peak memory 207376 kb
Host smart-d2cf0b45-5e46-47e3-9866-ca82b6936343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929856282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2929856282
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.2568135842
Short name T881
Test name
Test status
Simulation time 61476153 ps
CPU time 3.03 seconds
Started Jul 16 07:57:02 PM PDT 24
Finished Jul 16 07:57:05 PM PDT 24
Peak memory 208824 kb
Host smart-7b18be66-9aba-407f-b16e-fb7599d2c7aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568135842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.2568135842
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.2886229647
Short name T462
Test name
Test status
Simulation time 1534223918 ps
CPU time 56.93 seconds
Started Jul 16 07:56:57 PM PDT 24
Finished Jul 16 07:57:55 PM PDT 24
Peak memory 214520 kb
Host smart-69199259-e013-4e86-a592-676142ab3e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886229647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.2886229647
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.2927695056
Short name T167
Test name
Test status
Simulation time 1102853648 ps
CPU time 6.15 seconds
Started Jul 16 07:57:12 PM PDT 24
Finished Jul 16 07:57:19 PM PDT 24
Peak memory 211068 kb
Host smart-8f4fc204-34bf-45e8-92bb-7317c73461a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927695056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.2927695056
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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