Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.31	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	75	255	77.27

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	56	224	80.00	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4716

1

T1

7

T2

9

T3

8

auto[1]

593

1

T5

1

T15

1

T91

4

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4716

1

T1

7

T2

9

T3

8

auto[1]

593

1

T5

1

T15

1

T91

4

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4773

1

T1

7

T2

7

T3

4

auto[1]

536

1

T2

2

T3

4

T5

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4773

1

T1

7

T2

7

T3

4

auto[1]

536

1

T2

2

T3

4

T5

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	421	1			T5	1		T6	2		T89	1
auto[OpGenId]	1053	1			T1	3		T2	1		T14	6
auto[OpGenSwOut]	1162	1			T2	4		T6	1		T14	2
auto[OpGenHwOut]	2605	1			T1	4		T2	4		T3	8
auto[OpDisable]	68	1			T16	1		T52	1		T53	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	421	1			T5	1		T6	2		T89	1
auto[OpGenId]	1053	1			T1	3		T2	1		T14	6
auto[OpGenSwOut]	1162	1			T2	4		T6	1		T14	2
auto[OpGenHwOut]	2605	1			T1	4		T2	4		T3	8
auto[OpDisable]	68	1			T16	1		T52	1		T53	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4726

1

T1

7

T2

6

T3

8

auto[1]

583

1

T2

3

T5

1

T39

4

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4726

1

T1

7

T2

6

T3

8

auto[1]

583

1

T2

3

T5

1

T39

4

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5020

1

T1

7

T2

9

T3

8

auto[1]

289

1

T123

3

T83

5

T140

3

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1779	1			T1	1		T2	6		T3	4
auto[1]	703	1			T2	1		T3	1		T6	1
auto[2]	712	1			T1	3		T2	1		T3	1
auto[3]	710	1			T1	2		T14	1		T15	1
auto[4]	354	1			T3	2		T14	2		T90	3
auto[5]	354	1			T1	1		T2	1		T92	1
auto[6]	355	1			T15	1		T39	3		T40	1
auto[7]	342	1			T16	1		T39	1		T40	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1405	1			T1	1		T2	1		T3	2
clear_one[1]	703	1			T2	1		T3	1		T6	1
clear_one[2]	712	1			T1	3		T2	1		T3	1
clear_one[3]	710	1			T1	2		T14	1		T15	1
clear_none	1779	1			T1	1		T2	6		T3	4

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1027	1			T14	3		T39	5		T40	1
auto[StInit]	629	1			T2	3		T3	1		T6	1
auto[StCreatorRootKey]	541	1			T2	2		T3	1		T6	1
auto[StOwnerIntKey]	515	1			T2	1		T3	1		T6	1
auto[StOwnerKey]	484	1			T3	1		T5	1		T15	1
auto[StDisabled]	1828	1			T2	3		T3	4		T15	1
auto[StInvalid]	285	1			T1	7		T14	5		T55	5

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1027	1			T14	3		T39	5		T40	1
auto[StInit]	629	1			T2	3		T3	1		T6	1
auto[StCreatorRootKey]	541	1			T2	2		T3	1		T6	1
auto[StOwnerIntKey]	515	1			T2	1		T3	1		T6	1
auto[StOwnerKey]	484	1			T3	1		T5	1		T15	1
auto[StDisabled]	1828	1			T2	3		T3	4		T15	1
auto[StInvalid]	285	1			T1	7		T14	5		T55	5

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	56	224	80.00	56

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[0] - auto[1]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[0] - auto[1]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	8
[auto[0] - auto[1]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[2]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[2]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[3] - auto[6]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	4
[auto[3] - auto[6]]	[auto[StReset]]	[auto[OpDisable]]	--	--	4
[auto[3] - auto[6]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	16
[auto[3] - auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	4
[auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StInit]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StCreatorRootKey]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StCreatorRootKey]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	2
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpGenId]	154	1			T14	2		T209	1		T97	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	138	1			T55	1		T26	1		T32	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	271	1			T39	3		T40	1		T90	1
auto[0]	auto[StInit]	auto[OpAdvance]	36	1			T6	1		T228	1		T254	1
auto[0]	auto[StInit]	auto[OpGenId]	83	1			T83	1		T58	1		T27	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	107	1			T2	3		T93	1		T140	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	158	1			T3	1		T41	1		T88	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	18	1			T89	1		T108	1		T134	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	47	1			T209	1		T255	1		T68	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	51	1			T123	1		T141	1		T256	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	75	1			T2	1		T39	1		T228	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	10	1			T140	1		T155	1		T257	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	28	1			T2	1		T61	1		T227	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	26	1			T83	2		T141	1		T211	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	55	1			T15	1		T26	1		T258	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	10	1			T5	1		T155	1		T107	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	22	1			T216	1		T71	1		T65	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	23	1			T214	1		T259	1		T65	2
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	50	1			T3	1		T39	1		T90	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	30	1			T214	1		T61	1		T220	1
auto[0]	auto[StDisabled]	auto[OpGenId]	55	1			T142	4		T61	1		T257	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	76	1			T40	1		T217	1		T260	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	156	1			T2	1		T3	2		T39	1
auto[0]	auto[StDisabled]	auto[OpDisable]	24	1			T16	1		T52	1		T53	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	11	1			T47	1		T195	1		T261	1
auto[0]	auto[StInvalid]	auto[OpGenId]	15	1			T262	2		T114	1		T109	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	23	1			T14	1		T43	1		T99	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	27	1			T1	1		T97	1		T22	1
auto[1]	auto[StReset]	auto[OpGenId]	14	1			T71	1		T136	1		T263	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	24	1			T226	1		T212	1		T264	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	76	1			T90	1		T55	1		T97	1
auto[1]	auto[StInit]	auto[OpAdvance]	3	1			T265	1		T253	1		T266	1
auto[1]	auto[StInit]	auto[OpGenId]	6	1			T132	1		T267	1		T23	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	12	1			T159	1		T98	1		T231	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	24	1			T39	1		T225	1		T63	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	12	1			T42	1		T254	1		T268	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T135	1		T203	2		T269	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	17	1			T142	2		T270	1		T194	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	32	1			T3	1		T43	1		T271	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T134	1		T272	1		T263	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	14	1			T96	1		T273	1		T274	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	16	1			T6	1		T36	1		T263	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	35	1			T92	1		T42	1		T61	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T83	1		T61	1		T275	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	15	1			T61	1		T276	1		T277	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T93	1		T278	1		T268	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	37	1			T92	1		T28	1		T220	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	25	1			T28	1		T214	1		T227	1
auto[1]	auto[StDisabled]	auto[OpGenId]	53	1			T140	1		T61	2		T276	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	58	1			T2	1		T123	1		T26	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	156	1			T88	2		T90	1		T91	1
auto[1]	auto[StDisabled]	auto[OpDisable]	9	1			T67	1		T133	1		T279	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	5	1			T55	1		T280	1		T281	1
auto[1]	auto[StInvalid]	auto[OpGenId]	12	1			T14	1		T97	1		T22	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T282	1		T283	1		T284	2
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T55	1		T262	1		T47	1
auto[2]	auto[StReset]	auto[OpAdvance]	3	1			T145	1		T285	1		T286	1
auto[2]	auto[StReset]	auto[OpGenId]	18	1			T55	1		T42	1		T223	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	22	1			T32	1		T260	1		T287	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	44	1			T90	3		T51	1		T271	1
auto[2]	auto[StInit]	auto[OpAdvance]	9	1			T22	1		T288	1		T289	3
auto[2]	auto[StInit]	auto[OpGenId]	14	1			T68	2		T71	1		T65	2
auto[2]	auto[StInit]	auto[OpGenSwOut]	16	1			T26	1		T142	1		T290	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	21	1			T87	1		T271	1		T291	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	14	1			T6	1		T145	1		T135	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T27	1		T61	1		T143	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	15	1			T210	1		T219	1		T276	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	44	1			T292	1		T291	1		T293	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	10	1			T276	1		T294	1		T289	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	15	1			T259	1		T159	1		T295	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	20	1			T61	1		T220	1		T288	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	34	1			T3	1		T84	1		T296	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T143	1		T297	1		T273	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	10	1			T68	1		T65	1		T298	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	17	1			T290	1		T143	3		T65	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	42	1			T61	1		T291	1		T143	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	24	1			T142	1		T299	1		T220	1
auto[2]	auto[StDisabled]	auto[OpGenId]	50	1			T142	3		T61	1		T107	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	69	1			T93	1		T26	1		T210	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	143	1			T2	1		T39	1		T93	1
auto[2]	auto[StDisabled]	auto[OpDisable]	2	1			T75	1		T300	1		-	-
auto[2]	auto[StInvalid]	auto[OpAdvance]	12	1			T97	1		T301	1		T302	1
auto[2]	auto[StInvalid]	auto[OpGenId]	7	1			T1	2		T14	1		T303	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T55	1		T94	1		T304	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T1	1		T99	1		T305	1
auto[3]	auto[StReset]	auto[OpGenId]	24	1			T65	1		T94	1		T136	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	18	1			T42	1		T68	1		T22	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	43	1			T39	1		T306	1		T299	1
auto[3]	auto[StInit]	auto[OpAdvance]	2	1			T34	1		T297	1		-	-
auto[3]	auto[StInit]	auto[OpGenId]	11	1			T307	1		T298	1		T23	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	10	1			T223	1		T33	1		T299	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	23	1			T308	1		T309	1		T310	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T307	1		T285	1		T311	2
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T312	1		T313	1		T246	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T297	1		T240	1		T203	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	42	1			T90	1		T33	1		T314	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T307	1		T315	1		T10	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	15	1			T107	1		T132	1		T316	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	21	1			T210	1		T307	1		T275	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	48	1			T88	1		T91	1		T87	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T227	2		T317	1		T318	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	14	1			T226	1		T319	1		T320	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	15	1			T210	1		T229	1		T316	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	44	1			T15	1		T91	1		T87	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	25	1			T100	1		T143	2		T220	1
auto[3]	auto[StDisabled]	auto[OpGenId]	52	1			T123	1		T307	1		T71	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	61	1			T61	1		T227	1		T143	2
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	152	1			T91	2		T87	2		T296	1
auto[3]	auto[StDisabled]	auto[OpDisable]	13	1			T70	1		T65	1		T273	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	7	1			T321	1		T283	1		T284	1
auto[3]	auto[StInvalid]	auto[OpGenId]	15	1			T14	1		T55	1		T304	2
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T322	1		T323	1		T324	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	16	1			T1	2		T262	1		T94	1
auto[4]	auto[StReset]	auto[OpGenId]	10	1			T14	1		T107	1		T325	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	14	1			T107	1		T267	1		T193	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	30	1			T306	1		T31	1		T326	1
auto[4]	auto[StInit]	auto[OpAdvance]	3	1			T226	1		T238	1		T327	1
auto[4]	auto[StInit]	auto[OpGenId]	2	1			T237	1		T65	1		-	-
auto[4]	auto[StInit]	auto[OpGenSwOut]	3	1			T61	1		T220	1		T328	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	6	1			T306	1		T329	1		T330	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T226	1		T96	1		T263	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	4	1			T67	1		T220	1		T331	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T69	1		T220	1		T21	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	15	1			T84	1		T332	1		T333	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T209	1		T140	1		T136	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T241	1		T263	1		T334	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T196	1		T203	1		T334	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	17	1			T335	1		T68	1		T336	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T294	1		T263	1		T311	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	7	1			T112	1		T76	1		T337	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T140	1		T257	1		T241	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	19	1			T332	1		T61	1		T330	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	7	1			T277	1		T193	2		T338	1
auto[4]	auto[StDisabled]	auto[OpGenId]	22	1			T52	1		T211	1		T61	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	23	1			T107	1		T277	1		T70	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	95	1			T3	2		T90	3		T87	1
auto[4]	auto[StDisabled]	auto[OpDisable]	7	1			T288	1		T339	1		T340	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	4	1			T341	1		T342	1		T343	1
auto[4]	auto[StInvalid]	auto[OpGenId]	5	1			T344	1		T345	1		T343	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T14	1		T195	1		T282	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T94	1		T280	1		T261	1
auto[5]	auto[StReset]	auto[OpGenId]	8	1			T132	1		T133	1		T269	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	12	1			T212	1		T346	1		T203	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	23	1			T87	1		T271	1		T308	1
auto[5]	auto[StInit]	auto[OpAdvance]	2	1			T347	1		T348	1		-	-
auto[5]	auto[StInit]	auto[OpGenId]	8	1			T107	1		T220	1		T349	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	3	1			T23	1		T350	1		T56	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	13	1			T84	1		T349	1		T351	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T193	1		T273	1		T352	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T288	1		T263	2		T353	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	3	1			T241	1		T354	1		T101	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	23	1			T2	1		T92	1		T222	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T355	1		T356	1		-	-
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	3	1			T65	1		T357	1		T285	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T27	1		T358	1		T359	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	26	1			T332	1		T292	1		T291	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T360	1		T356	1		T361	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	7	1			T107	1		T193	1		T362	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T220	1		T273	1		T357	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	25	1			T296	1		T271	1		T295	5
auto[5]	auto[StDisabled]	auto[OpAdvance]	12	1			T297	2		T360	1		T337	1
auto[5]	auto[StDisabled]	auto[OpGenId]	27	1			T61	1		T220	3		T112	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	18	1			T155	1		T72	1		T297	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	75	1			T84	1		T27	1		T296	2
auto[5]	auto[StDisabled]	auto[OpDisable]	5	1			T241	1		T203	1		T269	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	6	1			T97	1		T344	1		T363	2
auto[5]	auto[StInvalid]	auto[OpGenId]	8	1			T1	1		T262	1		T22	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T195	1		T364	1		T365	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T304	1		T343	1		T323	2
auto[6]	auto[StReset]	auto[OpGenId]	10	1			T226	1		T299	1		T22	2
auto[6]	auto[StReset]	auto[OpGenSwOut]	12	1			T61	1		T267	1		T240	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	22	1			T39	1		T87	1		T258	1
auto[6]	auto[StInit]	auto[OpAdvance]	3	1			T366	1		T81	1		T367	1
auto[6]	auto[StInit]	auto[OpGenId]	3	1			T74	1		T135	1		T366	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	4	1			T28	1		T211	1		T187	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	14	1			T141	1		T368	1		T369	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T225	1		T366	1		T78	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	3	1			T307	1		T316	1		T80	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T61	1		T370	1		T371	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	20	1			T88	1		T91	1		T306	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T100	1		T372	1		T253	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T61	1		T70	1		T203	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T93	1		T33	1		T69	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	20	1			T39	1		T90	1		T212	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T193	1		T373	1		T374	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	5	1			T212	1		T113	1		T135	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T135	1		T273	1		T354	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	22	1			T88	1		T306	1		T293	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	12	1			T140	1		T141	1		T155	1
auto[6]	auto[StDisabled]	auto[OpGenId]	31	1			T140	1		T68	1		T71	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	34	1			T73	1		T107	1		T63	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	76	1			T15	1		T39	1		T40	1
auto[6]	auto[StDisabled]	auto[OpDisable]	3	1			T63	1		T375	1		T376	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	4	1			T341	1		T377	1		T378	1
auto[6]	auto[StInvalid]	auto[OpGenId]	6	1			T97	1		T304	1		T379	2
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T55	1		T42	1		T114	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T282	1		T380	2		T323	1
auto[7]	auto[StReset]	auto[OpGenId]	6	1			T235	1		T345	1		T377	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	6	1			T42	1		T241	1		T381	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	25	1			T306	1		T329	1		T330	1
auto[7]	auto[StInit]	auto[OpAdvance]	3	1			T226	1		T68	1		T331	1
auto[7]	auto[StInit]	auto[OpGenId]	8	1			T382	1		T136	1		T383	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	4	1			T203	1		T383	1		T76	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	15	1			T90	1		T258	1		T292	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	3	1			T384	1		T385	1		T386	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T216	1		T68	1		T132	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	16	1			T87	1		T296	1		T387	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T227	2		T95	1		T104	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T65	1		T241	1		T388	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T68	1		T389	1		T56	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	20	1			T223	1		T330	1		T390	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T65	1		T268	2		T285	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	3	1			T108	1		T391	1		T392	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T67	1		T144	1		T349	2
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	17	1			T227	1		T329	1		T387	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	14	1			T145	2		T393	1		T268	1
auto[7]	auto[StDisabled]	auto[OpGenId]	24	1			T16	1		T40	1		T58	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	23	1			T107	1		T220	1		T241	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	82	1			T39	1		T88	2		T92	1
auto[7]	auto[StDisabled]	auto[OpDisable]	5	1			T69	1		T267	1		T388	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	5	1			T280	1		T379	1		T341	1
auto[7]	auto[StInvalid]	auto[OpGenId]	9	1			T47	2		T99	1		T380	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T394	1		T380	1		T341	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T43	1		T94	1		T341	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1405

1

T1

1

T2

1

T3

2

clear_one[1]

auto[0]

auto[0]

auto[0]

414

1

T6

1

T14

1

T39

1

clear_one[1]

auto[0]

auto[0]

auto[1]

120

1

T93

1

T42

1

T271

1

clear_one[1]

auto[0]

auto[1]

auto[0]

126

1

T2

1

T3

1

T88

2

clear_one[1]

auto[0]

auto[1]

auto[1]

43

1

T123

4

T28

1

T214

1

clear_one[2]

auto[0]

auto[0]

auto[0]

402

1

T1

3

T3

1

T6

1

clear_one[2]

auto[0]

auto[0]

auto[1]

125

1

T2

1

T39

1

T84

3

clear_one[2]

auto[1]

auto[0]

auto[0]

139

1

T87

1

T296

1

T142

6

clear_one[2]

auto[1]

auto[0]

auto[1]

46

1

T26

1

T395

2

T71

1

clear_one[3]

auto[0]

auto[0]

auto[0]

418

1

T1

2

T14

1

T39

1

clear_one[3]

auto[0]

auto[1]

auto[0]

109

1

T88

1

T90

1

T123

1

clear_one[3]

auto[1]

auto[0]

auto[0]

145

1

T91

4

T87

4

T296

1

clear_one[3]

auto[1]

auto[1]

auto[0]

38

1

T15

1

T299

1

T74

1

clear_none

auto[0]

auto[0]

auto[0]

1253

1

T1

1

T2

3

T3

1

clear_none

auto[0]

auto[0]

auto[1]

137

1

T2

2

T39

3

T26

1

clear_none

auto[0]

auto[1]

auto[0]

116

1

T2

1

T3

3

T15

1

clear_none

auto[0]

auto[1]

auto[1]

48

1

T228

1

T26

1

T53

1

clear_none

auto[1]

auto[0]

auto[0]

134

1

T52

1

T210

1

T142

8

clear_none

auto[1]

auto[0]

auto[1]

35

1

T61

1

T395

1

T396

1

clear_none

auto[1]

auto[1]

auto[0]

27

1

T217

1

T223

1

T132

1

clear_none

auto[1]

auto[1]

auto[1]

29

1

T5

1

T220

2

T316

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1337	1			T1	1		T2	1		T3	2
clear_all	auto[1]	68	1			T83	2		T140	2		T155	2
clear_one[1]	auto[0]	654	1			T2	1		T3	1		T6	1
clear_one[1]	auto[1]	49	1			T123	3		T142	2		T155	2
clear_one[2]	auto[0]	657	1			T1	3		T2	1		T3	1
clear_one[2]	auto[1]	55	1			T142	5		T226	1		T143	6
clear_one[3]	auto[0]	665	1			T1	2		T14	1		T15	1
clear_one[3]	auto[1]	45	1			T226	1		T227	2		T143	3
clear_none	auto[0]	1707	1			T1	1		T2	6		T3	4
clear_none	auto[1]	72	1			T83	3		T140	1		T142	6