Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31643

1

T1

35

T2

113

T3

20

auto[1]

263

1

T123

4

T83

1

T140

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	31661	1			T1	35		T2	113		T3	20
auto[134217728:268435455]	9	1			T142	1		T196	1		T426	1
auto[268435456:402653183]	12	1			T142	2		T145	2		T268	1
auto[402653184:536870911]	7	1			T123	1		T145	1		T193	1
auto[536870912:671088639]	7	1			T349	1		T427	1		T338	1
auto[671088640:805306367]	10	1			T140	1		T142	2		T155	1
auto[805306368:939524095]	8	1			T142	1		T143	1		T145	1
auto[939524096:1073741823]	10	1			T140	1		T155	1		T349	1
auto[1073741824:1207959551]	8	1			T142	1		T143	1		T145	1
auto[1207959552:1342177279]	8	1			T145	1		T295	1		T427	1
auto[1342177280:1476395007]	5	1			T145	1		T315	1		T428	1
auto[1476395008:1610612735]	6	1			T143	1		T294	1		T295	1
auto[1610612736:1744830463]	7	1			T193	1		T295	1		T338	1
auto[1744830464:1879048191]	5	1			T226	1		T143	1		T318	1
auto[1879048192:2013265919]	6	1			T143	3		T289	1		T428	1
auto[2013265920:2147483647]	9	1			T142	2		T143	1		T297	1
auto[2147483648:2281701375]	12	1			T83	1		T142	2		T155	1
auto[2281701376:2415919103]	6	1			T142	2		T143	2		T427	1
auto[2415919104:2550136831]	8	1			T142	1		T227	1		T143	1
auto[2550136832:2684354559]	8	1			T142	1		T227	1		T427	1
auto[2684354560:2818572287]	12	1			T123	1		T142	1		T143	2
auto[2818572288:2952790015]	9	1			T140	1		T155	1		T227	1
auto[2952790016:3087007743]	6	1			T123	1		T227	1		T295	2
auto[3087007744:3221225471]	10	1			T143	1		T349	1		T294	1
auto[3221225472:3355443199]	7	1			T142	1		T226	1		T338	2
auto[3355443200:3489660927]	6	1			T142	1		T196	1		T427	1
auto[3489660928:3623878655]	10	1			T123	1		T142	2		T274	1
auto[3623878656:3758096383]	5	1			T142	1		T295	1		T427	1
auto[3758096384:3892314111]	9	1			T142	1		T227	1		T297	1
auto[3892314112:4026531839]	3	1			T193	1		T311	1		T429	1
auto[4026531840:4160749567]	9	1			T155	1		T193	1		T406	1
auto[4160749568:4294967295]	8	1			T145	1		T196	1		T427	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	31643	1			T1	35		T2	113		T3	20
auto[0:134217727]	auto[1]	18	1			T140	1		T142	1		T227	3
auto[134217728:268435455]	auto[1]	9	1			T142	1		T196	1		T426	1
auto[268435456:402653183]	auto[1]	12	1			T142	2		T145	2		T268	1
auto[402653184:536870911]	auto[1]	7	1			T123	1		T145	1		T193	1
auto[536870912:671088639]	auto[1]	7	1			T349	1		T427	1		T338	1
auto[671088640:805306367]	auto[1]	10	1			T140	1		T142	2		T155	1
auto[805306368:939524095]	auto[1]	8	1			T142	1		T143	1		T145	1
auto[939524096:1073741823]	auto[1]	10	1			T140	1		T155	1		T349	1
auto[1073741824:1207959551]	auto[1]	8	1			T142	1		T143	1		T145	1
auto[1207959552:1342177279]	auto[1]	8	1			T145	1		T295	1		T427	1
auto[1342177280:1476395007]	auto[1]	5	1			T145	1		T315	1		T428	1
auto[1476395008:1610612735]	auto[1]	6	1			T143	1		T294	1		T295	1
auto[1610612736:1744830463]	auto[1]	7	1			T193	1		T295	1		T338	1
auto[1744830464:1879048191]	auto[1]	5	1			T226	1		T143	1		T318	1
auto[1879048192:2013265919]	auto[1]	6	1			T143	3		T289	1		T428	1
auto[2013265920:2147483647]	auto[1]	9	1			T142	2		T143	1		T297	1
auto[2147483648:2281701375]	auto[1]	12	1			T83	1		T142	2		T155	1
auto[2281701376:2415919103]	auto[1]	6	1			T142	2		T143	2		T427	1
auto[2415919104:2550136831]	auto[1]	8	1			T142	1		T227	1		T143	1
auto[2550136832:2684354559]	auto[1]	8	1			T142	1		T227	1		T427	1
auto[2684354560:2818572287]	auto[1]	12	1			T123	1		T142	1		T143	2
auto[2818572288:2952790015]	auto[1]	9	1			T140	1		T155	1		T227	1
auto[2952790016:3087007743]	auto[1]	6	1			T123	1		T227	1		T295	2
auto[3087007744:3221225471]	auto[1]	10	1			T143	1		T349	1		T294	1
auto[3221225472:3355443199]	auto[1]	7	1			T142	1		T226	1		T338	2
auto[3355443200:3489660927]	auto[1]	6	1			T142	1		T196	1		T427	1
auto[3489660928:3623878655]	auto[1]	10	1			T123	1		T142	2		T274	1
auto[3623878656:3758096383]	auto[1]	5	1			T142	1		T295	1		T427	1
auto[3758096384:3892314111]	auto[1]	9	1			T142	1		T227	1		T297	1
auto[3892314112:4026531839]	auto[1]	3	1			T193	1		T311	1		T429	1
auto[4026531840:4160749567]	auto[1]	9	1			T155	1		T193	1		T406	1
auto[4160749568:4294967295]	auto[1]	8	1			T145	1		T196	1		T427	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1562

1

T1

2

T2

2

T4

3

auto[1]

1729

1

T1

2

T2

5

T4

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	109	1			T6	1		T41	1		T26	1
auto[134217728:268435455]	86	1			T14	1		T40	1		T41	1
auto[268435456:402653183]	115	1			T89	1		T42	1		T229	1
auto[402653184:536870911]	97	1			T2	1		T14	1		T52	1
auto[536870912:671088639]	92	1			T97	1		T32	1		T51	1
auto[671088640:805306367]	94	1			T2	1		T209	1		T51	1
auto[805306368:939524095]	109	1			T2	1		T93	1		T123	1
auto[939524096:1073741823]	104	1			T14	1		T15	1		T93	1
auto[1073741824:1207959551]	90	1			T32	1		T53	1		T83	1
auto[1207959552:1342177279]	119	1			T16	1		T228	1		T42	1
auto[1342177280:1476395007]	84	1			T4	1		T16	1		T141	1
auto[1476395008:1610612735]	100	1			T4	1		T53	1		T28	1
auto[1610612736:1744830463]	109	1			T55	2		T97	1		T83	1
auto[1744830464:1879048191]	99	1			T55	1		T100	1		T60	1
auto[1879048192:2013265919]	105	1			T141	1		T230	1		T61	3
auto[2013265920:2147483647]	101	1			T1	1		T14	1		T229	1
auto[2147483648:2281701375]	108	1			T216	1		T18	1		T227	1
auto[2281701376:2415919103]	88	1			T93	1		T58	1		T27	1
auto[2415919104:2550136831]	111	1			T89	1		T142	1		T216	1
auto[2550136832:2684354559]	106	1			T4	1		T15	1		T55	1
auto[2684354560:2818572287]	121	1			T1	1		T2	1		T15	2
auto[2818572288:2952790015]	95	1			T4	1		T40	1		T217	1
auto[2952790016:3087007743]	93	1			T2	2		T15	1		T52	1
auto[3087007744:3221225471]	109	1			T14	1		T123	1		T217	1
auto[3221225472:3355443199]	105	1			T26	1		T430	1		T142	1
auto[3355443200:3489660927]	106	1			T2	1		T55	1		T42	1
auto[3489660928:3623878655]	101	1			T1	1		T14	1		T15	1
auto[3623878656:3758096383]	115	1			T15	1		T123	1		T26	1
auto[3758096384:3892314111]	89	1			T1	1		T217	1		T141	1
auto[3892314112:4026531839]	115	1			T93	1		T55	1		T217	1
auto[4026531840:4160749567]	125	1			T93	1		T55	1		T97	1
auto[4160749568:4294967295]	91	1			T4	1		T26	2		T97	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	51	1			T41	1		T43	1		T61	1
auto[0:134217727]	auto[1]	58	1			T6	1		T26	1		T97	1
auto[134217728:268435455]	auto[0]	35	1			T14	1		T29	1		T100	1
auto[134217728:268435455]	auto[1]	51	1			T40	1		T41	1		T93	1
auto[268435456:402653183]	auto[0]	49	1			T61	1		T18	1		T64	1
auto[268435456:402653183]	auto[1]	66	1			T89	1		T42	1		T229	1
auto[402653184:536870911]	auto[0]	39	1			T14	1		T42	1		T100	1
auto[402653184:536870911]	auto[1]	58	1			T2	1		T52	1		T209	1
auto[536870912:671088639]	auto[0]	42	1			T32	1		T51	1		T61	1
auto[536870912:671088639]	auto[1]	50	1			T97	1		T210	1		T28	1
auto[671088640:805306367]	auto[0]	46	1			T209	1		T51	1		T62	1
auto[671088640:805306367]	auto[1]	48	1			T2	1		T68	1		T107	1
auto[805306368:939524095]	auto[0]	49	1			T223	1		T61	1		T222	1
auto[805306368:939524095]	auto[1]	60	1			T2	1		T93	1		T123	1
auto[939524096:1073741823]	auto[0]	49	1			T14	1		T15	1		T226	2
auto[939524096:1073741823]	auto[1]	55	1			T93	1		T210	1		T61	1
auto[1073741824:1207959551]	auto[0]	40	1			T53	1		T83	1		T61	2
auto[1073741824:1207959551]	auto[1]	50	1			T32	1		T270	1		T107	2
auto[1207959552:1342177279]	auto[0]	60	1			T16	1		T228	1		T42	1
auto[1207959552:1342177279]	auto[1]	59	1			T43	1		T67	1		T220	2
auto[1342177280:1476395007]	auto[0]	46	1			T4	1		T141	1		T230	1
auto[1342177280:1476395007]	auto[1]	38	1			T16	1		T28	1		T142	1
auto[1476395008:1610612735]	auto[0]	47	1			T61	1		T68	1		T74	1
auto[1476395008:1610612735]	auto[1]	53	1			T4	1		T53	1		T28	1
auto[1610612736:1744830463]	auto[0]	49	1			T55	2		T83	1		T42	1
auto[1610612736:1744830463]	auto[1]	60	1			T97	1		T100	2		T61	2
auto[1744830464:1879048191]	auto[0]	46	1			T100	1		T60	1		T68	1
auto[1744830464:1879048191]	auto[1]	53	1			T55	1		T61	1		T68	1
auto[1879048192:2013265919]	auto[0]	54	1			T61	3		T226	1		T69	1
auto[1879048192:2013265919]	auto[1]	51	1			T141	1		T230	1		T143	2
auto[2013265920:2147483647]	auto[0]	51	1			T1	1		T229	1		T264	1
auto[2013265920:2147483647]	auto[1]	50	1			T14	1		T68	1		T107	1
auto[2147483648:2281701375]	auto[0]	47	1			T216	1		T235	1		T68	1
auto[2147483648:2281701375]	auto[1]	61	1			T18	1		T227	1		T68	1
auto[2281701376:2415919103]	auto[0]	40	1			T210	1		T141	2		T235	1
auto[2281701376:2415919103]	auto[1]	48	1			T93	1		T58	1		T27	1
auto[2415919104:2550136831]	auto[0]	52	1			T61	2		T68	1		T107	2
auto[2415919104:2550136831]	auto[1]	59	1			T89	1		T142	1		T216	1
auto[2550136832:2684354559]	auto[0]	52	1			T4	1		T51	2		T100	1
auto[2550136832:2684354559]	auto[1]	54	1			T15	1		T55	1		T217	1
auto[2684354560:2818572287]	auto[0]	62	1			T15	2		T209	1		T60	2
auto[2684354560:2818572287]	auto[1]	59	1			T1	1		T2	1		T40	1
auto[2818572288:2952790015]	auto[0]	42	1			T43	1		T143	1		T107	1
auto[2818572288:2952790015]	auto[1]	53	1			T4	1		T40	1		T217	1
auto[2952790016:3087007743]	auto[0]	41	1			T2	1		T15	1		T210	1
auto[2952790016:3087007743]	auto[1]	52	1			T2	1		T52	1		T67	1
auto[3087007744:3221225471]	auto[0]	42	1			T43	1		T141	1		T257	1
auto[3087007744:3221225471]	auto[1]	67	1			T14	1		T123	1		T217	1
auto[3221225472:3355443199]	auto[0]	45	1			T155	1		T257	1		T107	1
auto[3221225472:3355443199]	auto[1]	60	1			T26	1		T430	1		T142	1
auto[3355443200:3489660927]	auto[0]	48	1			T2	1		T55	1		T51	1
auto[3355443200:3489660927]	auto[1]	58	1			T42	1		T51	1		T61	1
auto[3489660928:3623878655]	auto[0]	58	1			T1	1		T15	1		T40	1
auto[3489660928:3623878655]	auto[1]	43	1			T14	1		T7	1		T33	1
auto[3623878656:3758096383]	auto[0]	59	1			T15	1		T290	1		T264	1
auto[3623878656:3758096383]	auto[1]	56	1			T123	1		T26	1		T140	1
auto[3758096384:3892314111]	auto[0]	43	1			T141	1		T62	1		T74	2
auto[3758096384:3892314111]	auto[1]	46	1			T1	1		T217	1		T73	1
auto[3892314112:4026531839]	auto[0]	57	1			T55	1		T42	1		T141	1
auto[3892314112:4026531839]	auto[1]	58	1			T93	1		T217	1		T210	1
auto[4026531840:4160749567]	auto[0]	72	1			T55	1		T97	1		T83	1
auto[4026531840:4160749567]	auto[1]	53	1			T93	1		T225	1		T61	1
auto[4160749568:4294967295]	auto[0]	49	1			T4	1		T60	1		T61	2
auto[4160749568:4294967295]	auto[1]	42	1			T26	2		T97	1		T54	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1569

1

T1

2

T2

1

T4

4

auto[1]

1723

1

T1

2

T2

6

T4

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	97	1			T2	1		T93	1		T214	1
auto[134217728:268435455]	111	1			T43	1		T51	1		T141	1
auto[268435456:402653183]	92	1			T209	1		T217	1		T43	1
auto[402653184:536870911]	98	1			T4	1		T217	1		T26	1
auto[536870912:671088639]	108	1			T14	1		T15	1		T93	1
auto[671088640:805306367]	118	1			T14	1		T123	1		T55	2
auto[805306368:939524095]	89	1			T52	1		T217	1		T53	1
auto[939524096:1073741823]	104	1			T93	1		T83	1		T141	1
auto[1073741824:1207959551]	98	1			T15	1		T97	1		T61	1
auto[1207959552:1342177279]	97	1			T4	1		T55	1		T223	1
auto[1342177280:1476395007]	106	1			T2	1		T55	1		T42	1
auto[1476395008:1610612735]	104	1			T89	1		T93	1		T228	1
auto[1610612736:1744830463]	104	1			T2	1		T53	1		T230	1
auto[1744830464:1879048191]	110	1			T1	1		T2	1		T14	1
auto[1879048192:2013265919]	110	1			T4	1		T83	1		T42	1
auto[2013265920:2147483647]	114	1			T61	2		T226	1		T257	1
auto[2147483648:2281701375]	101	1			T16	1		T40	1		T52	1
auto[2281701376:2415919103]	100	1			T225	1		T210	1		T29	1
auto[2415919104:2550136831]	106	1			T15	1		T32	1		T51	1
auto[2550136832:2684354559]	108	1			T97	1		T142	1		T100	1
auto[2684354560:2818572287]	99	1			T40	1		T89	1		T55	1
auto[2818572288:2952790015]	103	1			T1	1		T14	2		T15	1
auto[2952790016:3087007743]	108	1			T123	1		T210	1		T67	1
auto[3087007744:3221225471]	104	1			T2	1		T209	1		T26	1
auto[3221225472:3355443199]	92	1			T4	2		T16	1		T93	1
auto[3355443200:3489660927]	106	1			T1	2		T55	1		T26	1
auto[3489660928:3623878655]	96	1			T2	1		T123	1		T210	1
auto[3623878656:3758096383]	90	1			T40	1		T41	2		T93	1
auto[3758096384:3892314111]	96	1			T2	1		T15	1		T209	1
auto[3892314112:4026531839]	101	1			T14	1		T217	1		T97	1
auto[4026531840:4160749567]	106	1			T15	2		T217	1		T26	1
auto[4160749568:4294967295]	116	1			T6	1		T40	1		T58	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	42	1			T61	2		T68	2		T262	1
auto[0:134217727]	auto[1]	55	1			T2	1		T93	1		T214	1
auto[134217728:268435455]	auto[0]	60	1			T51	1		T141	1		T60	1
auto[134217728:268435455]	auto[1]	51	1			T43	1		T61	2		T276	1
auto[268435456:402653183]	auto[0]	54	1			T209	1		T43	1		T141	1
auto[268435456:402653183]	auto[1]	38	1			T217	1		T61	2		T237	1
auto[402653184:536870911]	auto[0]	44	1			T4	1		T26	1		T142	1
auto[402653184:536870911]	auto[1]	54	1			T217	1		T97	1		T33	1
auto[536870912:671088639]	auto[0]	47	1			T42	1		T257	1		T143	1
auto[536870912:671088639]	auto[1]	61	1			T14	1		T15	1		T93	1
auto[671088640:805306367]	auto[0]	50	1			T14	1		T55	1		T210	1
auto[671088640:805306367]	auto[1]	68	1			T123	1		T55	1		T60	1
auto[805306368:939524095]	auto[0]	41	1			T42	1		T62	1		T61	1
auto[805306368:939524095]	auto[1]	48	1			T52	1		T217	1		T53	1
auto[939524096:1073741823]	auto[0]	54	1			T83	1		T141	1		T216	1
auto[939524096:1073741823]	auto[1]	50	1			T93	1		T230	1		T229	1
auto[1073741824:1207959551]	auto[0]	48	1			T220	1		T267	1		T431	1
auto[1073741824:1207959551]	auto[1]	50	1			T15	1		T97	1		T61	1
auto[1207959552:1342177279]	auto[0]	37	1			T55	1		T223	1		T257	1
auto[1207959552:1342177279]	auto[1]	60	1			T4	1		T28	1		T71	1
auto[1342177280:1476395007]	auto[0]	48	1			T43	1		T51	1		T210	1
auto[1342177280:1476395007]	auto[1]	58	1			T2	1		T55	1		T42	1
auto[1476395008:1610612735]	auto[0]	53	1			T228	1		T32	1		T51	1
auto[1476395008:1610612735]	auto[1]	51	1			T89	1		T93	1		T276	1
auto[1610612736:1744830463]	auto[0]	49	1			T230	1		T22	1		T267	1
auto[1610612736:1744830463]	auto[1]	55	1			T2	1		T53	1		T430	1
auto[1744830464:1879048191]	auto[0]	49	1			T1	1		T14	1		T42	1
auto[1744830464:1879048191]	auto[1]	61	1			T2	1		T61	3		T235	1
auto[1879048192:2013265919]	auto[0]	59	1			T4	1		T42	1		T51	1
auto[1879048192:2013265919]	auto[1]	51	1			T83	1		T210	1		T142	1
auto[2013265920:2147483647]	auto[0]	61	1			T61	1		T226	1		T257	1
auto[2013265920:2147483647]	auto[1]	53	1			T61	1		T143	1		T68	1
auto[2147483648:2281701375]	auto[0]	53	1			T16	1		T51	1		T60	1
auto[2147483648:2281701375]	auto[1]	48	1			T40	1		T52	1		T100	1
auto[2281701376:2415919103]	auto[0]	44	1			T61	2		T68	1		T307	1
auto[2281701376:2415919103]	auto[1]	56	1			T225	1		T210	1		T29	1
auto[2415919104:2550136831]	auto[0]	57	1			T15	1		T32	1		T51	1
auto[2415919104:2550136831]	auto[1]	49	1			T216	1		T61	2		T227	1
auto[2550136832:2684354559]	auto[0]	49	1			T100	1		T229	1		T74	1
auto[2550136832:2684354559]	auto[1]	59	1			T97	1		T142	1		T62	1
auto[2684354560:2818572287]	auto[0]	41	1			T40	1		T42	1		T256	1
auto[2684354560:2818572287]	auto[1]	58	1			T89	1		T55	1		T141	1
auto[2818572288:2952790015]	auto[0]	46	1			T15	1		T97	1		T141	1
auto[2818572288:2952790015]	auto[1]	57	1			T1	1		T14	2		T230	1
auto[2952790016:3087007743]	auto[0]	43	1			T210	1		T61	1		T143	1
auto[2952790016:3087007743]	auto[1]	65	1			T123	1		T67	1		T216	1
auto[3087007744:3221225471]	auto[0]	55	1			T209	1		T27	1		T61	1
auto[3087007744:3221225471]	auto[1]	49	1			T2	1		T26	1		T143	1
auto[3221225472:3355443199]	auto[0]	37	1			T4	2		T222	1		T432	1
auto[3221225472:3355443199]	auto[1]	55	1			T16	1		T93	1		T51	1
auto[3355443200:3489660927]	auto[0]	43	1			T1	1		T55	1		T220	1
auto[3355443200:3489660927]	auto[1]	63	1			T1	1		T26	1		T28	1
auto[3489660928:3623878655]	auto[0]	49	1			T210	1		T68	1		T270	1
auto[3489660928:3623878655]	auto[1]	47	1			T2	1		T123	1		T61	2
auto[3623878656:3758096383]	auto[0]	45	1			T41	1		T55	1		T83	1
auto[3623878656:3758096383]	auto[1]	45	1			T40	1		T41	1		T93	1
auto[3758096384:3892314111]	auto[0]	55	1			T2	1		T15	1		T83	1
auto[3758096384:3892314111]	auto[1]	41	1			T209	1		T26	1		T43	1
auto[3892314112:4026531839]	auto[0]	48	1			T14	1		T276	1		T68	1
auto[3892314112:4026531839]	auto[1]	53	1			T217	1		T97	1		T67	1
auto[4026531840:4160749567]	auto[0]	48	1			T15	2		T229	1		T61	1
auto[4026531840:4160749567]	auto[1]	58	1			T217	1		T26	1		T83	1
auto[4160749568:4294967295]	auto[0]	60	1			T58	1		T210	1		T54	1
auto[4160749568:4294967295]	auto[1]	56	1			T6	1		T40	1		T227	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1546

1

T1

2

T2

1

T4

3

auto[1]

1746

1

T1

2

T2

6

T4

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	108	1			T4	1		T40	1		T42	1
auto[134217728:268435455]	84	1			T2	1		T41	1		T93	1
auto[268435456:402653183]	108	1			T4	1		T14	2		T15	1
auto[402653184:536870911]	107	1			T2	1		T6	1		T93	1
auto[536870912:671088639]	108	1			T14	1		T55	1		T141	1
auto[671088640:805306367]	105	1			T53	1		T83	1		T141	1
auto[805306368:939524095]	96	1			T97	1		T230	1		T67	1
auto[939524096:1073741823]	93	1			T2	1		T141	1		T229	1
auto[1073741824:1207959551]	106	1			T52	1		T209	1		T26	1
auto[1207959552:1342177279]	101	1			T1	1		T14	1		T93	1
auto[1342177280:1476395007]	115	1			T15	1		T52	1		T43	1
auto[1476395008:1610612735]	119	1			T1	1		T4	1		T40	1
auto[1610612736:1744830463]	95	1			T40	1		T210	1		T67	1
auto[1744830464:1879048191]	98	1			T83	1		T54	1		T430	1
auto[1879048192:2013265919]	111	1			T1	1		T15	1		T32	1
auto[2013265920:2147483647]	102	1			T97	1		T42	1		T43	1
auto[2147483648:2281701375]	81	1			T16	1		T55	1		T26	1
auto[2281701376:2415919103]	102	1			T1	1		T42	1		T43	1
auto[2415919104:2550136831]	96	1			T93	1		T228	1		T217	1
auto[2550136832:2684354559]	93	1			T4	1		T33	1		T216	1
auto[2684354560:2818572287]	98	1			T14	1		T15	1		T16	1
auto[2818572288:2952790015]	97	1			T15	1		T217	1		T141	1
auto[2952790016:3087007743]	115	1			T4	1		T123	1		T42	1
auto[3087007744:3221225471]	93	1			T2	1		T40	1		T217	1
auto[3221225472:3355443199]	107	1			T89	1		T42	1		T142	1
auto[3355443200:3489660927]	96	1			T26	1		T97	1		T42	1
auto[3489660928:3623878655]	110	1			T2	1		T89	1		T97	1
auto[3623878656:3758096383]	109	1			T41	1		T26	1		T223	1
auto[3758096384:3892314111]	118	1			T2	1		T14	1		T15	1
auto[3892314112:4026531839]	100	1			T2	1		T210	1		T141	1
auto[4026531840:4160749567]	104	1			T15	1		T93	1		T217	1
auto[4160749568:4294967295]	117	1			T55	4		T217	1		T32	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	67	1			T40	1		T42	1		T27	1
auto[0:134217727]	auto[1]	41	1			T4	1		T220	1		T412	1
auto[134217728:268435455]	auto[0]	38	1			T83	1		T60	1		T229	1
auto[134217728:268435455]	auto[1]	46	1			T2	1		T41	1		T93	1
auto[268435456:402653183]	auto[0]	53	1			T4	1		T14	2		T15	1
auto[268435456:402653183]	auto[1]	55	1			T123	1		T72	1		T107	1
auto[402653184:536870911]	auto[0]	51	1			T51	1		T290	1		T264	1
auto[402653184:536870911]	auto[1]	56	1			T2	1		T6	1		T93	1
auto[536870912:671088639]	auto[0]	48	1			T141	1		T33	1		T226	1
auto[536870912:671088639]	auto[1]	60	1			T14	1		T55	1		T61	2
auto[671088640:805306367]	auto[0]	52	1			T83	1		T141	1		T100	1
auto[671088640:805306367]	auto[1]	53	1			T53	1		T155	1		T226	1
auto[805306368:939524095]	auto[0]	55	1			T60	1		T432	1		T262	1
auto[805306368:939524095]	auto[1]	41	1			T97	1		T230	1		T67	1
auto[939524096:1073741823]	auto[0]	52	1			T141	1		T68	2		T107	1
auto[939524096:1073741823]	auto[1]	41	1			T2	1		T229	1		T61	1
auto[1073741824:1207959551]	auto[0]	49	1			T209	1		T97	1		T210	1
auto[1073741824:1207959551]	auto[1]	57	1			T52	1		T26	1		T142	1
auto[1207959552:1342177279]	auto[0]	48	1			T26	1		T61	1		T226	1
auto[1207959552:1342177279]	auto[1]	53	1			T1	1		T14	1		T93	1
auto[1342177280:1476395007]	auto[0]	51	1			T15	1		T51	1		T28	2
auto[1342177280:1476395007]	auto[1]	64	1			T52	1		T43	1		T290	1
auto[1476395008:1610612735]	auto[0]	51	1			T1	1		T4	1		T40	1
auto[1476395008:1610612735]	auto[1]	68	1			T93	1		T123	1		T73	1
auto[1610612736:1744830463]	auto[0]	41	1			T235	1		T107	1		T99	1
auto[1610612736:1744830463]	auto[1]	54	1			T40	1		T210	1		T67	1
auto[1744830464:1879048191]	auto[0]	42	1			T68	1		T63	1		T47	1
auto[1744830464:1879048191]	auto[1]	56	1			T83	1		T54	1		T430	1
auto[1879048192:2013265919]	auto[0]	58	1			T32	1		T51	1		T225	1
auto[1879048192:2013265919]	auto[1]	53	1			T1	1		T15	1		T73	1
auto[2013265920:2147483647]	auto[0]	42	1			T43	1		T51	1		T61	1
auto[2013265920:2147483647]	auto[1]	60	1			T97	1		T42	1		T210	1
auto[2147483648:2281701375]	auto[0]	36	1			T55	1		T61	1		T264	2
auto[2147483648:2281701375]	auto[1]	45	1			T16	1		T26	1		T229	1
auto[2281701376:2415919103]	auto[0]	51	1			T1	1		T42	1		T43	1
auto[2281701376:2415919103]	auto[1]	51	1			T141	1		T100	1		T290	1
auto[2415919104:2550136831]	auto[0]	44	1			T228	1		T51	2		T141	1
auto[2415919104:2550136831]	auto[1]	52	1			T93	1		T217	1		T83	1
auto[2550136832:2684354559]	auto[0]	33	1			T61	1		T262	1		T144	1
auto[2550136832:2684354559]	auto[1]	60	1			T4	1		T33	1		T216	1
auto[2684354560:2818572287]	auto[0]	46	1			T14	1		T16	1		T29	1
auto[2684354560:2818572287]	auto[1]	52	1			T15	1		T209	1		T61	2
auto[2818572288:2952790015]	auto[0]	49	1			T15	1		T60	1		T229	1
auto[2818572288:2952790015]	auto[1]	48	1			T217	1		T141	1		T31	1
auto[2952790016:3087007743]	auto[0]	54	1			T4	1		T42	1		T61	1
auto[2952790016:3087007743]	auto[1]	61	1			T123	1		T43	1		T27	1
auto[3087007744:3221225471]	auto[0]	38	1			T60	1		T256	1		T61	1
auto[3087007744:3221225471]	auto[1]	55	1			T2	1		T40	1		T217	1
auto[3221225472:3355443199]	auto[0]	44	1			T42	1		T235	1		T222	1
auto[3221225472:3355443199]	auto[1]	63	1			T89	1		T142	1		T216	1
auto[3355443200:3489660927]	auto[0]	48	1			T42	1		T51	1		T7	1
auto[3355443200:3489660927]	auto[1]	48	1			T26	1		T97	1		T43	1
auto[3489660928:3623878655]	auto[0]	50	1			T61	1		T222	1		T108	1
auto[3489660928:3623878655]	auto[1]	60	1			T2	1		T89	1		T97	1
auto[3623878656:3758096383]	auto[0]	45	1			T223	1		T222	1		T68	1
auto[3623878656:3758096383]	auto[1]	64	1			T41	1		T26	1		T142	1
auto[3758096384:3892314111]	auto[0]	58	1			T15	1		T209	1		T55	1
auto[3758096384:3892314111]	auto[1]	60	1			T2	1		T14	1		T53	1
auto[3892314112:4026531839]	auto[0]	38	1			T2	1		T210	1		T141	1
auto[3892314112:4026531839]	auto[1]	62	1			T61	1		T227	2		T143	1
auto[4026531840:4160749567]	auto[0]	50	1			T15	1		T210	1		T230	1
auto[4026531840:4160749567]	auto[1]	54	1			T93	1		T217	1		T67	1
auto[4160749568:4294967295]	auto[0]	64	1			T55	3		T83	1		T100	1
auto[4160749568:4294967295]	auto[1]	53	1			T55	1		T217	1		T32	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1578

1

T1

2

T2

1

T4

3

auto[1]

1713

1

T1

2

T2

6

T4

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	115	1			T14	1		T52	1		T51	1
auto[134217728:268435455]	107	1			T1	1		T40	1		T97	1
auto[268435456:402653183]	106	1			T14	1		T41	1		T55	1
auto[402653184:536870911]	102	1			T15	1		T41	1		T83	1
auto[536870912:671088639]	93	1			T16	1		T97	1		T210	1
auto[671088640:805306367]	100	1			T1	1		T40	1		T73	1
auto[805306368:939524095]	90	1			T15	2		T40	1		T123	1
auto[939524096:1073741823]	87	1			T93	1		T83	1		T142	1
auto[1073741824:1207959551]	102	1			T217	1		T42	1		T51	1
auto[1207959552:1342177279]	108	1			T93	1		T217	1		T430	1
auto[1342177280:1476395007]	100	1			T2	1		T93	1		T55	1
auto[1476395008:1610612735]	122	1			T2	1		T14	1		T15	1
auto[1610612736:1744830463]	110	1			T28	1		T142	1		T33	1
auto[1744830464:1879048191]	105	1			T2	1		T58	1		T51	1
auto[1879048192:2013265919]	83	1			T1	1		T93	1		T55	1
auto[2013265920:2147483647]	106	1			T2	1		T6	1		T89	1
auto[2147483648:2281701375]	115	1			T123	1		T55	1		T141	1
auto[2281701376:2415919103]	107	1			T4	1		T14	1		T123	1
auto[2415919104:2550136831]	89	1			T228	1		T42	1		T142	1
auto[2550136832:2684354559]	104	1			T4	1		T42	1		T73	1
auto[2684354560:2818572287]	100	1			T4	1		T93	1		T217	1
auto[2818572288:2952790015]	108	1			T16	1		T55	1		T230	1
auto[2952790016:3087007743]	116	1			T1	1		T2	1		T93	1
auto[3087007744:3221225471]	109	1			T2	1		T15	1		T55	1
auto[3221225472:3355443199]	99	1			T15	1		T217	1		T42	1
auto[3355443200:3489660927]	116	1			T2	1		T210	1		T61	2
auto[3489660928:3623878655]	93	1			T14	1		T217	1		T141	1
auto[3623878656:3758096383]	125	1			T14	1		T15	1		T89	1
auto[3758096384:3892314111]	113	1			T52	1		T209	2		T26	2
auto[3892314112:4026531839]	85	1			T83	1		T43	1		T51	1
auto[4026531840:4160749567]	76	1			T209	1		T32	1		T51	2
auto[4160749568:4294967295]	100	1			T4	2		T26	1		T225	1