Unified Coverage Report :: Group Instance : max_owner_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4432

1

T1

8

T2

10

T4

8

auto[1]

2152

1

T2

4

T4

2

T6

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	206	1			T1	2		T83	2		T141	2
auto[134217728:268435455]	218	1			T41	2		T93	2		T83	2
auto[268435456:402653183]	190	1			T93	4		T55	2		T217	2
auto[402653184:536870911]	236	1			T93	2		T55	2		T217	2
auto[536870912:671088639]	224	1			T40	2		T53	2		T58	2
auto[671088640:805306367]	220	1			T14	2		T16	2		T26	4
auto[805306368:939524095]	196	1			T2	2		T123	2		T55	2
auto[939524096:1073741823]	210	1			T41	2		T93	2		T55	2
auto[1073741824:1207959551]	224	1			T1	2		T2	2		T6	2
auto[1207959552:1342177279]	204	1			T52	2		T26	2		T430	2
auto[1342177280:1476395007]	188	1			T14	2		T217	2		T67	2
auto[1476395008:1610612735]	216	1			T14	2		T53	2		T43	2
auto[1610612736:1744830463]	224	1			T33	2		T61	6		T107	4
auto[1744830464:1879048191]	212	1			T40	2		T51	4		T27	2
auto[1879048192:2013265919]	228	1			T141	4		T73	2		T60	6
auto[2013265920:2147483647]	168	1			T4	2		T93	2		T32	2
auto[2147483648:2281701375]	218	1			T15	2		T55	2		T141	2
auto[2281701376:2415919103]	208	1			T2	2		T14	2		T16	2
auto[2415919104:2550136831]	188	1			T4	2		T55	2		T26	2
auto[2550136832:2684354559]	206	1			T1	2		T54	2		T7	2
auto[2684354560:2818572287]	178	1			T4	4		T83	2		T61	4
auto[2818572288:2952790015]	200	1			T14	2		T97	2		T51	2
auto[2952790016:3087007743]	218	1			T2	4		T15	2		T217	2
auto[3087007744:3221225471]	196	1			T14	2		T40	2		T52	2
auto[3221225472:3355443199]	176	1			T15	2		T42	2		T141	2
auto[3355443200:3489660927]	244	1			T2	2		T210	2		T141	2
auto[3489660928:3623878655]	214	1			T2	2		T89	2		T97	2
auto[3623878656:3758096383]	190	1			T4	2		T123	2		T210	2
auto[3758096384:3892314111]	206	1			T1	2		T15	2		T209	2
auto[3892314112:4026531839]	186	1			T15	2		T210	2		T216	2
auto[4026531840:4160749567]	188	1			T15	2		T209	2		T43	2
auto[4160749568:4294967295]	204	1			T15	2		T42	2		T51	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	134	1			T1	2		T83	2		T141	2
auto[0:134217727]	auto[1]	72	1			T276	2		T275	2		T316	2
auto[134217728:268435455]	auto[0]	130	1			T93	2		T83	2		T230	2
auto[134217728:268435455]	auto[1]	88	1			T41	2		T67	2		T435	2
auto[268435456:402653183]	auto[0]	124	1			T93	4		T217	2		T42	2
auto[268435456:402653183]	auto[1]	66	1			T55	2		T83	2		T61	2
auto[402653184:536870911]	auto[0]	164	1			T93	2		T55	2		T217	2
auto[402653184:536870911]	auto[1]	72	1			T32	2		T61	6		T143	2
auto[536870912:671088639]	auto[0]	158	1			T40	2		T53	2		T61	4
auto[536870912:671088639]	auto[1]	66	1			T58	2		T68	2		T145	2
auto[671088640:805306367]	auto[0]	144	1			T26	2		T142	2		T155	2
auto[671088640:805306367]	auto[1]	76	1			T14	2		T16	2		T26	2
auto[805306368:939524095]	auto[0]	138	1			T97	2		T51	2		T61	4
auto[805306368:939524095]	auto[1]	58	1			T2	2		T123	2		T55	2
auto[939524096:1073741823]	auto[0]	144	1			T93	2		T55	2		T217	2
auto[939524096:1073741823]	auto[1]	66	1			T41	2		T108	2		T107	2
auto[1073741824:1207959551]	auto[0]	148	1			T1	2		T2	2		T40	2
auto[1073741824:1207959551]	auto[1]	76	1			T6	2		T89	2		T27	2
auto[1207959552:1342177279]	auto[0]	124	1			T52	2		T26	2		T100	2
auto[1207959552:1342177279]	auto[1]	80	1			T430	2		T229	2		T257	2
auto[1342177280:1476395007]	auto[0]	128	1			T14	2		T217	2		T33	2
auto[1342177280:1476395007]	auto[1]	60	1			T67	2		T316	2		T94	2
auto[1476395008:1610612735]	auto[0]	130	1			T53	2		T140	2		T61	4
auto[1476395008:1610612735]	auto[1]	86	1			T14	2		T43	2		T276	2
auto[1610612736:1744830463]	auto[0]	144	1			T33	2		T61	6		T107	4
auto[1610612736:1744830463]	auto[1]	80	1			T433	2		T144	2		T194	2
auto[1744830464:1879048191]	auto[0]	158	1			T40	2		T51	4		T27	2
auto[1744830464:1879048191]	auto[1]	54	1			T210	2		T230	2		T61	2
auto[1879048192:2013265919]	auto[0]	162	1			T141	4		T60	6		T216	2
auto[1879048192:2013265919]	auto[1]	66	1			T73	2		T61	2		T143	2
auto[2013265920:2147483647]	auto[0]	90	1			T93	2		T210	2		T256	2
auto[2013265920:2147483647]	auto[1]	78	1			T4	2		T32	2		T83	2
auto[2147483648:2281701375]	auto[0]	158	1			T15	2		T55	2		T141	2
auto[2147483648:2281701375]	auto[1]	60	1			T62	2		T71	2		T116	2
auto[2281701376:2415919103]	auto[0]	134	1			T2	2		T14	2		T16	2
auto[2281701376:2415919103]	auto[1]	74	1			T100	2		T222	2		T108	2
auto[2415919104:2550136831]	auto[0]	124	1			T4	2		T42	2		T62	2
auto[2415919104:2550136831]	auto[1]	64	1			T55	2		T26	2		T67	2
auto[2550136832:2684354559]	auto[0]	142	1			T1	2		T28	2		T61	6
auto[2550136832:2684354559]	auto[1]	64	1			T54	2		T7	2		T290	2
auto[2684354560:2818572287]	auto[0]	118	1			T4	4		T83	2		T61	4
auto[2684354560:2818572287]	auto[1]	60	1			T287	2		T220	4		T65	2
auto[2818572288:2952790015]	auto[0]	148	1			T14	2		T97	2		T60	2
auto[2818572288:2952790015]	auto[1]	52	1			T51	2		T107	2		T132	2
auto[2952790016:3087007743]	auto[0]	142	1			T2	2		T15	2		T210	2
auto[2952790016:3087007743]	auto[1]	76	1			T2	2		T217	2		T62	2
auto[3087007744:3221225471]	auto[0]	134	1			T14	2		T40	2		T52	2
auto[3087007744:3221225471]	auto[1]	62	1			T26	2		T97	2		T100	2
auto[3221225472:3355443199]	auto[0]	128	1			T15	2		T42	2		T141	2
auto[3221225472:3355443199]	auto[1]	48	1			T107	2		T220	2		T133	2
auto[3355443200:3489660927]	auto[0]	166	1			T2	2		T210	2		T230	2
auto[3355443200:3489660927]	auto[1]	78	1			T141	2		T276	2		T68	2
auto[3489660928:3623878655]	auto[0]	156	1			T2	2		T97	2		T43	2
auto[3489660928:3623878655]	auto[1]	58	1			T89	2		T29	2		T61	2
auto[3623878656:3758096383]	auto[0]	126	1			T4	2		T123	2		T210	2
auto[3623878656:3758096383]	auto[1]	64	1			T73	2		T108	2		T316	2
auto[3758096384:3892314111]	auto[0]	142	1			T1	2		T15	2		T209	2
auto[3758096384:3892314111]	auto[1]	64	1			T228	2		T107	2		T220	2
auto[3892314112:4026531839]	auto[0]	116	1			T15	2		T61	4		T235	2
auto[3892314112:4026531839]	auto[1]	70	1			T210	2		T216	2		T68	2
auto[4026531840:4160749567]	auto[0]	132	1			T15	2		T209	2		T43	2
auto[4026531840:4160749567]	auto[1]	56	1			T225	2		T229	2		T222	2
auto[4160749568:4294967295]	auto[0]	146	1			T15	2		T42	2		T142	2
auto[4160749568:4294967295]	auto[1]	58	1			T51	2		T229	2		T61	2