Unified Coverage Report :: Group Instance : salt_7

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2908

1

T1

4

T2

5

T4

1

auto[1]

297

1

T123

12

T83

3

T140

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	88	1			T14	1		T15	1		T52	1
auto[134217728:268435455]	104	1			T123	1		T43	1		T140	1
auto[268435456:402653183]	101	1			T14	1		T15	1		T40	1
auto[402653184:536870911]	108	1			T15	1		T123	2		T55	1
auto[536870912:671088639]	91	1			T123	2		T26	1		T83	1
auto[671088640:805306367]	111	1			T217	1		T142	1		T100	1
auto[805306368:939524095]	94	1			T4	1		T123	2		T97	1
auto[939524096:1073741823]	95	1			T89	1		T93	1		T55	2
auto[1073741824:1207959551]	94	1			T40	1		T210	1		T230	1
auto[1207959552:1342177279]	89	1			T1	1		T15	1		T43	1
auto[1342177280:1476395007]	108	1			T67	1		T142	1		T155	1
auto[1476395008:1610612735]	111	1			T2	1		T209	1		T26	1
auto[1610612736:1744830463]	116	1			T40	1		T89	1		T210	1
auto[1744830464:1879048191]	91	1			T123	2		T100	1		T155	1
auto[1879048192:2013265919]	91	1			T14	1		T15	1		T40	1
auto[2013265920:2147483647]	107	1			T141	2		T230	1		T67	2
auto[2147483648:2281701375]	95	1			T97	1		T210	1		T223	1
auto[2281701376:2415919103]	101	1			T123	1		T140	1		T141	1
auto[2415919104:2550136831]	107	1			T2	1		T14	1		T93	2
auto[2550136832:2684354559]	90	1			T123	1		T83	1		T230	1
auto[2684354560:2818572287]	112	1			T14	1		T123	1		T217	1
auto[2818572288:2952790015]	110	1			T209	1		T217	1		T26	1
auto[2952790016:3087007743]	85	1			T1	1		T2	3		T217	1
auto[3087007744:3221225471]	102	1			T14	1		T55	2		T53	1
auto[3221225472:3355443199]	106	1			T123	1		T42	1		T210	1
auto[3355443200:3489660927]	99	1			T41	1		T209	1		T32	1
auto[3489660928:3623878655]	97	1			T93	1		T97	1		T83	1
auto[3623878656:3758096383]	90	1			T55	1		T42	1		T43	1
auto[3758096384:3892314111]	110	1			T15	1		T16	1		T217	1
auto[3892314112:4026531839]	101	1			T1	1		T52	1		T42	1
auto[4026531840:4160749567]	95	1			T1	1		T41	1		T93	1
auto[4160749568:4294967295]	106	1			T16	1		T228	1		T55	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	80	1			T14	1		T15	1		T52	1
auto[0:134217727]	auto[1]	8	1			T227	1		T349	1		T297	1
auto[134217728:268435455]	auto[0]	92	1			T43	1		T61	2		T107	1
auto[134217728:268435455]	auto[1]	12	1			T123	1		T140	1		T142	1
auto[268435456:402653183]	auto[0]	87	1			T14	1		T15	1		T40	1
auto[268435456:402653183]	auto[1]	14	1			T123	1		T140	1		T226	1
auto[402653184:536870911]	auto[0]	93	1			T15	1		T55	1		T43	1
auto[402653184:536870911]	auto[1]	15	1			T123	2		T142	1		T227	1
auto[536870912:671088639]	auto[0]	85	1			T26	1		T83	1		T42	1
auto[536870912:671088639]	auto[1]	6	1			T123	2		T155	1		T295	1
auto[671088640:805306367]	auto[0]	98	1			T217	1		T100	1		T229	1
auto[671088640:805306367]	auto[1]	13	1			T142	1		T155	2		T143	1
auto[805306368:939524095]	auto[0]	83	1			T4	1		T123	2		T97	1
auto[805306368:939524095]	auto[1]	11	1			T227	1		T297	1		T193	1
auto[939524096:1073741823]	auto[0]	84	1			T89	1		T93	1		T55	2
auto[939524096:1073741823]	auto[1]	11	1			T142	1		T295	2		T338	1
auto[1073741824:1207959551]	auto[0]	86	1			T40	1		T210	1		T230	1
auto[1073741824:1207959551]	auto[1]	8	1			T227	1		T143	2		T349	1
auto[1207959552:1342177279]	auto[0]	78	1			T1	1		T15	1		T43	1
auto[1207959552:1342177279]	auto[1]	11	1			T141	1		T142	2		T349	2
auto[1342177280:1476395007]	auto[0]	92	1			T67	1		T155	1		T61	3
auto[1342177280:1476395007]	auto[1]	16	1			T142	1		T143	1		T145	1
auto[1476395008:1610612735]	auto[0]	102	1			T2	1		T209	1		T26	1
auto[1476395008:1610612735]	auto[1]	9	1			T83	1		T307	1		T145	1
auto[1610612736:1744830463]	auto[0]	104	1			T40	1		T89	1		T210	1
auto[1610612736:1744830463]	auto[1]	12	1			T142	2		T143	1		T427	1
auto[1744830464:1879048191]	auto[0]	85	1			T100	1		T61	1		T276	2
auto[1744830464:1879048191]	auto[1]	6	1			T123	2		T155	1		T349	1
auto[1879048192:2013265919]	auto[0]	83	1			T14	1		T15	1		T40	1
auto[1879048192:2013265919]	auto[1]	8	1			T227	1		T143	2		T278	1
auto[2013265920:2147483647]	auto[0]	102	1			T141	2		T230	1		T67	2
auto[2013265920:2147483647]	auto[1]	5	1			T142	1		T227	1		T145	1
auto[2147483648:2281701375]	auto[0]	89	1			T97	1		T210	1		T223	1
auto[2147483648:2281701375]	auto[1]	6	1			T142	1		T155	1		T295	1
auto[2281701376:2415919103]	auto[0]	91	1			T141	1		T28	1		T222	1
auto[2281701376:2415919103]	auto[1]	10	1			T123	1		T140	1		T142	1
auto[2415919104:2550136831]	auto[0]	99	1			T2	1		T14	1		T93	2
auto[2415919104:2550136831]	auto[1]	8	1			T142	3		T406	1		T356	1
auto[2550136832:2684354559]	auto[0]	82	1			T83	1		T230	1		T61	3
auto[2550136832:2684354559]	auto[1]	8	1			T123	1		T142	1		T349	1
auto[2684354560:2818572287]	auto[0]	104	1			T14	1		T217	1		T225	1
auto[2684354560:2818572287]	auto[1]	8	1			T123	1		T227	1		T297	1
auto[2818572288:2952790015]	auto[0]	96	1			T209	1		T217	1		T26	1
auto[2818572288:2952790015]	auto[1]	14	1			T83	1		T142	1		T143	1
auto[2952790016:3087007743]	auto[0]	79	1			T1	1		T2	3		T217	1
auto[2952790016:3087007743]	auto[1]	6	1			T143	1		T196	1		T289	1
auto[3087007744:3221225471]	auto[0]	93	1			T14	1		T55	2		T53	1
auto[3087007744:3221225471]	auto[1]	9	1			T278	1		T193	1		T196	2
auto[3221225472:3355443199]	auto[0]	100	1			T123	1		T42	1		T210	1
auto[3221225472:3355443199]	auto[1]	6	1			T142	1		T227	1		T349	2
auto[3355443200:3489660927]	auto[0]	91	1			T41	1		T209	1		T32	1
auto[3355443200:3489660927]	auto[1]	8	1			T227	1		T143	1		T297	1
auto[3489660928:3623878655]	auto[0]	94	1			T93	1		T97	1		T83	1
auto[3489660928:3623878655]	auto[1]	3	1			T145	1		T366	1		T436	1
auto[3623878656:3758096383]	auto[0]	82	1			T55	1		T42	1		T43	1
auto[3623878656:3758096383]	auto[1]	8	1			T427	1		T338	1		T428	1
auto[3758096384:3892314111]	auto[0]	102	1			T15	1		T16	1		T217	1
auto[3758096384:3892314111]	auto[1]	8	1			T83	1		T142	1		T297	1
auto[3892314112:4026531839]	auto[0]	89	1			T1	1		T52	1		T42	1
auto[3892314112:4026531839]	auto[1]	12	1			T142	1		T227	1		T143	1
auto[4026531840:4160749567]	auto[0]	86	1			T1	1		T41	1		T93	1
auto[4026531840:4160749567]	auto[1]	9	1			T123	1		T142	1		T155	1
auto[4160749568:4294967295]	auto[0]	97	1			T16	1		T228	1		T55	1
auto[4160749568:4294967295]	auto[1]	9	1			T227	1		T349	1		T294	1