Unified Coverage Report :: Group Instance : sealing_sw_binding_7

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1559

1

T1

2

T2

1

T4

3

auto[1]

1732

1

T1

2

T2

6

T4

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	99	1			T67	1		T142	2		T33	1
auto[134217728:268435455]	109	1			T52	1		T32	1		T83	1
auto[268435456:402653183]	106	1			T26	1		T32	1		T223	1
auto[402653184:536870911]	110	1			T2	1		T4	1		T93	1
auto[536870912:671088639]	97	1			T40	1		T26	1		T97	1
auto[671088640:805306367]	89	1			T41	1		T141	1		T61	1
auto[805306368:939524095]	114	1			T123	1		T217	1		T225	1
auto[939524096:1073741823]	103	1			T4	1		T123	1		T83	1
auto[1073741824:1207959551]	105	1			T93	1		T42	1		T43	1
auto[1207959552:1342177279]	107	1			T15	1		T93	1		T83	1
auto[1342177280:1476395007]	92	1			T15	1		T40	1		T73	1
auto[1476395008:1610612735]	106	1			T14	1		T15	1		T209	2
auto[1610612736:1744830463]	112	1			T2	1		T14	1		T217	1
auto[1744830464:1879048191]	102	1			T217	1		T42	1		T7	1
auto[1879048192:2013265919]	99	1			T52	1		T55	1		T217	1
auto[2013265920:2147483647]	111	1			T2	1		T4	1		T14	1
auto[2147483648:2281701375]	117	1			T55	1		T51	1		T216	1
auto[2281701376:2415919103]	89	1			T2	1		T55	1		T141	2
auto[2415919104:2550136831]	89	1			T1	1		T15	2		T230	1
auto[2550136832:2684354559]	97	1			T6	1		T16	1		T26	1
auto[2684354560:2818572287]	105	1			T97	1		T83	1		T42	1
auto[2818572288:2952790015]	103	1			T1	1		T2	1		T210	1
auto[2952790016:3087007743]	97	1			T93	1		T210	1		T61	2
auto[3087007744:3221225471]	97	1			T4	1		T228	1		T26	1
auto[3221225472:3355443199]	112	1			T16	1		T55	1		T42	1
auto[3355443200:3489660927]	101	1			T2	1		T14	2		T217	1
auto[3489660928:3623878655]	105	1			T1	1		T209	1		T55	1
auto[3623878656:3758096383]	103	1			T4	1		T41	1		T93	1
auto[3758096384:3892314111]	102	1			T15	1		T40	1		T55	1
auto[3892314112:4026531839]	116	1			T1	1		T15	1		T93	1
auto[4026531840:4160749567]	89	1			T2	1		T97	1		T42	1
auto[4160749568:4294967295]	108	1			T14	1		T40	1		T58	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	43	1			T33	1		T256	1		T68	1
auto[0:134217727]	auto[1]	56	1			T67	1		T142	2		T257	1
auto[134217728:268435455]	auto[0]	49	1			T32	1		T83	1		T62	1
auto[134217728:268435455]	auto[1]	60	1			T52	1		T43	1		T430	1
auto[268435456:402653183]	auto[0]	43	1			T32	1		T223	1		T299	1
auto[268435456:402653183]	auto[1]	63	1			T26	1		T18	1		T222	1
auto[402653184:536870911]	auto[0]	54	1			T4	1		T51	1		T229	1
auto[402653184:536870911]	auto[1]	56	1			T2	1		T93	1		T61	2
auto[536870912:671088639]	auto[0]	50	1			T40	1		T229	1		T216	1
auto[536870912:671088639]	auto[1]	47	1			T26	1		T97	1		T43	1
auto[671088640:805306367]	auto[0]	48	1			T141	1		T18	1		T227	1
auto[671088640:805306367]	auto[1]	41	1			T41	1		T61	1		T441	1
auto[805306368:939524095]	auto[0]	55	1			T60	1		T61	1		T68	1
auto[805306368:939524095]	auto[1]	59	1			T123	1		T217	1		T225	1
auto[939524096:1073741823]	auto[0]	56	1			T4	1		T83	1		T141	1
auto[939524096:1073741823]	auto[1]	47	1			T123	1		T33	1		T227	1
auto[1073741824:1207959551]	auto[0]	43	1			T42	1		T43	1		T155	1
auto[1073741824:1207959551]	auto[1]	62	1			T93	1		T54	1		T276	1
auto[1207959552:1342177279]	auto[0]	51	1			T15	1		T83	1		T51	1
auto[1207959552:1342177279]	auto[1]	56	1			T93	1		T214	1		T256	1
auto[1342177280:1476395007]	auto[0]	40	1			T15	1		T68	1		T270	1
auto[1342177280:1476395007]	auto[1]	52	1			T40	1		T73	1		T61	1
auto[1476395008:1610612735]	auto[0]	47	1			T15	1		T209	1		T97	1
auto[1476395008:1610612735]	auto[1]	59	1			T14	1		T209	1		T53	1
auto[1610612736:1744830463]	auto[0]	46	1			T51	1		T61	1		T68	1
auto[1610612736:1744830463]	auto[1]	66	1			T2	1		T14	1		T217	1
auto[1744830464:1879048191]	auto[0]	47	1			T42	1		T307	1		T432	1
auto[1744830464:1879048191]	auto[1]	55	1			T217	1		T7	1		T214	1
auto[1879048192:2013265919]	auto[0]	44	1			T42	1		T51	1		T230	1
auto[1879048192:2013265919]	auto[1]	55	1			T52	1		T55	1		T217	1
auto[2013265920:2147483647]	auto[0]	54	1			T55	1		T43	1		T100	1
auto[2013265920:2147483647]	auto[1]	57	1			T2	1		T4	1		T14	1
auto[2147483648:2281701375]	auto[0]	57	1			T51	1		T216	1		T68	1
auto[2147483648:2281701375]	auto[1]	60	1			T55	1		T68	2		T35	1
auto[2281701376:2415919103]	auto[0]	48	1			T2	1		T55	1		T60	1
auto[2281701376:2415919103]	auto[1]	41	1			T141	2		T307	1		T47	1
auto[2415919104:2550136831]	auto[0]	44	1			T15	2		T230	1		T61	1
auto[2415919104:2550136831]	auto[1]	45	1			T1	1		T290	1		T107	1
auto[2550136832:2684354559]	auto[0]	44	1			T43	1		T307	1		T64	1
auto[2550136832:2684354559]	auto[1]	53	1			T6	1		T16	1		T26	1
auto[2684354560:2818572287]	auto[0]	56	1			T42	1		T29	1		T60	1
auto[2684354560:2818572287]	auto[1]	49	1			T97	1		T83	1		T155	1
auto[2818572288:2952790015]	auto[0]	43	1			T210	1		T61	3		T257	1
auto[2818572288:2952790015]	auto[1]	60	1			T1	1		T2	1		T67	1
auto[2952790016:3087007743]	auto[0]	42	1			T210	1		T61	1		T290	1
auto[2952790016:3087007743]	auto[1]	55	1			T93	1		T61	1		T35	1
auto[3087007744:3221225471]	auto[0]	52	1			T4	1		T228	1		T141	1
auto[3087007744:3221225471]	auto[1]	45	1			T26	1		T51	1		T18	1
auto[3221225472:3355443199]	auto[0]	52	1			T16	1		T55	1		T257	1
auto[3221225472:3355443199]	auto[1]	60	1			T42	1		T27	1		T67	1
auto[3355443200:3489660927]	auto[0]	47	1			T14	2		T210	1		T141	1
auto[3355443200:3489660927]	auto[1]	54	1			T2	1		T217	1		T210	1
auto[3489660928:3623878655]	auto[0]	55	1			T1	1		T209	1		T227	1
auto[3489660928:3623878655]	auto[1]	50	1			T55	1		T27	1		T61	3
auto[3623878656:3758096383]	auto[0]	62	1			T51	1		T61	1		T68	1
auto[3623878656:3758096383]	auto[1]	41	1			T4	1		T41	1		T93	1
auto[3758096384:3892314111]	auto[0]	42	1			T15	1		T55	1		T68	2
auto[3758096384:3892314111]	auto[1]	60	1			T40	1		T83	1		T210	1
auto[3892314112:4026531839]	auto[0]	59	1			T1	1		T15	1		T26	1
auto[3892314112:4026531839]	auto[1]	57	1			T93	1		T97	1		T140	1
auto[4026531840:4160749567]	auto[0]	33	1			T61	1		T235	1		T34	1
auto[4026531840:4160749567]	auto[1]	56	1			T2	1		T97	1		T42	1
auto[4160749568:4294967295]	auto[0]	53	1			T14	1		T58	1		T100	1
auto[4160749568:4294967295]	auto[1]	55	1			T40	1		T230	1		T73	1