Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6778

1

T1

12

T2

10

T4

2

auto[1]

302

1

T123

5

T83

2

T140

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	2867	1			T1	6		T2	3		T4	1
auto[134217728:268435455]	163	1			T1	2		T14	1		T41	1
auto[268435456:402653183]	151	1			T2	1		T40	1		T89	1
auto[402653184:536870911]	158	1			T15	1		T55	2		T97	1
auto[536870912:671088639]	125	1			T52	1		T42	1		T140	1
auto[671088640:805306367]	159	1			T14	2		T52	1		T141	1
auto[805306368:939524095]	168	1			T2	1		T97	1		T83	1
auto[939524096:1073741823]	142	1			T2	1		T93	1		T217	1
auto[1073741824:1207959551]	122	1			T2	1		T14	1		T89	1
auto[1207959552:1342177279]	138	1			T15	1		T40	1		T26	1
auto[1342177280:1476395007]	105	1			T55	1		T217	1		T42	1
auto[1476395008:1610612735]	132	1			T42	1		T27	1		T28	1
auto[1610612736:1744830463]	143	1			T14	1		T15	1		T93	1
auto[1744830464:1879048191]	145	1			T1	1		T4	1		T97	1
auto[1879048192:2013265919]	147	1			T1	1		T209	1		T123	1
auto[2013265920:2147483647]	124	1			T209	1		T123	1		T97	2
auto[2147483648:2281701375]	119	1			T123	1		T26	1		T141	2
auto[2281701376:2415919103]	116	1			T123	1		T42	1		T43	1
auto[2415919104:2550136831]	133	1			T2	1		T14	2		T40	1
auto[2550136832:2684354559]	126	1			T1	1		T14	1		T16	1
auto[2684354560:2818572287]	129	1			T123	2		T140	1		T28	1
auto[2818572288:2952790015]	119	1			T55	1		T42	1		T61	2
auto[2952790016:3087007743]	130	1			T2	1		T15	1		T40	1
auto[3087007744:3221225471]	126	1			T67	1		T28	1		T100	1
auto[3221225472:3355443199]	128	1			T15	1		T209	1		T43	1
auto[3355443200:3489660927]	138	1			T15	1		T53	1		T42	1
auto[3489660928:3623878655]	144	1			T16	1		T41	1		T93	1
auto[3623878656:3758096383]	122	1			T14	1		T83	1		T210	2
auto[3758096384:3892314111]	130	1			T1	1		T40	1		T217	1
auto[3892314112:4026531839]	137	1			T141	1		T142	1		T100	2
auto[4026531840:4160749567]	149	1			T26	2		T32	1		T42	1
auto[4160749568:4294967295]	145	1			T2	1		T93	1		T97	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2853	1			T1	6		T2	3		T4	1
auto[0:134217727]	auto[1]	14	1			T123	1		T227	1		T143	1
auto[134217728:268435455]	auto[0]	156	1			T1	2		T14	1		T41	1
auto[134217728:268435455]	auto[1]	7	1			T143	1		T193	1		T196	1
auto[268435456:402653183]	auto[0]	139	1			T2	1		T40	1		T89	1
auto[268435456:402653183]	auto[1]	12	1			T140	2		T155	1		T143	1
auto[402653184:536870911]	auto[0]	147	1			T15	1		T55	2		T97	1
auto[402653184:536870911]	auto[1]	11	1			T155	1		T349	1		T427	1
auto[536870912:671088639]	auto[0]	118	1			T52	1		T42	1		T28	1
auto[536870912:671088639]	auto[1]	7	1			T140	1		T349	1		T145	1
auto[671088640:805306367]	auto[0]	150	1			T14	2		T52	1		T141	1
auto[671088640:805306367]	auto[1]	9	1			T349	1		T289	1		T315	1
auto[805306368:939524095]	auto[0]	160	1			T2	1		T97	1		T141	1
auto[805306368:939524095]	auto[1]	8	1			T83	1		T227	1		T143	2
auto[939524096:1073741823]	auto[0]	132	1			T2	1		T93	1		T217	1
auto[939524096:1073741823]	auto[1]	10	1			T155	1		T227	3		T307	1
auto[1073741824:1207959551]	auto[0]	115	1			T2	1		T14	1		T89	1
auto[1073741824:1207959551]	auto[1]	7	1			T142	1		T226	1		T295	1
auto[1207959552:1342177279]	auto[0]	126	1			T15	1		T40	1		T26	1
auto[1207959552:1342177279]	auto[1]	12	1			T141	1		T155	1		T145	1
auto[1342177280:1476395007]	auto[0]	101	1			T55	1		T217	1		T42	1
auto[1342177280:1476395007]	auto[1]	4	1			T226	1		T407	1		T436	1
auto[1476395008:1610612735]	auto[0]	118	1			T42	1		T27	1		T28	1
auto[1476395008:1610612735]	auto[1]	14	1			T142	1		T307	1		T427	1
auto[1610612736:1744830463]	auto[0]	131	1			T14	1		T15	1		T93	1
auto[1610612736:1744830463]	auto[1]	12	1			T142	1		T143	1		T349	1
auto[1744830464:1879048191]	auto[0]	134	1			T1	1		T4	1		T97	1
auto[1744830464:1879048191]	auto[1]	11	1			T142	2		T307	1		T349	1
auto[1879048192:2013265919]	auto[0]	142	1			T1	1		T209	1		T123	1
auto[1879048192:2013265919]	auto[1]	5	1			T227	1		T349	1		T193	1
auto[2013265920:2147483647]	auto[0]	116	1			T209	1		T123	1		T97	2
auto[2013265920:2147483647]	auto[1]	8	1			T142	1		T227	1		T196	1
auto[2147483648:2281701375]	auto[0]	107	1			T123	1		T26	1		T141	1
auto[2147483648:2281701375]	auto[1]	12	1			T141	1		T360	1		T274	1
auto[2281701376:2415919103]	auto[0]	108	1			T42	1		T43	1		T27	1
auto[2281701376:2415919103]	auto[1]	8	1			T123	1		T349	1		T427	1
auto[2415919104:2550136831]	auto[0]	119	1			T2	1		T14	2		T40	1
auto[2415919104:2550136831]	auto[1]	14	1			T123	1		T140	1		T227	1
auto[2550136832:2684354559]	auto[0]	115	1			T1	1		T14	1		T16	1
auto[2550136832:2684354559]	auto[1]	11	1			T295	1		T338	1		T315	1
auto[2684354560:2818572287]	auto[0]	117	1			T28	1		T73	1		T226	1
auto[2684354560:2818572287]	auto[1]	12	1			T123	2		T140	1		T227	1
auto[2818572288:2952790015]	auto[0]	112	1			T55	1		T42	1		T61	2
auto[2818572288:2952790015]	auto[1]	7	1			T295	2		T428	1		T437	1
auto[2952790016:3087007743]	auto[0]	122	1			T2	1		T15	1		T40	1
auto[2952790016:3087007743]	auto[1]	8	1			T142	2		T143	2		T295	1
auto[3087007744:3221225471]	auto[0]	121	1			T67	1		T28	1		T100	1
auto[3087007744:3221225471]	auto[1]	5	1			T268	1		T289	1		T383	1
auto[3221225472:3355443199]	auto[0]	118	1			T15	1		T209	1		T43	1
auto[3221225472:3355443199]	auto[1]	10	1			T142	1		T143	1		T360	1
auto[3355443200:3489660927]	auto[0]	130	1			T15	1		T53	1		T42	1
auto[3355443200:3489660927]	auto[1]	8	1			T349	1		T145	1		T297	1
auto[3489660928:3623878655]	auto[0]	132	1			T16	1		T41	1		T93	1
auto[3489660928:3623878655]	auto[1]	12	1			T142	3		T143	2		T360	1
auto[3623878656:3758096383]	auto[0]	115	1			T14	1		T83	1		T210	2
auto[3623878656:3758096383]	auto[1]	7	1			T143	2		T294	1		T318	2
auto[3758096384:3892314111]	auto[0]	121	1			T1	1		T40	1		T217	1
auto[3758096384:3892314111]	auto[1]	9	1			T155	2		T145	1		T295	1
auto[3892314112:4026531839]	auto[0]	126	1			T141	1		T100	2		T216	1
auto[3892314112:4026531839]	auto[1]	11	1			T142	1		T155	1		T226	1
auto[4026531840:4160749567]	auto[0]	137	1			T26	2		T32	1		T42	1
auto[4026531840:4160749567]	auto[1]	12	1			T142	2		T155	1		T227	1
auto[4160749568:4294967295]	auto[0]	140	1			T2	1		T93	1		T97	1
auto[4160749568:4294967295]	auto[1]	5	1			T83	1		T307	1		T268	1