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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.73 99.04 98.11 98.39 100.00 99.02 98.41 91.12


Total test records in report: 1080
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1007 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.569625562 Jul 17 07:02:28 PM PDT 24 Jul 17 07:02:35 PM PDT 24 165723070 ps
T1008 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.641310978 Jul 17 07:02:52 PM PDT 24 Jul 17 07:02:58 PM PDT 24 290418999 ps
T1009 /workspace/coverage/cover_reg_top/38.keymgr_intr_test.2101157794 Jul 17 07:03:20 PM PDT 24 Jul 17 07:03:25 PM PDT 24 19457593 ps
T1010 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2806550180 Jul 17 07:03:15 PM PDT 24 Jul 17 07:03:22 PM PDT 24 91311791 ps
T1011 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.208726170 Jul 17 07:03:17 PM PDT 24 Jul 17 07:03:26 PM PDT 24 1155100334 ps
T1012 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1566178628 Jul 17 07:03:18 PM PDT 24 Jul 17 07:03:24 PM PDT 24 55361411 ps
T1013 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2095003480 Jul 17 07:03:15 PM PDT 24 Jul 17 07:03:18 PM PDT 24 14170348 ps
T1014 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.804735106 Jul 17 07:02:31 PM PDT 24 Jul 17 07:02:39 PM PDT 24 32827962 ps
T1015 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.1347152064 Jul 17 07:02:29 PM PDT 24 Jul 17 07:02:41 PM PDT 24 236840388 ps
T1016 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.427829 Jul 17 07:02:53 PM PDT 24 Jul 17 07:02:59 PM PDT 24 178781467 ps
T1017 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.616777601 Jul 17 07:02:55 PM PDT 24 Jul 17 07:02:57 PM PDT 24 9902580 ps
T1018 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.436076263 Jul 17 07:03:17 PM PDT 24 Jul 17 07:03:23 PM PDT 24 16785472 ps
T1019 /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2518411420 Jul 17 07:02:53 PM PDT 24 Jul 17 07:02:56 PM PDT 24 20822126 ps
T1020 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.1265090656 Jul 17 07:03:18 PM PDT 24 Jul 17 07:03:24 PM PDT 24 27297099 ps
T1021 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1405866923 Jul 17 07:03:15 PM PDT 24 Jul 17 07:03:24 PM PDT 24 151605554 ps
T179 /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.2373176704 Jul 17 07:02:34 PM PDT 24 Jul 17 07:02:47 PM PDT 24 486978921 ps
T1022 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.118428779 Jul 17 07:02:35 PM PDT 24 Jul 17 07:02:47 PM PDT 24 682996839 ps
T1023 /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3241760536 Jul 17 07:02:31 PM PDT 24 Jul 17 07:02:55 PM PDT 24 2597966495 ps
T1024 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.981039591 Jul 17 07:02:30 PM PDT 24 Jul 17 07:02:41 PM PDT 24 530955709 ps
T1025 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.554393293 Jul 17 07:03:10 PM PDT 24 Jul 17 07:03:12 PM PDT 24 292730886 ps
T1026 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.4193784450 Jul 17 07:02:23 PM PDT 24 Jul 17 07:02:33 PM PDT 24 379488820 ps
T1027 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.2493594229 Jul 17 07:02:56 PM PDT 24 Jul 17 07:02:59 PM PDT 24 47501165 ps
T1028 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.925262193 Jul 17 07:02:53 PM PDT 24 Jul 17 07:02:57 PM PDT 24 43643602 ps
T1029 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2234408846 Jul 17 07:02:54 PM PDT 24 Jul 17 07:03:00 PM PDT 24 145923295 ps
T1030 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3415259556 Jul 17 07:02:52 PM PDT 24 Jul 17 07:02:56 PM PDT 24 47141394 ps
T1031 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.428491566 Jul 17 07:02:29 PM PDT 24 Jul 17 07:02:38 PM PDT 24 19441021 ps
T1032 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2407354124 Jul 17 07:02:31 PM PDT 24 Jul 17 07:02:47 PM PDT 24 1344175752 ps
T1033 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2535526159 Jul 17 07:03:17 PM PDT 24 Jul 17 07:03:24 PM PDT 24 54948436 ps
T1034 /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2776361446 Jul 17 07:03:14 PM PDT 24 Jul 17 07:03:17 PM PDT 24 30227821 ps
T1035 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.4077462115 Jul 17 07:03:15 PM PDT 24 Jul 17 07:03:19 PM PDT 24 136876047 ps
T1036 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3972338927 Jul 17 07:02:50 PM PDT 24 Jul 17 07:02:54 PM PDT 24 99759272 ps
T184 /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2891788002 Jul 17 07:03:16 PM PDT 24 Jul 17 07:03:26 PM PDT 24 270561954 ps
T1037 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2146913753 Jul 17 07:03:14 PM PDT 24 Jul 17 07:03:17 PM PDT 24 25753517 ps
T1038 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2544907872 Jul 17 07:03:14 PM PDT 24 Jul 17 07:03:18 PM PDT 24 15653795 ps
T1039 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.363037916 Jul 17 07:02:29 PM PDT 24 Jul 17 07:02:37 PM PDT 24 50452426 ps
T1040 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2537792161 Jul 17 07:02:52 PM PDT 24 Jul 17 07:02:57 PM PDT 24 430159457 ps
T1041 /workspace/coverage/cover_reg_top/5.keymgr_intr_test.1300961621 Jul 17 07:02:32 PM PDT 24 Jul 17 07:02:41 PM PDT 24 14007342 ps
T1042 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1402302355 Jul 17 07:03:17 PM PDT 24 Jul 17 07:03:23 PM PDT 24 11573950 ps
T1043 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.2480599334 Jul 17 07:02:32 PM PDT 24 Jul 17 07:02:39 PM PDT 24 8936707 ps
T1044 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.3573140282 Jul 17 07:02:53 PM PDT 24 Jul 17 07:02:56 PM PDT 24 53141145 ps
T1045 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.536185491 Jul 17 07:02:30 PM PDT 24 Jul 17 07:02:39 PM PDT 24 203397274 ps
T1046 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3131217276 Jul 17 07:02:53 PM PDT 24 Jul 17 07:02:56 PM PDT 24 12436211 ps
T171 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.2480260057 Jul 17 07:02:31 PM PDT 24 Jul 17 07:02:41 PM PDT 24 775373687 ps
T1047 /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3153519402 Jul 17 07:02:30 PM PDT 24 Jul 17 07:02:38 PM PDT 24 13743862 ps
T1048 /workspace/coverage/cover_reg_top/41.keymgr_intr_test.541195741 Jul 17 07:03:13 PM PDT 24 Jul 17 07:03:15 PM PDT 24 9997381 ps
T1049 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.983518538 Jul 17 07:03:16 PM PDT 24 Jul 17 07:03:27 PM PDT 24 729838009 ps
T1050 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.972103894 Jul 17 07:03:23 PM PDT 24 Jul 17 07:03:27 PM PDT 24 31257112 ps
T1051 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1133762374 Jul 17 07:02:52 PM PDT 24 Jul 17 07:02:56 PM PDT 24 91556902 ps
T1052 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.807222023 Jul 17 07:03:19 PM PDT 24 Jul 17 07:03:25 PM PDT 24 20537741 ps
T1053 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.4014540658 Jul 17 07:03:13 PM PDT 24 Jul 17 07:03:18 PM PDT 24 69328291 ps
T1054 /workspace/coverage/cover_reg_top/4.keymgr_intr_test.1670965250 Jul 17 07:02:38 PM PDT 24 Jul 17 07:02:43 PM PDT 24 12647663 ps
T1055 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3945790649 Jul 17 07:02:52 PM PDT 24 Jul 17 07:02:58 PM PDT 24 159440517 ps
T1056 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2717707308 Jul 17 07:02:29 PM PDT 24 Jul 17 07:02:43 PM PDT 24 887907743 ps
T1057 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1665066912 Jul 17 07:02:32 PM PDT 24 Jul 17 07:02:42 PM PDT 24 336745383 ps
T1058 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.912184421 Jul 17 07:02:28 PM PDT 24 Jul 17 07:02:34 PM PDT 24 64561238 ps
T1059 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.4108119542 Jul 17 07:02:52 PM PDT 24 Jul 17 07:02:58 PM PDT 24 143604867 ps
T1060 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.2363686558 Jul 17 07:03:17 PM PDT 24 Jul 17 07:03:22 PM PDT 24 13163565 ps
T1061 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.642929391 Jul 17 07:03:15 PM PDT 24 Jul 17 07:03:19 PM PDT 24 61176969 ps
T1062 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.850185731 Jul 17 07:02:33 PM PDT 24 Jul 17 07:02:42 PM PDT 24 216368212 ps
T1063 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1815165733 Jul 17 07:03:17 PM PDT 24 Jul 17 07:03:24 PM PDT 24 55948660 ps
T1064 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.3869819242 Jul 17 07:02:38 PM PDT 24 Jul 17 07:02:55 PM PDT 24 260121221 ps
T1065 /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2945004047 Jul 17 07:02:31 PM PDT 24 Jul 17 07:02:43 PM PDT 24 267578579 ps
T1066 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1117484132 Jul 17 07:03:16 PM PDT 24 Jul 17 07:03:26 PM PDT 24 162885326 ps
T1067 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.359429759 Jul 17 07:02:33 PM PDT 24 Jul 17 07:02:48 PM PDT 24 333003327 ps
T1068 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3361616751 Jul 17 07:03:13 PM PDT 24 Jul 17 07:03:17 PM PDT 24 198968910 ps
T1069 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.642694651 Jul 17 07:03:13 PM PDT 24 Jul 17 07:03:17 PM PDT 24 37901843 ps
T1070 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2857621706 Jul 17 07:03:17 PM PDT 24 Jul 17 07:03:24 PM PDT 24 112922102 ps
T1071 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3130084105 Jul 17 07:02:33 PM PDT 24 Jul 17 07:02:43 PM PDT 24 283522291 ps
T1072 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.789600072 Jul 17 07:02:29 PM PDT 24 Jul 17 07:02:42 PM PDT 24 136042224 ps
T1073 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3897418202 Jul 17 07:03:13 PM PDT 24 Jul 17 07:03:16 PM PDT 24 11141449 ps
T399 /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.3973442473 Jul 17 07:02:51 PM PDT 24 Jul 17 07:02:55 PM PDT 24 198920824 ps
T1074 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.919512851 Jul 17 07:03:14 PM PDT 24 Jul 17 07:03:17 PM PDT 24 36666575 ps
T1075 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1538849928 Jul 17 07:03:17 PM PDT 24 Jul 17 07:03:22 PM PDT 24 23679960 ps
T1076 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1512105485 Jul 17 07:02:19 PM PDT 24 Jul 17 07:02:25 PM PDT 24 64328738 ps
T1077 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2219205352 Jul 17 07:03:15 PM PDT 24 Jul 17 07:03:22 PM PDT 24 320153618 ps
T178 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.52805936 Jul 17 07:02:53 PM PDT 24 Jul 17 07:02:58 PM PDT 24 75361970 ps
T180 /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2043706505 Jul 17 07:02:29 PM PDT 24 Jul 17 07:02:39 PM PDT 24 1225377519 ps
T1078 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3871549952 Jul 17 07:02:29 PM PDT 24 Jul 17 07:02:39 PM PDT 24 402138907 ps
T1079 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1650848669 Jul 17 07:02:30 PM PDT 24 Jul 17 07:02:45 PM PDT 24 568811463 ps
T1080 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3855022754 Jul 17 07:02:29 PM PDT 24 Jul 17 07:02:46 PM PDT 24 454791999 ps

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.3600345172
Short name T2
Test name
Test status
Simulation time 1649260937 ps
CPU time 21.71 seconds
Started Jul 17 07:05:28 PM PDT 24
Finished Jul 17 07:05:53 PM PDT 24
Peak memory 222560 kb
Host smart-cdda4e08-4ed7-4cf1-81f9-d91705ab3765
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600345172 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.3600345172
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.2361366089
Short name T61
Test name
Test status
Simulation time 5110053849 ps
CPU time 64.89 seconds
Started Jul 17 07:06:19 PM PDT 24
Finished Jul 17 07:07:33 PM PDT 24
Peak memory 216364 kb
Host smart-ecfa79de-0d9a-400e-99a6-759a83886d28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361366089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.2361366089
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.120949352
Short name T11
Test name
Test status
Simulation time 991981567 ps
CPU time 24.41 seconds
Started Jul 17 07:06:07 PM PDT 24
Finished Jul 17 07:06:35 PM PDT 24
Peak memory 233228 kb
Host smart-08a3ff4a-7b10-42ec-9287-21f072f1e9ea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120949352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.120949352
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.452656771
Short name T65
Test name
Test status
Simulation time 3216962683 ps
CPU time 29.52 seconds
Started Jul 17 07:06:13 PM PDT 24
Finished Jul 17 07:06:53 PM PDT 24
Peak memory 216576 kb
Host smart-4eb247de-7849-4cea-9570-b9ba1737384c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452656771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.452656771
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.4215546141
Short name T150
Test name
Test status
Simulation time 114461478 ps
CPU time 1.2 seconds
Started Jul 17 07:02:52 PM PDT 24
Finished Jul 17 07:02:55 PM PDT 24
Peak memory 205608 kb
Host smart-46cee238-b3af-4686-ad9f-a2976eeb8e33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215546141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.4215546141
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.1283373174
Short name T142
Test name
Test status
Simulation time 1185537208 ps
CPU time 58.37 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:09:10 PM PDT 24
Peak memory 215696 kb
Host smart-c976f79d-59e9-4e4d-8379-fb86b8138b34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1283373174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.1283373174
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.478683034
Short name T220
Test name
Test status
Simulation time 52140057195 ps
CPU time 512.48 seconds
Started Jul 17 07:09:44 PM PDT 24
Finished Jul 17 07:18:28 PM PDT 24
Peak memory 222492 kb
Host smart-7699c6c1-c3e1-45ea-9138-c92955519d66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478683034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.478683034
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.3094613137
Short name T14
Test name
Test status
Simulation time 137869383 ps
CPU time 2.68 seconds
Started Jul 17 07:06:19 PM PDT 24
Finished Jul 17 07:06:31 PM PDT 24
Peak memory 214336 kb
Host smart-329e6837-14e5-496e-a4b9-9f314777f237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094613137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.3094613137
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.613971220
Short name T68
Test name
Test status
Simulation time 6102164263 ps
CPU time 141.06 seconds
Started Jul 17 07:06:15 PM PDT 24
Finished Jul 17 07:08:47 PM PDT 24
Peak memory 217244 kb
Host smart-0deb0ff9-ac93-4293-85e4-a42c791b8d18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613971220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.613971220
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.214198418
Short name T8
Test name
Test status
Simulation time 1680927497 ps
CPU time 16.54 seconds
Started Jul 17 07:08:06 PM PDT 24
Finished Jul 17 07:08:46 PM PDT 24
Peak memory 221268 kb
Host smart-65f3226b-352f-400d-b428-f04518f28b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214198418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.214198418
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.3572917989
Short name T42
Test name
Test status
Simulation time 1539433079 ps
CPU time 26.52 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:47 PM PDT 24
Peak memory 222484 kb
Host smart-29a0d76f-a628-49d1-be5f-45beb6bc2914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572917989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.3572917989
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.1872016565
Short name T124
Test name
Test status
Simulation time 566656338 ps
CPU time 4.23 seconds
Started Jul 17 07:02:54 PM PDT 24
Finished Jul 17 07:03:00 PM PDT 24
Peak memory 214224 kb
Host smart-214e2b97-d777-44fd-b222-1d9dafa8ee3a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872016565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.1872016565
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.1620558692
Short name T311
Test name
Test status
Simulation time 1015518098 ps
CPU time 54.55 seconds
Started Jul 17 07:05:29 PM PDT 24
Finished Jul 17 07:06:28 PM PDT 24
Peak memory 215304 kb
Host smart-823d6151-c07e-468c-85d7-305649fa2ae7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1620558692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.1620558692
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.568949163
Short name T18
Test name
Test status
Simulation time 116220039 ps
CPU time 2.78 seconds
Started Jul 17 07:07:59 PM PDT 24
Finished Jul 17 07:08:26 PM PDT 24
Peak memory 208532 kb
Host smart-325e6c94-2e08-4599-a742-a8a922109612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568949163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.568949163
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.4229249896
Short name T22
Test name
Test status
Simulation time 202355456 ps
CPU time 5.33 seconds
Started Jul 17 07:08:02 PM PDT 24
Finished Jul 17 07:08:30 PM PDT 24
Peak memory 214280 kb
Host smart-7b4761b6-44a5-445f-a348-4b2fb787e6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229249896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.4229249896
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.1401457475
Short name T143
Test name
Test status
Simulation time 792161033 ps
CPU time 13.34 seconds
Started Jul 17 07:07:49 PM PDT 24
Finished Jul 17 07:08:06 PM PDT 24
Peak memory 214340 kb
Host smart-2c69bc3c-69f6-4b59-845b-285939e60859
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1401457475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1401457475
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.912371516
Short name T349
Test name
Test status
Simulation time 156568014 ps
CPU time 6.76 seconds
Started Jul 17 07:07:51 PM PDT 24
Finished Jul 17 07:08:06 PM PDT 24
Peak memory 215248 kb
Host smart-1bb79907-8c8a-4491-a09f-5c0c77298db5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=912371516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.912371516
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.3687749060
Short name T26
Test name
Test status
Simulation time 215050609 ps
CPU time 5.15 seconds
Started Jul 17 07:07:53 PM PDT 24
Finished Jul 17 07:08:12 PM PDT 24
Peak memory 214140 kb
Host smart-6c15baff-55ba-4207-93e1-a79b96b3a3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687749060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3687749060
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.3023830987
Short name T203
Test name
Test status
Simulation time 4526221180 ps
CPU time 39.1 seconds
Started Jul 17 07:07:57 PM PDT 24
Finished Jul 17 07:08:57 PM PDT 24
Peak memory 222544 kb
Host smart-02afb464-7251-4981-9b8f-2828a2767c52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023830987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.3023830987
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.2388673253
Short name T366
Test name
Test status
Simulation time 834226294 ps
CPU time 40.48 seconds
Started Jul 17 07:07:51 PM PDT 24
Finished Jul 17 07:08:41 PM PDT 24
Peak memory 215872 kb
Host smart-e420a157-8f66-4050-9aaf-1e56f6eefa32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2388673253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.2388673253
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.58076467
Short name T32
Test name
Test status
Simulation time 669856927 ps
CPU time 3.09 seconds
Started Jul 17 07:06:13 PM PDT 24
Finished Jul 17 07:06:26 PM PDT 24
Peak memory 215468 kb
Host smart-1171b5b5-157e-4bd1-83bf-d754b18624ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58076467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.58076467
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.2314300839
Short name T101
Test name
Test status
Simulation time 261082283 ps
CPU time 5.76 seconds
Started Jul 17 07:06:10 PM PDT 24
Finished Jul 17 07:06:23 PM PDT 24
Peak memory 209528 kb
Host smart-f0aeb7ba-b035-4cce-b136-04f748ea8f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314300839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2314300839
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2626891992
Short name T45
Test name
Test status
Simulation time 84911723 ps
CPU time 3.65 seconds
Started Jul 17 07:06:05 PM PDT 24
Finished Jul 17 07:06:11 PM PDT 24
Peak memory 220584 kb
Host smart-9c164046-9ed5-4f00-8219-063ba7114318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626891992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2626891992
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.184045579
Short name T159
Test name
Test status
Simulation time 122097921 ps
CPU time 4.05 seconds
Started Jul 17 07:07:59 PM PDT 24
Finished Jul 17 07:08:24 PM PDT 24
Peak memory 218328 kb
Host smart-601f8852-8f9a-4f39-8092-c3cca456267e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184045579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.184045579
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.4180974550
Short name T172
Test name
Test status
Simulation time 344732008 ps
CPU time 5.15 seconds
Started Jul 17 07:03:13 PM PDT 24
Finished Jul 17 07:03:20 PM PDT 24
Peak memory 205500 kb
Host smart-fb547c84-952a-4333-bad8-158b82c466a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180974550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.4180974550
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.4165874109
Short name T428
Test name
Test status
Simulation time 139330570 ps
CPU time 5.52 seconds
Started Jul 17 07:06:10 PM PDT 24
Finished Jul 17 07:06:22 PM PDT 24
Peak memory 214336 kb
Host smart-7a6ccf31-5e67-4192-92fb-820dd028b674
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4165874109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.4165874109
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.1100707391
Short name T97
Test name
Test status
Simulation time 35771087 ps
CPU time 2.74 seconds
Started Jul 17 07:09:43 PM PDT 24
Finished Jul 17 07:09:56 PM PDT 24
Peak memory 221520 kb
Host smart-596ddec1-5378-4b4b-b286-50ad87dd58f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100707391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.1100707391
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.827359629
Short name T107
Test name
Test status
Simulation time 357267403 ps
CPU time 12.37 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:10:04 PM PDT 24
Peak memory 222672 kb
Host smart-cb414d18-94e8-4ef7-a345-0849b82a1e39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827359629 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.827359629
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.52178904
Short name T63
Test name
Test status
Simulation time 153058073 ps
CPU time 3.84 seconds
Started Jul 17 07:06:14 PM PDT 24
Finished Jul 17 07:06:29 PM PDT 24
Peak memory 218424 kb
Host smart-4e1a0eb9-563a-43bc-b1d8-6fe6dd80af02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52178904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.52178904
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.1187335727
Short name T263
Test name
Test status
Simulation time 3044415600 ps
CPU time 31.25 seconds
Started Jul 17 07:06:12 PM PDT 24
Finished Jul 17 07:06:53 PM PDT 24
Peak memory 216200 kb
Host smart-20226d9c-6a94-46b9-b2a3-06fe6d795eb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187335727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.1187335727
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.1073612358
Short name T56
Test name
Test status
Simulation time 25679002009 ps
CPU time 268.04 seconds
Started Jul 17 07:09:40 PM PDT 24
Finished Jul 17 07:14:15 PM PDT 24
Peak memory 217712 kb
Host smart-22a071b5-2dc0-4356-ba39-ce57c3359255
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073612358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.1073612358
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.3331769297
Short name T436
Test name
Test status
Simulation time 6492059097 ps
CPU time 81.15 seconds
Started Jul 17 07:09:45 PM PDT 24
Finished Jul 17 07:11:18 PM PDT 24
Peak memory 215512 kb
Host smart-4b34a681-1880-447a-a001-fe1ea58d9111
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3331769297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.3331769297
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.7647252
Short name T120
Test name
Test status
Simulation time 367092004 ps
CPU time 9.23 seconds
Started Jul 17 07:03:17 PM PDT 24
Finished Jul 17 07:03:30 PM PDT 24
Peak memory 214156 kb
Host smart-fc615544-5df5-4a07-ac84-e545390f0b79
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7647252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_S
EQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.ke
ymgr_shadow_reg_errors_with_csr_rw.7647252
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.752248643
Short name T15
Test name
Test status
Simulation time 75654187 ps
CPU time 3.72 seconds
Started Jul 17 07:09:45 PM PDT 24
Finished Jul 17 07:10:01 PM PDT 24
Peak memory 214272 kb
Host smart-61fde699-6125-47db-8f94-5cabeb4432ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752248643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.752248643
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.3060414796
Short name T163
Test name
Test status
Simulation time 37018415 ps
CPU time 1.6 seconds
Started Jul 17 07:05:28 PM PDT 24
Finished Jul 17 07:05:31 PM PDT 24
Peak memory 209488 kb
Host smart-c33d72f7-f320-4f4b-a6ea-a2a526849070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060414796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.3060414796
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2804555352
Short name T162
Test name
Test status
Simulation time 917133774 ps
CPU time 6.32 seconds
Started Jul 17 07:02:49 PM PDT 24
Finished Jul 17 07:02:57 PM PDT 24
Peak memory 213644 kb
Host smart-7429ca2c-6141-4591-b0f9-2779348ea14d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804555352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.2804555352
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.2438538467
Short name T307
Test name
Test status
Simulation time 138064773 ps
CPU time 2.92 seconds
Started Jul 17 07:07:56 PM PDT 24
Finished Jul 17 07:08:19 PM PDT 24
Peak memory 215284 kb
Host smart-687403d8-6e71-49b1-a277-3699aaff2182
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2438538467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.2438538467
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.3546974896
Short name T341
Test name
Test status
Simulation time 28934312 ps
CPU time 1.94 seconds
Started Jul 17 07:07:51 PM PDT 24
Finished Jul 17 07:08:01 PM PDT 24
Peak memory 214332 kb
Host smart-17e720d7-c358-4e3d-b68f-de46ecb382d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546974896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.3546974896
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.1877849850
Short name T17
Test name
Test status
Simulation time 12672563 ps
CPU time 0.79 seconds
Started Jul 17 07:06:13 PM PDT 24
Finished Jul 17 07:06:24 PM PDT 24
Peak memory 205996 kb
Host smart-9c51f2dc-b70b-42a0-9fc1-b584397f830b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877849850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.1877849850
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.3956008837
Short name T123
Test name
Test status
Simulation time 185516549 ps
CPU time 9.58 seconds
Started Jul 17 07:07:54 PM PDT 24
Finished Jul 17 07:08:20 PM PDT 24
Peak memory 214304 kb
Host smart-81162294-34ba-4256-96d7-5b90dcbcb4b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3956008837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.3956008837
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.1917674213
Short name T47
Test name
Test status
Simulation time 1868950273 ps
CPU time 4.6 seconds
Started Jul 17 07:06:12 PM PDT 24
Finished Jul 17 07:06:26 PM PDT 24
Peak memory 222448 kb
Host smart-a119470b-7cc5-420e-90d5-589a4afacc93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917674213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.1917674213
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.671057993
Short name T100
Test name
Test status
Simulation time 85194001 ps
CPU time 3.42 seconds
Started Jul 17 07:06:18 PM PDT 24
Finished Jul 17 07:06:31 PM PDT 24
Peak memory 221676 kb
Host smart-37590ca2-307e-4a31-94a3-58a6ef97a5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671057993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.671057993
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.1726593896
Short name T338
Test name
Test status
Simulation time 731058178 ps
CPU time 10.74 seconds
Started Jul 17 07:07:45 PM PDT 24
Finished Jul 17 07:07:57 PM PDT 24
Peak memory 214512 kb
Host smart-cbe7d419-0253-454d-8e32-3c85d0152247
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1726593896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.1726593896
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.1045966285
Short name T94
Test name
Test status
Simulation time 110193170 ps
CPU time 3.9 seconds
Started Jul 17 07:07:56 PM PDT 24
Finished Jul 17 07:08:20 PM PDT 24
Peak memory 214136 kb
Host smart-e4b322e2-5344-40b3-b4ae-50bc70819dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045966285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.1045966285
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.2047724143
Short name T140
Test name
Test status
Simulation time 70082308 ps
CPU time 3.88 seconds
Started Jul 17 07:08:06 PM PDT 24
Finished Jul 17 07:08:33 PM PDT 24
Peak memory 215060 kb
Host smart-9ee28976-d0d9-466a-8166-9d17cce4824b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2047724143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.2047724143
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.4121716175
Short name T273
Test name
Test status
Simulation time 6850220130 ps
CPU time 18.47 seconds
Started Jul 17 07:08:07 PM PDT 24
Finished Jul 17 07:08:49 PM PDT 24
Peak memory 222756 kb
Host smart-4c4908bd-06c9-485b-ae90-268334096802
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121716175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.4121716175
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.1939667518
Short name T156
Test name
Test status
Simulation time 64932724 ps
CPU time 2.03 seconds
Started Jul 17 07:07:54 PM PDT 24
Finished Jul 17 07:08:12 PM PDT 24
Peak memory 216884 kb
Host smart-a29dba24-7cae-4941-b469-f5504622a755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939667518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.1939667518
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2855578360
Short name T54
Test name
Test status
Simulation time 165867536 ps
CPU time 3.56 seconds
Started Jul 17 07:07:57 PM PDT 24
Finished Jul 17 07:08:21 PM PDT 24
Peak memory 218560 kb
Host smart-92a999d8-f32d-4847-af6b-8c19952265ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855578360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2855578360
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.3528450120
Short name T66
Test name
Test status
Simulation time 138544629 ps
CPU time 3.78 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:24 PM PDT 24
Peak memory 222428 kb
Host smart-44463f84-91bf-4c06-883b-637a52f6c808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528450120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.3528450120
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.2205668709
Short name T299
Test name
Test status
Simulation time 40213512 ps
CPU time 2.82 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:22 PM PDT 24
Peak memory 210328 kb
Host smart-5e5c352b-efc4-49ed-abe5-11b51b7cfac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205668709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.2205668709
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.942273939
Short name T235
Test name
Test status
Simulation time 75973762 ps
CPU time 2.43 seconds
Started Jul 17 07:07:54 PM PDT 24
Finished Jul 17 07:08:11 PM PDT 24
Peak memory 214588 kb
Host smart-c0be9224-f1ea-43f6-8fea-e7d7ec4322f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942273939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.942273939
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.3409464092
Short name T276
Test name
Test status
Simulation time 48745465 ps
CPU time 3.15 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:15 PM PDT 24
Peak memory 208076 kb
Host smart-97aa33bd-5353-4fd8-bf7f-ee17ecc83429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409464092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.3409464092
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.3342339459
Short name T59
Test name
Test status
Simulation time 127569928 ps
CPU time 2.81 seconds
Started Jul 17 07:07:54 PM PDT 24
Finished Jul 17 07:08:13 PM PDT 24
Peak memory 210388 kb
Host smart-1c886a2a-4c81-4475-a312-9f6ee0b6a89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342339459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.3342339459
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1187218594
Short name T170
Test name
Test status
Simulation time 185886202 ps
CPU time 5.07 seconds
Started Jul 17 07:03:19 PM PDT 24
Finished Jul 17 07:03:29 PM PDT 24
Peak memory 213792 kb
Host smart-53e3fa12-938b-4996-8750-bb26cb0b489d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187218594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.1187218594
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.4098409018
Short name T186
Test name
Test status
Simulation time 2426582456 ps
CPU time 6.46 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:19 PM PDT 24
Peak memory 214724 kb
Host smart-09f20fa5-daf2-41aa-be10-73506bd6c45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098409018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.4098409018
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.3855266282
Short name T157
Test name
Test status
Simulation time 111294693 ps
CPU time 3.72 seconds
Started Jul 17 07:06:15 PM PDT 24
Finished Jul 17 07:06:29 PM PDT 24
Peak memory 222700 kb
Host smart-b8bea505-9bec-4716-877d-18926b39d988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855266282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3855266282
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.2098882294
Short name T158
Test name
Test status
Simulation time 459945140 ps
CPU time 5.09 seconds
Started Jul 17 07:09:38 PM PDT 24
Finished Jul 17 07:09:45 PM PDT 24
Peak memory 222704 kb
Host smart-9adac08e-a384-454c-881d-866401593505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098882294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.2098882294
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.2466711158
Short name T475
Test name
Test status
Simulation time 201298518 ps
CPU time 3.14 seconds
Started Jul 17 07:06:14 PM PDT 24
Finished Jul 17 07:06:29 PM PDT 24
Peak memory 209008 kb
Host smart-dd1e6720-8803-4f98-aa8a-59645140e8fa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466711158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.2466711158
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.3823856401
Short name T81
Test name
Test status
Simulation time 1194717160 ps
CPU time 40.72 seconds
Started Jul 17 07:06:19 PM PDT 24
Finished Jul 17 07:07:10 PM PDT 24
Peak memory 222500 kb
Host smart-f01cb6a3-22da-4087-8994-d44886abf8bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823856401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.3823856401
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.1504948273
Short name T876
Test name
Test status
Simulation time 109645149 ps
CPU time 1.99 seconds
Started Jul 17 07:07:56 PM PDT 24
Finished Jul 17 07:08:18 PM PDT 24
Peak memory 214352 kb
Host smart-85b998aa-23aa-4063-ba21-935cea50f66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504948273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.1504948273
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.3466207111
Short name T95
Test name
Test status
Simulation time 598165869 ps
CPU time 4.37 seconds
Started Jul 17 07:08:02 PM PDT 24
Finished Jul 17 07:08:29 PM PDT 24
Peak memory 214412 kb
Host smart-05f36c2f-10f6-4a47-ad8b-1154a3a71475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466207111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.3466207111
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.3404082724
Short name T226
Test name
Test status
Simulation time 142855793 ps
CPU time 3.73 seconds
Started Jul 17 07:07:51 PM PDT 24
Finished Jul 17 07:08:02 PM PDT 24
Peak memory 215584 kb
Host smart-f8112b00-e80e-40c8-80df-92245853bd35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3404082724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.3404082724
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.2945530447
Short name T62
Test name
Test status
Simulation time 282369198 ps
CPU time 2.28 seconds
Started Jul 17 07:06:09 PM PDT 24
Finished Jul 17 07:06:16 PM PDT 24
Peak memory 219800 kb
Host smart-cdced6b6-d8e2-41e2-9be4-17ff94c5459e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945530447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2945530447
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.3202169755
Short name T439
Test name
Test status
Simulation time 84688814 ps
CPU time 5.13 seconds
Started Jul 17 07:06:15 PM PDT 24
Finished Jul 17 07:06:31 PM PDT 24
Peak memory 214332 kb
Host smart-a7392106-b39a-41bc-849d-0dbac0b96bab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3202169755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3202169755
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2891788002
Short name T184
Test name
Test status
Simulation time 270561954 ps
CPU time 6.31 seconds
Started Jul 17 07:03:16 PM PDT 24
Finished Jul 17 07:03:26 PM PDT 24
Peak memory 213752 kb
Host smart-76b5f460-847b-40a5-97e1-9cd0386445c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891788002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.2891788002
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.779972598
Short name T806
Test name
Test status
Simulation time 157144452 ps
CPU time 3.15 seconds
Started Jul 17 07:05:26 PM PDT 24
Finished Jul 17 07:05:30 PM PDT 24
Peak memory 210960 kb
Host smart-2f4a3c5c-a4b8-435e-90c1-7dd2ad29cf07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779972598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.779972598
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.661416006
Short name T343
Test name
Test status
Simulation time 132077723 ps
CPU time 3.34 seconds
Started Jul 17 07:05:29 PM PDT 24
Finished Jul 17 07:05:35 PM PDT 24
Peak memory 215260 kb
Host smart-3c91997c-c30a-4296-8c32-f253d9cabf08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661416006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.661416006
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.2423755284
Short name T138
Test name
Test status
Simulation time 2548364610 ps
CPU time 25.21 seconds
Started Jul 17 07:06:17 PM PDT 24
Finished Jul 17 07:06:53 PM PDT 24
Peak memory 222752 kb
Host smart-965fd237-bcdf-4722-8dca-ceb13cfa1b9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423755284 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.2423755284
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.3772378130
Short name T187
Test name
Test status
Simulation time 2588096856 ps
CPU time 23.01 seconds
Started Jul 17 07:06:17 PM PDT 24
Finished Jul 17 07:06:50 PM PDT 24
Peak memory 222612 kb
Host smart-7b56a125-1ba9-462c-9970-b0426c264e84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772378130 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.3772378130
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.2600012967
Short name T348
Test name
Test status
Simulation time 107935777 ps
CPU time 4.19 seconds
Started Jul 17 07:07:48 PM PDT 24
Finished Jul 17 07:07:54 PM PDT 24
Peak memory 222284 kb
Host smart-47ad5a58-4549-4089-8487-4f6315449450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600012967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.2600012967
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.1405075957
Short name T248
Test name
Test status
Simulation time 46348868 ps
CPU time 2.99 seconds
Started Jul 17 07:07:50 PM PDT 24
Finished Jul 17 07:07:56 PM PDT 24
Peak memory 210584 kb
Host smart-af6f750d-0bba-4baf-aed7-73f2f6300114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405075957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.1405075957
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.1974242169
Short name T373
Test name
Test status
Simulation time 369448689 ps
CPU time 16.79 seconds
Started Jul 17 07:07:50 PM PDT 24
Finished Jul 17 07:08:12 PM PDT 24
Peak memory 215708 kb
Host smart-82ec333f-e82c-43df-aac3-b5151d416160
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974242169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.1974242169
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.2034141596
Short name T98
Test name
Test status
Simulation time 7410300082 ps
CPU time 41.44 seconds
Started Jul 17 07:07:54 PM PDT 24
Finished Jul 17 07:08:50 PM PDT 24
Peak memory 214416 kb
Host smart-76167805-8f23-4fc4-baa2-f9477bdd760d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034141596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.2034141596
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.2012274449
Short name T584
Test name
Test status
Simulation time 939496827 ps
CPU time 7.1 seconds
Started Jul 17 07:08:06 PM PDT 24
Finished Jul 17 07:08:37 PM PDT 24
Peak memory 208660 kb
Host smart-963a0e84-b501-40e9-bcc6-b5ff3864c077
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012274449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2012274449
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.2955259754
Short name T356
Test name
Test status
Simulation time 127860070 ps
CPU time 6.93 seconds
Started Jul 17 07:06:06 PM PDT 24
Finished Jul 17 07:06:16 PM PDT 24
Peak memory 214444 kb
Host smart-fdaa6f9d-7040-415a-9a57-e7a3e29c56bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2955259754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.2955259754
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.4103195834
Short name T108
Test name
Test status
Simulation time 95531451 ps
CPU time 4.61 seconds
Started Jul 17 07:09:44 PM PDT 24
Finished Jul 17 07:10:01 PM PDT 24
Peak memory 207596 kb
Host smart-2dbf6bfb-3d70-4919-a2c3-8252a26e4df6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103195834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.4103195834
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3725201664
Short name T166
Test name
Test status
Simulation time 212795873 ps
CPU time 3.77 seconds
Started Jul 17 07:03:23 PM PDT 24
Finished Jul 17 07:03:30 PM PDT 24
Peak memory 213748 kb
Host smart-8711103b-5543-4f9d-b630-046a41127c8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725201664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.3725201664
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2043706505
Short name T180
Test name
Test status
Simulation time 1225377519 ps
CPU time 4.36 seconds
Started Jul 17 07:02:29 PM PDT 24
Finished Jul 17 07:02:39 PM PDT 24
Peak memory 213692 kb
Host smart-991fa977-9244-4934-b4ff-de233e867f53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043706505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.2043706505
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.672950158
Short name T176
Test name
Test status
Simulation time 285187479 ps
CPU time 4.66 seconds
Started Jul 17 07:02:35 PM PDT 24
Finished Jul 17 07:02:46 PM PDT 24
Peak memory 213632 kb
Host smart-214da87b-a0c8-46a6-8833-93fad9a27d2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672950158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.
672950158
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.1303680436
Short name T185
Test name
Test status
Simulation time 764359905 ps
CPU time 2.73 seconds
Started Jul 17 07:06:15 PM PDT 24
Finished Jul 17 07:06:29 PM PDT 24
Peak memory 209992 kb
Host smart-d87fad06-9712-4669-8e21-ddfb19f1fd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303680436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.1303680436
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.2018160589
Short name T160
Test name
Test status
Simulation time 166057778 ps
CPU time 2.57 seconds
Started Jul 17 07:09:44 PM PDT 24
Finished Jul 17 07:09:58 PM PDT 24
Peak memory 217780 kb
Host smart-f14a401a-a0d2-4271-9fa6-897e9097d630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018160589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.2018160589
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.929941358
Short name T73
Test name
Test status
Simulation time 91969345 ps
CPU time 1.59 seconds
Started Jul 17 07:05:29 PM PDT 24
Finished Jul 17 07:05:34 PM PDT 24
Peak memory 207704 kb
Host smart-e6a387c5-2791-40ca-a3c9-4de0d7af712f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929941358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.929941358
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.1534466594
Short name T21
Test name
Test status
Simulation time 1856129343 ps
CPU time 48.87 seconds
Started Jul 17 07:05:28 PM PDT 24
Finished Jul 17 07:06:20 PM PDT 24
Peak memory 209628 kb
Host smart-014608f8-5858-4000-b530-6665ed521545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534466594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.1534466594
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.3454544596
Short name T253
Test name
Test status
Simulation time 1299268898 ps
CPU time 13.8 seconds
Started Jul 17 07:05:28 PM PDT 24
Finished Jul 17 07:05:44 PM PDT 24
Peak memory 220136 kb
Host smart-53fcd523-e88b-4903-ba2a-c4e45954e160
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454544596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.3454544596
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.4121960016
Short name T365
Test name
Test status
Simulation time 133146701 ps
CPU time 3.38 seconds
Started Jul 17 07:06:13 PM PDT 24
Finished Jul 17 07:06:26 PM PDT 24
Peak memory 214312 kb
Host smart-069c005e-9728-4e82-aa1d-c68f636fd4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121960016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.4121960016
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.3471422090
Short name T297
Test name
Test status
Simulation time 506194931 ps
CPU time 7.71 seconds
Started Jul 17 07:06:12 PM PDT 24
Finished Jul 17 07:06:30 PM PDT 24
Peak memory 214320 kb
Host smart-17cb0f06-4a88-4ce2-bc50-892ff6acee7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3471422090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.3471422090
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.286596650
Short name T300
Test name
Test status
Simulation time 53409890 ps
CPU time 2.56 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:21 PM PDT 24
Peak memory 209216 kb
Host smart-2e5f9437-00d9-403b-b762-a0d822fba94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286596650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.286596650
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.126394299
Short name T798
Test name
Test status
Simulation time 1751442951 ps
CPU time 21.32 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:42 PM PDT 24
Peak memory 209356 kb
Host smart-9e8b8b96-af47-4b77-aa85-ff55c9016111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126394299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.126394299
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.3220255581
Short name T280
Test name
Test status
Simulation time 239890921 ps
CPU time 3.3 seconds
Started Jul 17 07:06:12 PM PDT 24
Finished Jul 17 07:06:25 PM PDT 24
Peak memory 218916 kb
Host smart-73b156de-7aeb-4fa7-816d-c85987e3796a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220255581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.3220255581
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_random.1489559467
Short name T386
Test name
Test status
Simulation time 3027479608 ps
CPU time 22.2 seconds
Started Jul 17 07:06:12 PM PDT 24
Finished Jul 17 07:06:44 PM PDT 24
Peak memory 220116 kb
Host smart-c73546d5-4455-4e50-95f1-d9930a37ae78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489559467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.1489559467
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.3584394027
Short name T251
Test name
Test status
Simulation time 138052070 ps
CPU time 3.34 seconds
Started Jul 17 07:06:09 PM PDT 24
Finished Jul 17 07:06:17 PM PDT 24
Peak memory 214804 kb
Host smart-e7e1d6ca-34f8-460d-b41d-15c96a63af1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584394027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.3584394027
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.2699712827
Short name T412
Test name
Test status
Simulation time 117828596 ps
CPU time 3.29 seconds
Started Jul 17 07:06:19 PM PDT 24
Finished Jul 17 07:06:32 PM PDT 24
Peak memory 214328 kb
Host smart-52b2072d-b904-4084-b569-5903538aab80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699712827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2699712827
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.2460646525
Short name T243
Test name
Test status
Simulation time 517203408 ps
CPU time 5.45 seconds
Started Jul 17 07:08:07 PM PDT 24
Finished Jul 17 07:08:36 PM PDT 24
Peak memory 210020 kb
Host smart-e0880e20-dcf8-4e23-bf90-7223f896f4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460646525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.2460646525
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.4083703373
Short name T145
Test name
Test status
Simulation time 693384410 ps
CPU time 9.44 seconds
Started Jul 17 07:05:30 PM PDT 24
Finished Jul 17 07:05:43 PM PDT 24
Peak memory 215196 kb
Host smart-f8c66d1d-a080-4830-8f0c-2c8c4aff0d26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4083703373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.4083703373
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3721822750
Short name T239
Test name
Test status
Simulation time 247076134 ps
CPU time 2.85 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:16 PM PDT 24
Peak memory 215908 kb
Host smart-8fc2e707-e0ac-444f-b1f8-9552dbbaa32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721822750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3721822750
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.831149404
Short name T402
Test name
Test status
Simulation time 178433767 ps
CPU time 2.51 seconds
Started Jul 17 07:08:06 PM PDT 24
Finished Jul 17 07:08:31 PM PDT 24
Peak memory 210356 kb
Host smart-2cc93581-1977-4233-a5bc-ab932dd0d39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831149404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.831149404
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.1799235990
Short name T912
Test name
Test status
Simulation time 125111911 ps
CPU time 2.86 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:15 PM PDT 24
Peak memory 214436 kb
Host smart-040d353b-9f0e-4d12-ad79-bae836bc9bc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1799235990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.1799235990
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.2505835517
Short name T242
Test name
Test status
Simulation time 150842530 ps
CPU time 2.17 seconds
Started Jul 17 07:07:51 PM PDT 24
Finished Jul 17 07:08:03 PM PDT 24
Peak memory 215788 kb
Host smart-f9d31ad6-b938-4fee-88ef-465b0320fc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505835517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.2505835517
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.4108944678
Short name T267
Test name
Test status
Simulation time 43966633 ps
CPU time 2.26 seconds
Started Jul 17 07:07:50 PM PDT 24
Finished Jul 17 07:07:59 PM PDT 24
Peak memory 214252 kb
Host smart-f0547dd6-51fe-43a0-a927-e9e962e05b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108944678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.4108944678
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.1982282084
Short name T33
Test name
Test status
Simulation time 100938257 ps
CPU time 4.18 seconds
Started Jul 17 07:08:03 PM PDT 24
Finished Jul 17 07:08:31 PM PDT 24
Peak memory 209612 kb
Host smart-7ec7d586-6652-4a29-8424-101748028a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982282084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1982282084
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.215716560
Short name T96
Test name
Test status
Simulation time 107312538 ps
CPU time 4.81 seconds
Started Jul 17 07:07:59 PM PDT 24
Finished Jul 17 07:08:25 PM PDT 24
Peak memory 222436 kb
Host smart-809a37e7-b6e6-4b1b-8f54-cf3a55001133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215716560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.215716560
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3020309964
Short name T954
Test name
Test status
Simulation time 366805380 ps
CPU time 9.94 seconds
Started Jul 17 07:02:30 PM PDT 24
Finished Jul 17 07:02:47 PM PDT 24
Peak memory 205704 kb
Host smart-2db94aa6-1ae0-40d4-9ba3-517cb6bb99bb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020309964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.3
020309964
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.271504870
Short name T962
Test name
Test status
Simulation time 256345216 ps
CPU time 6.04 seconds
Started Jul 17 07:02:23 PM PDT 24
Finished Jul 17 07:02:33 PM PDT 24
Peak memory 205568 kb
Host smart-50406458-c004-41e4-a4d9-e1de308b3348
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271504870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.271504870
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.188358563
Short name T992
Test name
Test status
Simulation time 26972837 ps
CPU time 1.23 seconds
Started Jul 17 07:02:33 PM PDT 24
Finished Jul 17 07:02:41 PM PDT 24
Peak memory 205468 kb
Host smart-22b0e1f2-5ebf-4a1d-b1f5-b75fbb0f2af6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188358563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.188358563
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.927564515
Short name T959
Test name
Test status
Simulation time 79884238 ps
CPU time 1.3 seconds
Started Jul 17 07:02:24 PM PDT 24
Finished Jul 17 07:02:29 PM PDT 24
Peak memory 213832 kb
Host smart-eba9d12b-49b1-4bf8-9d29-88c9de5af0fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927564515 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.927564515
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.425464820
Short name T955
Test name
Test status
Simulation time 46376474 ps
CPU time 1 seconds
Started Jul 17 07:02:24 PM PDT 24
Finished Jul 17 07:02:29 PM PDT 24
Peak memory 205504 kb
Host smart-25178a51-464f-4c46-a4c5-f33c04a85971
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425464820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.425464820
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.804735106
Short name T1014
Test name
Test status
Simulation time 32827962 ps
CPU time 0.67 seconds
Started Jul 17 07:02:31 PM PDT 24
Finished Jul 17 07:02:39 PM PDT 24
Peak memory 205448 kb
Host smart-f60bfb78-aa97-4260-9b1d-f0cd07039c74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804735106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.804735106
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3056747590
Short name T952
Test name
Test status
Simulation time 21028710 ps
CPU time 1.19 seconds
Started Jul 17 07:02:23 PM PDT 24
Finished Jul 17 07:02:28 PM PDT 24
Peak memory 205492 kb
Host smart-ced239b4-3c28-4336-8247-67aea5f31704
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056747590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.3056747590
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.850185731
Short name T1062
Test name
Test status
Simulation time 216368212 ps
CPU time 2.65 seconds
Started Jul 17 07:02:33 PM PDT 24
Finished Jul 17 07:02:42 PM PDT 24
Peak memory 214152 kb
Host smart-81c61f53-ed66-4c02-8914-d914bc1d62de
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850185731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow
_reg_errors.850185731
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1650848669
Short name T1079
Test name
Test status
Simulation time 568811463 ps
CPU time 7.94 seconds
Started Jul 17 07:02:30 PM PDT 24
Finished Jul 17 07:02:45 PM PDT 24
Peak memory 214180 kb
Host smart-d610d941-bbbe-4271-b8a9-cde45b8ae693
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650848669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.1650848669
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.981039591
Short name T1024
Test name
Test status
Simulation time 530955709 ps
CPU time 4.04 seconds
Started Jul 17 07:02:30 PM PDT 24
Finished Jul 17 07:02:41 PM PDT 24
Peak memory 213852 kb
Host smart-a9e51128-4caf-4438-963c-d49ae2cbd346
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981039591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.981039591
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.2480260057
Short name T171
Test name
Test status
Simulation time 775373687 ps
CPU time 3.08 seconds
Started Jul 17 07:02:31 PM PDT 24
Finished Jul 17 07:02:41 PM PDT 24
Peak memory 213928 kb
Host smart-1c9c5ded-c78a-472b-a03f-7c428e97ee75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480260057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.2480260057
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3855022754
Short name T1080
Test name
Test status
Simulation time 454791999 ps
CPU time 10.15 seconds
Started Jul 17 07:02:29 PM PDT 24
Finished Jul 17 07:02:46 PM PDT 24
Peak memory 205620 kb
Host smart-bbd4ec04-f099-4647-a42a-d2bfb306de79
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855022754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.3
855022754
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.789600072
Short name T1072
Test name
Test status
Simulation time 136042224 ps
CPU time 6.05 seconds
Started Jul 17 07:02:29 PM PDT 24
Finished Jul 17 07:02:42 PM PDT 24
Peak memory 205500 kb
Host smart-3fdcd522-3d45-489d-beaf-8a64d6033c80
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789600072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.789600072
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.912184421
Short name T1058
Test name
Test status
Simulation time 64561238 ps
CPU time 1.01 seconds
Started Jul 17 07:02:28 PM PDT 24
Finished Jul 17 07:02:34 PM PDT 24
Peak memory 205500 kb
Host smart-9601b7e9-f3cd-4fdc-b697-7fcfdc7dfa92
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912184421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.912184421
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1712144354
Short name T930
Test name
Test status
Simulation time 23554441 ps
CPU time 1.66 seconds
Started Jul 17 07:02:30 PM PDT 24
Finished Jul 17 07:02:38 PM PDT 24
Peak memory 213888 kb
Host smart-038dba44-b9fb-4249-ac0f-f794e3c9ecdc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712144354 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.1712144354
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.363037916
Short name T1039
Test name
Test status
Simulation time 50452426 ps
CPU time 1.06 seconds
Started Jul 17 07:02:29 PM PDT 24
Finished Jul 17 07:02:37 PM PDT 24
Peak memory 205504 kb
Host smart-a9551741-2089-454e-bb39-fff5a97306e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363037916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.363037916
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.2996677794
Short name T944
Test name
Test status
Simulation time 30873942 ps
CPU time 0.66 seconds
Started Jul 17 07:02:29 PM PDT 24
Finished Jul 17 07:02:37 PM PDT 24
Peak memory 205384 kb
Host smart-9e34543b-dfeb-4a9e-b142-27b8635492d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996677794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.2996677794
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.428491566
Short name T1031
Test name
Test status
Simulation time 19441021 ps
CPU time 1.34 seconds
Started Jul 17 07:02:29 PM PDT 24
Finished Jul 17 07:02:38 PM PDT 24
Peak memory 205344 kb
Host smart-86896cc8-5f81-45f8-9fbd-49dbf07616e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428491566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sam
e_csr_outstanding.428491566
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1512105485
Short name T1076
Test name
Test status
Simulation time 64328738 ps
CPU time 1.84 seconds
Started Jul 17 07:02:19 PM PDT 24
Finished Jul 17 07:02:25 PM PDT 24
Peak memory 214112 kb
Host smart-f15fef83-de2d-4c28-bab6-794c5a86dc7b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512105485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.1512105485
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.4193784450
Short name T1026
Test name
Test status
Simulation time 379488820 ps
CPU time 5.8 seconds
Started Jul 17 07:02:23 PM PDT 24
Finished Jul 17 07:02:33 PM PDT 24
Peak memory 214088 kb
Host smart-d014f110-93a9-4fd0-afc8-c1b68273f572
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193784450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.4193784450
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.2562837166
Short name T926
Test name
Test status
Simulation time 80257722 ps
CPU time 2.39 seconds
Started Jul 17 07:02:31 PM PDT 24
Finished Jul 17 07:02:41 PM PDT 24
Peak memory 213836 kb
Host smart-c6c7354f-91f8-45cb-b82a-583799b8627c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562837166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.2562837166
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.2190649066
Short name T405
Test name
Test status
Simulation time 198099965 ps
CPU time 4.22 seconds
Started Jul 17 07:02:30 PM PDT 24
Finished Jul 17 07:02:42 PM PDT 24
Peak memory 213784 kb
Host smart-607e2f58-8a02-4133-9b63-e90b9a9eb70a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190649066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.2190649066
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1365976201
Short name T953
Test name
Test status
Simulation time 59723364 ps
CPU time 1.47 seconds
Started Jul 17 07:02:56 PM PDT 24
Finished Jul 17 07:02:59 PM PDT 24
Peak memory 205592 kb
Host smart-8cf54517-3ddf-4c3d-a9d3-47676fe54653
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365976201 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1365976201
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3415259556
Short name T1030
Test name
Test status
Simulation time 47141394 ps
CPU time 1.21 seconds
Started Jul 17 07:02:52 PM PDT 24
Finished Jul 17 07:02:56 PM PDT 24
Peak memory 205572 kb
Host smart-467e9677-fef0-4274-b6f2-e90254ba7339
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415259556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.3415259556
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1919270861
Short name T936
Test name
Test status
Simulation time 10777531 ps
CPU time 0.75 seconds
Started Jul 17 07:02:54 PM PDT 24
Finished Jul 17 07:02:57 PM PDT 24
Peak memory 205376 kb
Host smart-b1e6159c-fce6-4b2d-b3cf-677b7bc6c3e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919270861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.1919270861
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.3764217307
Short name T984
Test name
Test status
Simulation time 45114298 ps
CPU time 1.47 seconds
Started Jul 17 07:02:50 PM PDT 24
Finished Jul 17 07:02:52 PM PDT 24
Peak memory 205564 kb
Host smart-a3c5a8bf-f7fb-4d6c-a475-f0a264c91d39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764217307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.3764217307
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.641310978
Short name T1008
Test name
Test status
Simulation time 290418999 ps
CPU time 4.32 seconds
Started Jul 17 07:02:52 PM PDT 24
Finished Jul 17 07:02:58 PM PDT 24
Peak memory 214176 kb
Host smart-9d6ab5ed-ec64-4a42-af31-8f95c8c437e8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641310978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_shadow_reg_errors_with_csr_rw.641310978
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1133762374
Short name T1051
Test name
Test status
Simulation time 91556902 ps
CPU time 1.48 seconds
Started Jul 17 07:02:52 PM PDT 24
Finished Jul 17 07:02:56 PM PDT 24
Peak memory 213736 kb
Host smart-a6b52c44-d57a-459b-b0a6-05ea7c6926d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133762374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.1133762374
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.52805936
Short name T178
Test name
Test status
Simulation time 75361970 ps
CPU time 3.42 seconds
Started Jul 17 07:02:53 PM PDT 24
Finished Jul 17 07:02:58 PM PDT 24
Peak memory 213760 kb
Host smart-8a71d6aa-34dc-4c37-b85b-fff418ef068e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52805936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err.52805936
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3151297648
Short name T949
Test name
Test status
Simulation time 201274397 ps
CPU time 1.58 seconds
Started Jul 17 07:03:13 PM PDT 24
Finished Jul 17 07:03:17 PM PDT 24
Peak memory 213788 kb
Host smart-1a3a5625-fff6-4f84-b327-d1ff939c8417
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151297648 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.3151297648
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3397977093
Short name T978
Test name
Test status
Simulation time 26081008 ps
CPU time 1.41 seconds
Started Jul 17 07:03:11 PM PDT 24
Finished Jul 17 07:03:13 PM PDT 24
Peak memory 205548 kb
Host smart-6e9c4f7a-8a25-4c2c-ac13-3bdc855e89a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397977093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.3397977093
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2122377420
Short name T973
Test name
Test status
Simulation time 54666646 ps
CPU time 0.69 seconds
Started Jul 17 07:02:54 PM PDT 24
Finished Jul 17 07:02:57 PM PDT 24
Peak memory 205376 kb
Host smart-c46a2c40-8cae-4018-a6f5-147eadf58b86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122377420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.2122377420
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3220133593
Short name T948
Test name
Test status
Simulation time 57729523 ps
CPU time 2.43 seconds
Started Jul 17 07:03:17 PM PDT 24
Finished Jul 17 07:03:24 PM PDT 24
Peak memory 205460 kb
Host smart-209d262d-a37e-41a9-aae1-77f52a2d1432
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220133593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.3220133593
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2537792161
Short name T1040
Test name
Test status
Simulation time 430159457 ps
CPU time 3.33 seconds
Started Jul 17 07:02:52 PM PDT 24
Finished Jul 17 07:02:57 PM PDT 24
Peak memory 214180 kb
Host smart-28f56e9f-6ca0-49b6-bc2e-417afbf1add4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537792161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.2537792161
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.4203423352
Short name T131
Test name
Test status
Simulation time 1887547096 ps
CPU time 8.79 seconds
Started Jul 17 07:02:52 PM PDT 24
Finished Jul 17 07:03:02 PM PDT 24
Peak memory 214124 kb
Host smart-ca15a693-4b7b-420b-8bf3-925cde6aa6a7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203423352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.4203423352
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2112281528
Short name T946
Test name
Test status
Simulation time 25099659 ps
CPU time 1.7 seconds
Started Jul 17 07:02:50 PM PDT 24
Finished Jul 17 07:02:52 PM PDT 24
Peak memory 213724 kb
Host smart-ee04c7df-ddec-431c-b03d-c3cc2f7eb672
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112281528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2112281528
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2535526159
Short name T1033
Test name
Test status
Simulation time 54948436 ps
CPU time 1.59 seconds
Started Jul 17 07:03:17 PM PDT 24
Finished Jul 17 07:03:24 PM PDT 24
Peak memory 213772 kb
Host smart-d89ceb89-ecb1-4a38-8a76-a884ffefbe91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535526159 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.2535526159
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2095003480
Short name T1013
Test name
Test status
Simulation time 14170348 ps
CPU time 1.11 seconds
Started Jul 17 07:03:15 PM PDT 24
Finished Jul 17 07:03:18 PM PDT 24
Peak memory 205408 kb
Host smart-f337d42c-8901-4eb7-94ad-c56e8ebcf043
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095003480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.2095003480
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3465983556
Short name T932
Test name
Test status
Simulation time 12318078 ps
CPU time 0.76 seconds
Started Jul 17 07:03:17 PM PDT 24
Finished Jul 17 07:03:22 PM PDT 24
Peak memory 205380 kb
Host smart-4cc56422-2f13-461b-bfc6-f28533267c72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465983556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3465983556
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.642694651
Short name T1069
Test name
Test status
Simulation time 37901843 ps
CPU time 1.6 seconds
Started Jul 17 07:03:13 PM PDT 24
Finished Jul 17 07:03:17 PM PDT 24
Peak memory 205588 kb
Host smart-23a1b123-8ce0-417c-abb7-f29eb89a91da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642694651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_sa
me_csr_outstanding.642694651
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.554393293
Short name T1025
Test name
Test status
Simulation time 292730886 ps
CPU time 1.73 seconds
Started Jul 17 07:03:10 PM PDT 24
Finished Jul 17 07:03:12 PM PDT 24
Peak memory 214064 kb
Host smart-501564fc-b12c-4a71-bfe5-93d75075a6ef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554393293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shado
w_reg_errors.554393293
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.3365315765
Short name T986
Test name
Test status
Simulation time 468953830 ps
CPU time 5.47 seconds
Started Jul 17 07:03:13 PM PDT 24
Finished Jul 17 07:03:21 PM PDT 24
Peak memory 214008 kb
Host smart-70354d21-8956-4a19-b54b-8b98a8268181
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365315765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.3365315765
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2219205352
Short name T1077
Test name
Test status
Simulation time 320153618 ps
CPU time 3.09 seconds
Started Jul 17 07:03:15 PM PDT 24
Finished Jul 17 07:03:22 PM PDT 24
Peak memory 213704 kb
Host smart-51e476d7-8a14-403f-bab7-6d057566dddc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219205352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.2219205352
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.3755341105
Short name T164
Test name
Test status
Simulation time 252304306 ps
CPU time 9.14 seconds
Started Jul 17 07:04:54 PM PDT 24
Finished Jul 17 07:05:05 PM PDT 24
Peak memory 213788 kb
Host smart-ed1a7a01-de91-4ace-821a-28a4fc53e7c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755341105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.3755341105
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.4014540658
Short name T1053
Test name
Test status
Simulation time 69328291 ps
CPU time 2.47 seconds
Started Jul 17 07:03:13 PM PDT 24
Finished Jul 17 07:03:18 PM PDT 24
Peak memory 213736 kb
Host smart-d0de23ff-c0eb-455f-8941-4f29cb5b51f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014540658 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.4014540658
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.919512851
Short name T1074
Test name
Test status
Simulation time 36666575 ps
CPU time 1.16 seconds
Started Jul 17 07:03:14 PM PDT 24
Finished Jul 17 07:03:17 PM PDT 24
Peak memory 205524 kb
Host smart-5f48e590-f4c9-4d40-bc6c-b659f95c7a14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919512851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.919512851
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3217048633
Short name T947
Test name
Test status
Simulation time 41656502 ps
CPU time 0.82 seconds
Started Jul 17 07:03:13 PM PDT 24
Finished Jul 17 07:03:17 PM PDT 24
Peak memory 205320 kb
Host smart-115fd64b-9845-4345-bea1-f97d6363b711
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217048633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3217048633
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1225448285
Short name T943
Test name
Test status
Simulation time 358185322 ps
CPU time 2.55 seconds
Started Jul 17 07:03:13 PM PDT 24
Finished Jul 17 07:03:17 PM PDT 24
Peak memory 205496 kb
Host smart-228912d5-82cd-46e5-a3d6-9f8c75a9a2cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225448285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.1225448285
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.208726170
Short name T1011
Test name
Test status
Simulation time 1155100334 ps
CPU time 4.68 seconds
Started Jul 17 07:03:17 PM PDT 24
Finished Jul 17 07:03:26 PM PDT 24
Peak memory 222192 kb
Host smart-6f01c90f-2ee4-450f-842e-0d9aa8da0df1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208726170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shado
w_reg_errors.208726170
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1405866923
Short name T1021
Test name
Test status
Simulation time 151605554 ps
CPU time 6.53 seconds
Started Jul 17 07:03:15 PM PDT 24
Finished Jul 17 07:03:24 PM PDT 24
Peak memory 214104 kb
Host smart-479fb0ac-5789-4704-8a27-89be3d773b2e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405866923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.1405866923
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.829065217
Short name T192
Test name
Test status
Simulation time 127441316 ps
CPU time 4.15 seconds
Started Jul 17 07:03:13 PM PDT 24
Finished Jul 17 07:03:19 PM PDT 24
Peak memory 216940 kb
Host smart-66e7471b-9297-4457-81ae-92d41f1a402e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829065217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.829065217
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.997065907
Short name T1004
Test name
Test status
Simulation time 183480396 ps
CPU time 2.57 seconds
Started Jul 17 07:03:11 PM PDT 24
Finished Jul 17 07:03:15 PM PDT 24
Peak memory 205524 kb
Host smart-6dde4c21-e574-4d1b-bd3a-ae8266a50e5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997065907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err
.997065907
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3374758243
Short name T937
Test name
Test status
Simulation time 30911989 ps
CPU time 1.01 seconds
Started Jul 17 07:03:14 PM PDT 24
Finished Jul 17 07:03:17 PM PDT 24
Peak memory 205440 kb
Host smart-86f9ddc3-4317-4d2a-84e9-510e5ec0ee96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374758243 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.3374758243
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2965180651
Short name T928
Test name
Test status
Simulation time 21259112 ps
CPU time 0.86 seconds
Started Jul 17 07:03:14 PM PDT 24
Finished Jul 17 07:03:17 PM PDT 24
Peak memory 205428 kb
Host smart-a64ff695-1308-4843-8011-3066e3469210
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965180651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.2965180651
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2219752344
Short name T923
Test name
Test status
Simulation time 42029046 ps
CPU time 0.85 seconds
Started Jul 17 07:03:13 PM PDT 24
Finished Jul 17 07:03:15 PM PDT 24
Peak memory 205376 kb
Host smart-36bc4b51-d3f2-4e8d-b999-65d5f41f8b0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219752344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2219752344
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3830462692
Short name T148
Test name
Test status
Simulation time 31728819 ps
CPU time 2.14 seconds
Started Jul 17 07:03:11 PM PDT 24
Finished Jul 17 07:03:13 PM PDT 24
Peak memory 205544 kb
Host smart-36011c79-4953-4cf3-9339-eb8c56b4c37f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830462692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.3830462692
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1117484132
Short name T1066
Test name
Test status
Simulation time 162885326 ps
CPU time 4.62 seconds
Started Jul 17 07:03:16 PM PDT 24
Finished Jul 17 07:03:26 PM PDT 24
Peak memory 218848 kb
Host smart-672cd3e9-6d49-4651-a1ba-e4f9dc341268
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117484132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.1117484132
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.4087642787
Short name T125
Test name
Test status
Simulation time 199933661 ps
CPU time 5.09 seconds
Started Jul 17 07:03:13 PM PDT 24
Finished Jul 17 07:03:20 PM PDT 24
Peak memory 220116 kb
Host smart-6d1b6d61-a5d6-4858-a032-bedb3b551cbc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087642787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.4087642787
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.585032843
Short name T995
Test name
Test status
Simulation time 146574777 ps
CPU time 2.35 seconds
Started Jul 17 07:03:12 PM PDT 24
Finished Jul 17 07:03:15 PM PDT 24
Peak memory 213736 kb
Host smart-dc509f6d-11c0-40f3-8b09-83c22ebc0296
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585032843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.585032843
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1177531946
Short name T174
Test name
Test status
Simulation time 130907330 ps
CPU time 3.03 seconds
Started Jul 17 07:03:10 PM PDT 24
Finished Jul 17 07:03:14 PM PDT 24
Peak memory 213860 kb
Host smart-77912222-505d-4718-b5a6-73d5f604710a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177531946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.1177531946
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2126041989
Short name T935
Test name
Test status
Simulation time 87542548 ps
CPU time 1.06 seconds
Started Jul 17 07:03:12 PM PDT 24
Finished Jul 17 07:03:14 PM PDT 24
Peak memory 205752 kb
Host smart-8bf1e358-b8cb-4a23-9cc4-8da75c511a04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126041989 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.2126041989
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1368386778
Short name T968
Test name
Test status
Simulation time 33268692 ps
CPU time 1.64 seconds
Started Jul 17 07:03:16 PM PDT 24
Finished Jul 17 07:03:22 PM PDT 24
Peak memory 205480 kb
Host smart-20097279-d99b-4743-a143-11ade3938d7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368386778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1368386778
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.940116052
Short name T989
Test name
Test status
Simulation time 28190305 ps
CPU time 0.85 seconds
Started Jul 17 07:03:13 PM PDT 24
Finished Jul 17 07:03:17 PM PDT 24
Peak memory 205376 kb
Host smart-85868f28-c430-4f63-9242-72118c5f83da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940116052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.940116052
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3361616751
Short name T1068
Test name
Test status
Simulation time 198968910 ps
CPU time 2.41 seconds
Started Jul 17 07:03:13 PM PDT 24
Finished Jul 17 07:03:17 PM PDT 24
Peak memory 205556 kb
Host smart-589744fc-c6d2-4420-8838-d47ab4f0a169
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361616751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.3361616751
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2307914045
Short name T130
Test name
Test status
Simulation time 309912217 ps
CPU time 1.78 seconds
Started Jul 17 07:03:11 PM PDT 24
Finished Jul 17 07:03:14 PM PDT 24
Peak memory 214136 kb
Host smart-91a9efb3-3f5e-40c1-9077-5dd1fdad2ee0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307914045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.2307914045
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.983518538
Short name T1049
Test name
Test status
Simulation time 729838009 ps
CPU time 7.01 seconds
Started Jul 17 07:03:16 PM PDT 24
Finished Jul 17 07:03:27 PM PDT 24
Peak memory 220060 kb
Host smart-d34eaa15-6a41-468d-8fd9-dd46f50e7945
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983518538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
keymgr_shadow_reg_errors_with_csr_rw.983518538
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2215034612
Short name T191
Test name
Test status
Simulation time 294711406 ps
CPU time 1.95 seconds
Started Jul 17 07:03:15 PM PDT 24
Finished Jul 17 07:03:21 PM PDT 24
Peak memory 213628 kb
Host smart-8c4ee22c-5fb5-46a2-a082-f5254a246db6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215034612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.2215034612
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.4253490703
Short name T975
Test name
Test status
Simulation time 798390118 ps
CPU time 6.07 seconds
Started Jul 17 07:03:17 PM PDT 24
Finished Jul 17 07:03:29 PM PDT 24
Peak memory 216176 kb
Host smart-1a81db68-6b10-4df5-8576-88a9eddddc40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253490703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.4253490703
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2468765942
Short name T965
Test name
Test status
Simulation time 48651121 ps
CPU time 1.26 seconds
Started Jul 17 07:03:10 PM PDT 24
Finished Jul 17 07:03:12 PM PDT 24
Peak memory 213864 kb
Host smart-cb715e04-4628-4355-8b18-430faeacf732
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468765942 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.2468765942
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.1692236909
Short name T983
Test name
Test status
Simulation time 107687650 ps
CPU time 1.44 seconds
Started Jul 17 07:03:14 PM PDT 24
Finished Jul 17 07:03:18 PM PDT 24
Peak memory 205552 kb
Host smart-63686a16-7494-4ead-b201-dff2b103eca7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692236909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.1692236909
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3897418202
Short name T1073
Test name
Test status
Simulation time 11141449 ps
CPU time 0.84 seconds
Started Jul 17 07:03:13 PM PDT 24
Finished Jul 17 07:03:16 PM PDT 24
Peak memory 205324 kb
Host smart-727e5f28-c524-4107-bcc2-505e1009e5c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897418202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3897418202
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.232391770
Short name T152
Test name
Test status
Simulation time 41559613 ps
CPU time 1.33 seconds
Started Jul 17 07:03:13 PM PDT 24
Finished Jul 17 07:03:17 PM PDT 24
Peak memory 205524 kb
Host smart-c500ec52-d5bb-41fe-bdea-d2c21dac3b00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232391770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_sa
me_csr_outstanding.232391770
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3014508926
Short name T1001
Test name
Test status
Simulation time 336300565 ps
CPU time 3.08 seconds
Started Jul 17 07:03:12 PM PDT 24
Finished Jul 17 07:03:16 PM PDT 24
Peak memory 214032 kb
Host smart-2827e156-110e-4ead-b6d5-a00dc4682d2d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014508926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3014508926
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2736346643
Short name T997
Test name
Test status
Simulation time 178503250 ps
CPU time 2.1 seconds
Started Jul 17 07:03:13 PM PDT 24
Finished Jul 17 07:03:18 PM PDT 24
Peak memory 213820 kb
Host smart-2319bf05-0aa6-4b52-81d8-2552f3aa4648
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736346643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.2736346643
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1815165733
Short name T1063
Test name
Test status
Simulation time 55948660 ps
CPU time 1.47 seconds
Started Jul 17 07:03:17 PM PDT 24
Finished Jul 17 07:03:24 PM PDT 24
Peak memory 205568 kb
Host smart-fed9cc76-c441-471c-aa31-883e21e11954
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815165733 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.1815165733
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.642929391
Short name T1061
Test name
Test status
Simulation time 61176969 ps
CPU time 1.14 seconds
Started Jul 17 07:03:15 PM PDT 24
Finished Jul 17 07:03:19 PM PDT 24
Peak memory 205516 kb
Host smart-16b0dc27-5f81-4344-8699-b8e1afa4719b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642929391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.642929391
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3474057436
Short name T960
Test name
Test status
Simulation time 65713860 ps
CPU time 0.77 seconds
Started Jul 17 07:03:15 PM PDT 24
Finished Jul 17 07:03:20 PM PDT 24
Peak memory 205232 kb
Host smart-9af6f33b-b853-4967-8240-8b8a32e1b886
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474057436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.3474057436
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.2150324883
Short name T971
Test name
Test status
Simulation time 115666458 ps
CPU time 2.62 seconds
Started Jul 17 07:03:14 PM PDT 24
Finished Jul 17 07:03:19 PM PDT 24
Peak memory 213752 kb
Host smart-26dc440c-8c83-4d07-85e2-575725247afd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150324883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.2150324883
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.4077462115
Short name T1035
Test name
Test status
Simulation time 136876047 ps
CPU time 1.52 seconds
Started Jul 17 07:03:15 PM PDT 24
Finished Jul 17 07:03:19 PM PDT 24
Peak memory 213972 kb
Host smart-f513be80-bcbe-4d2c-9175-b4718528a4f3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077462115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.4077462115
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.629591936
Short name T118
Test name
Test status
Simulation time 217138349 ps
CPU time 7.16 seconds
Started Jul 17 07:03:17 PM PDT 24
Finished Jul 17 07:03:28 PM PDT 24
Peak memory 214016 kb
Host smart-b3a6f1a7-ff32-4f0f-95c7-8b50b10fecd7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629591936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_shadow_reg_errors_with_csr_rw.629591936
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.1758462159
Short name T933
Test name
Test status
Simulation time 27196084 ps
CPU time 2.21 seconds
Started Jul 17 07:03:11 PM PDT 24
Finished Jul 17 07:03:15 PM PDT 24
Peak memory 213760 kb
Host smart-25577265-eec6-45ec-b11b-99f4889fae68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758462159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.1758462159
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1175544371
Short name T940
Test name
Test status
Simulation time 136374028 ps
CPU time 1.87 seconds
Started Jul 17 07:03:14 PM PDT 24
Finished Jul 17 07:03:19 PM PDT 24
Peak memory 213856 kb
Host smart-0083795d-22cc-4584-8c65-388d2955a488
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175544371 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.1175544371
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2857621706
Short name T1070
Test name
Test status
Simulation time 112922102 ps
CPU time 1.13 seconds
Started Jul 17 07:03:17 PM PDT 24
Finished Jul 17 07:03:24 PM PDT 24
Peak memory 205544 kb
Host smart-2d503572-37ca-4095-9eb8-e98999f5b3a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857621706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2857621706
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.3500680888
Short name T964
Test name
Test status
Simulation time 12020551 ps
CPU time 0.73 seconds
Started Jul 17 07:03:15 PM PDT 24
Finished Jul 17 07:03:19 PM PDT 24
Peak memory 205448 kb
Host smart-53fc093b-bf9a-4faf-8398-8da84476daaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500680888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.3500680888
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1187963909
Short name T149
Test name
Test status
Simulation time 70220391 ps
CPU time 2.16 seconds
Started Jul 17 07:03:14 PM PDT 24
Finished Jul 17 07:03:19 PM PDT 24
Peak memory 213772 kb
Host smart-bb5f9674-b3ee-4ac9-91b4-c7b1a9a8e6e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187963909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.1187963909
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3371324763
Short name T128
Test name
Test status
Simulation time 281905828 ps
CPU time 2.82 seconds
Started Jul 17 07:03:17 PM PDT 24
Finished Jul 17 07:03:25 PM PDT 24
Peak memory 213976 kb
Host smart-33b513de-12da-4c2d-9b5a-b22bc8960e12
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371324763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.3371324763
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2806550180
Short name T1010
Test name
Test status
Simulation time 91311791 ps
CPU time 3.89 seconds
Started Jul 17 07:03:15 PM PDT 24
Finished Jul 17 07:03:22 PM PDT 24
Peak memory 214180 kb
Host smart-3acb5174-cb5e-42e8-bde1-94574f97d6aa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806550180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2806550180
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2540270109
Short name T956
Test name
Test status
Simulation time 30476605 ps
CPU time 1.55 seconds
Started Jul 17 07:03:15 PM PDT 24
Finished Jul 17 07:03:19 PM PDT 24
Peak memory 213932 kb
Host smart-d66eeb39-01c0-4caa-9c16-4949e1e4e6bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540270109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.2540270109
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.731945040
Short name T934
Test name
Test status
Simulation time 74323836 ps
CPU time 1.62 seconds
Started Jul 17 07:03:19 PM PDT 24
Finished Jul 17 07:03:26 PM PDT 24
Peak memory 213760 kb
Host smart-00edf9a1-2ddb-40a7-9ce6-5ff184206302
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731945040 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.731945040
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.875500465
Short name T963
Test name
Test status
Simulation time 61803096 ps
CPU time 1.02 seconds
Started Jul 17 07:03:23 PM PDT 24
Finished Jul 17 07:03:27 PM PDT 24
Peak memory 205484 kb
Host smart-10f1f757-134c-40e0-b25e-15885c2c9f9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875500465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.875500465
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2926645638
Short name T950
Test name
Test status
Simulation time 13033421 ps
CPU time 0.85 seconds
Started Jul 17 07:03:15 PM PDT 24
Finished Jul 17 07:03:19 PM PDT 24
Peak memory 205276 kb
Host smart-b60ffac5-e9c0-44f8-96fc-ed7b8e3b50f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926645638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2926645638
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.961868931
Short name T146
Test name
Test status
Simulation time 303527084 ps
CPU time 1.35 seconds
Started Jul 17 07:03:15 PM PDT 24
Finished Jul 17 07:03:20 PM PDT 24
Peak memory 205576 kb
Host smart-f8abe794-6799-4d29-9387-d98d867831ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961868931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_sa
me_csr_outstanding.961868931
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1488886283
Short name T129
Test name
Test status
Simulation time 712511958 ps
CPU time 2.21 seconds
Started Jul 17 07:03:23 PM PDT 24
Finished Jul 17 07:03:28 PM PDT 24
Peak memory 214080 kb
Host smart-61e1c3bb-8e34-4d36-be70-4351e4d8d829
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488886283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.1488886283
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2064439530
Short name T127
Test name
Test status
Simulation time 75084122 ps
CPU time 4.07 seconds
Started Jul 17 07:03:16 PM PDT 24
Finished Jul 17 07:03:25 PM PDT 24
Peak memory 220232 kb
Host smart-69b9c424-4cbc-4965-91e4-22bfe1c358b0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064439530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.2064439530
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3363617260
Short name T991
Test name
Test status
Simulation time 72879437 ps
CPU time 2.91 seconds
Started Jul 17 07:03:17 PM PDT 24
Finished Jul 17 07:03:25 PM PDT 24
Peak memory 213620 kb
Host smart-9d982cdd-4420-4330-87a7-588d691e3dd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363617260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.3363617260
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.1347152064
Short name T1015
Test name
Test status
Simulation time 236840388 ps
CPU time 5.09 seconds
Started Jul 17 07:02:29 PM PDT 24
Finished Jul 17 07:02:41 PM PDT 24
Peak memory 205568 kb
Host smart-d5568e9f-fdbf-4408-a535-a85c85b3690d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347152064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.1
347152064
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3241760536
Short name T1023
Test name
Test status
Simulation time 2597966495 ps
CPU time 17.28 seconds
Started Jul 17 07:02:31 PM PDT 24
Finished Jul 17 07:02:55 PM PDT 24
Peak memory 205656 kb
Host smart-d29e679a-8d70-4a2a-bdfa-99ca27558267
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241760536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.3
241760536
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1446624753
Short name T996
Test name
Test status
Simulation time 19886347 ps
CPU time 0.84 seconds
Started Jul 17 07:02:31 PM PDT 24
Finished Jul 17 07:02:39 PM PDT 24
Peak memory 205484 kb
Host smart-2139f60c-154b-4f07-bec5-15ee34667937
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446624753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1
446624753
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.2340945860
Short name T1005
Test name
Test status
Simulation time 174028631 ps
CPU time 2.18 seconds
Started Jul 17 07:02:31 PM PDT 24
Finished Jul 17 07:02:40 PM PDT 24
Peak memory 213852 kb
Host smart-5ee47a52-09e7-48a2-9742-eb79cf5f2656
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340945860 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.2340945860
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3284340052
Short name T990
Test name
Test status
Simulation time 78861075 ps
CPU time 0.97 seconds
Started Jul 17 07:02:32 PM PDT 24
Finished Jul 17 07:02:41 PM PDT 24
Peak memory 205488 kb
Host smart-53526df0-f8fa-4627-89c1-8eca0911741b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284340052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.3284340052
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.2480599334
Short name T1043
Test name
Test status
Simulation time 8936707 ps
CPU time 0.67 seconds
Started Jul 17 07:02:32 PM PDT 24
Finished Jul 17 07:02:39 PM PDT 24
Peak memory 205372 kb
Host smart-48b0ab35-d52c-40ed-b0a7-5f02d3c44088
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480599334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.2480599334
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2947680380
Short name T147
Test name
Test status
Simulation time 424946287 ps
CPU time 2.75 seconds
Started Jul 17 07:02:29 PM PDT 24
Finished Jul 17 07:02:38 PM PDT 24
Peak memory 205620 kb
Host smart-464f127a-83a0-41eb-96f9-9ad37edf3289
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947680380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.2947680380
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.569625562
Short name T1007
Test name
Test status
Simulation time 165723070 ps
CPU time 2.44 seconds
Started Jul 17 07:02:28 PM PDT 24
Finished Jul 17 07:02:35 PM PDT 24
Peak memory 214052 kb
Host smart-4adf78c2-1659-4565-8a1d-081a112cbd97
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569625562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow
_reg_errors.569625562
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2717707308
Short name T1056
Test name
Test status
Simulation time 887907743 ps
CPU time 6.25 seconds
Started Jul 17 07:02:29 PM PDT 24
Finished Jul 17 07:02:43 PM PDT 24
Peak memory 213796 kb
Host smart-49cc2fb6-1891-499d-808c-aab7ed8c6003
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717707308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.2717707308
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3871549952
Short name T1078
Test name
Test status
Simulation time 402138907 ps
CPU time 3.94 seconds
Started Jul 17 07:02:29 PM PDT 24
Finished Jul 17 07:02:39 PM PDT 24
Peak memory 215200 kb
Host smart-9bbcde04-37ad-441f-8732-47a1c831454a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871549952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.3871549952
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1402302355
Short name T1042
Test name
Test status
Simulation time 11573950 ps
CPU time 0.78 seconds
Started Jul 17 07:03:17 PM PDT 24
Finished Jul 17 07:03:23 PM PDT 24
Peak memory 205240 kb
Host smart-0ce1bcec-5bb0-42a4-b729-bb070aa44954
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402302355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.1402302355
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1920837963
Short name T929
Test name
Test status
Simulation time 47552337 ps
CPU time 0.86 seconds
Started Jul 17 07:03:13 PM PDT 24
Finished Jul 17 07:03:16 PM PDT 24
Peak memory 205320 kb
Host smart-25796ec1-de7d-4f16-92ef-97e349e2383f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920837963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1920837963
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1724869012
Short name T994
Test name
Test status
Simulation time 39113871 ps
CPU time 0.8 seconds
Started Jul 17 07:03:17 PM PDT 24
Finished Jul 17 07:03:23 PM PDT 24
Peak memory 205308 kb
Host smart-9dac9946-47d3-48a3-9ae6-78b8ebac74dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724869012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.1724869012
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2146913753
Short name T1037
Test name
Test status
Simulation time 25753517 ps
CPU time 0.75 seconds
Started Jul 17 07:03:14 PM PDT 24
Finished Jul 17 07:03:17 PM PDT 24
Peak memory 205380 kb
Host smart-c2ab5070-df1f-480f-a628-f4ce1fb64c97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146913753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2146913753
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2544907872
Short name T1038
Test name
Test status
Simulation time 15653795 ps
CPU time 0.76 seconds
Started Jul 17 07:03:14 PM PDT 24
Finished Jul 17 07:03:18 PM PDT 24
Peak memory 205376 kb
Host smart-332433b5-9c22-4e83-8ef0-8f002d1e5287
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544907872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.2544907872
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.851766420
Short name T999
Test name
Test status
Simulation time 24497997 ps
CPU time 0.76 seconds
Started Jul 17 07:03:17 PM PDT 24
Finished Jul 17 07:03:22 PM PDT 24
Peak memory 205368 kb
Host smart-c6894cdb-c22e-435d-8672-3869a708049c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851766420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.851766420
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1136065281
Short name T1000
Test name
Test status
Simulation time 47244161 ps
CPU time 0.78 seconds
Started Jul 17 07:03:15 PM PDT 24
Finished Jul 17 07:03:20 PM PDT 24
Peak memory 205160 kb
Host smart-f5ce6ef5-db9e-4908-b4eb-c1c6911625fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136065281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.1136065281
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.2363686558
Short name T1060
Test name
Test status
Simulation time 13163565 ps
CPU time 0.74 seconds
Started Jul 17 07:03:17 PM PDT 24
Finished Jul 17 07:03:22 PM PDT 24
Peak memory 205308 kb
Host smart-bd9271dc-520b-44f6-b2b7-20c96cbb878b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363686558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.2363686558
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.361986265
Short name T939
Test name
Test status
Simulation time 13267489 ps
CPU time 0.71 seconds
Started Jul 17 07:03:16 PM PDT 24
Finished Jul 17 07:03:22 PM PDT 24
Peak memory 205308 kb
Host smart-39d4dcb2-6a7e-436a-9f75-7a33184b3843
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361986265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.361986265
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.807222023
Short name T1052
Test name
Test status
Simulation time 20537741 ps
CPU time 0.71 seconds
Started Jul 17 07:03:19 PM PDT 24
Finished Jul 17 07:03:25 PM PDT 24
Peak memory 205372 kb
Host smart-e3acabdd-fc6b-42f1-8dd0-83f4e72db467
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807222023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.807222023
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2697026637
Short name T153
Test name
Test status
Simulation time 250646137 ps
CPU time 3.48 seconds
Started Jul 17 07:02:31 PM PDT 24
Finished Jul 17 07:02:41 PM PDT 24
Peak memory 205596 kb
Host smart-18acd0ae-23e1-4330-b2ac-f8ffb225b94a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697026637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.2
697026637
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2407354124
Short name T1032
Test name
Test status
Simulation time 1344175752 ps
CPU time 9.2 seconds
Started Jul 17 07:02:31 PM PDT 24
Finished Jul 17 07:02:47 PM PDT 24
Peak memory 205668 kb
Host smart-cb229250-3e1c-44ce-84f7-b3b28c705823
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407354124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2
407354124
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.804420861
Short name T967
Test name
Test status
Simulation time 58672350 ps
CPU time 1.15 seconds
Started Jul 17 07:02:34 PM PDT 24
Finished Jul 17 07:02:42 PM PDT 24
Peak memory 205608 kb
Host smart-92a5939a-eec5-4324-bad7-e6fc2bba4fc6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804420861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.804420861
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2340777518
Short name T979
Test name
Test status
Simulation time 45152007 ps
CPU time 1.97 seconds
Started Jul 17 07:02:31 PM PDT 24
Finished Jul 17 07:02:40 PM PDT 24
Peak memory 213876 kb
Host smart-706e6d90-d3c1-4386-9dd5-bbbab657d9d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340777518 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2340777518
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3829161329
Short name T151
Test name
Test status
Simulation time 99892750 ps
CPU time 1.03 seconds
Started Jul 17 07:02:32 PM PDT 24
Finished Jul 17 07:02:39 PM PDT 24
Peak memory 205568 kb
Host smart-f26e1c65-9657-499a-ac34-a8bd1fae105e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829161329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3829161329
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3153519402
Short name T1047
Test name
Test status
Simulation time 13743862 ps
CPU time 0.72 seconds
Started Jul 17 07:02:30 PM PDT 24
Finished Jul 17 07:02:38 PM PDT 24
Peak memory 205372 kb
Host smart-0fb2caae-b4ed-4b2e-b5d4-cbe8e663184a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153519402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3153519402
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3130084105
Short name T1071
Test name
Test status
Simulation time 283522291 ps
CPU time 2.11 seconds
Started Jul 17 07:02:33 PM PDT 24
Finished Jul 17 07:02:43 PM PDT 24
Peak memory 205556 kb
Host smart-b0ccbf8b-d3a8-4cac-94e3-dd57d7869025
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130084105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.3130084105
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.536185491
Short name T1045
Test name
Test status
Simulation time 203397274 ps
CPU time 2.01 seconds
Started Jul 17 07:02:30 PM PDT 24
Finished Jul 17 07:02:39 PM PDT 24
Peak memory 213992 kb
Host smart-b76d4a7f-02ab-4746-a5d8-12ad1f89ee17
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536185491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow
_reg_errors.536185491
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.663551575
Short name T982
Test name
Test status
Simulation time 200855092 ps
CPU time 4.74 seconds
Started Jul 17 07:02:29 PM PDT 24
Finished Jul 17 07:02:41 PM PDT 24
Peak memory 214136 kb
Host smart-50dbc73e-09d3-4c25-8c5a-4bcaa431e4d2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663551575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_shadow_reg_errors_with_csr_rw.663551575
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.4231431664
Short name T202
Test name
Test status
Simulation time 382459664 ps
CPU time 2.55 seconds
Started Jul 17 07:02:30 PM PDT 24
Finished Jul 17 07:02:39 PM PDT 24
Peak memory 213788 kb
Host smart-eed277b3-e0b7-4823-8b48-344712af6679
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231431664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.4231431664
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.3320721042
Short name T169
Test name
Test status
Simulation time 150320456 ps
CPU time 4.91 seconds
Started Jul 17 07:02:32 PM PDT 24
Finished Jul 17 07:02:44 PM PDT 24
Peak memory 213752 kb
Host smart-8b844d62-b88e-4716-9ff2-6c600145ec53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320721042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.3320721042
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.436076263
Short name T1018
Test name
Test status
Simulation time 16785472 ps
CPU time 0.9 seconds
Started Jul 17 07:03:17 PM PDT 24
Finished Jul 17 07:03:23 PM PDT 24
Peak memory 205372 kb
Host smart-309f821c-0fa8-49e0-aba8-a9613de55bed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436076263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.436076263
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.1265090656
Short name T1020
Test name
Test status
Simulation time 27297099 ps
CPU time 0.89 seconds
Started Jul 17 07:03:18 PM PDT 24
Finished Jul 17 07:03:24 PM PDT 24
Peak memory 205356 kb
Host smart-d9b3adff-c3aa-4a70-a616-2c4bbdc6d408
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265090656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.1265090656
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.188646134
Short name T987
Test name
Test status
Simulation time 20408862 ps
CPU time 0.78 seconds
Started Jul 17 07:03:18 PM PDT 24
Finished Jul 17 07:03:24 PM PDT 24
Peak memory 205288 kb
Host smart-0c428b4a-decd-4770-aaf1-af49f141ad8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188646134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.188646134
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.1947101092
Short name T1006
Test name
Test status
Simulation time 34055949 ps
CPU time 0.75 seconds
Started Jul 17 07:03:19 PM PDT 24
Finished Jul 17 07:03:25 PM PDT 24
Peak memory 205368 kb
Host smart-5af77f4e-c417-4bbc-9236-28e9be9da350
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947101092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.1947101092
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.4116595793
Short name T1003
Test name
Test status
Simulation time 12738624 ps
CPU time 0.71 seconds
Started Jul 17 07:03:20 PM PDT 24
Finished Jul 17 07:03:25 PM PDT 24
Peak memory 205368 kb
Host smart-188edbd9-758c-457a-98c7-88371a545b78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116595793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.4116595793
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1566178628
Short name T1012
Test name
Test status
Simulation time 55361411 ps
CPU time 0.72 seconds
Started Jul 17 07:03:18 PM PDT 24
Finished Jul 17 07:03:24 PM PDT 24
Peak memory 205364 kb
Host smart-5992f9f2-a8c0-44b7-9c5d-0b9b589f3ba2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566178628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.1566178628
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2528840459
Short name T970
Test name
Test status
Simulation time 21554084 ps
CPU time 1 seconds
Started Jul 17 07:03:21 PM PDT 24
Finished Jul 17 07:03:26 PM PDT 24
Peak memory 205364 kb
Host smart-1129ac84-6e26-48da-9fa1-9ae115a32232
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528840459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.2528840459
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.1309658217
Short name T985
Test name
Test status
Simulation time 9116312 ps
CPU time 0.71 seconds
Started Jul 17 07:03:21 PM PDT 24
Finished Jul 17 07:03:26 PM PDT 24
Peak memory 205340 kb
Host smart-0542a467-b538-4f1a-8acd-4a68edabb020
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309658217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.1309658217
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.2101157794
Short name T1009
Test name
Test status
Simulation time 19457593 ps
CPU time 0.79 seconds
Started Jul 17 07:03:20 PM PDT 24
Finished Jul 17 07:03:25 PM PDT 24
Peak memory 205308 kb
Host smart-55f6bbb6-ad29-4422-8fc9-c94939763b74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101157794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.2101157794
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2497567581
Short name T980
Test name
Test status
Simulation time 66224077 ps
CPU time 0.75 seconds
Started Jul 17 07:03:21 PM PDT 24
Finished Jul 17 07:03:26 PM PDT 24
Peak memory 205232 kb
Host smart-0d714c13-c857-4278-a99e-580ed64af510
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497567581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2497567581
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2945004047
Short name T1065
Test name
Test status
Simulation time 267578579 ps
CPU time 5.06 seconds
Started Jul 17 07:02:31 PM PDT 24
Finished Jul 17 07:02:43 PM PDT 24
Peak memory 205568 kb
Host smart-95ad258a-69f9-4ab5-8fdb-a4596f78afc0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945004047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.2
945004047
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.3869819242
Short name T1064
Test name
Test status
Simulation time 260121221 ps
CPU time 12.78 seconds
Started Jul 17 07:02:38 PM PDT 24
Finished Jul 17 07:02:55 PM PDT 24
Peak memory 205552 kb
Host smart-89a5bb74-c9fb-44f5-ba6a-444e2ba18233
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869819242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.3
869819242
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3187606459
Short name T957
Test name
Test status
Simulation time 24011450 ps
CPU time 1.28 seconds
Started Jul 17 07:02:37 PM PDT 24
Finished Jul 17 07:02:44 PM PDT 24
Peak memory 205552 kb
Host smart-78f055e7-33c3-438b-be1c-7517537ea7ba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187606459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.3
187606459
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3770894828
Short name T190
Test name
Test status
Simulation time 54460393 ps
CPU time 1.52 seconds
Started Jul 17 07:02:37 PM PDT 24
Finished Jul 17 07:02:44 PM PDT 24
Peak memory 213816 kb
Host smart-1057a4be-c917-4b44-8118-12c45ac6567a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770894828 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.3770894828
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.3359968353
Short name T154
Test name
Test status
Simulation time 33050881 ps
CPU time 1.16 seconds
Started Jul 17 07:02:32 PM PDT 24
Finished Jul 17 07:02:40 PM PDT 24
Peak memory 205580 kb
Host smart-9763fcac-896c-4c30-ab98-742f047040d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359968353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.3359968353
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.1670965250
Short name T1054
Test name
Test status
Simulation time 12647663 ps
CPU time 0.71 seconds
Started Jul 17 07:02:38 PM PDT 24
Finished Jul 17 07:02:43 PM PDT 24
Peak memory 205376 kb
Host smart-fb77c4f5-c5a6-4a65-953c-25b236afbea9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670965250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.1670965250
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2922935118
Short name T998
Test name
Test status
Simulation time 186403645 ps
CPU time 3.01 seconds
Started Jul 17 07:02:31 PM PDT 24
Finished Jul 17 07:02:41 PM PDT 24
Peak memory 205544 kb
Host smart-5f5a0074-bacd-4750-b651-ee2fb23bbc87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922935118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.2922935118
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.283105584
Short name T126
Test name
Test status
Simulation time 81259929 ps
CPU time 2.47 seconds
Started Jul 17 07:02:33 PM PDT 24
Finished Jul 17 07:02:43 PM PDT 24
Peak memory 214124 kb
Host smart-2b76001d-962f-48d9-b0b1-8f60dd633dd8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283105584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow
_reg_errors.283105584
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.118428779
Short name T1022
Test name
Test status
Simulation time 682996839 ps
CPU time 5.21 seconds
Started Jul 17 07:02:35 PM PDT 24
Finished Jul 17 07:02:47 PM PDT 24
Peak memory 219808 kb
Host smart-c104e5ec-ec1d-4452-aebe-1be853c00cfb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118428779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_shadow_reg_errors_with_csr_rw.118428779
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1635111756
Short name T942
Test name
Test status
Simulation time 39635530 ps
CPU time 2.41 seconds
Started Jul 17 07:02:31 PM PDT 24
Finished Jul 17 07:02:40 PM PDT 24
Peak memory 216392 kb
Host smart-0a9f165e-0b15-4477-8cdc-63126e26fce9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635111756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.1635111756
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.972103894
Short name T1050
Test name
Test status
Simulation time 31257112 ps
CPU time 0.84 seconds
Started Jul 17 07:03:23 PM PDT 24
Finished Jul 17 07:03:27 PM PDT 24
Peak memory 205296 kb
Host smart-dce991f8-51f1-4703-a7ca-95e882cb12a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972103894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.972103894
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.541195741
Short name T1048
Test name
Test status
Simulation time 9997381 ps
CPU time 0.79 seconds
Started Jul 17 07:03:13 PM PDT 24
Finished Jul 17 07:03:15 PM PDT 24
Peak memory 205384 kb
Host smart-461a7cfd-4ebb-40fa-9186-a7b80b395462
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541195741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.541195741
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2776361446
Short name T1034
Test name
Test status
Simulation time 30227821 ps
CPU time 0.69 seconds
Started Jul 17 07:03:14 PM PDT 24
Finished Jul 17 07:03:17 PM PDT 24
Peak memory 205364 kb
Host smart-1f97b557-a0d7-4ba1-a6ab-8cd79a3e5ebd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776361446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2776361446
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.2865441771
Short name T938
Test name
Test status
Simulation time 43806421 ps
CPU time 0.82 seconds
Started Jul 17 07:03:18 PM PDT 24
Finished Jul 17 07:03:24 PM PDT 24
Peak memory 205304 kb
Host smart-398e314d-a3b6-4c5b-bd3e-bb45f7322534
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865441771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.2865441771
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1244555403
Short name T920
Test name
Test status
Simulation time 45693291 ps
CPU time 0.72 seconds
Started Jul 17 07:03:18 PM PDT 24
Finished Jul 17 07:03:24 PM PDT 24
Peak memory 205292 kb
Host smart-ff0db769-1b3c-4d84-b036-05ea0bf16905
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244555403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.1244555403
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.2171879834
Short name T924
Test name
Test status
Simulation time 10236514 ps
CPU time 0.69 seconds
Started Jul 17 07:03:17 PM PDT 24
Finished Jul 17 07:03:23 PM PDT 24
Peak memory 205304 kb
Host smart-e65d4220-85bc-4e7f-9ee3-db3c304672dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171879834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.2171879834
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2085359954
Short name T993
Test name
Test status
Simulation time 10218507 ps
CPU time 0.71 seconds
Started Jul 17 07:03:18 PM PDT 24
Finished Jul 17 07:03:24 PM PDT 24
Peak memory 205344 kb
Host smart-2139510c-5838-452b-852f-7165355aa4e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085359954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.2085359954
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.634498001
Short name T966
Test name
Test status
Simulation time 38550169 ps
CPU time 0.82 seconds
Started Jul 17 07:03:17 PM PDT 24
Finished Jul 17 07:03:22 PM PDT 24
Peak memory 205376 kb
Host smart-ef4aace1-106b-40be-8212-62e9bce438fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634498001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.634498001
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1771663132
Short name T922
Test name
Test status
Simulation time 24763953 ps
CPU time 0.84 seconds
Started Jul 17 07:03:17 PM PDT 24
Finished Jul 17 07:03:23 PM PDT 24
Peak memory 205380 kb
Host smart-c6a4466d-b932-451f-b2a7-85c09ff0ee60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771663132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.1771663132
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1538849928
Short name T1075
Test name
Test status
Simulation time 23679960 ps
CPU time 0.77 seconds
Started Jul 17 07:03:17 PM PDT 24
Finished Jul 17 07:03:22 PM PDT 24
Peak memory 205304 kb
Host smart-bfd2ac0c-ed61-4c9b-89a5-a9b9a5b4fc93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538849928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.1538849928
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.906429850
Short name T925
Test name
Test status
Simulation time 67508060 ps
CPU time 1.38 seconds
Started Jul 17 07:02:57 PM PDT 24
Finished Jul 17 07:03:00 PM PDT 24
Peak memory 213812 kb
Host smart-6b716e8d-9b70-49ff-9f4a-615f00ca2135
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906429850 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.906429850
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2460267109
Short name T976
Test name
Test status
Simulation time 47909215 ps
CPU time 0.91 seconds
Started Jul 17 07:02:32 PM PDT 24
Finished Jul 17 07:02:40 PM PDT 24
Peak memory 205572 kb
Host smart-68336679-1cb8-45c9-a618-12a20fd28c05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460267109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.2460267109
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.1300961621
Short name T1041
Test name
Test status
Simulation time 14007342 ps
CPU time 0.86 seconds
Started Jul 17 07:02:32 PM PDT 24
Finished Jul 17 07:02:41 PM PDT 24
Peak memory 205372 kb
Host smart-a63f1935-e724-4d3d-b4b2-5c8203aec128
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300961621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.1300961621
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.2616637310
Short name T941
Test name
Test status
Simulation time 86742989 ps
CPU time 1.63 seconds
Started Jul 17 07:02:32 PM PDT 24
Finished Jul 17 07:02:41 PM PDT 24
Peak memory 205496 kb
Host smart-85c27c29-ffb9-47da-8ad1-e379049f9800
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616637310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.2616637310
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1665066912
Short name T1057
Test name
Test status
Simulation time 336745383 ps
CPU time 2.72 seconds
Started Jul 17 07:02:32 PM PDT 24
Finished Jul 17 07:02:42 PM PDT 24
Peak memory 214012 kb
Host smart-8f338059-d66d-4bf8-9f92-f0b3d224cee5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665066912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.1665066912
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.359429759
Short name T1067
Test name
Test status
Simulation time 333003327 ps
CPU time 7.19 seconds
Started Jul 17 07:02:33 PM PDT 24
Finished Jul 17 07:02:48 PM PDT 24
Peak memory 214004 kb
Host smart-21973d76-9a40-4e97-b8b4-9bafcbb33a2c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359429759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_shadow_reg_errors_with_csr_rw.359429759
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.1163948047
Short name T977
Test name
Test status
Simulation time 460452970 ps
CPU time 3.06 seconds
Started Jul 17 07:02:35 PM PDT 24
Finished Jul 17 07:02:45 PM PDT 24
Peak memory 213656 kb
Host smart-c216e9e6-d2d2-4e3c-be43-62b2ff210f23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163948047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.1163948047
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.2373176704
Short name T179
Test name
Test status
Simulation time 486978921 ps
CPU time 5.36 seconds
Started Jul 17 07:02:34 PM PDT 24
Finished Jul 17 07:02:47 PM PDT 24
Peak memory 214048 kb
Host smart-2f51468a-283e-4e89-943b-f279ea9af092
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373176704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.2373176704
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2074397205
Short name T961
Test name
Test status
Simulation time 200780470 ps
CPU time 2.2 seconds
Started Jul 17 07:02:52 PM PDT 24
Finished Jul 17 07:02:55 PM PDT 24
Peak memory 213732 kb
Host smart-87f9b5d5-da8d-4619-b547-99272a03c3a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074397205 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.2074397205
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1071724077
Short name T945
Test name
Test status
Simulation time 29348767 ps
CPU time 1.17 seconds
Started Jul 17 07:02:48 PM PDT 24
Finished Jul 17 07:02:51 PM PDT 24
Peak memory 205640 kb
Host smart-b92a68ea-63d8-4301-9729-1a2daaede2bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071724077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1071724077
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.616777601
Short name T1017
Test name
Test status
Simulation time 9902580 ps
CPU time 0.74 seconds
Started Jul 17 07:02:55 PM PDT 24
Finished Jul 17 07:02:57 PM PDT 24
Peak memory 205304 kb
Host smart-de92f8f0-1b48-46b3-b754-aa9bdd9e6e45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616777601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.616777601
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.123266881
Short name T1002
Test name
Test status
Simulation time 91708093 ps
CPU time 1.54 seconds
Started Jul 17 07:02:52 PM PDT 24
Finished Jul 17 07:02:56 PM PDT 24
Peak memory 205584 kb
Host smart-83e1bdce-f4d2-43c8-8fc8-64e19d471ddf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123266881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sam
e_csr_outstanding.123266881
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.934389398
Short name T121
Test name
Test status
Simulation time 579203526 ps
CPU time 2.33 seconds
Started Jul 17 07:02:51 PM PDT 24
Finished Jul 17 07:02:55 PM PDT 24
Peak memory 214080 kb
Host smart-37fc8fac-43bf-40c0-9e2f-eb97924b7081
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934389398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow
_reg_errors.934389398
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.4108119542
Short name T1059
Test name
Test status
Simulation time 143604867 ps
CPU time 3.92 seconds
Started Jul 17 07:02:52 PM PDT 24
Finished Jul 17 07:02:58 PM PDT 24
Peak memory 214052 kb
Host smart-9cbe340a-fe3c-4252-901b-0247ba0712a2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108119542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.4108119542
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2234408846
Short name T1029
Test name
Test status
Simulation time 145923295 ps
CPU time 3.26 seconds
Started Jul 17 07:02:54 PM PDT 24
Finished Jul 17 07:03:00 PM PDT 24
Peak memory 213924 kb
Host smart-44295bcc-a511-4f92-91e0-515289a62564
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234408846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2234408846
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.952795442
Short name T173
Test name
Test status
Simulation time 533162830 ps
CPU time 3.81 seconds
Started Jul 17 07:02:57 PM PDT 24
Finished Jul 17 07:03:02 PM PDT 24
Peak memory 205568 kb
Host smart-7db3ca89-b8e9-4b64-93b1-5bde1c81951b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952795442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.
952795442
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.194605610
Short name T927
Test name
Test status
Simulation time 124952762 ps
CPU time 2.58 seconds
Started Jul 17 07:02:55 PM PDT 24
Finished Jul 17 07:03:00 PM PDT 24
Peak memory 213768 kb
Host smart-ccd52efe-50bc-4ad8-980c-00cb28ea36fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194605610 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.194605610
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3416850784
Short name T958
Test name
Test status
Simulation time 20882813 ps
CPU time 0.83 seconds
Started Jul 17 07:02:54 PM PDT 24
Finished Jul 17 07:02:57 PM PDT 24
Peak memory 205532 kb
Host smart-59f53370-fd92-4231-a4ee-014847a141a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416850784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.3416850784
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1705811932
Short name T988
Test name
Test status
Simulation time 34165147 ps
CPU time 2.4 seconds
Started Jul 17 07:02:53 PM PDT 24
Finished Jul 17 07:02:57 PM PDT 24
Peak memory 205508 kb
Host smart-ba49fad7-db13-417e-8a8d-fa7ce4779257
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705811932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.1705811932
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1588755753
Short name T122
Test name
Test status
Simulation time 385686298 ps
CPU time 3.05 seconds
Started Jul 17 07:02:51 PM PDT 24
Finished Jul 17 07:02:55 PM PDT 24
Peak memory 214024 kb
Host smart-d6033a96-c250-4090-8d29-837fe2f6b188
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588755753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.1588755753
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3945790649
Short name T1055
Test name
Test status
Simulation time 159440517 ps
CPU time 3.74 seconds
Started Jul 17 07:02:52 PM PDT 24
Finished Jul 17 07:02:58 PM PDT 24
Peak memory 214172 kb
Host smart-b3ba1f12-85f9-4009-957e-d3590108a21b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945790649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.3945790649
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1651018139
Short name T981
Test name
Test status
Simulation time 57252218 ps
CPU time 2.34 seconds
Started Jul 17 07:02:52 PM PDT 24
Finished Jul 17 07:02:55 PM PDT 24
Peak memory 215548 kb
Host smart-452738e3-3a8c-46a6-8b37-7833af9c33ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651018139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.1651018139
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.452110618
Short name T165
Test name
Test status
Simulation time 353174139 ps
CPU time 6.26 seconds
Started Jul 17 07:02:57 PM PDT 24
Finished Jul 17 07:03:04 PM PDT 24
Peak memory 213768 kb
Host smart-7c6caad6-6edd-4f91-a5e3-901f0eaaf9d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452110618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.
452110618
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.580705968
Short name T974
Test name
Test status
Simulation time 66397704 ps
CPU time 1.23 seconds
Started Jul 17 07:02:57 PM PDT 24
Finished Jul 17 07:03:00 PM PDT 24
Peak memory 213840 kb
Host smart-741d53b7-6d08-428c-bb68-174288b82176
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580705968 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.580705968
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2518411420
Short name T1019
Test name
Test status
Simulation time 20822126 ps
CPU time 1.01 seconds
Started Jul 17 07:02:53 PM PDT 24
Finished Jul 17 07:02:56 PM PDT 24
Peak memory 205528 kb
Host smart-45e357b4-7c21-47aa-9602-d96a2a07c306
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518411420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.2518411420
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.3176573215
Short name T921
Test name
Test status
Simulation time 33658204 ps
CPU time 0.83 seconds
Started Jul 17 07:02:49 PM PDT 24
Finished Jul 17 07:02:51 PM PDT 24
Peak memory 205372 kb
Host smart-04f33e92-6b5f-4cc3-a773-a87fe8ac5429
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176573215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.3176573215
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.2493594229
Short name T1027
Test name
Test status
Simulation time 47501165 ps
CPU time 1.71 seconds
Started Jul 17 07:02:56 PM PDT 24
Finished Jul 17 07:02:59 PM PDT 24
Peak memory 205540 kb
Host smart-2a022122-57b3-41bd-8492-9a47ee6d084f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493594229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.2493594229
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3972338927
Short name T1036
Test name
Test status
Simulation time 99759272 ps
CPU time 2.93 seconds
Started Jul 17 07:02:50 PM PDT 24
Finished Jul 17 07:02:54 PM PDT 24
Peak memory 218300 kb
Host smart-57d091d2-b363-4256-9e70-15fef9da2bee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972338927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.3972338927
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.2063390886
Short name T972
Test name
Test status
Simulation time 320114569 ps
CPU time 6.49 seconds
Started Jul 17 07:02:52 PM PDT 24
Finished Jul 17 07:03:00 PM PDT 24
Peak memory 213944 kb
Host smart-2fe76e56-f24b-488b-88dc-8d238dae5d16
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063390886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.2063390886
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1545819144
Short name T931
Test name
Test status
Simulation time 397782390 ps
CPU time 2.15 seconds
Started Jul 17 07:02:53 PM PDT 24
Finished Jul 17 07:02:57 PM PDT 24
Peak memory 215804 kb
Host smart-c9f5ae5b-0db6-468e-86f8-1315f9e00f30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545819144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1545819144
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.3973442473
Short name T399
Test name
Test status
Simulation time 198920824 ps
CPU time 2.56 seconds
Started Jul 17 07:02:51 PM PDT 24
Finished Jul 17 07:02:55 PM PDT 24
Peak memory 213740 kb
Host smart-37637ede-efe5-4fa8-b10a-ff917b017383
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973442473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.3973442473
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.3573140282
Short name T1044
Test name
Test status
Simulation time 53141145 ps
CPU time 1.13 seconds
Started Jul 17 07:02:53 PM PDT 24
Finished Jul 17 07:02:56 PM PDT 24
Peak memory 205500 kb
Host smart-07f3b12d-ae43-4970-bb65-91b89b36c86d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573140282 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.3573140282
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3131217276
Short name T1046
Test name
Test status
Simulation time 12436211 ps
CPU time 1.19 seconds
Started Jul 17 07:02:53 PM PDT 24
Finished Jul 17 07:02:56 PM PDT 24
Peak memory 205508 kb
Host smart-4f49e5cb-b129-472a-9a15-bf22d072e031
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131217276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.3131217276
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1885201398
Short name T951
Test name
Test status
Simulation time 11122449 ps
CPU time 0.78 seconds
Started Jul 17 07:02:52 PM PDT 24
Finished Jul 17 07:02:55 PM PDT 24
Peak memory 205316 kb
Host smart-3a434f0b-1111-430a-aed0-afd4492a8f43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885201398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.1885201398
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.925262193
Short name T1028
Test name
Test status
Simulation time 43643602 ps
CPU time 2.02 seconds
Started Jul 17 07:02:53 PM PDT 24
Finished Jul 17 07:02:57 PM PDT 24
Peak memory 205484 kb
Host smart-1a6e995e-52cc-4722-ac65-5388ab76f410
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925262193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sam
e_csr_outstanding.925262193
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2963232712
Short name T119
Test name
Test status
Simulation time 44807730 ps
CPU time 1.86 seconds
Started Jul 17 07:02:50 PM PDT 24
Finished Jul 17 07:02:53 PM PDT 24
Peak memory 214080 kb
Host smart-92137b31-6d11-4aa5-929a-f0c1b6813a31
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963232712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.2963232712
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2582877850
Short name T969
Test name
Test status
Simulation time 409134170 ps
CPU time 9.77 seconds
Started Jul 17 07:02:50 PM PDT 24
Finished Jul 17 07:03:01 PM PDT 24
Peak memory 214124 kb
Host smart-62199ab3-c858-47ca-ad84-41a45662be48
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582877850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.2582877850
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.427829
Short name T1016
Test name
Test status
Simulation time 178781467 ps
CPU time 3.99 seconds
Started Jul 17 07:02:53 PM PDT 24
Finished Jul 17 07:02:59 PM PDT 24
Peak memory 213756 kb
Host smart-81b23799-d59d-4816-b409-82adfbd7f27d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.427829
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3517128695
Short name T161
Test name
Test status
Simulation time 96916356 ps
CPU time 2.59 seconds
Started Jul 17 07:02:55 PM PDT 24
Finished Jul 17 07:02:59 PM PDT 24
Peak memory 213756 kb
Host smart-89352969-29c2-4822-a959-ec99cc36b2f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517128695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.3517128695
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.1213164287
Short name T505
Test name
Test status
Simulation time 48017980 ps
CPU time 0.92 seconds
Started Jul 17 07:05:28 PM PDT 24
Finished Jul 17 07:05:31 PM PDT 24
Peak memory 206136 kb
Host smart-45f24d6a-de88-4afc-a546-6b8f49a8a801
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213164287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.1213164287
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.1794851123
Short name T686
Test name
Test status
Simulation time 172204702 ps
CPU time 3.56 seconds
Started Jul 17 07:05:27 PM PDT 24
Finished Jul 17 07:05:31 PM PDT 24
Peak memory 215216 kb
Host smart-653999a7-891d-4071-9f4a-2b08c026ef1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1794851123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.1794851123
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.2945438720
Short name T550
Test name
Test status
Simulation time 104264231 ps
CPU time 2.49 seconds
Started Jul 17 07:05:30 PM PDT 24
Finished Jul 17 07:05:37 PM PDT 24
Peak memory 220784 kb
Host smart-100092ef-7dea-4798-a6f1-41af1494b177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945438720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.2945438720
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.1438079104
Short name T663
Test name
Test status
Simulation time 664197859 ps
CPU time 5.91 seconds
Started Jul 17 07:05:26 PM PDT 24
Finished Jul 17 07:05:33 PM PDT 24
Peak memory 214256 kb
Host smart-d0acf1fd-4494-4014-874a-538b958bf9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438079104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.1438079104
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.1985728057
Short name T638
Test name
Test status
Simulation time 175072897 ps
CPU time 3.39 seconds
Started Jul 17 07:05:27 PM PDT 24
Finished Jul 17 07:05:32 PM PDT 24
Peak memory 208584 kb
Host smart-d443a6f2-ad3a-448a-ac90-46bf239b819d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985728057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.1985728057
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.1530043779
Short name T717
Test name
Test status
Simulation time 811506836 ps
CPU time 16.3 seconds
Started Jul 17 07:05:29 PM PDT 24
Finished Jul 17 07:05:48 PM PDT 24
Peak memory 209488 kb
Host smart-cff9cd4f-c9d0-43fa-a9c7-08d405280ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530043779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.1530043779
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.961366092
Short name T49
Test name
Test status
Simulation time 1973957698 ps
CPU time 10.85 seconds
Started Jul 17 07:05:28 PM PDT 24
Finished Jul 17 07:05:42 PM PDT 24
Peak memory 238484 kb
Host smart-850cc695-037e-4f97-935a-6baa87469951
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961366092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.961366092
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.2638239145
Short name T719
Test name
Test status
Simulation time 4783669505 ps
CPU time 31.84 seconds
Started Jul 17 07:05:28 PM PDT 24
Finished Jul 17 07:06:01 PM PDT 24
Peak memory 208160 kb
Host smart-f8b9372b-5edd-4198-a3d3-7461f4409af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638239145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.2638239145
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.1830061388
Short name T780
Test name
Test status
Simulation time 245949560 ps
CPU time 3.4 seconds
Started Jul 17 07:05:32 PM PDT 24
Finished Jul 17 07:05:38 PM PDT 24
Peak memory 206876 kb
Host smart-d8b6314a-54dc-4284-901b-604784f79db0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830061388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.1830061388
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.3238863875
Short name T595
Test name
Test status
Simulation time 54929848 ps
CPU time 2.81 seconds
Started Jul 17 07:05:26 PM PDT 24
Finished Jul 17 07:05:31 PM PDT 24
Peak memory 208604 kb
Host smart-f4c2567a-76cc-43c3-bdcf-46642747ce14
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238863875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.3238863875
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.2706187292
Short name T616
Test name
Test status
Simulation time 368121255 ps
CPU time 3.34 seconds
Started Jul 17 07:05:30 PM PDT 24
Finished Jul 17 07:05:38 PM PDT 24
Peak memory 207656 kb
Host smart-b77dff8e-c25e-4513-b5d6-122a837a922f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706187292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.2706187292
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.2713864334
Short name T467
Test name
Test status
Simulation time 57958279 ps
CPU time 2.38 seconds
Started Jul 17 07:05:28 PM PDT 24
Finished Jul 17 07:05:32 PM PDT 24
Peak memory 207100 kb
Host smart-812c6a9b-13d4-4893-ab14-8fd945fccf3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713864334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2713864334
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.536659665
Short name T709
Test name
Test status
Simulation time 1655592429 ps
CPU time 7.76 seconds
Started Jul 17 07:05:31 PM PDT 24
Finished Jul 17 07:05:42 PM PDT 24
Peak memory 208476 kb
Host smart-af4fe619-e3b5-4e2b-b52d-ed8e336758be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536659665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.536659665
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.28195181
Short name T680
Test name
Test status
Simulation time 1999330790 ps
CPU time 12.43 seconds
Started Jul 17 07:05:31 PM PDT 24
Finished Jul 17 07:05:47 PM PDT 24
Peak memory 218456 kb
Host smart-0578cff4-175f-4e40-8196-447f6e3044e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28195181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.28195181
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.3124887379
Short name T608
Test name
Test status
Simulation time 25080940 ps
CPU time 0.71 seconds
Started Jul 17 07:05:31 PM PDT 24
Finished Jul 17 07:05:35 PM PDT 24
Peak memory 206004 kb
Host smart-a6cbb88a-29be-4170-9a69-e187b163dac7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124887379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.3124887379
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.1562434378
Short name T707
Test name
Test status
Simulation time 30728092 ps
CPU time 2.09 seconds
Started Jul 17 07:05:29 PM PDT 24
Finished Jul 17 07:05:35 PM PDT 24
Peak memory 214264 kb
Host smart-259d915c-8dbf-4077-b68f-c8a37631874b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562434378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.1562434378
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.65569749
Short name T77
Test name
Test status
Simulation time 104720616 ps
CPU time 2.77 seconds
Started Jul 17 07:05:29 PM PDT 24
Finished Jul 17 07:05:36 PM PDT 24
Peak memory 210160 kb
Host smart-29e0c33d-9798-46bc-bb54-6ab0bc419458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65569749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.65569749
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.4124622071
Short name T786
Test name
Test status
Simulation time 1198635992 ps
CPU time 3.96 seconds
Started Jul 17 07:05:31 PM PDT 24
Finished Jul 17 07:05:39 PM PDT 24
Peak memory 220564 kb
Host smart-93072ef0-2c49-42ff-ab16-4d04ee4c78e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124622071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.4124622071
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.3153779395
Short name T476
Test name
Test status
Simulation time 91877285 ps
CPU time 5.07 seconds
Started Jul 17 07:05:28 PM PDT 24
Finished Jul 17 07:05:34 PM PDT 24
Peak memory 215492 kb
Host smart-56e67dc8-b1b1-4978-958c-01a164da1c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153779395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.3153779395
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.1891492825
Short name T319
Test name
Test status
Simulation time 135239472 ps
CPU time 5.62 seconds
Started Jul 17 07:05:27 PM PDT 24
Finished Jul 17 07:05:33 PM PDT 24
Peak memory 218716 kb
Host smart-08941d6d-9a9d-4400-b7c9-4da14a0b43da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891492825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1891492825
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.3510530683
Short name T13
Test name
Test status
Simulation time 852642755 ps
CPU time 11.5 seconds
Started Jul 17 07:05:27 PM PDT 24
Finished Jul 17 07:05:39 PM PDT 24
Peak memory 234100 kb
Host smart-6def35f7-bef9-4002-93e7-9689d15944e1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510530683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.3510530683
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.3427821834
Short name T255
Test name
Test status
Simulation time 274992732 ps
CPU time 3.48 seconds
Started Jul 17 07:05:29 PM PDT 24
Finished Jul 17 07:05:36 PM PDT 24
Peak memory 207024 kb
Host smart-83abb71f-ffcd-4f9d-abbc-4fdb312adc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427821834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.3427821834
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.3292751231
Short name T258
Test name
Test status
Simulation time 76251490 ps
CPU time 1.9 seconds
Started Jul 17 07:05:28 PM PDT 24
Finished Jul 17 07:05:32 PM PDT 24
Peak memory 208732 kb
Host smart-0383c521-718b-4fa3-98ce-627bb4bdf931
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292751231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.3292751231
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.3643130932
Short name T799
Test name
Test status
Simulation time 206646258 ps
CPU time 2.8 seconds
Started Jul 17 07:05:30 PM PDT 24
Finished Jul 17 07:05:37 PM PDT 24
Peak memory 206772 kb
Host smart-b411837d-d531-4934-81b4-b9847ec92d5d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643130932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.3643130932
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.197726913
Short name T309
Test name
Test status
Simulation time 2009939470 ps
CPU time 25.96 seconds
Started Jul 17 07:05:27 PM PDT 24
Finished Jul 17 07:05:54 PM PDT 24
Peak memory 208820 kb
Host smart-9a7c5102-6de6-41ab-86f8-349e02b66d83
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197726913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.197726913
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.2778788373
Short name T566
Test name
Test status
Simulation time 29299093 ps
CPU time 1.6 seconds
Started Jul 17 07:05:29 PM PDT 24
Finished Jul 17 07:05:34 PM PDT 24
Peak memory 207508 kb
Host smart-a14cf12a-c168-4cb6-a481-fa0b7621ad52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778788373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.2778788373
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.476616398
Short name T737
Test name
Test status
Simulation time 45733297 ps
CPU time 1.85 seconds
Started Jul 17 07:05:27 PM PDT 24
Finished Jul 17 07:05:30 PM PDT 24
Peak memory 208596 kb
Host smart-ff160da8-839c-438e-b15e-29466315ab59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476616398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.476616398
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.2039449096
Short name T70
Test name
Test status
Simulation time 195608617 ps
CPU time 4.55 seconds
Started Jul 17 07:05:29 PM PDT 24
Finished Jul 17 07:05:37 PM PDT 24
Peak memory 214328 kb
Host smart-8d511418-76a7-4d9d-a76e-c311e67d7fb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039449096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.2039449096
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.2969090012
Short name T703
Test name
Test status
Simulation time 1502309076 ps
CPU time 17.67 seconds
Started Jul 17 07:05:29 PM PDT 24
Finished Jul 17 07:05:50 PM PDT 24
Peak memory 222544 kb
Host smart-5580b0c8-eb3a-4265-8347-442e18834cb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969090012 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.2969090012
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.1466764195
Short name T355
Test name
Test status
Simulation time 414084659 ps
CPU time 3.13 seconds
Started Jul 17 07:05:30 PM PDT 24
Finished Jul 17 07:05:36 PM PDT 24
Peak memory 214268 kb
Host smart-a85d920e-5282-4ea0-82e2-d611e6af748a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466764195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.1466764195
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.617367010
Short name T788
Test name
Test status
Simulation time 58184402 ps
CPU time 1.84 seconds
Started Jul 17 07:05:28 PM PDT 24
Finished Jul 17 07:05:33 PM PDT 24
Peak memory 209932 kb
Host smart-a691c7dd-5b5d-4bd4-ac61-180559f5ac6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617367010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.617367010
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.2283333959
Short name T501
Test name
Test status
Simulation time 12873541 ps
CPU time 0.76 seconds
Started Jul 17 07:06:17 PM PDT 24
Finished Jul 17 07:06:29 PM PDT 24
Peak memory 205992 kb
Host smart-3ffa44aa-3f4a-428a-a0f7-3637b4464016
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283333959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.2283333959
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.775308974
Short name T268
Test name
Test status
Simulation time 222450758 ps
CPU time 4.43 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:23 PM PDT 24
Peak memory 214340 kb
Host smart-43dd1660-6c9d-4a19-8722-4c23cc14ab8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=775308974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.775308974
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.850366378
Short name T600
Test name
Test status
Simulation time 125310173 ps
CPU time 3.28 seconds
Started Jul 17 07:06:13 PM PDT 24
Finished Jul 17 07:06:27 PM PDT 24
Peak memory 223008 kb
Host smart-8dc2cd48-4677-4a42-a468-0d0cfaeee1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850366378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.850366378
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.2704435203
Short name T674
Test name
Test status
Simulation time 353612581 ps
CPU time 4.16 seconds
Started Jul 17 07:06:12 PM PDT 24
Finished Jul 17 07:06:27 PM PDT 24
Peak memory 218336 kb
Host smart-7cca8f19-60e4-4060-af9e-afc773af5955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704435203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.2704435203
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.3566720977
Short name T647
Test name
Test status
Simulation time 107125157 ps
CPU time 3.45 seconds
Started Jul 17 07:06:13 PM PDT 24
Finished Jul 17 07:06:27 PM PDT 24
Peak memory 214524 kb
Host smart-ab90c961-114d-4f1d-8720-a7696d1cc3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566720977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.3566720977
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.4098403491
Short name T7
Test name
Test status
Simulation time 199026937 ps
CPU time 2.79 seconds
Started Jul 17 07:06:10 PM PDT 24
Finished Jul 17 07:06:21 PM PDT 24
Peak memory 209164 kb
Host smart-044b5f63-5fdd-41d5-8fe2-75fab9e65b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098403491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.4098403491
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.2363812120
Short name T880
Test name
Test status
Simulation time 99457656 ps
CPU time 4.21 seconds
Started Jul 17 07:06:13 PM PDT 24
Finished Jul 17 07:06:27 PM PDT 24
Peak memory 214308 kb
Host smart-6b101e7f-679a-4f58-8005-d665f2a54d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363812120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.2363812120
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.941986693
Short name T396
Test name
Test status
Simulation time 65968229 ps
CPU time 2.96 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:22 PM PDT 24
Peak memory 208780 kb
Host smart-e3688ed4-09da-4a44-aaa0-f22786fe8cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941986693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.941986693
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.840767248
Short name T466
Test name
Test status
Simulation time 289624823 ps
CPU time 4.72 seconds
Started Jul 17 07:06:10 PM PDT 24
Finished Jul 17 07:06:22 PM PDT 24
Peak memory 208692 kb
Host smart-75ad2985-1d23-4688-ba97-02ca56207247
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840767248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.840767248
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.1612675017
Short name T369
Test name
Test status
Simulation time 167780742 ps
CPU time 2.71 seconds
Started Jul 17 07:06:10 PM PDT 24
Finished Jul 17 07:06:20 PM PDT 24
Peak memory 208648 kb
Host smart-91593dff-1dae-426f-aa2d-cd4c59770258
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612675017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.1612675017
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.2338701105
Short name T591
Test name
Test status
Simulation time 610694792 ps
CPU time 8.72 seconds
Started Jul 17 07:06:13 PM PDT 24
Finished Jul 17 07:06:31 PM PDT 24
Peak memory 207016 kb
Host smart-00b9b80b-52d7-4b15-affa-15e8aa5af5b0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338701105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.2338701105
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.2457676287
Short name T331
Test name
Test status
Simulation time 97474538 ps
CPU time 4.06 seconds
Started Jul 17 07:06:13 PM PDT 24
Finished Jul 17 07:06:27 PM PDT 24
Peak memory 210276 kb
Host smart-a9c2dd78-0b15-4fc6-903e-31d60de66283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457676287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.2457676287
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.3724497923
Short name T665
Test name
Test status
Simulation time 7048568899 ps
CPU time 23.23 seconds
Started Jul 17 07:06:06 PM PDT 24
Finished Jul 17 07:06:32 PM PDT 24
Peak memory 208708 kb
Host smart-b8c9f4f8-70d9-4d2c-9008-c84199c3645b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724497923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3724497923
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.3574810532
Short name T376
Test name
Test status
Simulation time 8147562593 ps
CPU time 49.75 seconds
Started Jul 17 07:06:15 PM PDT 24
Finished Jul 17 07:07:16 PM PDT 24
Peak memory 216932 kb
Host smart-a1551dba-5cc1-4260-9368-40c862969acd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574810532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.3574810532
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.914376541
Short name T189
Test name
Test status
Simulation time 302611220 ps
CPU time 7.67 seconds
Started Jul 17 07:06:20 PM PDT 24
Finished Jul 17 07:06:37 PM PDT 24
Peak memory 219752 kb
Host smart-241405cb-6edd-4d16-aca6-e93c3f093704
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914376541 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.914376541
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3167020995
Short name T488
Test name
Test status
Simulation time 1324740181 ps
CPU time 10.21 seconds
Started Jul 17 07:06:12 PM PDT 24
Finished Jul 17 07:06:32 PM PDT 24
Peak memory 209412 kb
Host smart-1cc2d483-29b1-4fb4-a850-d1ea5809a7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167020995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3167020995
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.770513574
Short name T712
Test name
Test status
Simulation time 719378055 ps
CPU time 9.84 seconds
Started Jul 17 07:06:14 PM PDT 24
Finished Jul 17 07:06:35 PM PDT 24
Peak memory 211096 kb
Host smart-22ec5f6e-d1ed-492d-b811-b5ff69d7e6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770513574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.770513574
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.178476445
Short name T469
Test name
Test status
Simulation time 44539350 ps
CPU time 0.83 seconds
Started Jul 17 07:06:15 PM PDT 24
Finished Jul 17 07:06:27 PM PDT 24
Peak memory 206020 kb
Host smart-1fe91978-d456-4c1a-999e-070aa98e1119
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178476445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.178476445
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.2988281918
Short name T916
Test name
Test status
Simulation time 663248748 ps
CPU time 4.37 seconds
Started Jul 17 07:06:10 PM PDT 24
Finished Jul 17 07:06:23 PM PDT 24
Peak memory 214320 kb
Host smart-e9ec4c9b-338f-436a-acd0-3d23936e222e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988281918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.2988281918
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.814381891
Short name T250
Test name
Test status
Simulation time 91699145 ps
CPU time 3.08 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:22 PM PDT 24
Peak memory 209856 kb
Host smart-db9bef22-4e0a-4ab9-9ca8-25727cb0b06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814381891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.814381891
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.2662845023
Short name T873
Test name
Test status
Simulation time 168882954 ps
CPU time 3.03 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:23 PM PDT 24
Peak memory 207628 kb
Host smart-51ba22e5-e978-480f-9257-c0da5e93e700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662845023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.2662845023
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.2784186615
Short name T829
Test name
Test status
Simulation time 109069850 ps
CPU time 2.22 seconds
Started Jul 17 07:06:16 PM PDT 24
Finished Jul 17 07:06:28 PM PDT 24
Peak memory 207636 kb
Host smart-7d7d2808-3122-4bdb-994d-187992f019fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784186615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.2784186615
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.1645713631
Short name T87
Test name
Test status
Simulation time 1616741776 ps
CPU time 39.07 seconds
Started Jul 17 07:06:12 PM PDT 24
Finished Jul 17 07:07:01 PM PDT 24
Peak memory 209080 kb
Host smart-f984a42e-2438-4841-97ab-764f447e2b65
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645713631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.1645713631
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.135909974
Short name T764
Test name
Test status
Simulation time 455320916 ps
CPU time 6.44 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:27 PM PDT 24
Peak memory 208664 kb
Host smart-b2c58849-b6fa-4ae4-a31d-b7329e071a6e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135909974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.135909974
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.850955647
Short name T849
Test name
Test status
Simulation time 24602747 ps
CPU time 1.93 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:23 PM PDT 24
Peak memory 207664 kb
Host smart-463ffc7a-7b4f-4195-b9f6-bb5b7c5d5dba
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850955647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.850955647
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.2000942469
Short name T577
Test name
Test status
Simulation time 144398910 ps
CPU time 3.41 seconds
Started Jul 17 07:06:12 PM PDT 24
Finished Jul 17 07:06:26 PM PDT 24
Peak memory 209532 kb
Host smart-336ca833-8b21-42f2-876d-2a4a0d16715d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000942469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.2000942469
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.145105097
Short name T458
Test name
Test status
Simulation time 204164117 ps
CPU time 2.6 seconds
Started Jul 17 07:06:20 PM PDT 24
Finished Jul 17 07:06:32 PM PDT 24
Peak memory 206900 kb
Host smart-d808658f-ba14-4c43-b3a1-edc279fadb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145105097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.145105097
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.3809115976
Short name T884
Test name
Test status
Simulation time 241267978 ps
CPU time 3.55 seconds
Started Jul 17 07:06:14 PM PDT 24
Finished Jul 17 07:06:28 PM PDT 24
Peak memory 214172 kb
Host smart-8a74f79f-31f9-4e78-8bb2-35f21e8513b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809115976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3809115976
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.2749786847
Short name T623
Test name
Test status
Simulation time 1072808471 ps
CPU time 11.56 seconds
Started Jul 17 07:06:12 PM PDT 24
Finished Jul 17 07:06:32 PM PDT 24
Peak memory 218268 kb
Host smart-29154f62-5117-4054-a6b1-9d7c4970150c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749786847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2749786847
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.3054820963
Short name T706
Test name
Test status
Simulation time 43031230 ps
CPU time 2.55 seconds
Started Jul 17 07:06:13 PM PDT 24
Finished Jul 17 07:06:25 PM PDT 24
Peak memory 210488 kb
Host smart-7c2d5233-24f3-472c-a01a-be902da64013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054820963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.3054820963
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.738009946
Short name T315
Test name
Test status
Simulation time 157608858 ps
CPU time 3.06 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:23 PM PDT 24
Peak memory 214312 kb
Host smart-0585ea74-5caf-4868-88df-c94d3c368100
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=738009946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.738009946
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.1177612839
Short name T601
Test name
Test status
Simulation time 131474879 ps
CPU time 2 seconds
Started Jul 17 07:06:12 PM PDT 24
Finished Jul 17 07:06:24 PM PDT 24
Peak memory 207604 kb
Host smart-01f29338-3014-4076-aa53-79ab2898e101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177612839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1177612839
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.1316971597
Short name T684
Test name
Test status
Simulation time 86127007 ps
CPU time 3.89 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:24 PM PDT 24
Peak memory 214352 kb
Host smart-f3d038f1-5576-4e94-9c26-bd07d9c4edb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316971597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.1316971597
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sideload.2119200088
Short name T211
Test name
Test status
Simulation time 153855693 ps
CPU time 3.31 seconds
Started Jul 17 07:06:05 PM PDT 24
Finished Jul 17 07:06:11 PM PDT 24
Peak memory 208868 kb
Host smart-01091505-5410-4b23-94e9-e5a377033931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119200088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.2119200088
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.4115615073
Short name T533
Test name
Test status
Simulation time 21193685 ps
CPU time 1.79 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:21 PM PDT 24
Peak memory 207292 kb
Host smart-5c060dd2-729a-4f05-b0f4-c2a56f4277ac
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115615073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.4115615073
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.1781264742
Short name T613
Test name
Test status
Simulation time 161290268 ps
CPU time 3.73 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:23 PM PDT 24
Peak memory 206776 kb
Host smart-7ee4ee53-e0f5-4c16-bf43-1932e18e2a5a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781264742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.1781264742
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.2831327566
Short name T874
Test name
Test status
Simulation time 152528181 ps
CPU time 3.27 seconds
Started Jul 17 07:06:13 PM PDT 24
Finished Jul 17 07:06:27 PM PDT 24
Peak memory 209564 kb
Host smart-27bd03fc-290e-408f-a1bb-667550bc206d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831327566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.2831327566
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.2695475536
Short name T586
Test name
Test status
Simulation time 70744644 ps
CPU time 2.01 seconds
Started Jul 17 07:06:20 PM PDT 24
Finished Jul 17 07:06:32 PM PDT 24
Peak memory 208592 kb
Host smart-6ec561af-7756-4e24-9b0f-880e8b1e1327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695475536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.2695475536
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.3271725497
Short name T206
Test name
Test status
Simulation time 1231689711 ps
CPU time 8.22 seconds
Started Jul 17 07:06:14 PM PDT 24
Finished Jul 17 07:06:34 PM PDT 24
Peak memory 219220 kb
Host smart-368bee7f-e670-4bf6-a73a-ba6521da9664
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271725497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3271725497
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.1676824557
Short name T667
Test name
Test status
Simulation time 1885792634 ps
CPU time 3.23 seconds
Started Jul 17 07:06:13 PM PDT 24
Finished Jul 17 07:06:27 PM PDT 24
Peak memory 209984 kb
Host smart-7a429c63-2b73-43e9-baae-c59cdae2a63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676824557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.1676824557
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.1338233888
Short name T694
Test name
Test status
Simulation time 13080583 ps
CPU time 0.76 seconds
Started Jul 17 07:06:20 PM PDT 24
Finished Jul 17 07:06:30 PM PDT 24
Peak memory 205992 kb
Host smart-0b7b9210-20c5-4dc5-99ee-37e87093d0e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338233888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1338233888
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.187632450
Short name T429
Test name
Test status
Simulation time 353001996 ps
CPU time 5.43 seconds
Started Jul 17 07:06:18 PM PDT 24
Finished Jul 17 07:06:33 PM PDT 24
Peak memory 215236 kb
Host smart-832d6eb9-0db1-4f0a-965c-4e93dfc4989f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=187632450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.187632450
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.1362608949
Short name T452
Test name
Test status
Simulation time 92280013 ps
CPU time 4.04 seconds
Started Jul 17 07:06:18 PM PDT 24
Finished Jul 17 07:06:32 PM PDT 24
Peak memory 207212 kb
Host smart-54e1b0d2-89fc-4ad9-8873-c8370d558bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362608949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.1362608949
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.1931398021
Short name T378
Test name
Test status
Simulation time 81408708 ps
CPU time 1.61 seconds
Started Jul 17 07:06:18 PM PDT 24
Finished Jul 17 07:06:30 PM PDT 24
Peak memory 214348 kb
Host smart-d91dc061-e3f2-4308-a52b-273ffcd7666e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931398021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1931398021
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.2587693715
Short name T144
Test name
Test status
Simulation time 457669709 ps
CPU time 3.93 seconds
Started Jul 17 07:06:14 PM PDT 24
Finished Jul 17 07:06:29 PM PDT 24
Peak memory 208856 kb
Host smart-d649e767-6ff4-4b9b-97b5-f5b9bf5f4a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587693715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.2587693715
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.3733719665
Short name T682
Test name
Test status
Simulation time 1730225785 ps
CPU time 6.78 seconds
Started Jul 17 07:06:14 PM PDT 24
Finished Jul 17 07:06:32 PM PDT 24
Peak memory 214320 kb
Host smart-db52b92a-a941-47df-a459-ab1e233dce29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733719665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.3733719665
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.31183043
Short name T787
Test name
Test status
Simulation time 121520838 ps
CPU time 2.42 seconds
Started Jul 17 07:06:13 PM PDT 24
Finished Jul 17 07:06:26 PM PDT 24
Peak memory 206980 kb
Host smart-9336e4ed-cdf2-455e-9ce8-f2a5b67c727e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31183043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.31183043
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.2044039768
Short name T598
Test name
Test status
Simulation time 2135902034 ps
CPU time 15.54 seconds
Started Jul 17 07:06:14 PM PDT 24
Finished Jul 17 07:06:40 PM PDT 24
Peak memory 207036 kb
Host smart-9644b3ff-ac43-410c-ab8e-2eeea2afbb7a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044039768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.2044039768
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.3328671502
Short name T459
Test name
Test status
Simulation time 223519559 ps
CPU time 8.4 seconds
Started Jul 17 07:06:06 PM PDT 24
Finished Jul 17 07:06:18 PM PDT 24
Peak memory 207040 kb
Host smart-a2a19321-3f6e-4f6d-9370-d3d3a011df89
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328671502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.3328671502
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.775361345
Short name T111
Test name
Test status
Simulation time 474819498 ps
CPU time 5.73 seconds
Started Jul 17 07:06:15 PM PDT 24
Finished Jul 17 07:06:32 PM PDT 24
Peak memory 208120 kb
Host smart-d4e3b25f-ccb7-4c6d-bcb9-8770da56a1f0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775361345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.775361345
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_smoke.1096368590
Short name T215
Test name
Test status
Simulation time 60982315 ps
CPU time 2.8 seconds
Started Jul 17 07:06:13 PM PDT 24
Finished Jul 17 07:06:25 PM PDT 24
Peak memory 208556 kb
Host smart-78d1cc77-db94-4bdc-b5d3-b7772efbc02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096368590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.1096368590
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.2440888555
Short name T316
Test name
Test status
Simulation time 238207768 ps
CPU time 6.67 seconds
Started Jul 17 07:06:18 PM PDT 24
Finished Jul 17 07:06:35 PM PDT 24
Peak memory 214320 kb
Host smart-6497d400-02ba-43fa-9ba6-718ce78f593a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440888555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2440888555
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.1980311087
Short name T480
Test name
Test status
Simulation time 42865520 ps
CPU time 0.72 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:21 PM PDT 24
Peak memory 205984 kb
Host smart-17a65f15-0c45-45d8-aeac-7ea700bb7c46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980311087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1980311087
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.3080143363
Short name T437
Test name
Test status
Simulation time 64393273 ps
CPU time 2.91 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:24 PM PDT 24
Peak memory 214304 kb
Host smart-bef9c975-4d04-4a0e-8f50-687ff5b54706
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3080143363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.3080143363
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.1751087861
Short name T58
Test name
Test status
Simulation time 130049789 ps
CPU time 1.59 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:20 PM PDT 24
Peak memory 208352 kb
Host smart-1a3fde41-5a02-4ca3-be8f-b7d6e01df024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751087861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1751087861
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.2388165641
Short name T109
Test name
Test status
Simulation time 200228450 ps
CPU time 4.56 seconds
Started Jul 17 07:06:14 PM PDT 24
Finished Jul 17 07:06:30 PM PDT 24
Peak memory 214332 kb
Host smart-6c697ee4-219c-4b86-b555-64181eea3938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388165641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.2388165641
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.3037185745
Short name T772
Test name
Test status
Simulation time 140283768 ps
CPU time 6.09 seconds
Started Jul 17 07:06:07 PM PDT 24
Finished Jul 17 07:06:16 PM PDT 24
Peak memory 214232 kb
Host smart-03d08cd9-63b4-45fa-bc90-5da19b074876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037185745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3037185745
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.2558389395
Short name T60
Test name
Test status
Simulation time 280914202 ps
CPU time 3.16 seconds
Started Jul 17 07:06:13 PM PDT 24
Finished Jul 17 07:06:27 PM PDT 24
Peak memory 220156 kb
Host smart-c2d9095e-aa8f-4af3-92f4-d9d4b78b6299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558389395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.2558389395
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.1668629826
Short name T320
Test name
Test status
Simulation time 732752026 ps
CPU time 9.37 seconds
Started Jul 17 07:06:16 PM PDT 24
Finished Jul 17 07:06:36 PM PDT 24
Peak memory 218240 kb
Host smart-51ab93a5-96a8-4d6b-aabe-261a7b7ee2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668629826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.1668629826
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.1421211368
Short name T391
Test name
Test status
Simulation time 204567908 ps
CPU time 3.79 seconds
Started Jul 17 07:06:21 PM PDT 24
Finished Jul 17 07:06:33 PM PDT 24
Peak memory 208484 kb
Host smart-6108531c-ea1e-45d9-aea7-13c69d9bd3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421211368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.1421211368
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.41240774
Short name T351
Test name
Test status
Simulation time 72190668 ps
CPU time 3.46 seconds
Started Jul 17 07:06:17 PM PDT 24
Finished Jul 17 07:06:31 PM PDT 24
Peak memory 208060 kb
Host smart-194be577-7102-4607-b2fb-4100efc3ccdf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41240774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.41240774
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.4284007913
Short name T731
Test name
Test status
Simulation time 122805754 ps
CPU time 2.32 seconds
Started Jul 17 07:06:14 PM PDT 24
Finished Jul 17 07:06:28 PM PDT 24
Peak memory 207024 kb
Host smart-2b91e857-6e6c-4b1b-967a-527e87ef4f87
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284007913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.4284007913
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.1139215702
Short name T859
Test name
Test status
Simulation time 81475469 ps
CPU time 1.79 seconds
Started Jul 17 07:06:20 PM PDT 24
Finished Jul 17 07:06:31 PM PDT 24
Peak memory 206972 kb
Host smart-295c992e-29c0-419b-9030-95a66c927b9c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139215702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.1139215702
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.1754099720
Short name T325
Test name
Test status
Simulation time 486493492 ps
CPU time 6.57 seconds
Started Jul 17 07:06:17 PM PDT 24
Finished Jul 17 07:06:34 PM PDT 24
Peak memory 210236 kb
Host smart-e001d039-81bf-413a-883f-e41fc5086972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754099720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.1754099720
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.2307020351
Short name T679
Test name
Test status
Simulation time 275276889 ps
CPU time 3.13 seconds
Started Jul 17 07:06:20 PM PDT 24
Finished Jul 17 07:06:32 PM PDT 24
Peak memory 206896 kb
Host smart-9c7d05b5-b6fd-4865-96d9-0b05e209cd3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307020351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2307020351
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.1912498137
Short name T727
Test name
Test status
Simulation time 249075500 ps
CPU time 6.89 seconds
Started Jul 17 07:06:15 PM PDT 24
Finished Jul 17 07:06:33 PM PDT 24
Peak memory 208152 kb
Host smart-efa05ac9-ab91-4c6e-b627-8f319be461ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912498137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.1912498137
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.275141682
Short name T800
Test name
Test status
Simulation time 20515909 ps
CPU time 1.43 seconds
Started Jul 17 07:06:14 PM PDT 24
Finished Jul 17 07:06:27 PM PDT 24
Peak memory 209892 kb
Host smart-b802a207-6170-482f-90cc-9ba736b229b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275141682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.275141682
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.1446451756
Short name T85
Test name
Test status
Simulation time 29585396 ps
CPU time 0.74 seconds
Started Jul 17 07:06:14 PM PDT 24
Finished Jul 17 07:06:26 PM PDT 24
Peak memory 206000 kb
Host smart-cea3f7d8-976b-4817-8074-5a61b7b75ab2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446451756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.1446451756
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.1684140330
Short name T515
Test name
Test status
Simulation time 100367038 ps
CPU time 2.57 seconds
Started Jul 17 07:06:19 PM PDT 24
Finished Jul 17 07:06:32 PM PDT 24
Peak memory 222772 kb
Host smart-8401459c-de7b-4a5f-b529-39cb4c63df7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684140330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.1684140330
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.2943319084
Short name T75
Test name
Test status
Simulation time 399383844 ps
CPU time 4.2 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:23 PM PDT 24
Peak memory 218204 kb
Host smart-db24cb28-9ca8-40da-a1ec-027cd0bc4c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943319084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.2943319084
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.4146987590
Short name T103
Test name
Test status
Simulation time 321930862 ps
CPU time 7.04 seconds
Started Jul 17 07:06:13 PM PDT 24
Finished Jul 17 07:06:31 PM PDT 24
Peak memory 214252 kb
Host smart-9e468f31-02f2-4b4a-875f-88faa2d6c82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146987590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.4146987590
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.609773519
Short name T254
Test name
Test status
Simulation time 46013649 ps
CPU time 2.69 seconds
Started Jul 17 07:06:10 PM PDT 24
Finished Jul 17 07:06:20 PM PDT 24
Peak memory 209288 kb
Host smart-bd003dfc-b39b-42c1-9f25-b009b5f22085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609773519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.609773519
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.3755546093
Short name T664
Test name
Test status
Simulation time 1416401438 ps
CPU time 7.29 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:27 PM PDT 24
Peak memory 214384 kb
Host smart-6bd2c97f-2b84-4ce4-b9d9-4b6d7535b068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755546093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3755546093
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.3312489734
Short name T833
Test name
Test status
Simulation time 515524670 ps
CPU time 5.48 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:26 PM PDT 24
Peak memory 208604 kb
Host smart-d399a5eb-a69c-497c-963b-97f98edda455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312489734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.3312489734
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.832638800
Short name T573
Test name
Test status
Simulation time 140001188 ps
CPU time 2.76 seconds
Started Jul 17 07:06:10 PM PDT 24
Finished Jul 17 07:06:20 PM PDT 24
Peak memory 208624 kb
Host smart-b35b5a19-5cac-403e-9ed5-462f33d0634b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832638800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.832638800
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.649196424
Short name T326
Test name
Test status
Simulation time 136575765 ps
CPU time 2.67 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:23 PM PDT 24
Peak memory 208884 kb
Host smart-952b2796-2617-41ea-a83b-62e9aa1d2c9c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649196424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.649196424
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.1872476468
Short name T661
Test name
Test status
Simulation time 281177257 ps
CPU time 4.65 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:24 PM PDT 24
Peak memory 208732 kb
Host smart-15a0e2d8-9a12-4223-ae4d-ca32f5717690
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872476468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.1872476468
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.2794761960
Short name T223
Test name
Test status
Simulation time 2330274757 ps
CPU time 14.71 seconds
Started Jul 17 07:06:14 PM PDT 24
Finished Jul 17 07:06:40 PM PDT 24
Peak memory 209480 kb
Host smart-686ec485-d797-4635-a479-b86982d6cd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794761960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2794761960
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.3486044955
Short name T541
Test name
Test status
Simulation time 176288574 ps
CPU time 2.24 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:22 PM PDT 24
Peak memory 206948 kb
Host smart-c11223fd-b38f-43f6-9fad-44bf1c55145f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486044955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.3486044955
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.1071388805
Short name T197
Test name
Test status
Simulation time 61547438 ps
CPU time 3.57 seconds
Started Jul 17 07:06:13 PM PDT 24
Finished Jul 17 07:06:27 PM PDT 24
Peak memory 207324 kb
Host smart-5d37d37f-72b8-4c89-8190-fd1b482d62b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071388805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.1071388805
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.739607964
Short name T523
Test name
Test status
Simulation time 51487320 ps
CPU time 2.65 seconds
Started Jul 17 07:06:14 PM PDT 24
Finished Jul 17 07:06:28 PM PDT 24
Peak memory 209796 kb
Host smart-09ecb82f-1a14-4e16-ad20-77da2f193460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739607964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.739607964
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.1847710265
Short name T668
Test name
Test status
Simulation time 27626681 ps
CPU time 0.8 seconds
Started Jul 17 07:07:50 PM PDT 24
Finished Jul 17 07:07:54 PM PDT 24
Peak memory 205952 kb
Host smart-fd93e0cd-9e90-455b-8483-33ffbb75ca8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847710265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1847710265
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.1244025835
Short name T5
Test name
Test status
Simulation time 51081673 ps
CPU time 2.81 seconds
Started Jul 17 07:07:48 PM PDT 24
Finished Jul 17 07:07:52 PM PDT 24
Peak memory 207688 kb
Host smart-ac7de8c4-1f6a-4ac6-beec-272bd37de24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244025835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1244025835
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.991336477
Short name T654
Test name
Test status
Simulation time 231086903 ps
CPU time 3.22 seconds
Started Jul 17 07:07:48 PM PDT 24
Finished Jul 17 07:07:52 PM PDT 24
Peak memory 210180 kb
Host smart-2940516e-72b1-44c9-9c3c-fb835d5c17df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991336477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.991336477
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.1961728884
Short name T233
Test name
Test status
Simulation time 897539150 ps
CPU time 8.79 seconds
Started Jul 17 07:07:48 PM PDT 24
Finished Jul 17 07:07:57 PM PDT 24
Peak memory 214308 kb
Host smart-9f1f07d0-fe4a-4655-a5d0-cbb3d4e419ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961728884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.1961728884
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_random.838991631
Short name T678
Test name
Test status
Simulation time 293338116 ps
CPU time 5.09 seconds
Started Jul 17 07:07:48 PM PDT 24
Finished Jul 17 07:07:54 PM PDT 24
Peak memory 207644 kb
Host smart-c434765d-dd4e-4d9b-9f90-4612e7de4595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838991631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.838991631
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.3470508213
Short name T461
Test name
Test status
Simulation time 191981624 ps
CPU time 4.17 seconds
Started Jul 17 07:06:13 PM PDT 24
Finished Jul 17 07:06:28 PM PDT 24
Peak memory 208832 kb
Host smart-7e41dcf3-ae0b-462e-9256-0248ba7deb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470508213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.3470508213
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.1965712561
Short name T632
Test name
Test status
Simulation time 104585799 ps
CPU time 2.58 seconds
Started Jul 17 07:07:50 PM PDT 24
Finished Jul 17 07:08:00 PM PDT 24
Peak memory 206816 kb
Host smart-17601e6b-b439-4347-ae53-870dde35b7cc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965712561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.1965712561
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.2994091277
Short name T560
Test name
Test status
Simulation time 1228752995 ps
CPU time 5.05 seconds
Started Jul 17 07:07:48 PM PDT 24
Finished Jul 17 07:07:54 PM PDT 24
Peak memory 208396 kb
Host smart-2681c704-c3f9-4ddd-a60e-f7882350aba2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994091277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.2994091277
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.1612024209
Short name T887
Test name
Test status
Simulation time 122935172 ps
CPU time 4.68 seconds
Started Jul 17 07:07:50 PM PDT 24
Finished Jul 17 07:08:01 PM PDT 24
Peak memory 208548 kb
Host smart-ca18d44d-2b01-47b9-aa25-54b266b6d5a9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612024209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.1612024209
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2598342628
Short name T892
Test name
Test status
Simulation time 1116881044 ps
CPU time 3.04 seconds
Started Jul 17 07:07:49 PM PDT 24
Finished Jul 17 07:07:54 PM PDT 24
Peak memory 207916 kb
Host smart-eaacb868-f99c-40cd-aa52-e39d85af2b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598342628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2598342628
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.572782755
Short name T809
Test name
Test status
Simulation time 189400741 ps
CPU time 2.39 seconds
Started Jul 17 07:06:13 PM PDT 24
Finished Jul 17 07:06:27 PM PDT 24
Peak memory 206728 kb
Host smart-f3b7b37e-eb02-4238-9e04-e50e0a664be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572782755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.572782755
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.3860428332
Short name T784
Test name
Test status
Simulation time 2065742945 ps
CPU time 36.59 seconds
Started Jul 17 07:07:45 PM PDT 24
Finished Jul 17 07:08:22 PM PDT 24
Peak memory 221056 kb
Host smart-34ed2e6d-c1c4-4d68-bdf9-f694d6184e19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860428332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3860428332
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.4085001931
Short name T257
Test name
Test status
Simulation time 258233715 ps
CPU time 2.76 seconds
Started Jul 17 07:07:50 PM PDT 24
Finished Jul 17 07:07:56 PM PDT 24
Peak memory 214276 kb
Host smart-6c010142-e2ea-4749-a3ee-0e3058ef8197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085001931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.4085001931
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.501061971
Short name T48
Test name
Test status
Simulation time 39325284 ps
CPU time 1.44 seconds
Started Jul 17 07:07:49 PM PDT 24
Finished Jul 17 07:07:52 PM PDT 24
Peak memory 209676 kb
Host smart-d6cff80e-0807-4ca8-a0cf-91fbf8144c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501061971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.501061971
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.1656732612
Short name T636
Test name
Test status
Simulation time 27753534 ps
CPU time 0.81 seconds
Started Jul 17 07:07:52 PM PDT 24
Finished Jul 17 07:08:05 PM PDT 24
Peak memory 205940 kb
Host smart-cdc3ce63-5552-4276-9d3b-7512e1b28e66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656732612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.1656732612
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.773255150
Short name T574
Test name
Test status
Simulation time 122829572 ps
CPU time 5.16 seconds
Started Jul 17 07:07:52 PM PDT 24
Finished Jul 17 07:08:07 PM PDT 24
Peak memory 221920 kb
Host smart-180c338a-a031-424c-ae47-05dce4f5a666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773255150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.773255150
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.3519540265
Short name T455
Test name
Test status
Simulation time 70886438 ps
CPU time 1.57 seconds
Started Jul 17 07:07:48 PM PDT 24
Finished Jul 17 07:07:51 PM PDT 24
Peak memory 208204 kb
Host smart-b53cdae6-2cc9-4e8b-a95b-a74b87083dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519540265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3519540265
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.4090194804
Short name T898
Test name
Test status
Simulation time 86952037 ps
CPU time 1.95 seconds
Started Jul 17 07:07:48 PM PDT 24
Finished Jul 17 07:07:50 PM PDT 24
Peak memory 214336 kb
Host smart-6c597fcd-3cb5-4cda-aee1-be769fa4cc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090194804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.4090194804
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.2667981739
Short name T363
Test name
Test status
Simulation time 31360731 ps
CPU time 1.54 seconds
Started Jul 17 07:07:50 PM PDT 24
Finished Jul 17 07:07:57 PM PDT 24
Peak memory 214288 kb
Host smart-09438c3f-9e66-4fdf-9c29-ca5e05008c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667981739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2667981739
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.829372463
Short name T240
Test name
Test status
Simulation time 662013058 ps
CPU time 4.23 seconds
Started Jul 17 07:07:48 PM PDT 24
Finished Jul 17 07:07:53 PM PDT 24
Peak memory 216964 kb
Host smart-2be39af8-ddd0-467f-9db1-af2a5074e557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829372463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.829372463
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.1549812836
Short name T821
Test name
Test status
Simulation time 432246194 ps
CPU time 5.54 seconds
Started Jul 17 07:07:51 PM PDT 24
Finished Jul 17 07:08:06 PM PDT 24
Peak memory 208612 kb
Host smart-de94a527-5fb6-409e-a67e-254a89bfeb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549812836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.1549812836
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.3847684840
Short name T491
Test name
Test status
Simulation time 291448409 ps
CPU time 2.43 seconds
Started Jul 17 07:07:48 PM PDT 24
Finished Jul 17 07:07:51 PM PDT 24
Peak memory 206916 kb
Host smart-2cbd292b-6a45-4f09-8a28-db68d7cc5f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847684840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3847684840
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.813602787
Short name T293
Test name
Test status
Simulation time 103682185 ps
CPU time 3.12 seconds
Started Jul 17 07:13:51 PM PDT 24
Finished Jul 17 07:14:03 PM PDT 24
Peak memory 208688 kb
Host smart-3d52aa68-44cf-437a-a057-4aab5dd95807
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813602787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.813602787
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.3061207229
Short name T336
Test name
Test status
Simulation time 146645891 ps
CPU time 4.31 seconds
Started Jul 17 07:07:54 PM PDT 24
Finished Jul 17 07:08:13 PM PDT 24
Peak memory 206916 kb
Host smart-32ad0b55-95e4-452e-a962-271c260dee34
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061207229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.3061207229
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.668322877
Short name T39
Test name
Test status
Simulation time 64808490 ps
CPU time 3.02 seconds
Started Jul 17 07:07:51 PM PDT 24
Finished Jul 17 07:08:01 PM PDT 24
Peak memory 208804 kb
Host smart-f3824482-d202-471c-b0e6-bbd05c691266
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668322877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.668322877
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.3803777121
Short name T256
Test name
Test status
Simulation time 118039382 ps
CPU time 2.76 seconds
Started Jul 17 07:07:53 PM PDT 24
Finished Jul 17 07:08:10 PM PDT 24
Peak memory 209988 kb
Host smart-fe8130ee-f209-4218-ba00-59149e226674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803777121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3803777121
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.3026532689
Short name T86
Test name
Test status
Simulation time 63913216 ps
CPU time 2.26 seconds
Started Jul 17 07:07:49 PM PDT 24
Finished Jul 17 07:07:53 PM PDT 24
Peak memory 206764 kb
Host smart-508175ac-6076-4437-819f-a5ef74dd6788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026532689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.3026532689
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.2195123112
Short name T241
Test name
Test status
Simulation time 9220969399 ps
CPU time 43.74 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:56 PM PDT 24
Peak memory 222620 kb
Host smart-14889c64-f9c3-4ff5-9604-4ea8653c0c6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195123112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.2195123112
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.4143310530
Short name T80
Test name
Test status
Simulation time 581489082 ps
CPU time 5.49 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:19 PM PDT 24
Peak memory 218108 kb
Host smart-07d92ccd-8dc5-43b3-beb3-1cfe088c5c74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143310530 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.4143310530
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.4023513018
Short name T374
Test name
Test status
Simulation time 234373108 ps
CPU time 5.95 seconds
Started Jul 17 07:07:49 PM PDT 24
Finished Jul 17 07:07:56 PM PDT 24
Peak memory 209124 kb
Host smart-35ce1b54-0330-4cae-af62-9c7c30d47446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023513018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.4023513018
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.1735382248
Short name T881
Test name
Test status
Simulation time 127424241 ps
CPU time 3.35 seconds
Started Jul 17 07:07:50 PM PDT 24
Finished Jul 17 07:07:57 PM PDT 24
Peak memory 210388 kb
Host smart-03b60c39-8c62-4c42-a157-cf28a7d00dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735382248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1735382248
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.89179070
Short name T797
Test name
Test status
Simulation time 41595310 ps
CPU time 0.74 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:13 PM PDT 24
Peak memory 206000 kb
Host smart-bab9fd26-fc62-4184-abb1-23d6262e102f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89179070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.89179070
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.1467394180
Short name T902
Test name
Test status
Simulation time 155767840 ps
CPU time 3.78 seconds
Started Jul 17 07:07:58 PM PDT 24
Finished Jul 17 07:08:21 PM PDT 24
Peak memory 220500 kb
Host smart-f504a4dd-290d-49b2-87bb-d163150dbde7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467394180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1467394180
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2171471685
Short name T72
Test name
Test status
Simulation time 25764007 ps
CPU time 1.77 seconds
Started Jul 17 07:07:54 PM PDT 24
Finished Jul 17 07:08:10 PM PDT 24
Peak memory 207956 kb
Host smart-a25716d9-8af0-4885-81df-cd24e7c8c919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171471685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2171471685
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.218920863
Short name T658
Test name
Test status
Simulation time 122207439 ps
CPU time 2.32 seconds
Started Jul 17 07:07:54 PM PDT 24
Finished Jul 17 07:08:11 PM PDT 24
Peak memory 214328 kb
Host smart-60598c6d-82b6-4d0c-8fd2-d6ae75aab5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218920863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.218920863
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.3595544360
Short name T57
Test name
Test status
Simulation time 37245758 ps
CPU time 2.58 seconds
Started Jul 17 07:07:54 PM PDT 24
Finished Jul 17 07:08:11 PM PDT 24
Peak memory 214416 kb
Host smart-aa81e30d-ccd7-4b12-b8a7-81e41ae0880a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595544360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.3595544360
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.3346011090
Short name T512
Test name
Test status
Simulation time 506655651 ps
CPU time 3.1 seconds
Started Jul 17 07:07:56 PM PDT 24
Finished Jul 17 07:08:19 PM PDT 24
Peak memory 207440 kb
Host smart-e24770c5-56fa-4913-8676-3290dd5b16bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346011090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.3346011090
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.1572861150
Short name T699
Test name
Test status
Simulation time 818633741 ps
CPU time 24.79 seconds
Started Jul 17 07:07:53 PM PDT 24
Finished Jul 17 07:08:29 PM PDT 24
Peak memory 208808 kb
Host smart-bfba9c24-8253-4666-bc15-bf9fedf8db58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572861150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.1572861150
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.4187850752
Short name T497
Test name
Test status
Simulation time 35855017 ps
CPU time 2.42 seconds
Started Jul 17 07:07:56 PM PDT 24
Finished Jul 17 07:08:19 PM PDT 24
Peak memory 207752 kb
Host smart-854b9d54-9b96-48b6-aeee-2654a758e3e9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187850752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.4187850752
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.1758660092
Short name T730
Test name
Test status
Simulation time 179740504 ps
CPU time 5.78 seconds
Started Jul 17 07:07:52 PM PDT 24
Finished Jul 17 07:08:10 PM PDT 24
Peak memory 208484 kb
Host smart-0887eb1e-4d90-4e09-9b1b-22723744b561
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758660092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1758660092
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.1569019378
Short name T547
Test name
Test status
Simulation time 80976261 ps
CPU time 2.86 seconds
Started Jul 17 07:07:54 PM PDT 24
Finished Jul 17 07:08:11 PM PDT 24
Peak memory 207012 kb
Host smart-fa14f54e-b9e4-4130-acfa-b36d82774ca1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569019378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.1569019378
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.3342725924
Short name T384
Test name
Test status
Simulation time 567387117 ps
CPU time 12.8 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:26 PM PDT 24
Peak memory 209256 kb
Host smart-27696749-a4a9-4279-9d29-536648a09363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342725924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.3342725924
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.2116711789
Short name T424
Test name
Test status
Simulation time 78590134 ps
CPU time 3.42 seconds
Started Jul 17 07:07:54 PM PDT 24
Finished Jul 17 07:08:13 PM PDT 24
Peak memory 208996 kb
Host smart-97f7a4fd-44a3-4114-b13f-35e87f3f8f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116711789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.2116711789
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.2632171916
Short name T205
Test name
Test status
Simulation time 1519373267 ps
CPU time 54.09 seconds
Started Jul 17 07:07:53 PM PDT 24
Finished Jul 17 07:09:01 PM PDT 24
Peak memory 222496 kb
Host smart-e8b54878-369f-4c1b-81b8-182ad1af797a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632171916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.2632171916
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.890241179
Short name T415
Test name
Test status
Simulation time 3807206977 ps
CPU time 22.22 seconds
Started Jul 17 07:07:56 PM PDT 24
Finished Jul 17 07:08:38 PM PDT 24
Peak memory 222560 kb
Host smart-fe7a25dc-b259-476b-b75c-49aaf59b50d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890241179 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.890241179
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.2836323283
Short name T767
Test name
Test status
Simulation time 753080535 ps
CPU time 7.82 seconds
Started Jul 17 07:07:53 PM PDT 24
Finished Jul 17 07:08:14 PM PDT 24
Peak memory 209628 kb
Host smart-b2d2a811-bc13-414a-ba24-9abccf176ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836323283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.2836323283
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.3717268640
Short name T857
Test name
Test status
Simulation time 39928515 ps
CPU time 1.33 seconds
Started Jul 17 07:07:58 PM PDT 24
Finished Jul 17 07:08:19 PM PDT 24
Peak memory 210352 kb
Host smart-dc61510a-ac85-4696-ba24-d72eb937bcf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717268640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.3717268640
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.463701899
Short name T468
Test name
Test status
Simulation time 10001242 ps
CPU time 0.71 seconds
Started Jul 17 07:07:51 PM PDT 24
Finished Jul 17 07:07:59 PM PDT 24
Peak memory 206000 kb
Host smart-55402aed-00a2-482e-8276-237a38267560
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463701899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.463701899
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.2928816917
Short name T808
Test name
Test status
Simulation time 45889700 ps
CPU time 3.13 seconds
Started Jul 17 07:08:06 PM PDT 24
Finished Jul 17 07:08:33 PM PDT 24
Peak memory 214496 kb
Host smart-aba8249c-1073-4010-a091-9f2ce854ff50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2928816917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.2928816917
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.2910166970
Short name T610
Test name
Test status
Simulation time 202489788 ps
CPU time 5.32 seconds
Started Jul 17 07:08:06 PM PDT 24
Finished Jul 17 07:08:35 PM PDT 24
Peak memory 209548 kb
Host smart-5ef0b7c2-ec0d-4792-a92f-371484d96dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910166970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2910166970
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.3177518194
Short name T693
Test name
Test status
Simulation time 99994776 ps
CPU time 4.68 seconds
Started Jul 17 07:08:04 PM PDT 24
Finished Jul 17 07:08:31 PM PDT 24
Peak memory 213624 kb
Host smart-0ce2d8d6-8111-41a5-bfff-8989d3bf1f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177518194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.3177518194
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.142885329
Short name T284
Test name
Test status
Simulation time 80418169 ps
CPU time 2.93 seconds
Started Jul 17 07:08:06 PM PDT 24
Finished Jul 17 07:08:32 PM PDT 24
Peak memory 214144 kb
Host smart-e0566c26-66a4-4aad-8c4b-93981636ebc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142885329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.142885329
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.1751685957
Short name T621
Test name
Test status
Simulation time 88747094 ps
CPU time 1.81 seconds
Started Jul 17 07:08:03 PM PDT 24
Finished Jul 17 07:08:28 PM PDT 24
Peak memory 216220 kb
Host smart-e249d4a6-fda8-4bbf-9978-bdbabed94f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751685957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.1751685957
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.2178086699
Short name T705
Test name
Test status
Simulation time 800765510 ps
CPU time 6.28 seconds
Started Jul 17 07:07:59 PM PDT 24
Finished Jul 17 07:08:26 PM PDT 24
Peak memory 218224 kb
Host smart-39a23b88-f72d-454b-bdab-a9b1585af3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178086699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.2178086699
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.52286417
Short name T362
Test name
Test status
Simulation time 401420396 ps
CPU time 4.56 seconds
Started Jul 17 07:07:57 PM PDT 24
Finished Jul 17 07:08:22 PM PDT 24
Peak memory 208364 kb
Host smart-48e594c3-224b-417a-a1f1-64f0712e5fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52286417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.52286417
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.517164050
Short name T506
Test name
Test status
Simulation time 268067223 ps
CPU time 4 seconds
Started Jul 17 07:08:07 PM PDT 24
Finished Jul 17 07:08:34 PM PDT 24
Peak memory 208020 kb
Host smart-0d9b3d2a-9f96-411e-8a3a-3df38fd14f85
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517164050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.517164050
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.826213276
Short name T3
Test name
Test status
Simulation time 90266258 ps
CPU time 3.28 seconds
Started Jul 17 07:08:07 PM PDT 24
Finished Jul 17 07:08:33 PM PDT 24
Peak memory 206904 kb
Host smart-10db15f5-6ea7-4523-88e4-161996ace59d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826213276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.826213276
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.1804189841
Short name T308
Test name
Test status
Simulation time 826928910 ps
CPU time 9.34 seconds
Started Jul 17 07:08:08 PM PDT 24
Finished Jul 17 07:08:39 PM PDT 24
Peak memory 209080 kb
Host smart-22437a7c-1175-4b95-9299-9e24434cb9a9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804189841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.1804189841
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.4281410279
Short name T582
Test name
Test status
Simulation time 65109096 ps
CPU time 2.57 seconds
Started Jul 17 07:08:07 PM PDT 24
Finished Jul 17 07:08:32 PM PDT 24
Peak memory 209292 kb
Host smart-455be735-9e52-41d1-b658-01177c47df28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281410279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.4281410279
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.1596033453
Short name T779
Test name
Test status
Simulation time 69044734 ps
CPU time 1.72 seconds
Started Jul 17 07:07:57 PM PDT 24
Finished Jul 17 07:08:19 PM PDT 24
Peak memory 206084 kb
Host smart-36bb4466-9fe0-4c07-a7fc-1ffb838b1d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596033453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1596033453
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.236883633
Short name T207
Test name
Test status
Simulation time 814004699 ps
CPU time 7.84 seconds
Started Jul 17 07:08:04 PM PDT 24
Finished Jul 17 07:08:34 PM PDT 24
Peak memory 218216 kb
Host smart-d008b3f9-ebe3-47e3-994c-b3fd9124e248
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236883633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.236883633
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.4134072256
Short name T605
Test name
Test status
Simulation time 40047713 ps
CPU time 2.58 seconds
Started Jul 17 07:08:07 PM PDT 24
Finished Jul 17 07:08:32 PM PDT 24
Peak memory 218240 kb
Host smart-92ee5df4-3932-4105-93d0-dfd58655561f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134072256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.4134072256
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.3194002466
Short name T855
Test name
Test status
Simulation time 1298487535 ps
CPU time 22.89 seconds
Started Jul 17 07:08:06 PM PDT 24
Finished Jul 17 07:08:52 PM PDT 24
Peak memory 210268 kb
Host smart-906d6679-751f-42b4-a265-767e99bda123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194002466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3194002466
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.462225815
Short name T823
Test name
Test status
Simulation time 16631929 ps
CPU time 0.81 seconds
Started Jul 17 07:05:30 PM PDT 24
Finished Jul 17 07:05:35 PM PDT 24
Peak memory 205952 kb
Host smart-2eeee8e5-d9b7-474c-b638-94f6921e4b98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462225815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.462225815
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.2253741099
Short name T36
Test name
Test status
Simulation time 1562560182 ps
CPU time 3.81 seconds
Started Jul 17 07:05:28 PM PDT 24
Finished Jul 17 07:05:35 PM PDT 24
Peak memory 219800 kb
Host smart-3e6ca8f6-30a7-4293-ae7e-1cec2f5c5828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253741099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.2253741099
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.455581904
Short name T896
Test name
Test status
Simulation time 547591034 ps
CPU time 3.42 seconds
Started Jul 17 07:05:29 PM PDT 24
Finished Jul 17 07:05:35 PM PDT 24
Peak memory 209016 kb
Host smart-e6c85759-d685-40d7-ac13-f3a9a7b9be33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455581904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.455581904
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.3539737749
Short name T820
Test name
Test status
Simulation time 171755593 ps
CPU time 2.39 seconds
Started Jul 17 07:05:27 PM PDT 24
Finished Jul 17 07:05:31 PM PDT 24
Peak memory 214452 kb
Host smart-e7a2b080-0456-45e4-a4e3-fb2f20cf9a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539737749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.3539737749
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.3871862146
Short name T344
Test name
Test status
Simulation time 581851256 ps
CPU time 4.59 seconds
Started Jul 17 07:05:29 PM PDT 24
Finished Jul 17 07:05:36 PM PDT 24
Peak memory 214276 kb
Host smart-0be848cc-e2ad-4472-88b6-69bb08c59c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871862146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.3871862146
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.2032521897
Short name T548
Test name
Test status
Simulation time 275981878 ps
CPU time 5.09 seconds
Started Jul 17 07:05:26 PM PDT 24
Finished Jul 17 07:05:31 PM PDT 24
Peak memory 209704 kb
Host smart-54492ea0-e39f-4882-9718-2b0ce84ba526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032521897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.2032521897
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.1608271551
Short name T789
Test name
Test status
Simulation time 12519513772 ps
CPU time 38.49 seconds
Started Jul 17 07:05:28 PM PDT 24
Finished Jul 17 07:06:09 PM PDT 24
Peak memory 222484 kb
Host smart-6500f50f-6519-4391-9f80-b851d69fe546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608271551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.1608271551
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.3804698235
Short name T12
Test name
Test status
Simulation time 1465355568 ps
CPU time 7.38 seconds
Started Jul 17 07:05:30 PM PDT 24
Finished Jul 17 07:05:41 PM PDT 24
Peak memory 233548 kb
Host smart-5d1e4221-1920-4add-9a03-8e90b04bf48e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804698235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.3804698235
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.3706144833
Short name T910
Test name
Test status
Simulation time 44840866 ps
CPU time 2.24 seconds
Started Jul 17 07:05:26 PM PDT 24
Finished Jul 17 07:05:29 PM PDT 24
Peak memory 207224 kb
Host smart-c0c8284a-e123-463f-9bcd-76a9749dbdf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706144833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3706144833
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.1871637554
Short name T629
Test name
Test status
Simulation time 26955961 ps
CPU time 2.2 seconds
Started Jul 17 07:05:31 PM PDT 24
Finished Jul 17 07:05:37 PM PDT 24
Peak memory 208528 kb
Host smart-5d5f4841-f618-4e12-b38d-8607e4e12c27
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871637554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1871637554
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.403507971
Short name T690
Test name
Test status
Simulation time 306959253 ps
CPU time 3.97 seconds
Started Jul 17 07:05:26 PM PDT 24
Finished Jul 17 07:05:31 PM PDT 24
Peak memory 208896 kb
Host smart-6bd1847a-4b8a-4425-b02f-1dffc193e6d9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403507971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.403507971
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.2286746653
Short name T507
Test name
Test status
Simulation time 83761769 ps
CPU time 1.95 seconds
Started Jul 17 07:05:29 PM PDT 24
Finished Jul 17 07:05:35 PM PDT 24
Peak memory 207604 kb
Host smart-c4df6962-f0ff-46d8-bbc7-88084bad75c0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286746653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.2286746653
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.2623019003
Short name T472
Test name
Test status
Simulation time 1825970300 ps
CPU time 16.98 seconds
Started Jul 17 07:05:26 PM PDT 24
Finished Jul 17 07:05:44 PM PDT 24
Peak memory 209636 kb
Host smart-5e22825d-748a-4b2b-bbc4-255463bb68f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623019003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.2623019003
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.699254612
Short name T854
Test name
Test status
Simulation time 297153335 ps
CPU time 6.99 seconds
Started Jul 17 07:05:30 PM PDT 24
Finished Jul 17 07:05:41 PM PDT 24
Peak memory 208436 kb
Host smart-93ad240a-9454-4080-a499-9d802c1a79a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699254612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.699254612
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.2729581764
Short name T76
Test name
Test status
Simulation time 914888352 ps
CPU time 35.53 seconds
Started Jul 17 07:05:30 PM PDT 24
Finished Jul 17 07:06:09 PM PDT 24
Peak memory 220700 kb
Host smart-82244703-e6b0-445b-9d28-a342aeec751e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729581764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.2729581764
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.1097449401
Short name T867
Test name
Test status
Simulation time 1590877422 ps
CPU time 16.21 seconds
Started Jul 17 07:05:30 PM PDT 24
Finished Jul 17 07:05:50 PM PDT 24
Peak memory 220396 kb
Host smart-55c5609c-6a87-44f9-ad94-b197a770d06e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097449401 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.1097449401
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.3638181423
Short name T313
Test name
Test status
Simulation time 154057749 ps
CPU time 4.62 seconds
Started Jul 17 07:05:27 PM PDT 24
Finished Jul 17 07:05:33 PM PDT 24
Peak memory 207780 kb
Host smart-fcfbc092-ae17-47e8-b914-16b2dfeadd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638181423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.3638181423
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.2736597203
Short name T785
Test name
Test status
Simulation time 109941715 ps
CPU time 0.91 seconds
Started Jul 17 07:07:54 PM PDT 24
Finished Jul 17 07:08:11 PM PDT 24
Peak memory 206188 kb
Host smart-5f72e073-2181-4d3f-be1b-d79de9ac6483
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736597203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.2736597203
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.3538914589
Short name T406
Test name
Test status
Simulation time 934135064 ps
CPU time 6.84 seconds
Started Jul 17 07:07:51 PM PDT 24
Finished Jul 17 07:08:06 PM PDT 24
Peak memory 214332 kb
Host smart-44b36c99-7562-4b9b-89c1-e76826d84039
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3538914589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.3538914589
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.3743101026
Short name T900
Test name
Test status
Simulation time 128769945 ps
CPU time 1.67 seconds
Started Jul 17 07:07:51 PM PDT 24
Finished Jul 17 07:08:03 PM PDT 24
Peak memory 207224 kb
Host smart-a01ea1b1-8861-4c5c-b3fc-755a240f9346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743101026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3743101026
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.520342
Short name T751
Test name
Test status
Simulation time 352598074 ps
CPU time 10.67 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:23 PM PDT 24
Peak memory 221544 kb
Host smart-332f1c57-a7ff-4183-a1ad-0a13ce563c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.520342
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.3993041230
Short name T517
Test name
Test status
Simulation time 140690050 ps
CPU time 2.44 seconds
Started Jul 17 07:07:56 PM PDT 24
Finished Jul 17 07:08:20 PM PDT 24
Peak memory 214264 kb
Host smart-f1b68660-f4e1-4d50-8781-9a0e73df26fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993041230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.3993041230
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.4203445465
Short name T245
Test name
Test status
Simulation time 74468872 ps
CPU time 3.5 seconds
Started Jul 17 07:07:53 PM PDT 24
Finished Jul 17 07:08:10 PM PDT 24
Peak memory 209252 kb
Host smart-cbf6e967-4f54-4005-bf72-da41bd65ac08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203445465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.4203445465
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.1435774505
Short name T720
Test name
Test status
Simulation time 110831056 ps
CPU time 2.22 seconds
Started Jul 17 07:07:51 PM PDT 24
Finished Jul 17 07:08:02 PM PDT 24
Peak memory 207472 kb
Host smart-b3944585-9a66-4836-9349-678a6a762720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435774505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1435774505
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.650932935
Short name T864
Test name
Test status
Simulation time 765766554 ps
CPU time 17.94 seconds
Started Jul 17 07:07:49 PM PDT 24
Finished Jul 17 07:08:08 PM PDT 24
Peak memory 208308 kb
Host smart-9fd2e897-cb32-4bc6-810c-970c3e46548f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650932935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.650932935
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.1155984605
Short name T503
Test name
Test status
Simulation time 1098470718 ps
CPU time 7.29 seconds
Started Jul 17 07:07:51 PM PDT 24
Finished Jul 17 07:08:06 PM PDT 24
Peak memory 208520 kb
Host smart-adb82d34-64fb-43bc-a765-0c3140addb4f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155984605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1155984605
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.2457536492
Short name T540
Test name
Test status
Simulation time 38923929 ps
CPU time 1.85 seconds
Started Jul 17 07:07:50 PM PDT 24
Finished Jul 17 07:07:58 PM PDT 24
Peak memory 207960 kb
Host smart-bfb38f45-6f06-400c-95ba-90253f3ff813
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457536492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.2457536492
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.1957270590
Short name T710
Test name
Test status
Simulation time 2595390824 ps
CPU time 14.46 seconds
Started Jul 17 07:07:48 PM PDT 24
Finished Jul 17 07:08:04 PM PDT 24
Peak memory 209132 kb
Host smart-9ad1c6c3-4006-4744-a587-2ed88f1d55b8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957270590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.1957270590
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.3596297673
Short name T642
Test name
Test status
Simulation time 26701099 ps
CPU time 1.94 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:15 PM PDT 24
Peak memory 214432 kb
Host smart-cc1b7394-ef88-4129-ba01-e37b400de8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596297673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3596297673
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.2797229746
Short name T446
Test name
Test status
Simulation time 128998623 ps
CPU time 1.6 seconds
Started Jul 17 07:07:48 PM PDT 24
Finished Jul 17 07:07:51 PM PDT 24
Peak memory 206732 kb
Host smart-fb1d1837-6234-4bff-a68b-ae2ca7f3ca6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797229746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.2797229746
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.1828797874
Short name T249
Test name
Test status
Simulation time 16501049612 ps
CPU time 202.07 seconds
Started Jul 17 07:07:54 PM PDT 24
Finished Jul 17 07:11:32 PM PDT 24
Peak memory 222636 kb
Host smart-be2dd448-49df-4a36-a677-77788e7ad032
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828797874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.1828797874
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.3516193019
Short name T473
Test name
Test status
Simulation time 578930612 ps
CPU time 17.94 seconds
Started Jul 17 07:07:53 PM PDT 24
Finished Jul 17 07:08:25 PM PDT 24
Peak memory 209228 kb
Host smart-4f6ab8a6-d6bf-42df-96fa-ae42c91f57e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516193019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.3516193019
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.2590967736
Short name T401
Test name
Test status
Simulation time 184110745 ps
CPU time 2.62 seconds
Started Jul 17 07:07:53 PM PDT 24
Finished Jul 17 07:08:08 PM PDT 24
Peak memory 210416 kb
Host smart-55007493-b294-475b-95a6-04be819db27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590967736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.2590967736
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.2227595443
Short name T545
Test name
Test status
Simulation time 19498015 ps
CPU time 0.81 seconds
Started Jul 17 07:07:56 PM PDT 24
Finished Jul 17 07:08:18 PM PDT 24
Peak memory 205948 kb
Host smart-9b9ffbd5-970f-4564-a02f-dcba28870311
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227595443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.2227595443
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.966276533
Short name T865
Test name
Test status
Simulation time 52356731 ps
CPU time 2.49 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:15 PM PDT 24
Peak memory 214360 kb
Host smart-6062bca7-7cdf-4bfb-9133-91d32208328c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=966276533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.966276533
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1518810621
Short name T702
Test name
Test status
Simulation time 3141874858 ps
CPU time 24.2 seconds
Started Jul 17 07:07:54 PM PDT 24
Finished Jul 17 07:08:34 PM PDT 24
Peak memory 219948 kb
Host smart-3769d380-aa36-4fa7-96fb-530d18fe29ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518810621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1518810621
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2887900491
Short name T894
Test name
Test status
Simulation time 143610667 ps
CPU time 4.11 seconds
Started Jul 17 07:07:57 PM PDT 24
Finished Jul 17 07:08:22 PM PDT 24
Peak memory 214508 kb
Host smart-bad29689-315d-489c-a5c2-bac854446bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887900491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2887900491
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.2758736760
Short name T262
Test name
Test status
Simulation time 52132424 ps
CPU time 2.12 seconds
Started Jul 17 07:07:57 PM PDT 24
Finished Jul 17 07:08:20 PM PDT 24
Peak memory 214348 kb
Host smart-76f7e750-ef0c-46a2-ad5e-6a650e14c64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758736760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.2758736760
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_random.4280184607
Short name T791
Test name
Test status
Simulation time 65043372 ps
CPU time 3.4 seconds
Started Jul 17 07:07:56 PM PDT 24
Finished Jul 17 07:08:20 PM PDT 24
Peak memory 209044 kb
Host smart-7a62a14d-1e75-4b14-b496-949815611537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280184607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.4280184607
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.1279130104
Short name T810
Test name
Test status
Simulation time 120425361 ps
CPU time 4.41 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:17 PM PDT 24
Peak memory 206920 kb
Host smart-a1c7c97b-aca6-4838-af65-141c54de8800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279130104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.1279130104
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.2420682371
Short name T532
Test name
Test status
Simulation time 305032029 ps
CPU time 3.52 seconds
Started Jul 17 07:07:56 PM PDT 24
Finished Jul 17 07:08:20 PM PDT 24
Peak memory 208736 kb
Host smart-cfff1502-79db-4ce4-959b-b4ee758b2941
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420682371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.2420682371
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.2028273002
Short name T559
Test name
Test status
Simulation time 46801995 ps
CPU time 2.31 seconds
Started Jul 17 07:07:54 PM PDT 24
Finished Jul 17 07:08:12 PM PDT 24
Peak memory 208140 kb
Host smart-b916f28c-bd08-4854-aae0-42d3f67ec23d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028273002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2028273002
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.2085918739
Short name T387
Test name
Test status
Simulation time 86577832 ps
CPU time 3.13 seconds
Started Jul 17 07:07:54 PM PDT 24
Finished Jul 17 07:08:12 PM PDT 24
Peak memory 206992 kb
Host smart-a8337f2e-e840-4f02-a23d-cf0b2bcd22c1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085918739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.2085918739
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.805066819
Short name T441
Test name
Test status
Simulation time 1409363366 ps
CPU time 10.94 seconds
Started Jul 17 07:08:06 PM PDT 24
Finished Jul 17 07:08:40 PM PDT 24
Peak memory 214332 kb
Host smart-eab0c63d-7bf0-4d1d-8837-73082bdc2a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805066819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.805066819
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.3337009377
Short name T213
Test name
Test status
Simulation time 34328105 ps
CPU time 1.95 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:15 PM PDT 24
Peak memory 208944 kb
Host smart-8bbf84a3-d3f4-4b86-b431-96da54d90ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337009377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3337009377
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.961374350
Short name T132
Test name
Test status
Simulation time 664769988 ps
CPU time 7.9 seconds
Started Jul 17 07:08:06 PM PDT 24
Finished Jul 17 07:08:37 PM PDT 24
Peak memory 222684 kb
Host smart-06409c57-dfb3-42d6-ac9c-46f1a6b26910
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961374350 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.961374350
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.4042999698
Short name T886
Test name
Test status
Simulation time 31563921 ps
CPU time 2.24 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:15 PM PDT 24
Peak memory 208108 kb
Host smart-132ae512-8dbe-4879-bfbc-374d52821480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042999698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.4042999698
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.3627514473
Short name T470
Test name
Test status
Simulation time 25978872 ps
CPU time 0.79 seconds
Started Jul 17 07:07:50 PM PDT 24
Finished Jul 17 07:07:57 PM PDT 24
Peak memory 206020 kb
Host smart-579428b4-c730-4118-9f39-0633e3ac1fdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627514473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3627514473
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.311317121
Short name T426
Test name
Test status
Simulation time 56882876 ps
CPU time 3.64 seconds
Started Jul 17 07:07:59 PM PDT 24
Finished Jul 17 07:08:26 PM PDT 24
Peak memory 214560 kb
Host smart-48ddb478-8377-4ee5-986f-93aa28cc9032
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=311317121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.311317121
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.3979326547
Short name T116
Test name
Test status
Simulation time 102060719 ps
CPU time 4.26 seconds
Started Jul 17 07:07:51 PM PDT 24
Finished Jul 17 07:08:05 PM PDT 24
Peak memory 209000 kb
Host smart-6e09cc03-b127-4309-b246-fb68a4dff811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979326547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.3979326547
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.1923854264
Short name T891
Test name
Test status
Simulation time 291434238 ps
CPU time 2.54 seconds
Started Jul 17 07:07:56 PM PDT 24
Finished Jul 17 07:08:19 PM PDT 24
Peak memory 208052 kb
Host smart-986b3a7f-45dc-4086-a1bf-417dce82a807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923854264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.1923854264
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.1734994081
Short name T379
Test name
Test status
Simulation time 29989693 ps
CPU time 2.43 seconds
Started Jul 17 07:08:03 PM PDT 24
Finished Jul 17 07:08:28 PM PDT 24
Peak memory 214332 kb
Host smart-ab8898e4-0bc6-4898-8068-48472fac1add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734994081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.1734994081
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.1663455532
Short name T323
Test name
Test status
Simulation time 44307828 ps
CPU time 2.55 seconds
Started Jul 17 07:08:06 PM PDT 24
Finished Jul 17 07:08:32 PM PDT 24
Peak memory 214204 kb
Host smart-d81ab1eb-8830-4e92-96a2-215260688554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663455532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.1663455532
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.1864591273
Short name T381
Test name
Test status
Simulation time 346238545 ps
CPU time 4.28 seconds
Started Jul 17 07:08:08 PM PDT 24
Finished Jul 17 07:08:34 PM PDT 24
Peak memory 222468 kb
Host smart-69d01308-8c18-48ee-8a99-ae98232bc1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864591273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.1864591273
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.2109930698
Short name T743
Test name
Test status
Simulation time 535639030 ps
CPU time 4.09 seconds
Started Jul 17 07:07:59 PM PDT 24
Finished Jul 17 07:08:24 PM PDT 24
Peak memory 218532 kb
Host smart-7b29f564-059f-4a91-9a4b-429e3ab71009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109930698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.2109930698
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.3733224092
Short name T453
Test name
Test status
Simulation time 134164388 ps
CPU time 3.5 seconds
Started Jul 17 07:08:06 PM PDT 24
Finished Jul 17 07:08:33 PM PDT 24
Peak memory 206772 kb
Host smart-c0f53fc1-b16e-4205-a8f8-e953c463d962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733224092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.3733224092
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.1476126376
Short name T490
Test name
Test status
Simulation time 210851910 ps
CPU time 2.49 seconds
Started Jul 17 07:08:07 PM PDT 24
Finished Jul 17 07:08:33 PM PDT 24
Peak memory 207112 kb
Host smart-b7741833-6137-440f-b8f6-680f2460353b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476126376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1476126376
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.4139995894
Short name T450
Test name
Test status
Simulation time 120921937 ps
CPU time 3.04 seconds
Started Jul 17 07:07:59 PM PDT 24
Finished Jul 17 07:08:23 PM PDT 24
Peak memory 206984 kb
Host smart-21b9de1d-d467-47fe-b4e8-7b9416b20538
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139995894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.4139995894
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.885435591
Short name T569
Test name
Test status
Simulation time 57907884 ps
CPU time 3.07 seconds
Started Jul 17 07:07:59 PM PDT 24
Finished Jul 17 07:08:23 PM PDT 24
Peak memory 208784 kb
Host smart-b71bdd71-aa84-4ae3-a25b-dcca1eaff30b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885435591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.885435591
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.1476150473
Short name T431
Test name
Test status
Simulation time 171163863 ps
CPU time 2.22 seconds
Started Jul 17 07:07:49 PM PDT 24
Finished Jul 17 07:07:53 PM PDT 24
Peak memory 209112 kb
Host smart-fe048e3c-33d6-4a3a-9c9b-e80c6242212a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476150473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.1476150473
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.250231253
Short name T742
Test name
Test status
Simulation time 4049471944 ps
CPU time 22.35 seconds
Started Jul 17 07:07:57 PM PDT 24
Finished Jul 17 07:08:40 PM PDT 24
Peak memory 208692 kb
Host smart-3caa2a0d-8ce8-42f6-9455-05206e019248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250231253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.250231253
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.4040571016
Short name T265
Test name
Test status
Simulation time 310088177 ps
CPU time 15.06 seconds
Started Jul 17 07:07:51 PM PDT 24
Finished Jul 17 07:08:14 PM PDT 24
Peak memory 214472 kb
Host smart-9a0cb8df-3573-406d-b35f-6af2f9f2e35d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040571016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.4040571016
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.2804351977
Short name T732
Test name
Test status
Simulation time 176971001 ps
CPU time 4.26 seconds
Started Jul 17 07:07:59 PM PDT 24
Finished Jul 17 07:08:24 PM PDT 24
Peak memory 208588 kb
Host smart-c095a353-6466-4750-9279-bf60004704b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804351977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.2804351977
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.4225024890
Short name T400
Test name
Test status
Simulation time 42635843 ps
CPU time 2.49 seconds
Started Jul 17 07:07:50 PM PDT 24
Finished Jul 17 07:07:58 PM PDT 24
Peak memory 214392 kb
Host smart-b983399e-7358-450a-9e39-1691724f5d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225024890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.4225024890
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.3798107350
Short name T614
Test name
Test status
Simulation time 12699572 ps
CPU time 0.86 seconds
Started Jul 17 07:07:57 PM PDT 24
Finished Jul 17 07:08:18 PM PDT 24
Peak memory 205948 kb
Host smart-c03484ee-52c9-4934-b3cd-b4a4af18d0f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798107350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.3798107350
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.375843630
Short name T37
Test name
Test status
Simulation time 111245621 ps
CPU time 4.77 seconds
Started Jul 17 07:07:54 PM PDT 24
Finished Jul 17 07:08:13 PM PDT 24
Peak memory 210184 kb
Host smart-a338a933-1c74-4e6b-a811-614d1db17647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375843630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.375843630
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.2596509030
Short name T74
Test name
Test status
Simulation time 167381106 ps
CPU time 4.22 seconds
Started Jul 17 07:07:56 PM PDT 24
Finished Jul 17 07:08:20 PM PDT 24
Peak memory 219016 kb
Host smart-21e7318e-850f-4f5a-944f-c097f1bbc4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596509030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2596509030
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.1735026934
Short name T364
Test name
Test status
Simulation time 248604086 ps
CPU time 2.6 seconds
Started Jul 17 07:07:52 PM PDT 24
Finished Jul 17 07:08:06 PM PDT 24
Peak memory 214244 kb
Host smart-1a7cfc36-ece7-4c4f-8149-7f801c3ea18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735026934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1735026934
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.4259570424
Short name T622
Test name
Test status
Simulation time 612407688 ps
CPU time 7.46 seconds
Started Jul 17 07:07:57 PM PDT 24
Finished Jul 17 07:08:25 PM PDT 24
Peak memory 214416 kb
Host smart-ec36b70b-d3c7-41b7-bd44-0d6af1e56f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259570424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.4259570424
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.2279211551
Short name T877
Test name
Test status
Simulation time 463656542 ps
CPU time 11.63 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:27 PM PDT 24
Peak memory 210076 kb
Host smart-ea9a427e-ca6c-4791-be5b-bb4228d2f9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279211551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.2279211551
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.532615130
Short name T502
Test name
Test status
Simulation time 837578348 ps
CPU time 3.39 seconds
Started Jul 17 07:07:50 PM PDT 24
Finished Jul 17 07:07:59 PM PDT 24
Peak memory 208592 kb
Host smart-fa2adf19-d1cf-40b2-9234-e2c0e9e1c2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532615130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.532615130
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.102376677
Short name T889
Test name
Test status
Simulation time 451473648 ps
CPU time 12.14 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:28 PM PDT 24
Peak memory 208244 kb
Host smart-268aa986-c5a7-4607-a577-96d51de7a457
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102376677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.102376677
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.1850884623
Short name T617
Test name
Test status
Simulation time 1517302266 ps
CPU time 21.24 seconds
Started Jul 17 07:07:51 PM PDT 24
Finished Jul 17 07:08:21 PM PDT 24
Peak memory 208408 kb
Host smart-5bcf45f8-633b-4c26-8e95-e18b718936d2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850884623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.1850884623
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3526212269
Short name T457
Test name
Test status
Simulation time 1476669361 ps
CPU time 36.23 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:49 PM PDT 24
Peak memory 208352 kb
Host smart-6bd236a5-f67e-4c17-a74f-df8756f50de1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526212269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3526212269
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.659244651
Short name T862
Test name
Test status
Simulation time 199268028 ps
CPU time 2.95 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:15 PM PDT 24
Peak memory 214388 kb
Host smart-06c613b8-01c8-40c1-aaf5-d174710a62df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659244651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.659244651
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.2603666984
Short name T117
Test name
Test status
Simulation time 650653533 ps
CPU time 12.25 seconds
Started Jul 17 07:07:50 PM PDT 24
Finished Jul 17 07:08:10 PM PDT 24
Peak memory 208488 kb
Host smart-adeeb7a0-59c7-438e-a9e1-afe64a75e8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603666984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.2603666984
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.3290524990
Short name T761
Test name
Test status
Simulation time 233613316 ps
CPU time 6.75 seconds
Started Jul 17 07:07:57 PM PDT 24
Finished Jul 17 07:08:25 PM PDT 24
Peak memory 209036 kb
Host smart-1bada6a8-fd1a-4712-ae24-a6439adddc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290524990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.3290524990
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.1715136562
Short name T659
Test name
Test status
Simulation time 175305017 ps
CPU time 3.67 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:19 PM PDT 24
Peak memory 211132 kb
Host smart-0369e454-25e5-4710-9ccd-abe51d04893a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715136562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.1715136562
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.112617544
Short name T652
Test name
Test status
Simulation time 86493055 ps
CPU time 0.98 seconds
Started Jul 17 07:08:06 PM PDT 24
Finished Jul 17 07:08:30 PM PDT 24
Peak memory 206040 kb
Host smart-780f3376-4a95-4f82-9647-e9ef68ebc89c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112617544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.112617544
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.729800096
Short name T812
Test name
Test status
Simulation time 190887625 ps
CPU time 5.67 seconds
Started Jul 17 07:07:59 PM PDT 24
Finished Jul 17 07:08:26 PM PDT 24
Peak memory 215552 kb
Host smart-d4164f21-2ffc-4f20-ae3f-d63e2dec32b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=729800096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.729800096
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.3136409020
Short name T16
Test name
Test status
Simulation time 129206686 ps
CPU time 2.66 seconds
Started Jul 17 07:07:59 PM PDT 24
Finished Jul 17 07:08:25 PM PDT 24
Peak memory 209356 kb
Host smart-d0177787-271f-422a-b8a1-d7d2b53cf90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136409020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.3136409020
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.1009627074
Short name T201
Test name
Test status
Simulation time 76628147 ps
CPU time 2.26 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:15 PM PDT 24
Peak memory 208272 kb
Host smart-163fdb86-d1a3-4ea3-a90f-4140d8f8b794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009627074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.1009627074
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.3611595914
Short name T736
Test name
Test status
Simulation time 1005666937 ps
CPU time 24.84 seconds
Started Jul 17 07:07:58 PM PDT 24
Finished Jul 17 07:08:44 PM PDT 24
Peak memory 210172 kb
Host smart-3a186e1a-0403-4356-ba8d-71b52adb148d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611595914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.3611595914
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.1390855159
Short name T448
Test name
Test status
Simulation time 162383533 ps
CPU time 2.45 seconds
Started Jul 17 07:07:57 PM PDT 24
Finished Jul 17 07:08:20 PM PDT 24
Peak memory 208436 kb
Host smart-2711d494-3e35-4cc2-b343-dc443270bae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390855159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.1390855159
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.1233637545
Short name T291
Test name
Test status
Simulation time 34737161 ps
CPU time 2.46 seconds
Started Jul 17 07:07:58 PM PDT 24
Finished Jul 17 07:08:21 PM PDT 24
Peak memory 208368 kb
Host smart-1f1c8243-a983-4ea7-96a2-f218d8180c6c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233637545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.1233637545
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.4270102362
Short name T449
Test name
Test status
Simulation time 1482703003 ps
CPU time 20.77 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:34 PM PDT 24
Peak memory 208648 kb
Host smart-93583c8a-0cd4-4043-aa78-c4de83c14c2b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270102362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.4270102362
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.3164987528
Short name T861
Test name
Test status
Simulation time 826360981 ps
CPU time 6.7 seconds
Started Jul 17 07:07:56 PM PDT 24
Finished Jul 17 07:08:24 PM PDT 24
Peak memory 208696 kb
Host smart-1ae12afd-fd7a-4c29-908a-e111ffb98cc0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164987528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.3164987528
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.2257540920
Short name T847
Test name
Test status
Simulation time 930896923 ps
CPU time 2.28 seconds
Started Jul 17 07:08:07 PM PDT 24
Finished Jul 17 07:08:32 PM PDT 24
Peak memory 209456 kb
Host smart-b511751c-5af7-4695-a2ac-d8e91265ac25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257540920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.2257540920
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.1278037399
Short name T782
Test name
Test status
Simulation time 142457828 ps
CPU time 2.5 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:15 PM PDT 24
Peak memory 206744 kb
Host smart-7447b544-d40a-41ed-84b4-3b3c24071ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278037399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.1278037399
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.2030076326
Short name T493
Test name
Test status
Simulation time 357228864 ps
CPU time 5.56 seconds
Started Jul 17 07:08:06 PM PDT 24
Finished Jul 17 07:08:35 PM PDT 24
Peak memory 207644 kb
Host smart-83916a75-ea3d-4627-a885-91703b753229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030076326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.2030076326
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.399519815
Short name T139
Test name
Test status
Simulation time 213425467 ps
CPU time 2.36 seconds
Started Jul 17 07:08:07 PM PDT 24
Finished Jul 17 07:08:32 PM PDT 24
Peak memory 210256 kb
Host smart-87e2e7dc-cffa-4ce3-b7ad-fee706471b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399519815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.399519815
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.895340551
Short name T518
Test name
Test status
Simulation time 135408034 ps
CPU time 0.75 seconds
Started Jul 17 07:07:51 PM PDT 24
Finished Jul 17 07:08:02 PM PDT 24
Peak memory 205904 kb
Host smart-f1e61056-97f6-4115-96f8-c91b438088c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895340551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.895340551
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.3999933095
Short name T347
Test name
Test status
Simulation time 358221462 ps
CPU time 4.13 seconds
Started Jul 17 07:08:03 PM PDT 24
Finished Jul 17 07:08:30 PM PDT 24
Peak memory 222548 kb
Host smart-bf232b95-c47c-426e-84af-ccc6d1814881
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3999933095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.3999933095
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.310658644
Short name T35
Test name
Test status
Simulation time 593444780 ps
CPU time 4.35 seconds
Started Jul 17 07:07:50 PM PDT 24
Finished Jul 17 07:08:02 PM PDT 24
Peak memory 210224 kb
Host smart-d5126633-4386-4dca-aa7d-8cf3655901bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310658644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.310658644
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.3538294213
Short name T641
Test name
Test status
Simulation time 110514188 ps
CPU time 3.36 seconds
Started Jul 17 07:08:04 PM PDT 24
Finished Jul 17 07:08:30 PM PDT 24
Peak memory 207768 kb
Host smart-1eb45ef2-7cb3-4d40-9f85-9b4ec7ffad7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538294213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3538294213
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.1357698108
Short name T776
Test name
Test status
Simulation time 219575762 ps
CPU time 5.31 seconds
Started Jul 17 07:07:50 PM PDT 24
Finished Jul 17 07:08:02 PM PDT 24
Peak memory 209480 kb
Host smart-5c7445e8-9c2e-4927-8a20-14d29bdb322c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357698108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.1357698108
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_random.755403858
Short name T413
Test name
Test status
Simulation time 85707341 ps
CPU time 3.67 seconds
Started Jul 17 07:08:06 PM PDT 24
Finished Jul 17 07:08:33 PM PDT 24
Peak memory 208716 kb
Host smart-b8ced23d-559c-49da-9b34-ec76e0a6129e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755403858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.755403858
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.2933757850
Short name T711
Test name
Test status
Simulation time 187009957 ps
CPU time 4.54 seconds
Started Jul 17 07:08:00 PM PDT 24
Finished Jul 17 07:08:25 PM PDT 24
Peak memory 208044 kb
Host smart-679824df-41f3-46e8-ab7d-9df5d4c62eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933757850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.2933757850
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.850127977
Short name T91
Test name
Test status
Simulation time 1961546577 ps
CPU time 4.06 seconds
Started Jul 17 07:08:03 PM PDT 24
Finished Jul 17 07:08:30 PM PDT 24
Peak memory 206972 kb
Host smart-f2ebaba7-0e17-4944-afe3-9d676fe6bd5a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850127977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.850127977
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.670152162
Short name T637
Test name
Test status
Simulation time 715385222 ps
CPU time 17.64 seconds
Started Jul 17 07:08:02 PM PDT 24
Finished Jul 17 07:08:42 PM PDT 24
Peak memory 208784 kb
Host smart-9e599048-7886-4eb9-baea-3191291fce80
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670152162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.670152162
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.4029533714
Short name T271
Test name
Test status
Simulation time 471803031 ps
CPU time 2.56 seconds
Started Jul 17 07:08:06 PM PDT 24
Finished Jul 17 07:08:32 PM PDT 24
Peak memory 207588 kb
Host smart-2a9a15aa-a8b0-4829-b0fa-5bb94824f88d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029533714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.4029533714
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.4112088156
Short name T41
Test name
Test status
Simulation time 79678495 ps
CPU time 3.95 seconds
Started Jul 17 07:07:51 PM PDT 24
Finished Jul 17 07:08:05 PM PDT 24
Peak memory 215316 kb
Host smart-9078710e-b188-4561-9924-3e5d99f09615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112088156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.4112088156
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.3126680244
Short name T766
Test name
Test status
Simulation time 231459949 ps
CPU time 2.55 seconds
Started Jul 17 07:08:00 PM PDT 24
Finished Jul 17 07:08:25 PM PDT 24
Peak memory 208240 kb
Host smart-25fb5c9a-2ad7-45bb-9cfe-1544c57b31fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126680244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.3126680244
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.3101850336
Short name T836
Test name
Test status
Simulation time 2607314515 ps
CPU time 26.94 seconds
Started Jul 17 07:07:52 PM PDT 24
Finished Jul 17 07:08:29 PM PDT 24
Peak memory 214412 kb
Host smart-979aad40-18c9-4736-b8cf-304ad34717fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101850336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.3101850336
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.3636321652
Short name T875
Test name
Test status
Simulation time 223072848 ps
CPU time 2.87 seconds
Started Jul 17 07:07:50 PM PDT 24
Finished Jul 17 07:07:59 PM PDT 24
Peak memory 209836 kb
Host smart-5aadc09b-04c8-4983-9db8-7f9d06811d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636321652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.3636321652
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.471911758
Short name T597
Test name
Test status
Simulation time 26556651 ps
CPU time 0.75 seconds
Started Jul 17 07:08:01 PM PDT 24
Finished Jul 17 07:08:24 PM PDT 24
Peak memory 206004 kb
Host smart-83c25d24-097a-4183-846b-aa3e4a875aa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471911758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.471911758
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.3695269777
Short name T20
Test name
Test status
Simulation time 51659674 ps
CPU time 2.4 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:15 PM PDT 24
Peak memory 216184 kb
Host smart-db967ac7-b488-48d9-aecd-f6c5dc71ace5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695269777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.3695269777
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.1913737765
Short name T519
Test name
Test status
Simulation time 90871225 ps
CPU time 1.6 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:17 PM PDT 24
Peak memory 208136 kb
Host smart-d3d8bd29-8403-4964-8d76-a5064d064730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913737765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.1913737765
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.55470466
Short name T342
Test name
Test status
Simulation time 62663664 ps
CPU time 3.46 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:19 PM PDT 24
Peak memory 221952 kb
Host smart-d273d00e-abe8-4b6b-91e9-bb2010c3dbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55470466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.55470466
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.1345835892
Short name T729
Test name
Test status
Simulation time 135798779 ps
CPU time 2.07 seconds
Started Jul 17 07:07:54 PM PDT 24
Finished Jul 17 07:08:12 PM PDT 24
Peak memory 215388 kb
Host smart-4b01c0bd-b398-4672-9a1d-93a1dc9ea030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345835892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.1345835892
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.4291012590
Short name T683
Test name
Test status
Simulation time 179523679 ps
CPU time 4.13 seconds
Started Jul 17 07:07:54 PM PDT 24
Finished Jul 17 07:08:14 PM PDT 24
Peak memory 207020 kb
Host smart-924ed125-69e1-4d09-b86e-43caac0de383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291012590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.4291012590
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.2572859192
Short name T420
Test name
Test status
Simulation time 185049814 ps
CPU time 2.3 seconds
Started Jul 17 07:07:54 PM PDT 24
Finished Jul 17 07:08:11 PM PDT 24
Peak memory 207412 kb
Host smart-f26d5d91-ffd9-4ea8-bd83-de1175c89957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572859192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.2572859192
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.1879325446
Short name T856
Test name
Test status
Simulation time 126356352 ps
CPU time 3.88 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:16 PM PDT 24
Peak memory 208696 kb
Host smart-450f1259-07c8-469c-9e92-5080cdb94dbc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879325446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.1879325446
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.1741780764
Short name T851
Test name
Test status
Simulation time 219592285 ps
CPU time 4.81 seconds
Started Jul 17 07:07:53 PM PDT 24
Finished Jul 17 07:08:11 PM PDT 24
Peak memory 207972 kb
Host smart-3d91fbe3-dffe-436c-a285-632c8ef02c59
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741780764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.1741780764
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.2575212366
Short name T811
Test name
Test status
Simulation time 114800645 ps
CPU time 3.01 seconds
Started Jul 17 07:07:56 PM PDT 24
Finished Jul 17 07:08:18 PM PDT 24
Peak memory 207180 kb
Host smart-2abf3dcc-209d-4480-b961-0a9c9c1b4cd4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575212366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.2575212366
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.3313458941
Short name T583
Test name
Test status
Simulation time 121841653 ps
CPU time 2.24 seconds
Started Jul 17 07:07:59 PM PDT 24
Finished Jul 17 07:08:23 PM PDT 24
Peak memory 218312 kb
Host smart-ca46a433-02bf-450a-ab90-46a5b49eea00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313458941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.3313458941
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.1662571427
Short name T526
Test name
Test status
Simulation time 3116665804 ps
CPU time 23.01 seconds
Started Jul 17 07:07:54 PM PDT 24
Finished Jul 17 07:08:31 PM PDT 24
Peak memory 208052 kb
Host smart-6e29d961-6c58-4312-8fe8-686d378b34cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662571427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.1662571427
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.4068292074
Short name T244
Test name
Test status
Simulation time 11370883324 ps
CPU time 31.49 seconds
Started Jul 17 07:08:00 PM PDT 24
Finished Jul 17 07:08:54 PM PDT 24
Peak memory 208212 kb
Host smart-fb437a50-fdb6-4c6c-8356-ce5ddb4ccbf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068292074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.4068292074
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.3578372608
Short name T133
Test name
Test status
Simulation time 195299963 ps
CPU time 8.98 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:25 PM PDT 24
Peak memory 220060 kb
Host smart-c27259b6-aef8-4b60-a9c2-84c4ccec941b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578372608 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.3578372608
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.460047045
Short name T704
Test name
Test status
Simulation time 245334228 ps
CPU time 2.61 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:15 PM PDT 24
Peak memory 208148 kb
Host smart-109592b9-fcea-4a27-b3f1-29be227d1715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460047045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.460047045
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.3469043351
Short name T696
Test name
Test status
Simulation time 64378145 ps
CPU time 1.92 seconds
Started Jul 17 07:08:00 PM PDT 24
Finished Jul 17 07:08:22 PM PDT 24
Peak memory 210024 kb
Host smart-3fce9f7d-7a0f-4434-90bc-8e93e409e039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469043351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.3469043351
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.3608579620
Short name T733
Test name
Test status
Simulation time 66283947 ps
CPU time 0.88 seconds
Started Jul 17 07:08:07 PM PDT 24
Finished Jul 17 07:08:30 PM PDT 24
Peak memory 206012 kb
Host smart-ce8b6c2e-9ec0-43b1-b46d-8489f6aa6d15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608579620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3608579620
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.829897060
Short name T286
Test name
Test status
Simulation time 700400961 ps
CPU time 5.64 seconds
Started Jul 17 07:07:59 PM PDT 24
Finished Jul 17 07:08:26 PM PDT 24
Peak memory 214340 kb
Host smart-4ef71b80-39c0-4170-bcf6-5552ed382580
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=829897060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.829897060
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.3514914863
Short name T416
Test name
Test status
Simulation time 111828231 ps
CPU time 2.53 seconds
Started Jul 17 07:08:06 PM PDT 24
Finished Jul 17 07:08:31 PM PDT 24
Peak memory 210124 kb
Host smart-bc6c7617-ac7d-49d4-b622-afd4631f822c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514914863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3514914863
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.1350094818
Short name T232
Test name
Test status
Simulation time 650487479 ps
CPU time 7.34 seconds
Started Jul 17 07:07:59 PM PDT 24
Finished Jul 17 07:08:28 PM PDT 24
Peak memory 219312 kb
Host smart-e02ee20b-d129-48c8-a81b-383ac47ec60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350094818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1350094818
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.1776189770
Short name T281
Test name
Test status
Simulation time 259759812 ps
CPU time 3.11 seconds
Started Jul 17 07:08:08 PM PDT 24
Finished Jul 17 07:08:33 PM PDT 24
Peak memory 222440 kb
Host smart-a70bbecf-1f51-4025-aa23-c3b86ae90011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776189770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.1776189770
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.381531765
Short name T871
Test name
Test status
Simulation time 90837397 ps
CPU time 3.14 seconds
Started Jul 17 07:08:05 PM PDT 24
Finished Jul 17 07:08:32 PM PDT 24
Peak memory 222316 kb
Host smart-6dcccc53-551f-4b45-a95e-a6cb5a81f86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381531765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.381531765
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.789146586
Short name T434
Test name
Test status
Simulation time 681881956 ps
CPU time 4.12 seconds
Started Jul 17 07:08:07 PM PDT 24
Finished Jul 17 07:08:34 PM PDT 24
Peak memory 207644 kb
Host smart-2dda7e80-4298-47b6-83d4-d08936473d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789146586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.789146586
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.465455444
Short name T826
Test name
Test status
Simulation time 95319847 ps
CPU time 2.97 seconds
Started Jul 17 07:08:05 PM PDT 24
Finished Jul 17 07:08:30 PM PDT 24
Peak memory 208160 kb
Host smart-893f07b9-d6ed-474f-b6e8-d580528938d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465455444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.465455444
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.357958986
Short name T520
Test name
Test status
Simulation time 67974183 ps
CPU time 1.81 seconds
Started Jul 17 07:08:07 PM PDT 24
Finished Jul 17 07:08:31 PM PDT 24
Peak memory 206992 kb
Host smart-1a2fd18d-2e3a-401d-a6b6-66e9aaf7d722
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357958986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.357958986
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.1180252732
Short name T716
Test name
Test status
Simulation time 49568847 ps
CPU time 2.65 seconds
Started Jul 17 07:07:59 PM PDT 24
Finished Jul 17 07:08:23 PM PDT 24
Peak memory 208612 kb
Host smart-b1a8b3d5-64e1-4e76-8abb-49563d30e3ed
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180252732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.1180252732
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.3851440810
Short name T230
Test name
Test status
Simulation time 92331346 ps
CPU time 3.34 seconds
Started Jul 17 07:08:07 PM PDT 24
Finished Jul 17 07:08:33 PM PDT 24
Peak memory 218312 kb
Host smart-e4c8a09f-0590-4ad0-be14-aa7317eda6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851440810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3851440810
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.3580979555
Short name T648
Test name
Test status
Simulation time 3341518210 ps
CPU time 26.51 seconds
Started Jul 17 07:07:56 PM PDT 24
Finished Jul 17 07:08:43 PM PDT 24
Peak memory 208292 kb
Host smart-f9866c71-2a55-415d-8317-c1089b9c152e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580979555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.3580979555
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.108898253
Short name T334
Test name
Test status
Simulation time 843066453 ps
CPU time 16.01 seconds
Started Jul 17 07:08:03 PM PDT 24
Finished Jul 17 07:08:41 PM PDT 24
Peak memory 216532 kb
Host smart-66a81a96-e0d9-41bf-b12c-f2d4f91efa76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108898253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.108898253
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.3378137605
Short name T137
Test name
Test status
Simulation time 170477504 ps
CPU time 9.81 seconds
Started Jul 17 07:08:03 PM PDT 24
Finished Jul 17 07:08:36 PM PDT 24
Peak memory 222632 kb
Host smart-7ee66d39-b00f-479b-8cc4-79033ef50c6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378137605 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.3378137605
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.3509690119
Short name T277
Test name
Test status
Simulation time 2214584646 ps
CPU time 56.63 seconds
Started Jul 17 07:08:06 PM PDT 24
Finished Jul 17 07:09:26 PM PDT 24
Peak memory 222268 kb
Host smart-0f909f00-4b66-4e76-bc83-46687ff2166f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509690119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.3509690119
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.2988488656
Short name T735
Test name
Test status
Simulation time 1178976048 ps
CPU time 10.33 seconds
Started Jul 17 07:08:03 PM PDT 24
Finished Jul 17 07:08:36 PM PDT 24
Peak memory 210548 kb
Host smart-a54bd313-baab-43b7-a8ae-f92c14a02110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988488656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.2988488656
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.1933616162
Short name T746
Test name
Test status
Simulation time 29203261 ps
CPU time 0.9 seconds
Started Jul 17 07:07:53 PM PDT 24
Finished Jul 17 07:08:09 PM PDT 24
Peak memory 206140 kb
Host smart-9f73e0e5-daf2-4298-ac3f-ef2ffaf33b01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933616162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.1933616162
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.1143022459
Short name T802
Test name
Test status
Simulation time 53647974 ps
CPU time 2.61 seconds
Started Jul 17 07:07:48 PM PDT 24
Finished Jul 17 07:07:52 PM PDT 24
Peak memory 209256 kb
Host smart-1c8fbc04-dea3-4625-bdc1-f7bd63d2275d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143022459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1143022459
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.1561378305
Short name T304
Test name
Test status
Simulation time 285388444 ps
CPU time 6.72 seconds
Started Jul 17 07:07:51 PM PDT 24
Finished Jul 17 07:08:08 PM PDT 24
Peak memory 222432 kb
Host smart-4430fbc7-9599-47c0-903f-c895b10ef4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561378305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.1561378305
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.4132857999
Short name T51
Test name
Test status
Simulation time 59358814 ps
CPU time 2.08 seconds
Started Jul 17 07:07:51 PM PDT 24
Finished Jul 17 07:08:03 PM PDT 24
Peak memory 214340 kb
Host smart-387470db-d04a-442e-a404-eefb06f2f06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132857999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.4132857999
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.465829889
Short name T749
Test name
Test status
Simulation time 855537309 ps
CPU time 5.16 seconds
Started Jul 17 07:07:51 PM PDT 24
Finished Jul 17 07:08:05 PM PDT 24
Peak memory 209888 kb
Host smart-0e179966-f0de-4b1e-8ef3-a9944d0042e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465829889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.465829889
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.352982796
Short name T357
Test name
Test status
Simulation time 177264357 ps
CPU time 4.45 seconds
Started Jul 17 07:08:02 PM PDT 24
Finished Jul 17 07:08:29 PM PDT 24
Peak memory 208464 kb
Host smart-0fae80a1-bd39-4355-a566-db9a474bf73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352982796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.352982796
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.3238977710
Short name T645
Test name
Test status
Simulation time 24689087 ps
CPU time 1.93 seconds
Started Jul 17 07:08:03 PM PDT 24
Finished Jul 17 07:08:28 PM PDT 24
Peak memory 207208 kb
Host smart-00669d49-87a6-44d5-b467-0bc625532315
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238977710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3238977710
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.837708669
Short name T481
Test name
Test status
Simulation time 56043304 ps
CPU time 3.1 seconds
Started Jul 17 07:08:02 PM PDT 24
Finished Jul 17 07:08:28 PM PDT 24
Peak memory 207040 kb
Host smart-6771abba-b1b3-4465-aa0c-f8d66ab01ad4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837708669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.837708669
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.1015823998
Short name T897
Test name
Test status
Simulation time 34563227 ps
CPU time 2.29 seconds
Started Jul 17 07:07:50 PM PDT 24
Finished Jul 17 07:07:57 PM PDT 24
Peak memory 206884 kb
Host smart-24f129ab-53c7-4efd-bdfe-287d9b6693e1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015823998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.1015823998
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.826947688
Short name T418
Test name
Test status
Simulation time 71148375 ps
CPU time 1.9 seconds
Started Jul 17 07:07:49 PM PDT 24
Finished Jul 17 07:07:54 PM PDT 24
Peak memory 215828 kb
Host smart-583bf238-aad9-413a-be8a-8d26f0dc2326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826947688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.826947688
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.1184114358
Short name T695
Test name
Test status
Simulation time 512644364 ps
CPU time 3.7 seconds
Started Jul 17 07:08:03 PM PDT 24
Finished Jul 17 07:08:30 PM PDT 24
Peak memory 206996 kb
Host smart-93bb8b1c-17f2-468c-b65d-71f93b7300fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184114358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.1184114358
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.1506743510
Short name T279
Test name
Test status
Simulation time 1534814474 ps
CPU time 10.76 seconds
Started Jul 17 07:07:54 PM PDT 24
Finished Jul 17 07:08:21 PM PDT 24
Peak memory 216936 kb
Host smart-6b6411f6-66d4-44fa-8ba5-e181a5351e10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506743510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.1506743510
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.1277953165
Short name T599
Test name
Test status
Simulation time 85643124 ps
CPU time 3.01 seconds
Started Jul 17 07:07:51 PM PDT 24
Finished Jul 17 07:08:05 PM PDT 24
Peak memory 208368 kb
Host smart-98962e85-e8cd-4eb6-ad4b-8a77b39e36a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277953165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1277953165
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.2720669617
Short name T397
Test name
Test status
Simulation time 55641346 ps
CPU time 1.48 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:17 PM PDT 24
Peak memory 209628 kb
Host smart-ea445797-b505-4ee3-b8c0-b3665f103dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720669617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.2720669617
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.2318968729
Short name T444
Test name
Test status
Simulation time 18346525 ps
CPU time 0.83 seconds
Started Jul 17 07:08:01 PM PDT 24
Finished Jul 17 07:08:24 PM PDT 24
Peak memory 206004 kb
Host smart-54888e52-e9af-4850-8acf-4b8db1d98a12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318968729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.2318968729
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.684564293
Short name T650
Test name
Test status
Simulation time 113341858 ps
CPU time 4.34 seconds
Started Jul 17 07:07:56 PM PDT 24
Finished Jul 17 07:08:19 PM PDT 24
Peak memory 218528 kb
Host smart-2f040558-42ee-4bdd-b751-6603adc5a1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684564293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.684564293
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.1652358190
Short name T456
Test name
Test status
Simulation time 104217952 ps
CPU time 1.6 seconds
Started Jul 17 07:07:54 PM PDT 24
Finished Jul 17 07:08:10 PM PDT 24
Peak memory 207452 kb
Host smart-56e3366f-9d52-407d-bcb8-726bcb287d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652358190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.1652358190
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.2748210239
Short name T302
Test name
Test status
Simulation time 201793330 ps
CPU time 4.8 seconds
Started Jul 17 07:07:53 PM PDT 24
Finished Jul 17 07:08:11 PM PDT 24
Peak memory 214364 kb
Host smart-7adb246c-69ed-425b-b284-3f28eb5a9a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748210239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.2748210239
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.142813622
Short name T321
Test name
Test status
Simulation time 74646949 ps
CPU time 2.48 seconds
Started Jul 17 07:07:57 PM PDT 24
Finished Jul 17 07:08:21 PM PDT 24
Peak memory 214996 kb
Host smart-2b7ae532-79f8-45e0-8d46-5b51f2f80cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142813622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.142813622
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.3932391249
Short name T757
Test name
Test status
Simulation time 199362902 ps
CPU time 4.85 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:17 PM PDT 24
Peak memory 222476 kb
Host smart-2aa74e74-6ac4-48ea-a4ea-3e0780e0f951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932391249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.3932391249
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.3628427385
Short name T333
Test name
Test status
Simulation time 59087141 ps
CPU time 2.74 seconds
Started Jul 17 07:07:56 PM PDT 24
Finished Jul 17 07:08:19 PM PDT 24
Peak memory 208216 kb
Host smart-a2ab25ca-6b8a-499b-944d-376e43d14c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628427385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.3628427385
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.4226130189
Short name T804
Test name
Test status
Simulation time 156583566 ps
CPU time 2.08 seconds
Started Jul 17 07:07:52 PM PDT 24
Finished Jul 17 07:08:05 PM PDT 24
Peak memory 206988 kb
Host smart-24b8be92-5190-4577-bf2b-a064da3d2daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226130189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.4226130189
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.401005216
Short name T639
Test name
Test status
Simulation time 73943454 ps
CPU time 1.76 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:17 PM PDT 24
Peak memory 207064 kb
Host smart-c749440c-6f62-42d7-b6df-c5dd0a3da39e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401005216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.401005216
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.3478512324
Short name T692
Test name
Test status
Simulation time 120764218 ps
CPU time 2.28 seconds
Started Jul 17 07:07:54 PM PDT 24
Finished Jul 17 07:08:12 PM PDT 24
Peak memory 206948 kb
Host smart-bfb0adb3-17ab-4828-9d2f-b64ac0ecb3ac
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478512324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3478512324
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.1081015911
Short name T770
Test name
Test status
Simulation time 730639871 ps
CPU time 8.68 seconds
Started Jul 17 07:07:54 PM PDT 24
Finished Jul 17 07:08:17 PM PDT 24
Peak memory 208964 kb
Host smart-5679d3b9-4ded-44c0-abed-2f493cba7e65
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081015911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1081015911
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.3778583515
Short name T644
Test name
Test status
Simulation time 590563371 ps
CPU time 3.8 seconds
Started Jul 17 07:07:54 PM PDT 24
Finished Jul 17 07:08:12 PM PDT 24
Peak memory 209752 kb
Host smart-55b294dd-2ec9-4413-9700-2fb395146bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778583515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.3778583515
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.3277307268
Short name T868
Test name
Test status
Simulation time 1080144633 ps
CPU time 18.36 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:30 PM PDT 24
Peak memory 208420 kb
Host smart-74f28082-e880-4c52-a8a0-2d76cca3c945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277307268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3277307268
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.3972050766
Short name T655
Test name
Test status
Simulation time 5601473157 ps
CPU time 55.16 seconds
Started Jul 17 07:07:59 PM PDT 24
Finished Jul 17 07:09:15 PM PDT 24
Peak memory 220836 kb
Host smart-be71c0f2-2c3c-4073-b52d-dd892ca38e84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972050766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.3972050766
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.1295284638
Short name T177
Test name
Test status
Simulation time 53933283 ps
CPU time 2.01 seconds
Started Jul 17 07:07:56 PM PDT 24
Finished Jul 17 07:08:18 PM PDT 24
Peak memory 210596 kb
Host smart-8a6654aa-3dc3-4234-91ef-bd905d0d0048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295284638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.1295284638
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2438482894
Short name T454
Test name
Test status
Simulation time 14060230 ps
CPU time 0.8 seconds
Started Jul 17 07:06:05 PM PDT 24
Finished Jul 17 07:06:08 PM PDT 24
Peak memory 206008 kb
Host smart-f0825a01-e293-4dad-9e14-9e0f9b314974
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438482894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2438482894
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.723873270
Short name T318
Test name
Test status
Simulation time 109532376 ps
CPU time 6.12 seconds
Started Jul 17 07:05:30 PM PDT 24
Finished Jul 17 07:05:41 PM PDT 24
Peak memory 222340 kb
Host smart-aa5a9068-8243-45c3-b054-20994910da09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=723873270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.723873270
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.3823850986
Short name T903
Test name
Test status
Simulation time 46588163 ps
CPU time 1.59 seconds
Started Jul 17 07:05:30 PM PDT 24
Finished Jul 17 07:05:36 PM PDT 24
Peak memory 208092 kb
Host smart-a7a2d146-f600-49e0-bfdb-e0446c43fa49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823850986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.3823850986
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.3899944215
Short name T524
Test name
Test status
Simulation time 389442281 ps
CPU time 3.8 seconds
Started Jul 17 07:05:31 PM PDT 24
Finished Jul 17 07:05:38 PM PDT 24
Peak memory 207572 kb
Host smart-be690089-cb06-45ee-a643-29c1a4d391a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899944215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.3899944215
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.3481074278
Short name T831
Test name
Test status
Simulation time 266476493 ps
CPU time 4 seconds
Started Jul 17 07:05:28 PM PDT 24
Finished Jul 17 07:05:36 PM PDT 24
Peak memory 214424 kb
Host smart-0369dbf4-d0f2-4171-a28b-5c1328fead1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481074278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3481074278
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.2148707969
Short name T1
Test name
Test status
Simulation time 164695767 ps
CPU time 2.09 seconds
Started Jul 17 07:05:28 PM PDT 24
Finished Jul 17 07:05:33 PM PDT 24
Peak memory 214256 kb
Host smart-7b978b25-ebf6-40f6-92ef-e668e93faaed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148707969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.2148707969
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.1623184940
Short name T392
Test name
Test status
Simulation time 3664893727 ps
CPU time 18.59 seconds
Started Jul 17 07:05:30 PM PDT 24
Finished Jul 17 07:05:52 PM PDT 24
Peak memory 210744 kb
Host smart-e4410060-4326-488c-997e-1361ad6bcd34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623184940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.1623184940
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.1736345432
Short name T432
Test name
Test status
Simulation time 28470701 ps
CPU time 2.22 seconds
Started Jul 17 07:05:31 PM PDT 24
Finished Jul 17 07:05:37 PM PDT 24
Peak memory 207624 kb
Host smart-08604a4b-5e18-42f7-9c08-8474d2a0ac25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736345432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.1736345432
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.2662769021
Short name T50
Test name
Test status
Simulation time 817919961 ps
CPU time 9.34 seconds
Started Jul 17 07:06:04 PM PDT 24
Finished Jul 17 07:06:14 PM PDT 24
Peak memory 230768 kb
Host smart-246510ae-ad49-4687-a6c4-417efd568b09
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662769021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.2662769021
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.4275064230
Short name T395
Test name
Test status
Simulation time 175156668 ps
CPU time 2.34 seconds
Started Jul 17 07:05:31 PM PDT 24
Finished Jul 17 07:05:37 PM PDT 24
Peak memory 206900 kb
Host smart-1ad8c419-4290-45a8-b4f2-c35b5b9ea577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275064230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.4275064230
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.2639359062
Short name T860
Test name
Test status
Simulation time 181612923 ps
CPU time 3.05 seconds
Started Jul 17 07:05:30 PM PDT 24
Finished Jul 17 07:05:37 PM PDT 24
Peak memory 207040 kb
Host smart-ddca576a-3619-4ae4-97af-39289145c2a3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639359062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.2639359062
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.1721571180
Short name T88
Test name
Test status
Simulation time 71406142 ps
CPU time 3.41 seconds
Started Jul 17 07:05:30 PM PDT 24
Finished Jul 17 07:05:37 PM PDT 24
Peak memory 207996 kb
Host smart-51b79046-3e6a-4a90-8351-8582b40f9aac
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721571180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1721571180
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.3291670056
Short name T602
Test name
Test status
Simulation time 853404097 ps
CPU time 4.77 seconds
Started Jul 17 07:05:30 PM PDT 24
Finished Jul 17 07:05:38 PM PDT 24
Peak memory 208404 kb
Host smart-9ed3f3cf-d4c5-43d4-bdf5-740cbce34057
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291670056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.3291670056
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.2106831503
Short name T915
Test name
Test status
Simulation time 1388481370 ps
CPU time 25.21 seconds
Started Jul 17 07:05:29 PM PDT 24
Finished Jul 17 07:05:58 PM PDT 24
Peak memory 209552 kb
Host smart-da91ce25-1164-45f0-86a9-434366a184c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106831503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.2106831503
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.1934836647
Short name T483
Test name
Test status
Simulation time 649880398 ps
CPU time 3.3 seconds
Started Jul 17 07:05:31 PM PDT 24
Finished Jul 17 07:05:38 PM PDT 24
Peak memory 208540 kb
Host smart-62581233-146d-461a-a430-5ca7c04be584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934836647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.1934836647
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.3792915140
Short name T734
Test name
Test status
Simulation time 542368119 ps
CPU time 20.14 seconds
Started Jul 17 07:06:06 PM PDT 24
Finished Jul 17 07:06:28 PM PDT 24
Peak memory 222528 kb
Host smart-3ea5390f-fd38-41c5-a326-f8306729f6af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792915140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.3792915140
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.357215202
Short name T135
Test name
Test status
Simulation time 501719067 ps
CPU time 7.86 seconds
Started Jul 17 07:06:07 PM PDT 24
Finished Jul 17 07:06:17 PM PDT 24
Peak memory 222592 kb
Host smart-62f5a876-3982-4849-b06c-dbd0c1745809
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357215202 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.357215202
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.2528145554
Short name T722
Test name
Test status
Simulation time 866693200 ps
CPU time 31.38 seconds
Started Jul 17 07:05:30 PM PDT 24
Finished Jul 17 07:06:05 PM PDT 24
Peak memory 209804 kb
Host smart-8c000040-783d-4894-98c6-4b7e1fe2700b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528145554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2528145554
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.1868900068
Short name T792
Test name
Test status
Simulation time 88411889 ps
CPU time 3.15 seconds
Started Jul 17 07:05:30 PM PDT 24
Finished Jul 17 07:05:37 PM PDT 24
Peak memory 210192 kb
Host smart-c8003565-28cb-45c3-ab5d-f667c8fd59c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868900068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1868900068
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.2600666414
Short name T443
Test name
Test status
Simulation time 20341103 ps
CPU time 0.84 seconds
Started Jul 17 07:08:06 PM PDT 24
Finished Jul 17 07:08:30 PM PDT 24
Peak memory 206004 kb
Host smart-87b94ffa-099a-48c0-899a-22d169c7e0b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600666414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.2600666414
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.2984896679
Short name T407
Test name
Test status
Simulation time 290051026 ps
CPU time 5.01 seconds
Started Jul 17 07:08:07 PM PDT 24
Finished Jul 17 07:08:35 PM PDT 24
Peak memory 215512 kb
Host smart-1bec7be4-f805-4dde-9aec-fcbd0d39598a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2984896679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.2984896679
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.3592353409
Short name T31
Test name
Test status
Simulation time 1675535141 ps
CPU time 38.46 seconds
Started Jul 17 07:08:01 PM PDT 24
Finished Jul 17 07:09:01 PM PDT 24
Peak memory 214776 kb
Host smart-5f233888-b2bb-415f-9b85-97afcc09a7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592353409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.3592353409
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.2871140275
Short name T848
Test name
Test status
Simulation time 400880147 ps
CPU time 3.95 seconds
Started Jul 17 07:08:07 PM PDT 24
Finished Jul 17 07:08:34 PM PDT 24
Peak memory 222472 kb
Host smart-924f0166-d8ed-4597-8d2a-4f1c8693b7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871140275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.2871140275
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.1124715647
Short name T99
Test name
Test status
Simulation time 264782971 ps
CPU time 2.71 seconds
Started Jul 17 07:07:59 PM PDT 24
Finished Jul 17 07:08:25 PM PDT 24
Peak memory 214324 kb
Host smart-0efbcdae-dfae-4a73-8563-1e306cfd053f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124715647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.1124715647
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.2104431638
Short name T890
Test name
Test status
Simulation time 96163128 ps
CPU time 3.02 seconds
Started Jul 17 07:08:05 PM PDT 24
Finished Jul 17 07:08:32 PM PDT 24
Peak memory 222216 kb
Host smart-61694f95-c89d-4790-843d-be06687274fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104431638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.2104431638
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.702030052
Short name T870
Test name
Test status
Simulation time 1252792703 ps
CPU time 2.65 seconds
Started Jul 17 07:08:06 PM PDT 24
Finished Jul 17 07:08:32 PM PDT 24
Peak memory 209384 kb
Host smart-4618982f-1802-4a29-aac1-de049f2ed2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702030052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.702030052
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.4149484421
Short name T222
Test name
Test status
Simulation time 454655888 ps
CPU time 4.91 seconds
Started Jul 17 07:08:06 PM PDT 24
Finished Jul 17 07:08:34 PM PDT 24
Peak memory 218424 kb
Host smart-51ab9ba0-5e5c-4fe3-82c7-b108dbd8d5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149484421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.4149484421
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.2142940258
Short name T417
Test name
Test status
Simulation time 2004195582 ps
CPU time 4.28 seconds
Started Jul 17 07:07:56 PM PDT 24
Finished Jul 17 07:08:20 PM PDT 24
Peak memory 208456 kb
Host smart-9483d713-6574-461d-b171-a564dc888111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142940258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.2142940258
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.746695053
Short name T771
Test name
Test status
Simulation time 39261775 ps
CPU time 1.76 seconds
Started Jul 17 07:08:02 PM PDT 24
Finished Jul 17 07:08:25 PM PDT 24
Peak memory 207028 kb
Host smart-79e8eca7-6efb-4348-a069-903bc78f032d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746695053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.746695053
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.4072814867
Short name T653
Test name
Test status
Simulation time 150154845 ps
CPU time 5.27 seconds
Started Jul 17 07:07:54 PM PDT 24
Finished Jul 17 07:08:14 PM PDT 24
Peak memory 206864 kb
Host smart-a0a4f11b-d912-4a8b-b0cc-e9ddd67dc974
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072814867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.4072814867
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2920709881
Short name T423
Test name
Test status
Simulation time 827269822 ps
CPU time 20.39 seconds
Started Jul 17 07:08:01 PM PDT 24
Finished Jul 17 07:08:44 PM PDT 24
Peak memory 207832 kb
Host smart-901dacc4-afd9-408f-825e-07ee2a3d5d45
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920709881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2920709881
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.3866837567
Short name T753
Test name
Test status
Simulation time 111054705 ps
CPU time 2.73 seconds
Started Jul 17 07:08:00 PM PDT 24
Finished Jul 17 07:08:25 PM PDT 24
Peak memory 214380 kb
Host smart-4134fd91-c132-43a6-a163-c5f68b008386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866837567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3866837567
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.3143321993
Short name T462
Test name
Test status
Simulation time 1394665815 ps
CPU time 4.86 seconds
Started Jul 17 07:08:06 PM PDT 24
Finished Jul 17 07:08:34 PM PDT 24
Peak memory 208224 kb
Host smart-bcf56d5c-4553-49a8-818a-d60600cc8e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143321993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.3143321993
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.1963875335
Short name T238
Test name
Test status
Simulation time 882799882 ps
CPU time 7.25 seconds
Started Jul 17 07:08:03 PM PDT 24
Finished Jul 17 07:08:34 PM PDT 24
Peak memory 214344 kb
Host smart-f461eccd-d532-42a5-a610-14b984f2e0eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963875335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.1963875335
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.2137521583
Short name T71
Test name
Test status
Simulation time 5356359136 ps
CPU time 15.77 seconds
Started Jul 17 07:07:59 PM PDT 24
Finished Jul 17 07:08:36 PM PDT 24
Peak memory 223264 kb
Host smart-2ea053f0-6577-4e29-aec8-0acb3affea13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137521583 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.2137521583
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.2664275497
Short name T27
Test name
Test status
Simulation time 33330241 ps
CPU time 2.58 seconds
Started Jul 17 07:08:06 PM PDT 24
Finished Jul 17 07:08:32 PM PDT 24
Peak memory 207748 kb
Host smart-d2cf582b-a6f8-4457-b571-071bc8bc85cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664275497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.2664275497
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.918175936
Short name T522
Test name
Test status
Simulation time 31133555 ps
CPU time 1.52 seconds
Started Jul 17 07:07:59 PM PDT 24
Finished Jul 17 07:08:21 PM PDT 24
Peak memory 209572 kb
Host smart-e445bd49-9b3c-4420-b476-a9511364017d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918175936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.918175936
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.2901670593
Short name T879
Test name
Test status
Simulation time 13841040 ps
CPU time 0.89 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:14 PM PDT 24
Peak memory 205928 kb
Host smart-7759e303-8f37-429d-afbc-361b08a7e3b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901670593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.2901670593
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.1189224255
Short name T783
Test name
Test status
Simulation time 603237814 ps
CPU time 4.01 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:16 PM PDT 24
Peak memory 214328 kb
Host smart-637db5c9-df8b-4106-8a6b-ad02440436b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189224255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.1189224255
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.3366439657
Short name T199
Test name
Test status
Simulation time 148254456 ps
CPU time 3.28 seconds
Started Jul 17 07:07:50 PM PDT 24
Finished Jul 17 07:08:00 PM PDT 24
Peak memory 208300 kb
Host smart-77ad961f-aa50-407b-b744-04f0ca2c9607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366439657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.3366439657
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2388801340
Short name T322
Test name
Test status
Simulation time 299381360 ps
CPU time 2.59 seconds
Started Jul 17 07:07:57 PM PDT 24
Finished Jul 17 07:08:21 PM PDT 24
Peak memory 215220 kb
Host smart-6f13de65-cdf1-449a-832a-58fa81980c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388801340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2388801340
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.1781686868
Short name T287
Test name
Test status
Simulation time 676378866 ps
CPU time 4.47 seconds
Started Jul 17 07:07:54 PM PDT 24
Finished Jul 17 07:08:15 PM PDT 24
Peak memory 207032 kb
Host smart-45b3db57-831e-4dd8-ac12-f5f5f3fa5949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781686868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.1781686868
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.3477799472
Short name T252
Test name
Test status
Simulation time 1577558823 ps
CPU time 4.86 seconds
Started Jul 17 07:07:50 PM PDT 24
Finished Jul 17 07:07:59 PM PDT 24
Peak memory 214240 kb
Host smart-956b048c-2c14-4149-9c9b-67fe6e7f9a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477799472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.3477799472
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.192115950
Short name T570
Test name
Test status
Simulation time 17426469432 ps
CPU time 46.94 seconds
Started Jul 17 07:07:51 PM PDT 24
Finished Jul 17 07:08:48 PM PDT 24
Peak memory 208948 kb
Host smart-cbd60233-3023-45e3-8d22-83d2f9b2aeed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192115950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.192115950
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.2054947177
Short name T500
Test name
Test status
Simulation time 1521685224 ps
CPU time 38.17 seconds
Started Jul 17 07:07:51 PM PDT 24
Finished Jul 17 07:08:36 PM PDT 24
Peak memory 208868 kb
Host smart-2874e000-4153-4968-9584-918611bea37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054947177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.2054947177
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.573863554
Short name T596
Test name
Test status
Simulation time 131726642 ps
CPU time 2.62 seconds
Started Jul 17 07:07:52 PM PDT 24
Finished Jul 17 07:08:05 PM PDT 24
Peak memory 207016 kb
Host smart-5c7d37ce-6568-4238-a475-87f69f44c625
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573863554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.573863554
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.2960331299
Short name T499
Test name
Test status
Simulation time 85721019 ps
CPU time 3.79 seconds
Started Jul 17 07:07:51 PM PDT 24
Finished Jul 17 07:08:05 PM PDT 24
Peak memory 208512 kb
Host smart-9b290420-84b2-4174-a992-19432e05b0fd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960331299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.2960331299
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.3341287535
Short name T846
Test name
Test status
Simulation time 78876086 ps
CPU time 2.8 seconds
Started Jul 17 07:07:50 PM PDT 24
Finished Jul 17 07:07:58 PM PDT 24
Peak memory 208032 kb
Host smart-f562aac8-bd58-4308-9229-42ff2beb1ed1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341287535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.3341287535
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.1678578659
Short name T209
Test name
Test status
Simulation time 71846673 ps
CPU time 3.24 seconds
Started Jul 17 07:07:53 PM PDT 24
Finished Jul 17 07:08:10 PM PDT 24
Peak memory 209824 kb
Host smart-d587d770-49e8-4791-8db2-6e5aae2e7a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678578659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1678578659
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.1411030534
Short name T625
Test name
Test status
Simulation time 1917308746 ps
CPU time 6.73 seconds
Started Jul 17 07:07:50 PM PDT 24
Finished Jul 17 07:08:02 PM PDT 24
Peak memory 207056 kb
Host smart-18ec8074-6bbf-47d5-b112-d142eaee1754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411030534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.1411030534
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.2412713132
Short name T762
Test name
Test status
Simulation time 5755264391 ps
CPU time 30.29 seconds
Started Jul 17 07:07:53 PM PDT 24
Finished Jul 17 07:08:37 PM PDT 24
Peak memory 215468 kb
Host smart-89c5fdc9-8575-4c72-8747-ee8832010f08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412713132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2412713132
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.157331231
Short name T562
Test name
Test status
Simulation time 321428902 ps
CPU time 4.22 seconds
Started Jul 17 07:07:50 PM PDT 24
Finished Jul 17 07:08:01 PM PDT 24
Peak memory 207684 kb
Host smart-3115b723-22ed-429f-ac8e-9befb606015e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157331231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.157331231
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.3037784137
Short name T593
Test name
Test status
Simulation time 68974195 ps
CPU time 1.84 seconds
Started Jul 17 07:07:56 PM PDT 24
Finished Jul 17 07:08:18 PM PDT 24
Peak memory 209816 kb
Host smart-35397872-8208-4115-9998-e164a191a389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037784137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.3037784137
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.2106954984
Short name T542
Test name
Test status
Simulation time 14527954 ps
CPU time 0.79 seconds
Started Jul 17 07:07:58 PM PDT 24
Finished Jul 17 07:08:21 PM PDT 24
Peak memory 205996 kb
Host smart-9ac36cfc-9369-4bad-8a68-bbf12b841d25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106954984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2106954984
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.2586705790
Short name T278
Test name
Test status
Simulation time 67787256 ps
CPU time 3.1 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:16 PM PDT 24
Peak memory 214372 kb
Host smart-3d5d2a22-accd-4912-9632-151ddfe5de93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2586705790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.2586705790
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.2066976507
Short name T10
Test name
Test status
Simulation time 353600778 ps
CPU time 15.26 seconds
Started Jul 17 07:07:57 PM PDT 24
Finished Jul 17 07:08:33 PM PDT 24
Peak memory 214656 kb
Host smart-93293cb5-2375-46ee-86c4-efc3ea8b90e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066976507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.2066976507
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.2837475807
Short name T82
Test name
Test status
Simulation time 693957022 ps
CPU time 2.65 seconds
Started Jul 17 07:08:00 PM PDT 24
Finished Jul 17 07:08:25 PM PDT 24
Peak memory 207504 kb
Host smart-73b27bc4-4df9-4582-8bf6-bc2185f8ec7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837475807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.2837475807
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.4207517788
Short name T24
Test name
Test status
Simulation time 891056872 ps
CPU time 9.51 seconds
Started Jul 17 07:07:56 PM PDT 24
Finished Jul 17 07:08:25 PM PDT 24
Peak memory 214332 kb
Host smart-3ea60da5-6b63-416f-9b1b-192d407b0646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207517788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.4207517788
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.4125374683
Short name T825
Test name
Test status
Simulation time 64470772 ps
CPU time 3.1 seconds
Started Jul 17 07:08:02 PM PDT 24
Finished Jul 17 07:08:28 PM PDT 24
Peak memory 214852 kb
Host smart-bf3cc708-0380-4799-8c54-93af568e751b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125374683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.4125374683
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.906117015
Short name T640
Test name
Test status
Simulation time 399858595 ps
CPU time 3.8 seconds
Started Jul 17 07:07:59 PM PDT 24
Finished Jul 17 07:08:24 PM PDT 24
Peak memory 209652 kb
Host smart-9ec5ec4f-11a8-422e-879f-b2f6c14f237f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906117015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.906117015
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.7484644
Short name T744
Test name
Test status
Simulation time 492303404 ps
CPU time 6.3 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:21 PM PDT 24
Peak memory 207376 kb
Host smart-a1fc599c-b1ef-45a6-be24-121dcf41341f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7484644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.7484644
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.2501929977
Short name T543
Test name
Test status
Simulation time 863043497 ps
CPU time 20.5 seconds
Started Jul 17 07:07:56 PM PDT 24
Finished Jul 17 07:08:37 PM PDT 24
Peak memory 208040 kb
Host smart-a160b9c2-0bd5-4375-b1ab-5f6eea1ad5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501929977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.2501929977
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.2392432158
Short name T728
Test name
Test status
Simulation time 39440204 ps
CPU time 2.47 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:16 PM PDT 24
Peak memory 207040 kb
Host smart-ab1e1b75-618d-4d22-9824-786ba71879bc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392432158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.2392432158
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.3738131329
Short name T572
Test name
Test status
Simulation time 320799921 ps
CPU time 2.41 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:15 PM PDT 24
Peak memory 206844 kb
Host smart-bd92354d-0b2a-42af-bef0-6f2f7d4533fe
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738131329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3738131329
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.1533665345
Short name T556
Test name
Test status
Simulation time 113912555 ps
CPU time 2.91 seconds
Started Jul 17 07:07:53 PM PDT 24
Finished Jul 17 07:08:10 PM PDT 24
Peak memory 207028 kb
Host smart-b8d97a11-38d9-4f58-9e16-30fa5ae369dd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533665345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.1533665345
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.1853346416
Short name T795
Test name
Test status
Simulation time 133214107 ps
CPU time 1.87 seconds
Started Jul 17 07:08:06 PM PDT 24
Finished Jul 17 07:08:31 PM PDT 24
Peak memory 215896 kb
Host smart-870d95e1-37bb-46d2-9757-dfeb67fc5c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853346416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.1853346416
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.3721607948
Short name T697
Test name
Test status
Simulation time 71296877 ps
CPU time 1.64 seconds
Started Jul 17 07:07:54 PM PDT 24
Finished Jul 17 07:08:11 PM PDT 24
Peak memory 206788 kb
Host smart-4a627be6-f56e-40f3-b1f7-07379cc9f36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721607948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.3721607948
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.477827508
Short name T853
Test name
Test status
Simulation time 437484158 ps
CPU time 22.19 seconds
Started Jul 17 07:07:58 PM PDT 24
Finished Jul 17 07:08:42 PM PDT 24
Peak memory 215440 kb
Host smart-5c8fc712-492f-4514-ad06-a9d65335df66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477827508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.477827508
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.129291229
Short name T28
Test name
Test status
Simulation time 90198767 ps
CPU time 4.26 seconds
Started Jul 17 07:07:56 PM PDT 24
Finished Jul 17 07:08:20 PM PDT 24
Peak memory 209656 kb
Host smart-3ab29113-2ac6-4931-bb83-ac5b239d5e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129291229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.129291229
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.1384340888
Short name T666
Test name
Test status
Simulation time 445756900 ps
CPU time 2.5 seconds
Started Jul 17 07:08:07 PM PDT 24
Finished Jul 17 07:08:32 PM PDT 24
Peak memory 210080 kb
Host smart-746fbc13-22c2-4de1-b3a7-7206fcd057e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384340888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.1384340888
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.3796960240
Short name T110
Test name
Test status
Simulation time 23876291 ps
CPU time 0.73 seconds
Started Jul 17 07:07:50 PM PDT 24
Finished Jul 17 07:07:56 PM PDT 24
Peak memory 205892 kb
Host smart-89036bfc-1797-4c45-9f80-85e53200e8a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796960240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.3796960240
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.3542279726
Short name T909
Test name
Test status
Simulation time 790839502 ps
CPU time 9.97 seconds
Started Jul 17 07:08:06 PM PDT 24
Finished Jul 17 07:08:40 PM PDT 24
Peak memory 214260 kb
Host smart-16e04476-ebf1-43c0-b79e-447c9f327107
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3542279726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.3542279726
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.3048652367
Short name T700
Test name
Test status
Simulation time 817165728 ps
CPU time 12.51 seconds
Started Jul 17 07:08:07 PM PDT 24
Finished Jul 17 07:08:42 PM PDT 24
Peak memory 208696 kb
Host smart-7af2f925-133c-42fd-a896-40da25b91fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048652367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.3048652367
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.4199393818
Short name T282
Test name
Test status
Simulation time 32058108 ps
CPU time 1.97 seconds
Started Jul 17 07:07:53 PM PDT 24
Finished Jul 17 07:08:07 PM PDT 24
Peak memory 214348 kb
Host smart-3b93ffd6-dc77-4295-9d02-aefdc62bc66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199393818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.4199393818
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.232274709
Short name T283
Test name
Test status
Simulation time 1181670651 ps
CPU time 4.24 seconds
Started Jul 17 07:08:08 PM PDT 24
Finished Jul 17 07:08:34 PM PDT 24
Peak memory 221904 kb
Host smart-1b8364ef-7a24-45e9-a3d5-01603aacd789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232274709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.232274709
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.182925498
Short name T474
Test name
Test status
Simulation time 333295275 ps
CPU time 3.39 seconds
Started Jul 17 07:08:03 PM PDT 24
Finished Jul 17 07:08:30 PM PDT 24
Peak memory 214308 kb
Host smart-94fa1f0f-88a7-4e7b-b14e-27758256aa94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182925498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.182925498
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.396354905
Short name T354
Test name
Test status
Simulation time 234943969 ps
CPU time 4.51 seconds
Started Jul 17 07:08:03 PM PDT 24
Finished Jul 17 07:08:30 PM PDT 24
Peak memory 208992 kb
Host smart-544cf5c5-7117-46fa-8759-0d2f0911c8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396354905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.396354905
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.3095033536
Short name T259
Test name
Test status
Simulation time 524663987 ps
CPU time 11.65 seconds
Started Jul 17 07:07:59 PM PDT 24
Finished Jul 17 07:08:32 PM PDT 24
Peak memory 208632 kb
Host smart-9a6ef566-eae6-4363-94a5-8492c5e1e7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095033536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.3095033536
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.3878975786
Short name T330
Test name
Test status
Simulation time 251070461 ps
CPU time 6.87 seconds
Started Jul 17 07:08:02 PM PDT 24
Finished Jul 17 07:08:32 PM PDT 24
Peak memory 209000 kb
Host smart-cc59320e-8366-466b-96fe-e9a00cda1948
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878975786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.3878975786
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.172758330
Short name T840
Test name
Test status
Simulation time 449506379 ps
CPU time 6.69 seconds
Started Jul 17 07:08:00 PM PDT 24
Finished Jul 17 07:08:29 PM PDT 24
Peak memory 208652 kb
Host smart-f4da40ec-692a-4499-a699-db3ad6625b85
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172758330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.172758330
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.4177542404
Short name T841
Test name
Test status
Simulation time 131021941 ps
CPU time 2.24 seconds
Started Jul 17 07:08:00 PM PDT 24
Finished Jul 17 07:08:25 PM PDT 24
Peak memory 206684 kb
Host smart-3d5121f4-c0e7-4741-a4e0-6e3fb99773d3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177542404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.4177542404
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.49177558
Short name T805
Test name
Test status
Simulation time 525495105 ps
CPU time 8.14 seconds
Started Jul 17 07:07:53 PM PDT 24
Finished Jul 17 07:08:15 PM PDT 24
Peak memory 214340 kb
Host smart-170dc91c-11a5-4871-9d19-0c5a4db8cc34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49177558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.49177558
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.1905935754
Short name T615
Test name
Test status
Simulation time 169846586 ps
CPU time 2.62 seconds
Started Jul 17 07:08:06 PM PDT 24
Finished Jul 17 07:08:32 PM PDT 24
Peak memory 206948 kb
Host smart-30642fe7-9867-4cdd-9555-5687b8d2ba7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905935754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.1905935754
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.1014458842
Short name T327
Test name
Test status
Simulation time 1354258364 ps
CPU time 46.67 seconds
Started Jul 17 07:07:51 PM PDT 24
Finished Jul 17 07:08:46 PM PDT 24
Peak memory 222492 kb
Host smart-a7937a03-c6e4-41f2-b15f-59502b2b2d6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014458842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1014458842
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.1840956772
Short name T188
Test name
Test status
Simulation time 232698809 ps
CPU time 9.13 seconds
Started Jul 17 07:07:51 PM PDT 24
Finished Jul 17 07:08:08 PM PDT 24
Peak memory 220112 kb
Host smart-623a2b1b-f4f6-4ef9-bed4-d9f663dac826
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840956772 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.1840956772
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.3358778314
Short name T619
Test name
Test status
Simulation time 194005840 ps
CPU time 6.19 seconds
Started Jul 17 07:08:03 PM PDT 24
Finished Jul 17 07:08:32 PM PDT 24
Peak memory 214332 kb
Host smart-abb70365-a2da-4749-ab94-a22bd1b8a98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358778314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.3358778314
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.3998477607
Short name T726
Test name
Test status
Simulation time 47503974 ps
CPU time 0.88 seconds
Started Jul 17 07:07:58 PM PDT 24
Finished Jul 17 07:08:19 PM PDT 24
Peak memory 205744 kb
Host smart-6e8581a8-7779-467c-867e-5b18464850fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998477607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.3998477607
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.2861697888
Short name T538
Test name
Test status
Simulation time 293214383 ps
CPU time 2.34 seconds
Started Jul 17 07:07:54 PM PDT 24
Finished Jul 17 07:08:12 PM PDT 24
Peak memory 218376 kb
Host smart-d578f53b-a08b-4444-89f4-551a8ac812a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861697888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.2861697888
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.379726789
Short name T380
Test name
Test status
Simulation time 40417345 ps
CPU time 2.31 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:15 PM PDT 24
Peak memory 215536 kb
Host smart-b11991a0-9447-4e7f-a9a5-6be3d848f017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379726789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.379726789
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.827831615
Short name T55
Test name
Test status
Simulation time 883269135 ps
CPU time 3.37 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:19 PM PDT 24
Peak memory 214400 kb
Host smart-feeb63c4-6934-4eb4-8664-3d26271d4b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827831615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.827831615
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.3432708097
Short name T576
Test name
Test status
Simulation time 52922028 ps
CPU time 3.73 seconds
Started Jul 17 07:07:54 PM PDT 24
Finished Jul 17 07:08:12 PM PDT 24
Peak memory 210532 kb
Host smart-1b3b07b6-31fe-410e-9aae-fa7e49e512b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432708097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3432708097
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.2539632590
Short name T198
Test name
Test status
Simulation time 4574246388 ps
CPU time 28.47 seconds
Started Jul 17 07:07:50 PM PDT 24
Finished Jul 17 07:08:22 PM PDT 24
Peak memory 209488 kb
Host smart-3fca6839-a751-4cc7-a865-a40ccf885e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539632590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.2539632590
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2419194860
Short name T624
Test name
Test status
Simulation time 56543076 ps
CPU time 2.98 seconds
Started Jul 17 07:07:51 PM PDT 24
Finished Jul 17 07:08:01 PM PDT 24
Peak memory 206704 kb
Host smart-1950446f-9fe6-433c-957c-9c71a2dc2efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419194860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2419194860
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.3214471978
Short name T793
Test name
Test status
Simulation time 38241610 ps
CPU time 1.7 seconds
Started Jul 17 07:07:50 PM PDT 24
Finished Jul 17 07:07:56 PM PDT 24
Peak memory 206880 kb
Host smart-2fa3f8d4-932b-472b-a520-9b07b46083df
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214471978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.3214471978
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.2535929839
Short name T92
Test name
Test status
Simulation time 403870164 ps
CPU time 3.85 seconds
Started Jul 17 07:07:53 PM PDT 24
Finished Jul 17 07:08:09 PM PDT 24
Peak memory 207032 kb
Host smart-07d8656e-e36d-458a-a8c1-180f68454ce2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535929839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.2535929839
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.1451558593
Short name T633
Test name
Test status
Simulation time 188378121 ps
CPU time 5.61 seconds
Started Jul 17 07:07:57 PM PDT 24
Finished Jul 17 07:08:23 PM PDT 24
Peak memory 208260 kb
Host smart-6e2c85b3-8adb-4e21-b1af-9dd8baecda03
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451558593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.1451558593
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.1391199965
Short name T430
Test name
Test status
Simulation time 71021692 ps
CPU time 1.85 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:15 PM PDT 24
Peak memory 209260 kb
Host smart-62250409-306b-439e-ad35-24dec9a4a929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391199965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.1391199965
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.579363391
Short name T612
Test name
Test status
Simulation time 3353453454 ps
CPU time 15.45 seconds
Started Jul 17 07:07:51 PM PDT 24
Finished Jul 17 07:08:16 PM PDT 24
Peak memory 208116 kb
Host smart-6a85f991-781a-4b7d-9bf8-ff094fcddabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579363391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.579363391
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.1609350698
Short name T275
Test name
Test status
Simulation time 2657447346 ps
CPU time 8.84 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:22 PM PDT 24
Peak memory 218056 kb
Host smart-9f757b91-f0c0-4630-9245-dafb8372fd2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609350698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1609350698
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3806184212
Short name T411
Test name
Test status
Simulation time 568437986 ps
CPU time 4.45 seconds
Started Jul 17 07:07:56 PM PDT 24
Finished Jul 17 07:08:21 PM PDT 24
Peak memory 207692 kb
Host smart-058385f2-e283-4b17-9319-e0c9f1bb5a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806184212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3806184212
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1205325145
Short name T181
Test name
Test status
Simulation time 167576549 ps
CPU time 3.07 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:16 PM PDT 24
Peak memory 210220 kb
Host smart-6e785338-5f9b-47c2-b13b-5090e1ed6586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205325145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1205325145
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.1669589110
Short name T516
Test name
Test status
Simulation time 17795210 ps
CPU time 0.84 seconds
Started Jul 17 07:08:01 PM PDT 24
Finished Jul 17 07:08:23 PM PDT 24
Peak memory 205992 kb
Host smart-654e8573-e605-4f9e-af29-da1888358083
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669589110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1669589110
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.3577312711
Short name T463
Test name
Test status
Simulation time 909715324 ps
CPU time 21.3 seconds
Started Jul 17 07:08:02 PM PDT 24
Finished Jul 17 07:08:45 PM PDT 24
Peak memory 208816 kb
Host smart-18ca42c9-3124-4b89-8f3a-af1f7bbe4c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577312711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.3577312711
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.3687810508
Short name T544
Test name
Test status
Simulation time 106576114 ps
CPU time 3.54 seconds
Started Jul 17 07:08:06 PM PDT 24
Finished Jul 17 07:08:33 PM PDT 24
Peak memory 214180 kb
Host smart-1fb16199-9478-46e0-a926-13a98b610e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687810508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.3687810508
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.2601533078
Short name T656
Test name
Test status
Simulation time 190460401 ps
CPU time 3.38 seconds
Started Jul 17 07:08:07 PM PDT 24
Finished Jul 17 07:08:33 PM PDT 24
Peak memory 222492 kb
Host smart-5a00a9d3-ace5-464a-b77b-e42556e8cb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601533078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2601533078
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.3130913500
Short name T210
Test name
Test status
Simulation time 50731832 ps
CPU time 3.53 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:19 PM PDT 24
Peak memory 218184 kb
Host smart-2aadb83f-eb86-48b4-85c4-c15727a0ceee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130913500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.3130913500
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.3158925136
Short name T913
Test name
Test status
Simulation time 259987006 ps
CPU time 5.99 seconds
Started Jul 17 07:07:58 PM PDT 24
Finished Jul 17 07:08:23 PM PDT 24
Peak memory 208636 kb
Host smart-91d894ca-aafe-4248-bbeb-8ee36e4651f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158925136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.3158925136
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.884842264
Short name T906
Test name
Test status
Simulation time 106022243 ps
CPU time 4.56 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:20 PM PDT 24
Peak memory 207168 kb
Host smart-6b5d2dc3-e10f-4002-bf61-4429b429d935
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884842264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.884842264
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.2240681835
Short name T508
Test name
Test status
Simulation time 121768928 ps
CPU time 3.01 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:16 PM PDT 24
Peak memory 208660 kb
Host smart-e2100469-6786-4dcf-a76b-9cbc8173d016
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240681835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.2240681835
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.2353446443
Short name T485
Test name
Test status
Simulation time 1601771093 ps
CPU time 45.81 seconds
Started Jul 17 07:07:58 PM PDT 24
Finished Jul 17 07:09:06 PM PDT 24
Peak memory 208308 kb
Host smart-6d82dd3a-7bfd-4676-8075-9d80c87482d7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353446443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.2353446443
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.2289008908
Short name T555
Test name
Test status
Simulation time 159496625 ps
CPU time 3.32 seconds
Started Jul 17 07:07:58 PM PDT 24
Finished Jul 17 07:08:23 PM PDT 24
Peak memory 209448 kb
Host smart-6c568c54-97d5-4bc0-8d02-81e5f3f9ce9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289008908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.2289008908
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.1510870379
Short name T218
Test name
Test status
Simulation time 15339665589 ps
CPU time 33.22 seconds
Started Jul 17 07:07:58 PM PDT 24
Finished Jul 17 07:08:52 PM PDT 24
Peak memory 208948 kb
Host smart-3976340b-57a0-438d-b609-ecde647e7089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510870379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1510870379
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.1040469876
Short name T774
Test name
Test status
Simulation time 5984663923 ps
CPU time 131.23 seconds
Started Jul 17 07:08:05 PM PDT 24
Finished Jul 17 07:10:38 PM PDT 24
Peak memory 216200 kb
Host smart-e27e9311-e217-4031-88ab-5eb57e2b88aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040469876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.1040469876
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.2531018482
Short name T298
Test name
Test status
Simulation time 1828009457 ps
CPU time 12.67 seconds
Started Jul 17 07:08:00 PM PDT 24
Finished Jul 17 07:08:35 PM PDT 24
Peak memory 210344 kb
Host smart-7c755b77-31d5-4233-bc54-7a940348a43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531018482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.2531018482
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.366041779
Short name T168
Test name
Test status
Simulation time 35005491 ps
CPU time 1.29 seconds
Started Jul 17 07:08:00 PM PDT 24
Finished Jul 17 07:08:22 PM PDT 24
Peak memory 210352 kb
Host smart-a526ca18-d13c-464a-804a-e68ccae18ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366041779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.366041779
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.2530174025
Short name T838
Test name
Test status
Simulation time 31812377 ps
CPU time 0.98 seconds
Started Jul 17 07:07:49 PM PDT 24
Finished Jul 17 07:07:53 PM PDT 24
Peak memory 206128 kb
Host smart-cd553ae9-61ea-44fa-a724-273d890e444b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530174025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.2530174025
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.245928801
Short name T289
Test name
Test status
Simulation time 369776790 ps
CPU time 10.27 seconds
Started Jul 17 07:08:08 PM PDT 24
Finished Jul 17 07:08:41 PM PDT 24
Peak memory 214696 kb
Host smart-b6eeabe4-ee67-48cf-8efd-7df28e9696cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=245928801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.245928801
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.2316871591
Short name T30
Test name
Test status
Simulation time 2488530878 ps
CPU time 24.15 seconds
Started Jul 17 07:07:54 PM PDT 24
Finished Jul 17 07:08:34 PM PDT 24
Peak memory 222108 kb
Host smart-f9ac700c-aed8-4876-8da2-ec9923f2514c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316871591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2316871591
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.3760227880
Short name T69
Test name
Test status
Simulation time 187150983 ps
CPU time 5.1 seconds
Started Jul 17 07:08:03 PM PDT 24
Finished Jul 17 07:08:31 PM PDT 24
Peak memory 207428 kb
Host smart-96931c49-63c3-45f2-985f-141537778ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760227880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.3760227880
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.3843594102
Short name T102
Test name
Test status
Simulation time 198501781 ps
CPU time 2.39 seconds
Started Jul 17 07:07:50 PM PDT 24
Finished Jul 17 07:07:57 PM PDT 24
Peak memory 217280 kb
Host smart-632c26f4-26cf-4bea-aeb4-b95f9c7a254b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843594102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.3843594102
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.2804061887
Short name T863
Test name
Test status
Simulation time 586873378 ps
CPU time 4.14 seconds
Started Jul 17 07:07:50 PM PDT 24
Finished Jul 17 07:08:01 PM PDT 24
Peak memory 206228 kb
Host smart-ff2588b4-0466-4056-be09-0521ceff9844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804061887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.2804061887
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.2955758041
Short name T908
Test name
Test status
Simulation time 134621705 ps
CPU time 3.14 seconds
Started Jul 17 07:08:06 PM PDT 24
Finished Jul 17 07:08:32 PM PDT 24
Peak memory 214492 kb
Host smart-ccb99304-332e-422f-b2fb-b5d4584d5f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955758041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.2955758041
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.2865081577
Short name T681
Test name
Test status
Simulation time 171657499 ps
CPU time 4.49 seconds
Started Jul 17 07:08:03 PM PDT 24
Finished Jul 17 07:08:31 PM PDT 24
Peak memory 207952 kb
Host smart-13168e48-c0ee-4618-900c-31731a76d262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865081577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.2865081577
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.1348020576
Short name T212
Test name
Test status
Simulation time 356518182 ps
CPU time 3.66 seconds
Started Jul 17 07:08:02 PM PDT 24
Finished Jul 17 07:08:28 PM PDT 24
Peak memory 209088 kb
Host smart-d12d3c61-95ad-4a29-a0e0-e3ac0ab21c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348020576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.1348020576
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.2378507957
Short name T510
Test name
Test status
Simulation time 81184135 ps
CPU time 2.24 seconds
Started Jul 17 07:08:03 PM PDT 24
Finished Jul 17 07:08:28 PM PDT 24
Peak memory 206968 kb
Host smart-be2a47d0-5818-4925-8495-f3c96fc5339b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378507957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2378507957
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.2956099929
Short name T628
Test name
Test status
Simulation time 96862915 ps
CPU time 2.72 seconds
Started Jul 17 07:08:03 PM PDT 24
Finished Jul 17 07:08:29 PM PDT 24
Peak memory 206868 kb
Host smart-9f1af3cc-69c9-4662-bf5b-c62bea9d3d0d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956099929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.2956099929
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.4153996878
Short name T708
Test name
Test status
Simulation time 1059267740 ps
CPU time 6.53 seconds
Started Jul 17 07:08:07 PM PDT 24
Finished Jul 17 07:08:37 PM PDT 24
Peak memory 208888 kb
Host smart-ec9ab0b7-dbb9-4567-b32d-a290f51555fc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153996878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.4153996878
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.4087073024
Short name T660
Test name
Test status
Simulation time 318200986 ps
CPU time 3.81 seconds
Started Jul 17 07:07:50 PM PDT 24
Finished Jul 17 07:07:58 PM PDT 24
Peak memory 218216 kb
Host smart-3aafa9c4-c046-40fa-a2b3-22207c68fe05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087073024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.4087073024
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.2461987244
Short name T778
Test name
Test status
Simulation time 135514703 ps
CPU time 3.71 seconds
Started Jul 17 07:07:58 PM PDT 24
Finished Jul 17 07:08:24 PM PDT 24
Peak memory 208468 kb
Host smart-4d4235a8-80ec-4384-8201-55c37e7735f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461987244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.2461987244
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.2670628246
Short name T388
Test name
Test status
Simulation time 908405227 ps
CPU time 9.88 seconds
Started Jul 17 07:07:50 PM PDT 24
Finished Jul 17 07:08:04 PM PDT 24
Peak memory 215996 kb
Host smart-2134d10f-752e-43f1-b962-cd7a0601a48f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670628246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.2670628246
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.2172847556
Short name T835
Test name
Test status
Simulation time 41924442 ps
CPU time 2.59 seconds
Started Jul 17 07:08:03 PM PDT 24
Finished Jul 17 07:08:28 PM PDT 24
Peak memory 209420 kb
Host smart-75d32b1c-2b4f-4dad-9f77-b1a32b36901c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172847556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.2172847556
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.996865402
Short name T44
Test name
Test status
Simulation time 74875355 ps
CPU time 2.1 seconds
Started Jul 17 07:07:51 PM PDT 24
Finished Jul 17 07:08:03 PM PDT 24
Peak memory 209976 kb
Host smart-e66984b7-b5e7-4f2b-a61c-2265d6c100c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996865402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.996865402
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.2354427860
Short name T492
Test name
Test status
Simulation time 29598566 ps
CPU time 0.76 seconds
Started Jul 17 07:08:08 PM PDT 24
Finished Jul 17 07:08:31 PM PDT 24
Peak memory 206072 kb
Host smart-02d8e144-d3b6-4564-8d2a-ac893934a477
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354427860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.2354427860
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.415657530
Short name T274
Test name
Test status
Simulation time 612185120 ps
CPU time 6.13 seconds
Started Jul 17 07:07:52 PM PDT 24
Finished Jul 17 07:08:11 PM PDT 24
Peak memory 215416 kb
Host smart-cf693bd0-5297-4e41-ae2f-e875c08b2680
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=415657530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.415657530
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.3957050214
Short name T53
Test name
Test status
Simulation time 172128365 ps
CPU time 2.32 seconds
Started Jul 17 07:08:08 PM PDT 24
Finished Jul 17 07:08:33 PM PDT 24
Peak memory 207684 kb
Host smart-8ee7ed32-e856-4a5f-a9f5-ceb0ceb56b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957050214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.3957050214
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.3324084333
Short name T845
Test name
Test status
Simulation time 321804162 ps
CPU time 7.02 seconds
Started Jul 17 07:08:14 PM PDT 24
Finished Jul 17 07:08:40 PM PDT 24
Peak memory 221384 kb
Host smart-f9724335-49da-4b20-a099-9e2338687306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324084333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.3324084333
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.3576671001
Short name T303
Test name
Test status
Simulation time 38759394 ps
CPU time 2.64 seconds
Started Jul 17 07:08:04 PM PDT 24
Finished Jul 17 07:08:29 PM PDT 24
Peak memory 214260 kb
Host smart-21fabde3-b871-4a33-a26a-648146c900bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576671001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.3576671001
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.2498160186
Short name T266
Test name
Test status
Simulation time 102611280 ps
CPU time 3.54 seconds
Started Jul 17 07:08:13 PM PDT 24
Finished Jul 17 07:08:36 PM PDT 24
Peak memory 220156 kb
Host smart-bfd5cdc8-cc7d-4edb-8f3e-577324952f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498160186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2498160186
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.2677730331
Short name T409
Test name
Test status
Simulation time 1002597684 ps
CPU time 8.73 seconds
Started Jul 17 07:07:52 PM PDT 24
Finished Jul 17 07:08:11 PM PDT 24
Peak memory 218184 kb
Host smart-ae16a896-3597-4c69-aefd-9525c4eab2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677730331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2677730331
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.3087955397
Short name T389
Test name
Test status
Simulation time 949067599 ps
CPU time 2.94 seconds
Started Jul 17 07:07:52 PM PDT 24
Finished Jul 17 07:08:06 PM PDT 24
Peak memory 207132 kb
Host smart-3b884b04-ff51-4d8c-a2d2-4f2dda8ee8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087955397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.3087955397
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.3728570137
Short name T914
Test name
Test status
Simulation time 39313283 ps
CPU time 1.96 seconds
Started Jul 17 07:07:52 PM PDT 24
Finished Jul 17 07:08:05 PM PDT 24
Peak memory 208792 kb
Host smart-5bb21794-e6ec-4565-88d4-6409e95ee2c4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728570137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3728570137
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.2613264661
Short name T858
Test name
Test status
Simulation time 236222379 ps
CPU time 3.36 seconds
Started Jul 17 07:07:57 PM PDT 24
Finished Jul 17 07:08:21 PM PDT 24
Peak memory 208564 kb
Host smart-1ad4a04d-02d1-47c0-942c-5402b719c261
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613264661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.2613264661
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.3672746887
Short name T496
Test name
Test status
Simulation time 336085166 ps
CPU time 2.8 seconds
Started Jul 17 07:07:55 PM PDT 24
Finished Jul 17 07:08:15 PM PDT 24
Peak memory 207100 kb
Host smart-0d94fba0-0321-4f6f-8b58-044b03fdab29
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672746887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.3672746887
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.3204011557
Short name T89
Test name
Test status
Simulation time 214066676 ps
CPU time 2.45 seconds
Started Jul 17 07:08:08 PM PDT 24
Finished Jul 17 07:08:33 PM PDT 24
Peak memory 215304 kb
Host smart-d4accfb4-7a6e-4cbb-9d79-8fad61a70035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204011557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.3204011557
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.950972656
Short name T581
Test name
Test status
Simulation time 1290924090 ps
CPU time 11.02 seconds
Started Jul 17 07:07:54 PM PDT 24
Finished Jul 17 07:08:20 PM PDT 24
Peak memory 207900 kb
Host smart-2647fc00-abee-4cfd-b330-b5afc416791b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950972656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.950972656
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.1421226708
Short name T78
Test name
Test status
Simulation time 12384107625 ps
CPU time 279.7 seconds
Started Jul 17 07:08:13 PM PDT 24
Finished Jul 17 07:13:12 PM PDT 24
Peak memory 216508 kb
Host smart-fbf5fec0-4653-4035-ab21-60e86b41678c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421226708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.1421226708
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.28430074
Short name T895
Test name
Test status
Simulation time 2040047816 ps
CPU time 25.47 seconds
Started Jul 17 07:08:14 PM PDT 24
Finished Jul 17 07:08:58 PM PDT 24
Peak memory 222128 kb
Host smart-f15b2030-2935-43e3-b479-22b4f5a563f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28430074 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.28430074
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3253263097
Short name T824
Test name
Test status
Simulation time 48667488 ps
CPU time 3.24 seconds
Started Jul 17 07:08:14 PM PDT 24
Finished Jul 17 07:08:36 PM PDT 24
Peak memory 208104 kb
Host smart-9b682c99-b859-4648-8649-f6ad0a762a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253263097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3253263097
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.350960626
Short name T167
Test name
Test status
Simulation time 26192094 ps
CPU time 1.66 seconds
Started Jul 17 07:08:14 PM PDT 24
Finished Jul 17 07:08:35 PM PDT 24
Peak memory 209972 kb
Host smart-3eed2725-34a3-4f95-8092-1488191b4aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350960626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.350960626
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1059241287
Short name T460
Test name
Test status
Simulation time 30610191 ps
CPU time 0.72 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:09:50 PM PDT 24
Peak memory 205848 kb
Host smart-2056d0a4-999d-4965-9ceb-3d8f9933f319
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059241287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1059241287
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.4122097211
Short name T383
Test name
Test status
Simulation time 36872063 ps
CPU time 2.65 seconds
Started Jul 17 07:08:04 PM PDT 24
Finished Jul 17 07:08:29 PM PDT 24
Peak memory 215480 kb
Host smart-98599d92-f1a7-4f9d-ac22-9f0b15963d11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4122097211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.4122097211
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.1424107476
Short name T828
Test name
Test status
Simulation time 123266759 ps
CPU time 2.38 seconds
Started Jul 17 07:08:04 PM PDT 24
Finished Jul 17 07:08:29 PM PDT 24
Peak memory 207616 kb
Host smart-6c09dfe9-a616-48ce-a130-6956c991c093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424107476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.1424107476
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.1737916548
Short name T819
Test name
Test status
Simulation time 371079379 ps
CPU time 4.8 seconds
Started Jul 17 07:08:04 PM PDT 24
Finished Jul 17 07:08:31 PM PDT 24
Peak memory 215600 kb
Host smart-c8e8cb00-631c-42a9-95fc-0f22fba74534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737916548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.1737916548
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.681552327
Short name T114
Test name
Test status
Simulation time 150877714 ps
CPU time 1.72 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:09:51 PM PDT 24
Peak memory 214256 kb
Host smart-df970449-14c7-420e-9349-1be4ec02f46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681552327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.681552327
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.177317522
Short name T878
Test name
Test status
Simulation time 2826921103 ps
CPU time 11.57 seconds
Started Jul 17 07:08:13 PM PDT 24
Finished Jul 17 07:08:44 PM PDT 24
Peak memory 209184 kb
Host smart-673f7872-1416-4c7e-b2d9-e9a0a7e4f013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177317522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.177317522
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.150374138
Short name T93
Test name
Test status
Simulation time 656970872 ps
CPU time 12.77 seconds
Started Jul 17 07:08:16 PM PDT 24
Finished Jul 17 07:08:47 PM PDT 24
Peak memory 214316 kb
Host smart-84785ec1-920e-4546-a55b-5fb44b72cbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150374138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.150374138
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.171460578
Short name T312
Test name
Test status
Simulation time 506769152 ps
CPU time 2.62 seconds
Started Jul 17 07:08:04 PM PDT 24
Finished Jul 17 07:08:29 PM PDT 24
Peak memory 206996 kb
Host smart-39696bf1-0083-4095-bd4e-e1a1ba756fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171460578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.171460578
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2219620273
Short name T368
Test name
Test status
Simulation time 32506278 ps
CPU time 2.13 seconds
Started Jul 17 07:08:02 PM PDT 24
Finished Jul 17 07:08:27 PM PDT 24
Peak memory 208756 kb
Host smart-9e74c9e9-7f6b-4407-81b3-544e24c3a416
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219620273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2219620273
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.78817229
Short name T90
Test name
Test status
Simulation time 450247740 ps
CPU time 4.86 seconds
Started Jul 17 07:08:07 PM PDT 24
Finished Jul 17 07:08:34 PM PDT 24
Peak memory 208924 kb
Host smart-e5c5f5b7-43f3-4988-baa3-ab9d8c931b6e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78817229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.78817229
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.2230446281
Short name T714
Test name
Test status
Simulation time 89702337 ps
CPU time 2.72 seconds
Started Jul 17 07:08:14 PM PDT 24
Finished Jul 17 07:08:36 PM PDT 24
Peak memory 207612 kb
Host smart-405c3cc0-d660-41a2-9b1f-3edcee3ec13f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230446281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.2230446281
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.797480688
Short name T580
Test name
Test status
Simulation time 118940786 ps
CPU time 2.75 seconds
Started Jul 17 07:09:35 PM PDT 24
Finished Jul 17 07:09:38 PM PDT 24
Peak memory 210156 kb
Host smart-9cb7d587-8c89-4e8a-b170-192dc73becba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797480688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.797480688
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.3357860667
Short name T224
Test name
Test status
Simulation time 65997432 ps
CPU time 2.06 seconds
Started Jul 17 07:08:03 PM PDT 24
Finished Jul 17 07:08:28 PM PDT 24
Peak memory 206956 kb
Host smart-1bd9b916-a5b4-4aea-ba17-52f11b37ffa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357860667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.3357860667
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.3737776389
Short name T372
Test name
Test status
Simulation time 311409380 ps
CPU time 11.25 seconds
Started Jul 17 07:09:34 PM PDT 24
Finished Jul 17 07:09:46 PM PDT 24
Peak memory 222824 kb
Host smart-a1b434db-1269-4ccc-95c0-d60acaca5b57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737776389 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.3737776389
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.2481713715
Short name T113
Test name
Test status
Simulation time 672291221 ps
CPU time 12.49 seconds
Started Jul 17 07:08:14 PM PDT 24
Finished Jul 17 07:08:45 PM PDT 24
Peak memory 208400 kb
Host smart-b3d17b0b-8006-4d4a-a287-7225c468c9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481713715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.2481713715
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.1920469344
Short name T208
Test name
Test status
Simulation time 381213911 ps
CPU time 2.52 seconds
Started Jul 17 07:09:42 PM PDT 24
Finished Jul 17 07:09:55 PM PDT 24
Peak memory 209844 kb
Host smart-8f71d057-a4c8-4f39-bf6e-b93976ef70be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920469344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.1920469344
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.1453950040
Short name T768
Test name
Test status
Simulation time 32991733 ps
CPU time 0.93 seconds
Started Jul 17 07:09:44 PM PDT 24
Finished Jul 17 07:09:56 PM PDT 24
Peak memory 206140 kb
Host smart-e213a846-fa75-4069-afb8-130182ad4fd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453950040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1453950040
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.1649726301
Short name T295
Test name
Test status
Simulation time 3819941943 ps
CPU time 47.56 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:10:37 PM PDT 24
Peak memory 214628 kb
Host smart-7f96dd1e-2552-4cf1-b4e7-d2f5d5781da2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1649726301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.1649726301
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.4277354526
Short name T9
Test name
Test status
Simulation time 367108880 ps
CPU time 3.24 seconds
Started Jul 17 07:09:43 PM PDT 24
Finished Jul 17 07:09:57 PM PDT 24
Peak memory 217532 kb
Host smart-5de5814e-74c0-4f17-99e5-c7843caf3504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277354526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.4277354526
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.3367663197
Short name T594
Test name
Test status
Simulation time 1896059876 ps
CPU time 6.35 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:09:57 PM PDT 24
Peak memory 207128 kb
Host smart-801f08b7-cb57-4e5a-93e9-1d897cc13e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367663197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.3367663197
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.297630516
Short name T587
Test name
Test status
Simulation time 58434525 ps
CPU time 3.02 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:09:53 PM PDT 24
Peak memory 214160 kb
Host smart-a4e0c744-2a85-4db0-a583-e029bfced185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297630516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.297630516
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.3285639394
Short name T261
Test name
Test status
Simulation time 238986057 ps
CPU time 2.26 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:09:52 PM PDT 24
Peak memory 214280 kb
Host smart-8ea17c42-138e-4dae-8b21-c1e0eb77d39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285639394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.3285639394
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.490946564
Short name T6
Test name
Test status
Simulation time 54367606 ps
CPU time 2.53 seconds
Started Jul 17 07:09:44 PM PDT 24
Finished Jul 17 07:09:58 PM PDT 24
Peak memory 209296 kb
Host smart-039a648d-e392-437f-a629-a16893670217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490946564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.490946564
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.3593093309
Short name T568
Test name
Test status
Simulation time 213840983 ps
CPU time 3.73 seconds
Started Jul 17 07:09:42 PM PDT 24
Finished Jul 17 07:09:56 PM PDT 24
Peak memory 207572 kb
Host smart-9a47b124-04db-404a-9dcc-de0141970521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593093309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.3593093309
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.853052528
Short name T385
Test name
Test status
Simulation time 179618227 ps
CPU time 3.19 seconds
Started Jul 17 07:09:40 PM PDT 24
Finished Jul 17 07:09:49 PM PDT 24
Peak memory 206888 kb
Host smart-fd1d4438-ef37-480d-80b2-958de6467fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853052528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.853052528
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.2206185419
Short name T482
Test name
Test status
Simulation time 806537459 ps
CPU time 7.39 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:09:57 PM PDT 24
Peak memory 208996 kb
Host smart-0989f850-ef46-43d0-8225-9d140da2e830
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206185419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.2206185419
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.223310630
Short name T306
Test name
Test status
Simulation time 208273107 ps
CPU time 7.15 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:09:59 PM PDT 24
Peak memory 208532 kb
Host smart-22bb0497-90d4-4b47-a195-9565405f096f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223310630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.223310630
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.2355102817
Short name T332
Test name
Test status
Simulation time 56682319 ps
CPU time 2.65 seconds
Started Jul 17 07:09:39 PM PDT 24
Finished Jul 17 07:09:45 PM PDT 24
Peak memory 206936 kb
Host smart-dfda938c-68e4-49cf-ae90-9ce13e8c96c3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355102817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.2355102817
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.4234664456
Short name T228
Test name
Test status
Simulation time 265892920 ps
CPU time 1.71 seconds
Started Jul 17 07:09:43 PM PDT 24
Finished Jul 17 07:09:55 PM PDT 24
Peak memory 209124 kb
Host smart-2e842822-f4be-492b-ab99-e8708175d460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234664456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.4234664456
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.4210054325
Short name T673
Test name
Test status
Simulation time 119896735 ps
CPU time 2.08 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:09:49 PM PDT 24
Peak memory 207084 kb
Host smart-a723b502-d663-465f-9c73-72269ba8e74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210054325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.4210054325
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.3944595764
Short name T553
Test name
Test status
Simulation time 845705877 ps
CPU time 9.36 seconds
Started Jul 17 07:09:43 PM PDT 24
Finished Jul 17 07:10:04 PM PDT 24
Peak memory 220696 kb
Host smart-8669d88d-4c6d-4882-8d2d-7c56d7273195
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944595764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.3944595764
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.2840423016
Short name T136
Test name
Test status
Simulation time 267780893 ps
CPU time 9.26 seconds
Started Jul 17 07:09:43 PM PDT 24
Finished Jul 17 07:10:03 PM PDT 24
Peak memory 222612 kb
Host smart-54d0dfc8-e0e4-45eb-a72a-8168f90ecf24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840423016 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.2840423016
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.2682097998
Short name T194
Test name
Test status
Simulation time 246367426 ps
CPU time 5.27 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:09:56 PM PDT 24
Peak memory 214356 kb
Host smart-26708835-b704-4b61-8227-5655e1f0f635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682097998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.2682097998
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.3861210715
Short name T183
Test name
Test status
Simulation time 68049668 ps
CPU time 2.25 seconds
Started Jul 17 07:09:40 PM PDT 24
Finished Jul 17 07:09:48 PM PDT 24
Peak memory 209840 kb
Host smart-63ecb629-c103-4db2-8f3b-8c24fbf7520b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861210715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.3861210715
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.524769305
Short name T521
Test name
Test status
Simulation time 16364913 ps
CPU time 0.76 seconds
Started Jul 17 07:06:03 PM PDT 24
Finished Jul 17 07:06:05 PM PDT 24
Peak memory 205988 kb
Host smart-fa23c8c1-6d3e-45c3-a813-6298e9f1dd53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524769305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.524769305
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.103500871
Short name T34
Test name
Test status
Simulation time 43791179 ps
CPU time 2.56 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:21 PM PDT 24
Peak memory 220456 kb
Host smart-655f5d39-85f8-4386-a6b8-da125c575964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103500871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.103500871
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.2300334641
Short name T339
Test name
Test status
Simulation time 528534762 ps
CPU time 7.58 seconds
Started Jul 17 07:06:06 PM PDT 24
Finished Jul 17 07:06:16 PM PDT 24
Peak memory 218240 kb
Host smart-feb66914-9c4e-4de6-853c-537e0c50f26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300334641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.2300334641
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.1399956740
Short name T552
Test name
Test status
Simulation time 1470522580 ps
CPU time 4.95 seconds
Started Jul 17 07:06:04 PM PDT 24
Finished Jul 17 07:06:09 PM PDT 24
Peak memory 214388 kb
Host smart-62460789-e4be-467a-8e8c-202ddfc48989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399956740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1399956740
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.3631466450
Short name T748
Test name
Test status
Simulation time 286921736 ps
CPU time 2.08 seconds
Started Jul 17 07:06:08 PM PDT 24
Finished Jul 17 07:06:14 PM PDT 24
Peak memory 214300 kb
Host smart-3e51a4bc-748e-4cf8-b243-cef2474fe2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631466450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.3631466450
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_random.2184969134
Short name T370
Test name
Test status
Simulation time 639420948 ps
CPU time 5.38 seconds
Started Jul 17 07:06:05 PM PDT 24
Finished Jul 17 07:06:12 PM PDT 24
Peak memory 209180 kb
Host smart-9234a892-0626-42d9-b974-ec06f5630831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184969134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2184969134
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sideload.2357733737
Short name T830
Test name
Test status
Simulation time 80517381 ps
CPU time 2.51 seconds
Started Jul 17 07:06:04 PM PDT 24
Finished Jul 17 07:06:08 PM PDT 24
Peak memory 207496 kb
Host smart-f691cf43-11bb-446e-8ba0-ef1f26c9b430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357733737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.2357733737
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.2540780843
Short name T310
Test name
Test status
Simulation time 92654109 ps
CPU time 3.21 seconds
Started Jul 17 07:06:06 PM PDT 24
Finished Jul 17 07:06:12 PM PDT 24
Peak memory 208756 kb
Host smart-00409913-1239-4bfb-ab4f-67c0e129ea0a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540780843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.2540780843
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.1053543925
Short name T529
Test name
Test status
Simulation time 80767136 ps
CPU time 3.4 seconds
Started Jul 17 07:06:04 PM PDT 24
Finished Jul 17 07:06:08 PM PDT 24
Peak memory 206912 kb
Host smart-d32d0e26-bb3c-40dd-89fc-f46d2f27c54e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053543925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.1053543925
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.2712840388
Short name T627
Test name
Test status
Simulation time 4551896246 ps
CPU time 40.24 seconds
Started Jul 17 07:06:10 PM PDT 24
Finished Jul 17 07:06:58 PM PDT 24
Peak memory 208756 kb
Host smart-6eac3f94-c2e5-43db-bd98-7f3d53391555
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712840388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.2712840388
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.1813916553
Short name T635
Test name
Test status
Simulation time 733115249 ps
CPU time 3.68 seconds
Started Jul 17 07:06:05 PM PDT 24
Finished Jul 17 07:06:12 PM PDT 24
Peak memory 208316 kb
Host smart-7954dec1-aa91-46f1-9d80-d55be179ee12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813916553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.1813916553
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.2057972949
Short name T528
Test name
Test status
Simulation time 708658306 ps
CPU time 4.83 seconds
Started Jul 17 07:06:07 PM PDT 24
Finished Jul 17 07:06:14 PM PDT 24
Peak memory 206164 kb
Host smart-a2f32d04-99d9-4013-b40b-1078e8b4af11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057972949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.2057972949
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.1920414483
Short name T288
Test name
Test status
Simulation time 3349257755 ps
CPU time 75.63 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:07:36 PM PDT 24
Peak memory 215488 kb
Host smart-a05a9576-044b-4f3f-9304-60b4cbf0c9b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920414483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.1920414483
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.1949312428
Short name T755
Test name
Test status
Simulation time 11429539570 ps
CPU time 18.6 seconds
Started Jul 17 07:06:05 PM PDT 24
Finished Jul 17 07:06:26 PM PDT 24
Peak memory 222636 kb
Host smart-31b6b802-8f65-4f08-bb82-5881da4fb763
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949312428 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.1949312428
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.3940039535
Short name T272
Test name
Test status
Simulation time 103235378 ps
CPU time 2.83 seconds
Started Jul 17 07:06:04 PM PDT 24
Finished Jul 17 07:06:09 PM PDT 24
Peak memory 218236 kb
Host smart-df5d6afc-e4da-44ca-a43c-99d0a60b3eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940039535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.3940039535
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.4160792919
Short name T398
Test name
Test status
Simulation time 418681419 ps
CPU time 2.59 seconds
Started Jul 17 07:06:03 PM PDT 24
Finished Jul 17 07:06:06 PM PDT 24
Peak memory 210512 kb
Host smart-f5b3406a-ad72-4a26-8567-803c66dfe5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160792919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.4160792919
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.2329579477
Short name T565
Test name
Test status
Simulation time 22777699 ps
CPU time 0.73 seconds
Started Jul 17 07:09:44 PM PDT 24
Finished Jul 17 07:09:56 PM PDT 24
Peak memory 206008 kb
Host smart-7cfcacdd-9eda-42d0-8b8e-416aa4ccae71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329579477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.2329579477
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.646075745
Short name T438
Test name
Test status
Simulation time 235114968 ps
CPU time 12.7 seconds
Started Jul 17 07:09:45 PM PDT 24
Finished Jul 17 07:10:10 PM PDT 24
Peak memory 214332 kb
Host smart-74429303-1276-4cc4-8fb0-d4d29336d862
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=646075745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.646075745
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.408646526
Short name T246
Test name
Test status
Simulation time 160826932 ps
CPU time 2.93 seconds
Started Jul 17 07:09:45 PM PDT 24
Finished Jul 17 07:10:00 PM PDT 24
Peak memory 209564 kb
Host smart-4790c16c-f420-4fce-8fc6-e0177b40e4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408646526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.408646526
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.2545095569
Short name T79
Test name
Test status
Simulation time 273510289 ps
CPU time 2.96 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:09:50 PM PDT 24
Peak memory 210704 kb
Host smart-7a6c235e-a6a3-490d-8b58-a3b87a1e8e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545095569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.2545095569
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.700948724
Short name T822
Test name
Test status
Simulation time 40941783 ps
CPU time 2.38 seconds
Started Jul 17 07:09:42 PM PDT 24
Finished Jul 17 07:09:54 PM PDT 24
Peak memory 214552 kb
Host smart-c4e2ae97-c3da-4c16-b21a-7cb99372f028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700948724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.700948724
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.117086416
Short name T305
Test name
Test status
Simulation time 315516502 ps
CPU time 4.62 seconds
Started Jul 17 07:09:45 PM PDT 24
Finished Jul 17 07:10:01 PM PDT 24
Peak memory 206908 kb
Host smart-58cf913f-6b19-4ab2-a2d6-da9998cedf10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117086416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.117086416
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.491887671
Short name T671
Test name
Test status
Simulation time 257501129 ps
CPU time 1.66 seconds
Started Jul 17 07:09:43 PM PDT 24
Finished Jul 17 07:09:55 PM PDT 24
Peak memory 219272 kb
Host smart-aebbbe2d-e0d7-4a08-909e-6bb4cd73f42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491887671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.491887671
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.3918922800
Short name T662
Test name
Test status
Simulation time 114879848 ps
CPU time 3.88 seconds
Started Jul 17 07:09:43 PM PDT 24
Finished Jul 17 07:09:58 PM PDT 24
Peak memory 210100 kb
Host smart-764646ec-c64a-4d43-91f0-dd26ec2447f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918922800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.3918922800
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.2177819547
Short name T773
Test name
Test status
Simulation time 1242509866 ps
CPU time 17.28 seconds
Started Jul 17 07:09:46 PM PDT 24
Finished Jul 17 07:10:16 PM PDT 24
Peak memory 208628 kb
Host smart-84867a8d-3f49-490b-b99a-c44cbeaa451a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177819547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.2177819547
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.3851546849
Short name T296
Test name
Test status
Simulation time 116537943 ps
CPU time 2.29 seconds
Started Jul 17 07:09:43 PM PDT 24
Finished Jul 17 07:09:56 PM PDT 24
Peak memory 207452 kb
Host smart-1c214dd5-32bd-4f33-a8a1-61159fddeeb6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851546849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.3851546849
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.2974475237
Short name T917
Test name
Test status
Simulation time 34364429 ps
CPU time 2.22 seconds
Started Jul 17 07:09:46 PM PDT 24
Finished Jul 17 07:10:00 PM PDT 24
Peak memory 206948 kb
Host smart-f7519dff-ffdb-43db-b7f9-feb85d4277d2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974475237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.2974475237
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1656231418
Short name T314
Test name
Test status
Simulation time 619846324 ps
CPU time 2.81 seconds
Started Jul 17 07:09:44 PM PDT 24
Finished Jul 17 07:09:59 PM PDT 24
Peak memory 207008 kb
Host smart-b5504c48-7def-43b6-b871-15f42b87f8de
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656231418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1656231418
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.2434464561
Short name T537
Test name
Test status
Simulation time 1697646239 ps
CPU time 3.39 seconds
Started Jul 17 07:09:44 PM PDT 24
Finished Jul 17 07:09:58 PM PDT 24
Peak memory 208688 kb
Host smart-c8457866-a214-435f-9a6a-6106da9dc4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434464561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.2434464561
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.2452562805
Short name T807
Test name
Test status
Simulation time 66414229 ps
CPU time 2.89 seconds
Started Jul 17 07:09:42 PM PDT 24
Finished Jul 17 07:09:56 PM PDT 24
Peak memory 208276 kb
Host smart-4f8e7c90-f9b6-49a6-ad98-a6af82cea4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452562805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.2452562805
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.3738946416
Short name T214
Test name
Test status
Simulation time 1432483226 ps
CPU time 12.13 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:10:04 PM PDT 24
Peak memory 208608 kb
Host smart-12fab289-8761-498f-93a7-ccdbe6ef9a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738946416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.3738946416
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.3324339733
Short name T818
Test name
Test status
Simulation time 163385263 ps
CPU time 2.18 seconds
Started Jul 17 07:09:44 PM PDT 24
Finished Jul 17 07:09:58 PM PDT 24
Peak memory 209996 kb
Host smart-7f5d5b8b-a631-4da5-93e8-afc955fd4862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324339733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.3324339733
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.1283415657
Short name T670
Test name
Test status
Simulation time 12998263 ps
CPU time 0.71 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:09:50 PM PDT 24
Peak memory 205956 kb
Host smart-abe68e0c-5bc0-4a5f-9bd1-e1920c159072
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283415657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.1283415657
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.641393947
Short name T155
Test name
Test status
Simulation time 621309453 ps
CPU time 8.73 seconds
Started Jul 17 07:09:46 PM PDT 24
Finished Jul 17 07:10:07 PM PDT 24
Peak memory 214252 kb
Host smart-00f36e47-ecf8-4bb2-b003-12e54ff6c3c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=641393947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.641393947
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.2252048929
Short name T888
Test name
Test status
Simulation time 68654868 ps
CPU time 2.57 seconds
Started Jul 17 07:09:35 PM PDT 24
Finished Jul 17 07:09:38 PM PDT 24
Peak memory 222824 kb
Host smart-a068ca03-fcea-4789-a03e-a67e63db82cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252048929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.2252048929
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.3465783614
Short name T724
Test name
Test status
Simulation time 247331202 ps
CPU time 2.16 seconds
Started Jul 17 07:09:47 PM PDT 24
Finished Jul 17 07:10:01 PM PDT 24
Peak memory 208004 kb
Host smart-1fe01e68-2b6e-4210-a939-b5f0a9569a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465783614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3465783614
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.3181151980
Short name T105
Test name
Test status
Simulation time 324591725 ps
CPU time 7.61 seconds
Started Jul 17 07:09:43 PM PDT 24
Finished Jul 17 07:10:02 PM PDT 24
Peak memory 219184 kb
Host smart-a0271bbf-d393-49d9-aacd-ea1359ea0056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181151980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.3181151980
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.1548144564
Short name T646
Test name
Test status
Simulation time 161087824 ps
CPU time 3.38 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:09:51 PM PDT 24
Peak memory 220984 kb
Host smart-eb62b823-3092-4e0c-b15b-6c4dccecb4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548144564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.1548144564
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.563377620
Short name T489
Test name
Test status
Simulation time 83407829 ps
CPU time 3.44 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:09:51 PM PDT 24
Peak memory 207856 kb
Host smart-6f6a5479-4b4e-4159-b224-a7a11fa95ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563377620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.563377620
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.435265309
Short name T471
Test name
Test status
Simulation time 1494118561 ps
CPU time 11.77 seconds
Started Jul 17 07:09:46 PM PDT 24
Finished Jul 17 07:10:11 PM PDT 24
Peak memory 214080 kb
Host smart-4e5df0ef-2e71-4e23-917c-42954aeb1f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435265309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.435265309
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.1404553254
Short name T219
Test name
Test status
Simulation time 479714809 ps
CPU time 5.93 seconds
Started Jul 17 07:09:47 PM PDT 24
Finished Jul 17 07:10:05 PM PDT 24
Peak memory 208816 kb
Host smart-9176d2a4-2088-4545-bca3-06e5d3840586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404553254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.1404553254
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.1046600010
Short name T843
Test name
Test status
Simulation time 1708831762 ps
CPU time 42.46 seconds
Started Jul 17 07:09:46 PM PDT 24
Finished Jul 17 07:10:41 PM PDT 24
Peak memory 207780 kb
Host smart-651a91d2-e4ce-4191-b574-c1ff399223d2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046600010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.1046600010
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.1437058488
Short name T685
Test name
Test status
Simulation time 678740783 ps
CPU time 7.5 seconds
Started Jul 17 07:09:45 PM PDT 24
Finished Jul 17 07:10:05 PM PDT 24
Peak memory 208088 kb
Host smart-8f8b41f0-b48e-47ef-96fe-6f76186f24f6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437058488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.1437058488
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.2440640628
Short name T754
Test name
Test status
Simulation time 712519656 ps
CPU time 3.06 seconds
Started Jul 17 07:09:48 PM PDT 24
Finished Jul 17 07:10:02 PM PDT 24
Peak memory 208684 kb
Host smart-dfc0b8f4-0f65-4872-9c8e-1e1ba5ea8f4d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440640628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.2440640628
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.4012445553
Short name T419
Test name
Test status
Simulation time 565250157 ps
CPU time 3.3 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:09:52 PM PDT 24
Peak memory 215780 kb
Host smart-17e720d2-5d58-4645-982c-7b1fe271d378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012445553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.4012445553
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.1224257745
Short name T221
Test name
Test status
Simulation time 188523641 ps
CPU time 5.86 seconds
Started Jul 17 07:09:44 PM PDT 24
Finished Jul 17 07:10:00 PM PDT 24
Peak memory 208416 kb
Host smart-a80ca2af-3f73-429d-86d2-4bb91820b38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224257745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.1224257745
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.1709006084
Short name T337
Test name
Test status
Simulation time 209788167 ps
CPU time 5.77 seconds
Started Jul 17 07:09:43 PM PDT 24
Finished Jul 17 07:10:00 PM PDT 24
Peak memory 207552 kb
Host smart-c75c2f3e-c706-4414-84dd-6ed1b57baf91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709006084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.1709006084
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.2783954359
Short name T509
Test name
Test status
Simulation time 619605294 ps
CPU time 2.28 seconds
Started Jul 17 07:09:39 PM PDT 24
Finished Jul 17 07:09:46 PM PDT 24
Peak memory 210384 kb
Host smart-b686d805-7a0f-49b5-9b29-8112260f0c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783954359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.2783954359
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.2974387862
Short name T549
Test name
Test status
Simulation time 261861624 ps
CPU time 1.02 seconds
Started Jul 17 07:09:45 PM PDT 24
Finished Jul 17 07:09:58 PM PDT 24
Peak memory 205900 kb
Host smart-16e0bc08-0707-4a15-bb64-1bf4407355ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974387862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.2974387862
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.2963321790
Short name T285
Test name
Test status
Simulation time 51052138 ps
CPU time 3.62 seconds
Started Jul 17 07:09:42 PM PDT 24
Finished Jul 17 07:09:56 PM PDT 24
Peak memory 215388 kb
Host smart-ed349a46-4af6-4383-bbfb-c7d37e63bdb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2963321790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2963321790
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.1982031454
Short name T328
Test name
Test status
Simulation time 129853569 ps
CPU time 3.73 seconds
Started Jul 17 07:09:44 PM PDT 24
Finished Jul 17 07:09:59 PM PDT 24
Peak memory 210748 kb
Host smart-35fd24c4-594a-4bdd-82f0-40973a630076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982031454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.1982031454
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.2975792610
Short name T676
Test name
Test status
Simulation time 259631603 ps
CPU time 3.23 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:09:52 PM PDT 24
Peak memory 217320 kb
Host smart-2c45b9f6-885e-476f-9ccd-dd9980d18941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975792610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.2975792610
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.1095004433
Short name T231
Test name
Test status
Simulation time 66259629 ps
CPU time 3.79 seconds
Started Jul 17 07:09:43 PM PDT 24
Finished Jul 17 07:09:58 PM PDT 24
Peak memory 214328 kb
Host smart-5730bab2-f494-41ef-b350-4ec0efa48afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095004433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.1095004433
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.1799707164
Short name T893
Test name
Test status
Simulation time 472649372 ps
CPU time 2.78 seconds
Started Jul 17 07:09:43 PM PDT 24
Finished Jul 17 07:09:57 PM PDT 24
Peak memory 215464 kb
Host smart-72e60d1b-e10e-4edf-b711-1e3633f42f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799707164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.1799707164
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.1332779538
Short name T630
Test name
Test status
Simulation time 426345279 ps
CPU time 4.54 seconds
Started Jul 17 07:09:40 PM PDT 24
Finished Jul 17 07:09:51 PM PDT 24
Peak memory 216868 kb
Host smart-e3b9f7cf-5483-47c1-af4c-2a9649e8cc06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332779538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.1332779538
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.4006416379
Short name T358
Test name
Test status
Simulation time 123927909 ps
CPU time 3.78 seconds
Started Jul 17 07:09:40 PM PDT 24
Finished Jul 17 07:09:50 PM PDT 24
Peak memory 208688 kb
Host smart-472c2b70-7b43-45d8-9cb6-4a2335e5702f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006416379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.4006416379
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.2199499188
Short name T741
Test name
Test status
Simulation time 3091921927 ps
CPU time 58.28 seconds
Started Jul 17 07:09:39 PM PDT 24
Finished Jul 17 07:10:42 PM PDT 24
Peak memory 209072 kb
Host smart-86f81f6a-b003-4c00-9e15-6055b50c5dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199499188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.2199499188
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.2101106455
Short name T775
Test name
Test status
Simulation time 146094460 ps
CPU time 3.56 seconds
Started Jul 17 07:09:39 PM PDT 24
Finished Jul 17 07:09:44 PM PDT 24
Peak memory 209036 kb
Host smart-0f1ee256-e047-4831-97dc-0e1a39b3a07f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101106455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.2101106455
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.3190013864
Short name T563
Test name
Test status
Simulation time 227898973 ps
CPU time 2.51 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:09:51 PM PDT 24
Peak memory 207000 kb
Host smart-f26a0df0-0fe6-496b-bb9f-6b9bdd3a7884
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190013864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.3190013864
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.1630616039
Short name T486
Test name
Test status
Simulation time 71942299 ps
CPU time 3.22 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:09:55 PM PDT 24
Peak memory 208048 kb
Host smart-6160c1ac-12dc-4028-9726-ea6d9025867e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630616039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.1630616039
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.1572010713
Short name T290
Test name
Test status
Simulation time 1871887242 ps
CPU time 8.2 seconds
Started Jul 17 07:09:44 PM PDT 24
Finished Jul 17 07:10:04 PM PDT 24
Peak memory 218108 kb
Host smart-07fdc31b-f99f-4d08-b86a-d16369b23c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572010713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.1572010713
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.2385695127
Short name T495
Test name
Test status
Simulation time 80968931 ps
CPU time 2.8 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:09:51 PM PDT 24
Peak memory 206044 kb
Host smart-8b2df48a-6b87-4ad0-816a-799a0e999365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385695127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2385695127
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.3081861641
Short name T442
Test name
Test status
Simulation time 1244246009 ps
CPU time 30.13 seconds
Started Jul 17 07:09:45 PM PDT 24
Finished Jul 17 07:10:27 PM PDT 24
Peak memory 216336 kb
Host smart-756f0b23-bfc7-4e92-a8b0-b78db6f984d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081861641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.3081861641
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.2049100088
Short name T750
Test name
Test status
Simulation time 433873138 ps
CPU time 20.5 seconds
Started Jul 17 07:09:43 PM PDT 24
Finished Jul 17 07:10:15 PM PDT 24
Peak memory 221132 kb
Host smart-490fc79c-d586-41b0-9961-40704847f72e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049100088 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.2049100088
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.2714207687
Short name T564
Test name
Test status
Simulation time 148601456 ps
CPU time 5.1 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:09:56 PM PDT 24
Peak memory 208696 kb
Host smart-3532c077-761c-4c67-b057-3cf1a1579923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714207687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.2714207687
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.3777560701
Short name T175
Test name
Test status
Simulation time 119074450 ps
CPU time 3.54 seconds
Started Jul 17 07:09:42 PM PDT 24
Finished Jul 17 07:09:55 PM PDT 24
Peak memory 210972 kb
Host smart-81684078-72b6-4beb-8ac6-0f9243f6742b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777560701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.3777560701
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.2638182083
Short name T530
Test name
Test status
Simulation time 109001170 ps
CPU time 0.78 seconds
Started Jul 17 07:09:44 PM PDT 24
Finished Jul 17 07:09:56 PM PDT 24
Peak memory 205984 kb
Host smart-673d264d-563d-4301-8afe-efdfcb2ff05f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638182083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.2638182083
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.3102099971
Short name T236
Test name
Test status
Simulation time 51932077 ps
CPU time 1.95 seconds
Started Jul 17 07:09:43 PM PDT 24
Finished Jul 17 07:09:56 PM PDT 24
Peak memory 216384 kb
Host smart-98af5329-0623-489a-8311-b0916b5129ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102099971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.3102099971
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.4161685779
Short name T52
Test name
Test status
Simulation time 1215995885 ps
CPU time 11.99 seconds
Started Jul 17 07:09:45 PM PDT 24
Finished Jul 17 07:10:09 PM PDT 24
Peak memory 209392 kb
Host smart-96af51c2-50a7-46a0-9fbf-14c541d1d59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161685779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.4161685779
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.2943345232
Short name T721
Test name
Test status
Simulation time 396997201 ps
CPU time 2.62 seconds
Started Jul 17 07:09:45 PM PDT 24
Finished Jul 17 07:10:00 PM PDT 24
Peak memory 214236 kb
Host smart-a84997a1-8c76-4825-bbd2-dc2ca62b0ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943345232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.2943345232
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.4144814955
Short name T479
Test name
Test status
Simulation time 110963227 ps
CPU time 4.25 seconds
Started Jul 17 07:09:45 PM PDT 24
Finished Jul 17 07:10:01 PM PDT 24
Peak memory 222520 kb
Host smart-146d6929-a7d7-47b9-a32f-7716e909f044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144814955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.4144814955
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_random.2934632523
Short name T739
Test name
Test status
Simulation time 103304961 ps
CPU time 4.46 seconds
Started Jul 17 07:09:42 PM PDT 24
Finished Jul 17 07:09:57 PM PDT 24
Peak memory 209576 kb
Host smart-267c0885-a5e2-4858-8833-21c14666ba06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934632523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.2934632523
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.3854296679
Short name T260
Test name
Test status
Simulation time 6363428824 ps
CPU time 44.42 seconds
Started Jul 17 07:09:44 PM PDT 24
Finished Jul 17 07:10:39 PM PDT 24
Peak memory 208908 kb
Host smart-9b3b5c61-060a-4cfd-b706-e05009d25116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854296679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.3854296679
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.3407317781
Short name T578
Test name
Test status
Simulation time 2146834827 ps
CPU time 19.6 seconds
Started Jul 17 07:09:43 PM PDT 24
Finished Jul 17 07:10:14 PM PDT 24
Peak memory 208556 kb
Host smart-65f41ade-5a80-4163-99d5-9a1e6286d463
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407317781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.3407317781
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.222115754
Short name T816
Test name
Test status
Simulation time 296232514 ps
CPU time 3.1 seconds
Started Jul 17 07:09:44 PM PDT 24
Finished Jul 17 07:10:00 PM PDT 24
Peak memory 206956 kb
Host smart-d1f47ea6-c14a-4e3a-82ac-2dc676edb11d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222115754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.222115754
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.3385496639
Short name T603
Test name
Test status
Simulation time 43699252 ps
CPU time 2.48 seconds
Started Jul 17 07:09:44 PM PDT 24
Finished Jul 17 07:09:58 PM PDT 24
Peak memory 206884 kb
Host smart-7dc51423-1ea5-45eb-bf69-735d7c40e608
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385496639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.3385496639
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.2205393804
Short name T435
Test name
Test status
Simulation time 53211949 ps
CPU time 1.93 seconds
Started Jul 17 07:09:44 PM PDT 24
Finished Jul 17 07:09:57 PM PDT 24
Peak memory 208348 kb
Host smart-1e58ceb9-5269-450f-9de0-5b4279c846e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205393804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.2205393804
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.2072270689
Short name T701
Test name
Test status
Simulation time 74489354 ps
CPU time 3.33 seconds
Started Jul 17 07:09:47 PM PDT 24
Finished Jul 17 07:10:02 PM PDT 24
Peak memory 208716 kb
Host smart-51e8e7d9-5c71-4f3c-bc61-15fc32e84ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072270689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.2072270689
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.1267602491
Short name T883
Test name
Test status
Simulation time 2921542769 ps
CPU time 22.25 seconds
Started Jul 17 07:09:44 PM PDT 24
Finished Jul 17 07:10:18 PM PDT 24
Peak memory 219568 kb
Host smart-ffbdcc19-f2b6-475c-8172-b9b201b1a0a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267602491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.1267602491
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.2588561035
Short name T134
Test name
Test status
Simulation time 754172698 ps
CPU time 21.68 seconds
Started Jul 17 07:09:44 PM PDT 24
Finished Jul 17 07:10:16 PM PDT 24
Peak memory 222604 kb
Host smart-af3927da-7506-4404-a242-19d9de95ef35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588561035 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.2588561035
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.2508308725
Short name T433
Test name
Test status
Simulation time 79946008 ps
CPU time 4.05 seconds
Started Jul 17 07:09:42 PM PDT 24
Finished Jul 17 07:09:57 PM PDT 24
Peak memory 209424 kb
Host smart-f338759b-384c-4350-bd85-52673a52c2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508308725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.2508308725
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.1298998349
Short name T182
Test name
Test status
Simulation time 34497737 ps
CPU time 2.11 seconds
Started Jul 17 07:09:45 PM PDT 24
Finished Jul 17 07:09:59 PM PDT 24
Peak memory 209996 kb
Host smart-2268ede8-8921-4ef9-9b47-8f5a9fd6af7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298998349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1298998349
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.95770090
Short name T832
Test name
Test status
Simulation time 33983957 ps
CPU time 0.74 seconds
Started Jul 17 07:09:39 PM PDT 24
Finished Jul 17 07:09:42 PM PDT 24
Peak memory 205920 kb
Host smart-5b836dad-74de-4628-a12d-9bad93cb9f9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95770090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.95770090
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.2757397664
Short name T427
Test name
Test status
Simulation time 652970288 ps
CPU time 9.45 seconds
Started Jul 17 07:09:47 PM PDT 24
Finished Jul 17 07:10:09 PM PDT 24
Peak memory 214348 kb
Host smart-88447330-1414-40df-8727-0d9721547df0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2757397664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.2757397664
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.3205014733
Short name T752
Test name
Test status
Simulation time 136916355 ps
CPU time 3.7 seconds
Started Jul 17 07:09:38 PM PDT 24
Finished Jul 17 07:09:43 PM PDT 24
Peak memory 221860 kb
Host smart-a2586b08-4c6d-453e-a77a-8225045e8abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205014733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3205014733
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.981722832
Short name T834
Test name
Test status
Simulation time 1378745049 ps
CPU time 18.29 seconds
Started Jul 17 07:09:39 PM PDT 24
Finished Jul 17 07:10:00 PM PDT 24
Peak memory 208520 kb
Host smart-92eff191-990a-4e13-9900-eb01c4b68861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981722832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.981722832
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.370262383
Short name T23
Test name
Test status
Simulation time 1267768060 ps
CPU time 16.39 seconds
Started Jul 17 07:09:44 PM PDT 24
Finished Jul 17 07:10:12 PM PDT 24
Peak memory 209056 kb
Host smart-0421b203-7aa3-4cae-8565-d977bc303a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370262383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.370262383
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.4148123288
Short name T195
Test name
Test status
Simulation time 274529139 ps
CPU time 3.77 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:09:52 PM PDT 24
Peak memory 221184 kb
Host smart-bfb9c4a6-95f9-478e-809e-3bc93ffa46f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148123288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.4148123288
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.2171951584
Short name T725
Test name
Test status
Simulation time 237699668 ps
CPU time 2.41 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:09:51 PM PDT 24
Peak memory 209856 kb
Host smart-16058464-6136-4efd-ac15-c7740125445f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171951584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.2171951584
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.385097410
Short name T745
Test name
Test status
Simulation time 964103807 ps
CPU time 5.67 seconds
Started Jul 17 07:09:47 PM PDT 24
Finished Jul 17 07:10:05 PM PDT 24
Peak memory 208224 kb
Host smart-e4bfc093-5f43-4abd-98c3-75a924cc0c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385097410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.385097410
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.2906331525
Short name T763
Test name
Test status
Simulation time 291872581 ps
CPU time 3.15 seconds
Started Jul 17 07:09:47 PM PDT 24
Finished Jul 17 07:10:02 PM PDT 24
Peak memory 206824 kb
Host smart-d5efec03-15cb-4280-860f-9a8ea7740ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906331525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2906331525
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1982252202
Short name T511
Test name
Test status
Simulation time 1708349122 ps
CPU time 49.92 seconds
Started Jul 17 07:09:46 PM PDT 24
Finished Jul 17 07:10:48 PM PDT 24
Peak memory 208688 kb
Host smart-ce8ad696-5c21-49da-8791-cdc9e6a9dd44
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982252202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1982252202
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.2666985229
Short name T790
Test name
Test status
Simulation time 539284663 ps
CPU time 3.02 seconds
Started Jul 17 07:09:46 PM PDT 24
Finished Jul 17 07:10:02 PM PDT 24
Peak memory 208664 kb
Host smart-e5567696-85f6-474e-943a-3a7c74c2dd07
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666985229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.2666985229
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.91525581
Short name T84
Test name
Test status
Simulation time 40557967 ps
CPU time 1.83 seconds
Started Jul 17 07:09:46 PM PDT 24
Finished Jul 17 07:10:01 PM PDT 24
Peak memory 207260 kb
Host smart-517dd15a-a77b-4b96-a2be-370212359013
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91525581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.91525581
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.1338871081
Short name T905
Test name
Test status
Simulation time 168711569 ps
CPU time 2.08 seconds
Started Jul 17 07:09:39 PM PDT 24
Finished Jul 17 07:09:45 PM PDT 24
Peak memory 207388 kb
Host smart-051ebfdd-8d89-4a72-8ec9-ed6632f1dbf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338871081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.1338871081
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.367136069
Short name T813
Test name
Test status
Simulation time 200535300 ps
CPU time 2.81 seconds
Started Jul 17 07:09:47 PM PDT 24
Finished Jul 17 07:10:02 PM PDT 24
Peak memory 206044 kb
Host smart-a45275ba-7624-4be4-a77c-e0245cec6346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367136069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.367136069
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.4083222350
Short name T371
Test name
Test status
Simulation time 190525824 ps
CPU time 9.55 seconds
Started Jul 17 07:09:35 PM PDT 24
Finished Jul 17 07:09:45 PM PDT 24
Peak memory 215556 kb
Host smart-76e45049-6d96-4b68-b185-10fbdc347711
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083222350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.4083222350
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.1099434487
Short name T872
Test name
Test status
Simulation time 421589033 ps
CPU time 4.86 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:09:54 PM PDT 24
Peak memory 210152 kb
Host smart-38a88974-bb41-401e-a944-95d21b4380b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099434487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.1099434487
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.3062828093
Short name T723
Test name
Test status
Simulation time 66781611 ps
CPU time 2.99 seconds
Started Jul 17 07:09:38 PM PDT 24
Finished Jul 17 07:09:43 PM PDT 24
Peak memory 210212 kb
Host smart-459c3b0f-1de5-4be9-8c1c-bed6c99cbebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062828093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.3062828093
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.1077082584
Short name T907
Test name
Test status
Simulation time 23457080 ps
CPU time 0.86 seconds
Started Jul 17 07:09:47 PM PDT 24
Finished Jul 17 07:10:00 PM PDT 24
Peak memory 206012 kb
Host smart-f81f6587-6beb-4502-923f-ba3f83685675
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077082584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.1077082584
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.18012140
Short name T408
Test name
Test status
Simulation time 38894699 ps
CPU time 2.68 seconds
Started Jul 17 07:09:44 PM PDT 24
Finished Jul 17 07:09:57 PM PDT 24
Peak memory 214348 kb
Host smart-9ce9a3f1-6771-4d84-a01e-7c13b482721c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=18012140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.18012140
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.3572974308
Short name T25
Test name
Test status
Simulation time 252197696 ps
CPU time 1.44 seconds
Started Jul 17 07:09:46 PM PDT 24
Finished Jul 17 07:09:59 PM PDT 24
Peak memory 220540 kb
Host smart-546aca62-ee0b-41ca-bb8e-0615293207c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572974308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.3572974308
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.2217096365
Short name T375
Test name
Test status
Simulation time 79261583 ps
CPU time 3.72 seconds
Started Jul 17 07:09:43 PM PDT 24
Finished Jul 17 07:09:57 PM PDT 24
Peak memory 209232 kb
Host smart-c2aa8564-a5cf-4f43-813b-3becb0ccd147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217096365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2217096365
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.1582522233
Short name T324
Test name
Test status
Simulation time 146134275 ps
CPU time 3.82 seconds
Started Jul 17 07:09:46 PM PDT 24
Finished Jul 17 07:10:02 PM PDT 24
Peak memory 214280 kb
Host smart-133a81c5-5f5b-47cd-8e96-02d5ef86bfa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582522233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1582522233
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.87608671
Short name T885
Test name
Test status
Simulation time 491112589 ps
CPU time 5.34 seconds
Started Jul 17 07:09:43 PM PDT 24
Finished Jul 17 07:10:00 PM PDT 24
Peak memory 222460 kb
Host smart-d23af9c3-a222-4ebc-a0be-72c8637ec09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87608671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.87608671
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.2117530732
Short name T478
Test name
Test status
Simulation time 308149150 ps
CPU time 4.2 seconds
Started Jul 17 07:09:38 PM PDT 24
Finished Jul 17 07:09:45 PM PDT 24
Peak memory 218276 kb
Host smart-8585cd90-3eeb-4665-bc6a-0add9fd741bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117530732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.2117530732
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.3747654758
Short name T382
Test name
Test status
Simulation time 181764989 ps
CPU time 4.61 seconds
Started Jul 17 07:09:39 PM PDT 24
Finished Jul 17 07:09:47 PM PDT 24
Peak memory 208632 kb
Host smart-4701e02a-8016-460c-ad81-8a8d4edd559d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747654758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.3747654758
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.4091417177
Short name T769
Test name
Test status
Simulation time 1664564271 ps
CPU time 48.77 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:10:37 PM PDT 24
Peak memory 207984 kb
Host smart-bfe69ac3-f0c4-4a27-b565-fc64899bd3e8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091417177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.4091417177
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.2095533577
Short name T558
Test name
Test status
Simulation time 101389955 ps
CPU time 4.3 seconds
Started Jul 17 07:09:44 PM PDT 24
Finished Jul 17 07:10:00 PM PDT 24
Peak memory 208568 kb
Host smart-fcb3705d-1d7d-46a3-9dcd-33e3a07977f2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095533577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.2095533577
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.4161294011
Short name T477
Test name
Test status
Simulation time 1112366579 ps
CPU time 14.27 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:10:06 PM PDT 24
Peak memory 208204 kb
Host smart-ff1aeafa-474a-41bb-a35d-1077fc6fbec6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161294011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.4161294011
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.903977375
Short name T689
Test name
Test status
Simulation time 406567853 ps
CPU time 3.05 seconds
Started Jul 17 07:09:49 PM PDT 24
Finished Jul 17 07:10:03 PM PDT 24
Peak memory 209868 kb
Host smart-1dfb02f2-2d54-4ada-88b7-ba75999d4637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903977375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.903977375
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.1542279118
Short name T410
Test name
Test status
Simulation time 337917780 ps
CPU time 2.9 seconds
Started Jul 17 07:09:39 PM PDT 24
Finished Jul 17 07:09:46 PM PDT 24
Peak memory 207012 kb
Host smart-3c486ec0-27e8-4d47-a4a0-2433d2aefc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542279118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.1542279118
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.858301298
Short name T361
Test name
Test status
Simulation time 2369811266 ps
CPU time 51.95 seconds
Started Jul 17 07:09:43 PM PDT 24
Finished Jul 17 07:10:46 PM PDT 24
Peak memory 222120 kb
Host smart-ee0ab748-9cfa-4c30-9b8f-86d2bcf7075f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858301298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.858301298
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3193887529
Short name T675
Test name
Test status
Simulation time 148737487 ps
CPU time 2.73 seconds
Started Jul 17 07:09:43 PM PDT 24
Finished Jul 17 07:09:57 PM PDT 24
Peak memory 209596 kb
Host smart-f409b098-d998-413d-99c3-edbd596fff7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193887529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3193887529
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.3004698802
Short name T589
Test name
Test status
Simulation time 1394874563 ps
CPU time 7.53 seconds
Started Jul 17 07:11:16 PM PDT 24
Finished Jul 17 07:11:24 PM PDT 24
Peak memory 210932 kb
Host smart-a16d7434-6a75-4bc1-90c1-763d5d7f0432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004698802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.3004698802
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.4164350629
Short name T657
Test name
Test status
Simulation time 198484872 ps
CPU time 0.81 seconds
Started Jul 17 07:09:47 PM PDT 24
Finished Jul 17 07:10:00 PM PDT 24
Peak memory 205976 kb
Host smart-e00a9eb6-d328-469f-909d-a1a8b0bb335c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164350629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.4164350629
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.2852787300
Short name T294
Test name
Test status
Simulation time 460606098 ps
CPU time 3.78 seconds
Started Jul 17 07:09:45 PM PDT 24
Finished Jul 17 07:10:00 PM PDT 24
Peak memory 214404 kb
Host smart-ca9f6f95-0aa1-4af4-aead-77ce8d375c6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2852787300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.2852787300
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.2686091346
Short name T777
Test name
Test status
Simulation time 89828386 ps
CPU time 3.93 seconds
Started Jul 17 07:09:45 PM PDT 24
Finished Jul 17 07:10:01 PM PDT 24
Peak memory 217220 kb
Host smart-04796d00-b473-4251-98fc-d1c9dd848fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686091346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2686091346
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.3755204476
Short name T677
Test name
Test status
Simulation time 46271183 ps
CPU time 2.89 seconds
Started Jul 17 07:09:45 PM PDT 24
Finished Jul 17 07:10:00 PM PDT 24
Peak memory 214532 kb
Host smart-bde4c83e-f532-451a-a021-767470af56fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755204476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.3755204476
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.2102651861
Short name T104
Test name
Test status
Simulation time 125978669 ps
CPU time 2.7 seconds
Started Jul 17 07:09:45 PM PDT 24
Finished Jul 17 07:09:59 PM PDT 24
Peak memory 221612 kb
Host smart-41d980aa-9e41-407e-a571-2d5648fa7240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102651861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.2102651861
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.1966056898
Short name T844
Test name
Test status
Simulation time 658931034 ps
CPU time 6.72 seconds
Started Jul 17 07:09:44 PM PDT 24
Finished Jul 17 07:10:02 PM PDT 24
Peak memory 222620 kb
Host smart-36c99daf-846d-4d9c-94a9-de5c742e361e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966056898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.1966056898
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.3163677650
Short name T64
Test name
Test status
Simulation time 629006537 ps
CPU time 5.55 seconds
Started Jul 17 07:09:45 PM PDT 24
Finished Jul 17 07:10:03 PM PDT 24
Peak memory 220508 kb
Host smart-61069fd3-c4c5-4f20-b8d7-45bca902452f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163677650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3163677650
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.4204896157
Short name T393
Test name
Test status
Simulation time 153616868 ps
CPU time 6.25 seconds
Started Jul 17 07:09:44 PM PDT 24
Finished Jul 17 07:10:02 PM PDT 24
Peak memory 218584 kb
Host smart-f70491cc-24ec-4f1b-85ef-7e176313c6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204896157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.4204896157
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.3665629848
Short name T115
Test name
Test status
Simulation time 106496787 ps
CPU time 4.06 seconds
Started Jul 17 07:09:45 PM PDT 24
Finished Jul 17 07:10:01 PM PDT 24
Peak memory 206896 kb
Host smart-714975c3-790f-4e69-ae94-b6725f1c1af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665629848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.3665629848
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.3117172684
Short name T575
Test name
Test status
Simulation time 184208081 ps
CPU time 6.95 seconds
Started Jul 17 07:09:45 PM PDT 24
Finished Jul 17 07:10:04 PM PDT 24
Peak memory 208624 kb
Host smart-cd9634bf-5e81-4f20-b3b3-c45dd6f4731a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117172684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.3117172684
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.726744939
Short name T329
Test name
Test status
Simulation time 2190709525 ps
CPU time 13.46 seconds
Started Jul 17 07:09:42 PM PDT 24
Finished Jul 17 07:10:05 PM PDT 24
Peak memory 208856 kb
Host smart-0f3ee0cd-6e71-4c7b-8b44-e9a879ff2338
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726744939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.726744939
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.2939771464
Short name T504
Test name
Test status
Simulation time 80205326 ps
CPU time 1.81 seconds
Started Jul 17 07:09:42 PM PDT 24
Finished Jul 17 07:09:55 PM PDT 24
Peak memory 206748 kb
Host smart-2aea816c-30bf-4f5f-bf64-0c010ae7d509
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939771464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.2939771464
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2123661450
Short name T367
Test name
Test status
Simulation time 197944255 ps
CPU time 3.8 seconds
Started Jul 17 07:09:46 PM PDT 24
Finished Jul 17 07:10:02 PM PDT 24
Peak memory 214480 kb
Host smart-2c09e541-866d-4c50-9150-589a3cba8850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123661450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2123661450
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.1553578939
Short name T796
Test name
Test status
Simulation time 492926640 ps
CPU time 9.02 seconds
Started Jul 17 07:09:43 PM PDT 24
Finished Jul 17 07:10:03 PM PDT 24
Peak memory 208500 kb
Host smart-ca1042bb-15b4-4487-920a-e1d2bab7373d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553578939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.1553578939
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.2481898740
Short name T561
Test name
Test status
Simulation time 1892858007 ps
CPU time 31.74 seconds
Started Jul 17 07:09:46 PM PDT 24
Finished Jul 17 07:10:30 PM PDT 24
Peak memory 219796 kb
Host smart-e297c121-a17c-447a-ba35-7513a376a79f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481898740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2481898740
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.3362144610
Short name T672
Test name
Test status
Simulation time 614918809 ps
CPU time 5.72 seconds
Started Jul 17 07:09:45 PM PDT 24
Finished Jul 17 07:10:03 PM PDT 24
Peak memory 210204 kb
Host smart-183f336c-4872-41d0-8f54-4f357ce8cde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362144610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3362144610
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.1965275935
Short name T850
Test name
Test status
Simulation time 27032545 ps
CPU time 1.86 seconds
Started Jul 17 07:09:47 PM PDT 24
Finished Jul 17 07:10:01 PM PDT 24
Peak memory 209896 kb
Host smart-8bb05f79-368a-40e9-bb25-58d9238f71e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965275935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1965275935
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.507561359
Short name T447
Test name
Test status
Simulation time 124854793 ps
CPU time 0.76 seconds
Started Jul 17 07:09:42 PM PDT 24
Finished Jul 17 07:09:53 PM PDT 24
Peak memory 206008 kb
Host smart-ef31550b-73b6-46a3-be95-1804ffdd48ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507561359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.507561359
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.2284141457
Short name T227
Test name
Test status
Simulation time 182279422 ps
CPU time 8.71 seconds
Started Jul 17 07:09:39 PM PDT 24
Finished Jul 17 07:09:51 PM PDT 24
Peak memory 222480 kb
Host smart-a8d61099-52b5-4cf2-b467-08265efe9b6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2284141457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.2284141457
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.2229444573
Short name T29
Test name
Test status
Simulation time 1495249205 ps
CPU time 12.3 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:10:04 PM PDT 24
Peak memory 222852 kb
Host smart-d17bcdc7-6dd6-42e0-a9d5-b9dde1ff6739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229444573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.2229444573
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.4272225697
Short name T611
Test name
Test status
Simulation time 460274942 ps
CPU time 11.12 seconds
Started Jul 17 07:09:40 PM PDT 24
Finished Jul 17 07:09:56 PM PDT 24
Peak memory 209808 kb
Host smart-5708ba67-8e22-42a7-91f0-3d42c663ed10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272225697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.4272225697
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.3735308836
Short name T918
Test name
Test status
Simulation time 130654431 ps
CPU time 3.2 seconds
Started Jul 17 07:09:39 PM PDT 24
Finished Jul 17 07:09:44 PM PDT 24
Peak memory 218796 kb
Host smart-84284754-a2ef-4475-b443-51b06722d72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735308836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.3735308836
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.4129840574
Short name T765
Test name
Test status
Simulation time 81942504 ps
CPU time 1.55 seconds
Started Jul 17 07:09:39 PM PDT 24
Finished Jul 17 07:09:45 PM PDT 24
Peak memory 214268 kb
Host smart-50114c80-d683-4bfe-be7a-d1707b7662de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129840574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.4129840574
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.3889851772
Short name T852
Test name
Test status
Simulation time 315809808 ps
CPU time 4.42 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:09:53 PM PDT 24
Peak memory 214420 kb
Host smart-f0cc7daa-cffd-4ea2-8f11-475f99eab276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889851772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.3889851772
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.2397996281
Short name T217
Test name
Test status
Simulation time 2154615318 ps
CPU time 32.78 seconds
Started Jul 17 07:09:42 PM PDT 24
Finished Jul 17 07:10:25 PM PDT 24
Peak memory 209580 kb
Host smart-5ff28d31-1ade-450c-b32d-057b7ad94a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397996281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.2397996281
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1101252058
Short name T626
Test name
Test status
Simulation time 193214022 ps
CPU time 7.19 seconds
Started Jul 17 07:09:47 PM PDT 24
Finished Jul 17 07:10:06 PM PDT 24
Peak memory 207944 kb
Host smart-c6ca8a16-a6dd-4093-9711-5f3387157fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101252058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1101252058
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.1169739727
Short name T781
Test name
Test status
Simulation time 200444767 ps
CPU time 5.06 seconds
Started Jul 17 07:09:39 PM PDT 24
Finished Jul 17 07:09:48 PM PDT 24
Peak memory 207896 kb
Host smart-196c3f4b-4ed3-493c-bec6-91dd585751e0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169739727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.1169739727
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.3294610278
Short name T390
Test name
Test status
Simulation time 5348577395 ps
CPU time 27.15 seconds
Started Jul 17 07:09:43 PM PDT 24
Finished Jul 17 07:10:21 PM PDT 24
Peak memory 208380 kb
Host smart-05a96b14-fd8c-4b94-aa5c-995aa86218a1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294610278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.3294610278
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.4250966442
Short name T557
Test name
Test status
Simulation time 1072962774 ps
CPU time 7.27 seconds
Started Jul 17 07:09:39 PM PDT 24
Finished Jul 17 07:09:50 PM PDT 24
Peak memory 208844 kb
Host smart-68cf9ff1-887c-4273-ae0b-5bfb4d1e8cc0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250966442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.4250966442
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.1327758680
Short name T817
Test name
Test status
Simulation time 290539893 ps
CPU time 2.76 seconds
Started Jul 17 07:09:40 PM PDT 24
Finished Jul 17 07:09:47 PM PDT 24
Peak memory 214316 kb
Host smart-8b37697e-bfdb-4fda-9660-93cc4d8a4a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327758680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.1327758680
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.1436363926
Short name T567
Test name
Test status
Simulation time 388756442 ps
CPU time 2.9 seconds
Started Jul 17 07:09:46 PM PDT 24
Finished Jul 17 07:10:02 PM PDT 24
Peak memory 206824 kb
Host smart-a388c943-f205-4416-ba65-7a285fa85e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436363926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.1436363926
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.3507432311
Short name T715
Test name
Test status
Simulation time 1409325465 ps
CPU time 14.88 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:10:04 PM PDT 24
Peak memory 214928 kb
Host smart-8392b912-290a-4d07-8786-47c4a51abe65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507432311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.3507432311
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.785074095
Short name T759
Test name
Test status
Simulation time 495462201 ps
CPU time 21.04 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:10:11 PM PDT 24
Peak memory 222432 kb
Host smart-b575aac0-f59f-4849-a33f-3af852b7a05d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785074095 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.785074095
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.767881937
Short name T270
Test name
Test status
Simulation time 387709604 ps
CPU time 6.25 seconds
Started Jul 17 07:09:34 PM PDT 24
Finished Jul 17 07:09:40 PM PDT 24
Peak memory 209144 kb
Host smart-f4b372c7-7bef-4da2-9797-3d520813f615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767881937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.767881937
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2858952040
Short name T919
Test name
Test status
Simulation time 89326621 ps
CPU time 1.35 seconds
Started Jul 17 07:09:38 PM PDT 24
Finished Jul 17 07:09:40 PM PDT 24
Peak memory 209676 kb
Host smart-295453c9-2ab6-43ac-bf55-c1e9abad7404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858952040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2858952040
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.1479228186
Short name T464
Test name
Test status
Simulation time 13116699 ps
CPU time 0.9 seconds
Started Jul 17 07:09:44 PM PDT 24
Finished Jul 17 07:09:56 PM PDT 24
Peak memory 205992 kb
Host smart-d69fae46-b3bb-4d22-9b68-a4bd857ba3a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479228186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.1479228186
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.1767052692
Short name T83
Test name
Test status
Simulation time 45631307 ps
CPU time 3.37 seconds
Started Jul 17 07:09:42 PM PDT 24
Finished Jul 17 07:09:56 PM PDT 24
Peak memory 214336 kb
Host smart-aa015502-fcea-448f-aa34-184ce7fb53d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1767052692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.1767052692
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.3756462040
Short name T527
Test name
Test status
Simulation time 280738475 ps
CPU time 3.52 seconds
Started Jul 17 07:09:46 PM PDT 24
Finished Jul 17 07:10:02 PM PDT 24
Peak memory 208896 kb
Host smart-d3023e8e-1a70-4bfb-a40f-b3382a46a395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756462040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.3756462040
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.3314590091
Short name T801
Test name
Test status
Simulation time 129616993 ps
CPU time 4.52 seconds
Started Jul 17 07:09:46 PM PDT 24
Finished Jul 17 07:10:03 PM PDT 24
Peak memory 214360 kb
Host smart-f6ab4117-330c-43d0-96eb-99d85ea1c03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314590091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.3314590091
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.1543901604
Short name T301
Test name
Test status
Simulation time 100065071 ps
CPU time 2.36 seconds
Started Jul 17 07:09:43 PM PDT 24
Finished Jul 17 07:09:56 PM PDT 24
Peak memory 211436 kb
Host smart-7e13ac86-83f9-4003-9292-fe6221a78d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543901604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.1543901604
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2644403399
Short name T237
Test name
Test status
Simulation time 817020239 ps
CPU time 4.18 seconds
Started Jul 17 07:09:42 PM PDT 24
Finished Jul 17 07:09:57 PM PDT 24
Peak memory 220056 kb
Host smart-e6133f86-1340-415e-ba65-7790ef9c54dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644403399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2644403399
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.3028783245
Short name T535
Test name
Test status
Simulation time 956490038 ps
CPU time 7.99 seconds
Started Jul 17 07:09:42 PM PDT 24
Finished Jul 17 07:10:01 PM PDT 24
Peak memory 207628 kb
Host smart-a74d8a71-8374-4c52-9560-b718f5d59057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028783245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3028783245
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.1431413786
Short name T590
Test name
Test status
Simulation time 166450082 ps
CPU time 4.69 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:09:53 PM PDT 24
Peak memory 208336 kb
Host smart-f2c19d92-f6b1-4d43-acbb-544c87749cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431413786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1431413786
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.2039307354
Short name T688
Test name
Test status
Simulation time 924457145 ps
CPU time 5.29 seconds
Started Jul 17 07:09:43 PM PDT 24
Finished Jul 17 07:09:59 PM PDT 24
Peak memory 208864 kb
Host smart-b6680cb0-e188-4d19-981c-93ed3ebd52a8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039307354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.2039307354
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.3561677630
Short name T607
Test name
Test status
Simulation time 153147679 ps
CPU time 3.02 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:09:53 PM PDT 24
Peak memory 208736 kb
Host smart-9fd4601e-3b19-4d39-a47c-64286b7092f1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561677630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3561677630
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.4156361674
Short name T551
Test name
Test status
Simulation time 75977144 ps
CPU time 3.29 seconds
Started Jul 17 07:09:42 PM PDT 24
Finished Jul 17 07:09:56 PM PDT 24
Peak memory 208792 kb
Host smart-f684d3e4-f7cb-4a5e-88cd-4776afd56850
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156361674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.4156361674
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.166170354
Short name T609
Test name
Test status
Simulation time 402380930 ps
CPU time 3.46 seconds
Started Jul 17 07:09:43 PM PDT 24
Finished Jul 17 07:09:57 PM PDT 24
Peak memory 208052 kb
Host smart-9c6384f9-fad7-4dcc-9a9f-ee3cc3f7d41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166170354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.166170354
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.688382374
Short name T631
Test name
Test status
Simulation time 5430540377 ps
CPU time 18.51 seconds
Started Jul 17 07:09:39 PM PDT 24
Finished Jul 17 07:10:01 PM PDT 24
Peak memory 208388 kb
Host smart-45c32312-ce1b-407e-ae92-2e4a76b5dd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688382374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.688382374
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.3293135180
Short name T229
Test name
Test status
Simulation time 142457073 ps
CPU time 3.76 seconds
Started Jul 17 07:09:42 PM PDT 24
Finished Jul 17 07:09:57 PM PDT 24
Peak memory 209992 kb
Host smart-2d5ba900-c41e-4074-bf50-7d8df8eac4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293135180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.3293135180
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.3536482042
Short name T404
Test name
Test status
Simulation time 155884578 ps
CPU time 4.3 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:09:53 PM PDT 24
Peak memory 211116 kb
Host smart-ccb66e18-f392-4903-82b3-b3fe3e4b9095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536482042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.3536482042
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.2063471014
Short name T718
Test name
Test status
Simulation time 29563052 ps
CPU time 0.75 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:09:51 PM PDT 24
Peak memory 205996 kb
Host smart-af5ec7b5-68d6-43b8-94d8-e3a72f42d7dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063471014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.2063471014
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.129891943
Short name T360
Test name
Test status
Simulation time 358840627 ps
CPU time 4.82 seconds
Started Jul 17 07:09:45 PM PDT 24
Finished Jul 17 07:10:01 PM PDT 24
Peak memory 213488 kb
Host smart-a4dbd5d1-aade-4b16-80ac-da12f52fb12f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=129891943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.129891943
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.2136684555
Short name T19
Test name
Test status
Simulation time 51677656 ps
CPU time 1.75 seconds
Started Jul 17 07:09:47 PM PDT 24
Finished Jul 17 07:10:01 PM PDT 24
Peak memory 208916 kb
Host smart-f06cfd12-e5bb-4ea7-812c-aaf696a1a0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136684555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.2136684555
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.294051536
Short name T839
Test name
Test status
Simulation time 129705643 ps
CPU time 4.16 seconds
Started Jul 17 07:09:47 PM PDT 24
Finished Jul 17 07:10:03 PM PDT 24
Peak memory 214252 kb
Host smart-051af3f7-8efd-4455-ad38-20a75c64fb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294051536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.294051536
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1767921109
Short name T394
Test name
Test status
Simulation time 93584375 ps
CPU time 2.48 seconds
Started Jul 17 07:09:43 PM PDT 24
Finished Jul 17 07:09:57 PM PDT 24
Peak memory 214404 kb
Host smart-85d7e079-8cd4-4e9d-bcc5-e9445fa7ac6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767921109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1767921109
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.2531633265
Short name T43
Test name
Test status
Simulation time 89581011 ps
CPU time 2.47 seconds
Started Jul 17 07:09:45 PM PDT 24
Finished Jul 17 07:10:00 PM PDT 24
Peak memory 221648 kb
Host smart-16e1576e-9715-41c8-acb8-006d87273ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531633265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.2531633265
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.3507883336
Short name T414
Test name
Test status
Simulation time 427874929 ps
CPU time 3.33 seconds
Started Jul 17 07:09:45 PM PDT 24
Finished Jul 17 07:10:00 PM PDT 24
Peak memory 209160 kb
Host smart-0b7b4d28-4791-4890-a204-96482301a2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507883336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.3507883336
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.64775114
Short name T620
Test name
Test status
Simulation time 145836101 ps
CPU time 4.75 seconds
Started Jul 17 07:09:43 PM PDT 24
Finished Jul 17 07:09:59 PM PDT 24
Peak memory 219836 kb
Host smart-bbb26e21-89ba-4aeb-b322-f6d59f8c9c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64775114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.64775114
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.99699909
Short name T359
Test name
Test status
Simulation time 34157490 ps
CPU time 2.45 seconds
Started Jul 17 07:09:45 PM PDT 24
Finished Jul 17 07:09:59 PM PDT 24
Peak memory 208728 kb
Host smart-6f134c83-b368-48d6-b8a6-2d1d0a543553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99699909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.99699909
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.2183655091
Short name T837
Test name
Test status
Simulation time 343572785 ps
CPU time 5.57 seconds
Started Jul 17 07:09:44 PM PDT 24
Finished Jul 17 07:10:01 PM PDT 24
Peak memory 208284 kb
Host smart-0493940f-ab6f-44aa-bd20-013028d26d91
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183655091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.2183655091
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.2553289996
Short name T588
Test name
Test status
Simulation time 168593111 ps
CPU time 5.1 seconds
Started Jul 17 07:09:44 PM PDT 24
Finished Jul 17 07:09:59 PM PDT 24
Peak memory 208840 kb
Host smart-7a1bb828-5fb0-454d-a5c6-dd3350ae700c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553289996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.2553289996
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.810768626
Short name T422
Test name
Test status
Simulation time 34698119 ps
CPU time 2.19 seconds
Started Jul 17 07:09:44 PM PDT 24
Finished Jul 17 07:09:57 PM PDT 24
Peak memory 207008 kb
Host smart-040d403e-265c-4847-9f0c-d0c266280f51
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810768626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.810768626
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.2994857451
Short name T346
Test name
Test status
Simulation time 41379247 ps
CPU time 2.26 seconds
Started Jul 17 07:09:42 PM PDT 24
Finished Jul 17 07:09:55 PM PDT 24
Peak memory 214388 kb
Host smart-8fd92ae2-1225-4e77-ba06-4b44347995a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994857451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.2994857451
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.3738907353
Short name T911
Test name
Test status
Simulation time 299188803 ps
CPU time 2.77 seconds
Started Jul 17 07:09:44 PM PDT 24
Finished Jul 17 07:09:57 PM PDT 24
Peak memory 208636 kb
Host smart-56b8178d-0ebd-45d5-9107-d9f898e3e89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738907353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.3738907353
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.1893124689
Short name T269
Test name
Test status
Simulation time 227636858 ps
CPU time 11.55 seconds
Started Jul 17 07:09:47 PM PDT 24
Finished Jul 17 07:10:11 PM PDT 24
Peak memory 222520 kb
Host smart-cde9cf38-06de-4060-a51a-f38df035411a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893124689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1893124689
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.3296964061
Short name T760
Test name
Test status
Simulation time 9515180574 ps
CPU time 58.6 seconds
Started Jul 17 07:09:45 PM PDT 24
Finished Jul 17 07:10:55 PM PDT 24
Peak memory 209048 kb
Host smart-819c95fa-1aa5-4aeb-a9dc-55fbe4c1b22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296964061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3296964061
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.646987499
Short name T571
Test name
Test status
Simulation time 97097729 ps
CPU time 2.94 seconds
Started Jul 17 07:09:41 PM PDT 24
Finished Jul 17 07:09:50 PM PDT 24
Peak memory 210948 kb
Host smart-c90c3e95-560f-47fd-91d9-ecfd49e6c039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646987499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.646987499
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.3497075045
Short name T484
Test name
Test status
Simulation time 16018364 ps
CPU time 0.79 seconds
Started Jul 17 07:06:05 PM PDT 24
Finished Jul 17 07:06:08 PM PDT 24
Peak memory 205992 kb
Host smart-e20933e0-c8d4-4533-bfc8-7fad5f4013c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497075045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.3497075045
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.536688505
Short name T193
Test name
Test status
Simulation time 386179103 ps
CPU time 4.1 seconds
Started Jul 17 07:06:07 PM PDT 24
Finished Jul 17 07:06:13 PM PDT 24
Peak memory 221884 kb
Host smart-c3f8c669-ba38-47f8-875d-673ce8d7fdf5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=536688505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.536688505
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.1326904577
Short name T546
Test name
Test status
Simulation time 92726588 ps
CPU time 3.21 seconds
Started Jul 17 07:06:08 PM PDT 24
Finished Jul 17 07:06:14 PM PDT 24
Peak memory 219152 kb
Host smart-35b3b9d1-0aed-41eb-b76f-08b65d2954fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326904577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.1326904577
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.3031079260
Short name T67
Test name
Test status
Simulation time 190467437 ps
CPU time 2.79 seconds
Started Jul 17 07:06:10 PM PDT 24
Finished Jul 17 07:06:20 PM PDT 24
Peak memory 207448 kb
Host smart-a6f02616-7bcb-4a58-80a5-da475b2a4b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031079260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.3031079260
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.774566
Short name T345
Test name
Test status
Simulation time 63992667 ps
CPU time 2.16 seconds
Started Jul 17 07:06:06 PM PDT 24
Finished Jul 17 07:06:11 PM PDT 24
Peak memory 214332 kb
Host smart-1c2c64f8-e29e-4621-9043-3f759e40b580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.774566
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.1554821001
Short name T827
Test name
Test status
Simulation time 123997048 ps
CPU time 3.08 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:22 PM PDT 24
Peak memory 215312 kb
Host smart-092bec5f-1774-42f1-b784-af60ed9018ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554821001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.1554821001
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.3663593768
Short name T264
Test name
Test status
Simulation time 80637247 ps
CPU time 4 seconds
Started Jul 17 07:06:04 PM PDT 24
Finished Jul 17 07:06:11 PM PDT 24
Peak memory 222500 kb
Host smart-48cad413-6426-44ad-bd29-2d3ebc357f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663593768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.3663593768
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.2713737487
Short name T352
Test name
Test status
Simulation time 454744244 ps
CPU time 7.12 seconds
Started Jul 17 07:06:10 PM PDT 24
Finished Jul 17 07:06:25 PM PDT 24
Peak memory 207604 kb
Host smart-34401515-fc9c-434a-a251-607d981a9c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713737487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.2713737487
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.1397301825
Short name T112
Test name
Test status
Simulation time 197872665 ps
CPU time 2.77 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:22 PM PDT 24
Peak memory 207268 kb
Host smart-5fee35b6-618d-459f-ac87-d64ac067c56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397301825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.1397301825
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.3650775693
Short name T592
Test name
Test status
Simulation time 130428951 ps
CPU time 4.81 seconds
Started Jul 17 07:06:04 PM PDT 24
Finished Jul 17 07:06:11 PM PDT 24
Peak memory 208108 kb
Host smart-ddc6b9bf-f458-492d-9857-a8a2561018da
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650775693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.3650775693
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.3238020238
Short name T514
Test name
Test status
Simulation time 283857609 ps
CPU time 4.21 seconds
Started Jul 17 07:06:09 PM PDT 24
Finished Jul 17 07:06:18 PM PDT 24
Peak memory 208480 kb
Host smart-9859111c-437b-405e-be53-99bc2f74f109
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238020238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.3238020238
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.2633266032
Short name T525
Test name
Test status
Simulation time 54429370 ps
CPU time 2.83 seconds
Started Jul 17 07:06:10 PM PDT 24
Finished Jul 17 07:06:21 PM PDT 24
Peak memory 208584 kb
Host smart-187107be-385a-4c0d-b975-2756e30d9be4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633266032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.2633266032
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.2775629043
Short name T531
Test name
Test status
Simulation time 74022728 ps
CPU time 2.64 seconds
Started Jul 17 07:06:06 PM PDT 24
Finished Jul 17 07:06:11 PM PDT 24
Peak memory 207332 kb
Host smart-6146e775-388f-40ee-a7f1-a4499e9241ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775629043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.2775629043
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.449480459
Short name T534
Test name
Test status
Simulation time 49887948 ps
CPU time 2.03 seconds
Started Jul 17 07:06:05 PM PDT 24
Finished Jul 17 07:06:10 PM PDT 24
Peak memory 206728 kb
Host smart-51fd1ac2-a544-43eb-8e88-ff172a5f1a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449480459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.449480459
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.2298795339
Short name T421
Test name
Test status
Simulation time 1115675099 ps
CPU time 24.96 seconds
Started Jul 17 07:06:03 PM PDT 24
Finished Jul 17 07:06:29 PM PDT 24
Peak memory 215260 kb
Host smart-26e6477e-550d-4d9a-9794-c4f3a82b2768
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298795339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.2298795339
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.3306897974
Short name T669
Test name
Test status
Simulation time 133067731 ps
CPU time 4.49 seconds
Started Jul 17 07:06:10 PM PDT 24
Finished Jul 17 07:06:22 PM PDT 24
Peak memory 210020 kb
Host smart-6438b74e-1cd0-4662-9a7e-3febce58db62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306897974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.3306897974
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.557901363
Short name T651
Test name
Test status
Simulation time 545678471 ps
CPU time 3.62 seconds
Started Jul 17 07:06:07 PM PDT 24
Finished Jul 17 07:06:13 PM PDT 24
Peak memory 210204 kb
Host smart-80c21735-65db-460e-90de-ded1638aa8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557901363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.557901363
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.1617764461
Short name T200
Test name
Test status
Simulation time 94792446 ps
CPU time 0.97 seconds
Started Jul 17 07:06:04 PM PDT 24
Finished Jul 17 07:06:07 PM PDT 24
Peak memory 206072 kb
Host smart-8f5f84f3-33e1-4ca1-a951-2b7ab8b7576c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617764461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.1617764461
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.2672766291
Short name T141
Test name
Test status
Simulation time 41719955 ps
CPU time 2.87 seconds
Started Jul 17 07:06:10 PM PDT 24
Finished Jul 17 07:06:21 PM PDT 24
Peak memory 215520 kb
Host smart-e3089ccd-c046-4687-a7f5-a1644f8ca5a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2672766291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.2672766291
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.4062652499
Short name T842
Test name
Test status
Simulation time 813966983 ps
CPU time 4.46 seconds
Started Jul 17 07:06:08 PM PDT 24
Finished Jul 17 07:06:15 PM PDT 24
Peak memory 214336 kb
Host smart-82d74486-2867-418a-8032-b061271c64f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062652499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.4062652499
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.2212316353
Short name T758
Test name
Test status
Simulation time 1251546887 ps
CPU time 4.95 seconds
Started Jul 17 07:06:08 PM PDT 24
Finished Jul 17 07:06:17 PM PDT 24
Peak memory 206064 kb
Host smart-93c29575-1953-4e46-a8ef-3f3586083ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212316353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.2212316353
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.218153873
Short name T247
Test name
Test status
Simulation time 74314455 ps
CPU time 3.83 seconds
Started Jul 17 07:06:10 PM PDT 24
Finished Jul 17 07:06:21 PM PDT 24
Peak memory 215540 kb
Host smart-468915dc-252a-4fa9-8f4c-9aaabc0d7baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218153873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.218153873
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.2855934548
Short name T815
Test name
Test status
Simulation time 37231659 ps
CPU time 2.35 seconds
Started Jul 17 07:06:08 PM PDT 24
Finished Jul 17 07:06:14 PM PDT 24
Peak memory 208272 kb
Host smart-e3e663c7-84bc-4994-ab20-06f8d736ce80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855934548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.2855934548
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.2921113171
Short name T536
Test name
Test status
Simulation time 122958845 ps
CPU time 2.43 seconds
Started Jul 17 07:06:10 PM PDT 24
Finished Jul 17 07:06:20 PM PDT 24
Peak memory 206748 kb
Host smart-50e1d9b8-f56b-4917-91b8-56227b49f757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921113171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.2921113171
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.3795626966
Short name T713
Test name
Test status
Simulation time 79662204 ps
CPU time 3.57 seconds
Started Jul 17 07:06:09 PM PDT 24
Finished Jul 17 07:06:18 PM PDT 24
Peak memory 208880 kb
Host smart-85642947-6c18-4067-ba70-d1e44b252814
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795626966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.3795626966
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.3071720950
Short name T554
Test name
Test status
Simulation time 87417124 ps
CPU time 3.45 seconds
Started Jul 17 07:06:10 PM PDT 24
Finished Jul 17 07:06:21 PM PDT 24
Peak memory 208584 kb
Host smart-d3c2c431-09eb-47ef-9b68-bd220733ceb7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071720950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.3071720950
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.582511507
Short name T740
Test name
Test status
Simulation time 235264436 ps
CPU time 6.1 seconds
Started Jul 17 07:06:05 PM PDT 24
Finished Jul 17 07:06:13 PM PDT 24
Peak memory 208348 kb
Host smart-936b1cd7-9544-44f5-ae98-ad2d36c2a785
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582511507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.582511507
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.219419257
Short name T513
Test name
Test status
Simulation time 62221549 ps
CPU time 3.27 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:23 PM PDT 24
Peak memory 207464 kb
Host smart-5f4931d1-04ea-4004-9a59-50f1d48570e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219419257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.219419257
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.67396078
Short name T498
Test name
Test status
Simulation time 44812497 ps
CPU time 2.25 seconds
Started Jul 17 07:06:09 PM PDT 24
Finished Jul 17 07:06:15 PM PDT 24
Peak memory 208204 kb
Host smart-2a442e21-f656-4cf4-b8fa-a00e5cbd6b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67396078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.67396078
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.1861125406
Short name T340
Test name
Test status
Simulation time 20135827690 ps
CPU time 184.9 seconds
Started Jul 17 07:06:10 PM PDT 24
Finished Jul 17 07:09:22 PM PDT 24
Peak memory 216528 kb
Host smart-dd3f8f00-0858-4976-9484-880de2750646
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861125406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.1861125406
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.517312306
Short name T317
Test name
Test status
Simulation time 256713762 ps
CPU time 3.98 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:25 PM PDT 24
Peak memory 208580 kb
Host smart-93ecb234-43a6-485e-8acf-01cce8f33666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517312306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.517312306
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.2970212939
Short name T403
Test name
Test status
Simulation time 106362743 ps
CPU time 2.47 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:23 PM PDT 24
Peak memory 209912 kb
Host smart-e25004b7-a1f5-4012-a4d1-7d49b41d072d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970212939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.2970212939
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.1803793824
Short name T106
Test name
Test status
Simulation time 30416346 ps
CPU time 0.9 seconds
Started Jul 17 07:06:14 PM PDT 24
Finished Jul 17 07:06:26 PM PDT 24
Peak memory 206068 kb
Host smart-6605124a-b209-4f68-b31d-4571fe38583f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803793824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.1803793824
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.1608200275
Short name T196
Test name
Test status
Simulation time 120706765 ps
CPU time 4.5 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:25 PM PDT 24
Peak memory 215628 kb
Host smart-ff6ab108-a763-45da-a3fe-0d952dda5743
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1608200275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.1608200275
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.2042275773
Short name T46
Test name
Test status
Simulation time 327288876 ps
CPU time 3.4 seconds
Started Jul 17 07:06:12 PM PDT 24
Finished Jul 17 07:06:24 PM PDT 24
Peak memory 209540 kb
Host smart-8df024a1-b1e8-463b-b7ff-6f47e9122fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042275773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.2042275773
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.571812162
Short name T350
Test name
Test status
Simulation time 89456198 ps
CPU time 1.93 seconds
Started Jul 17 07:06:12 PM PDT 24
Finished Jul 17 07:06:23 PM PDT 24
Peak memory 214304 kb
Host smart-a59ad60b-3ffe-4584-895f-2e0489d32329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571812162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.571812162
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.294958837
Short name T579
Test name
Test status
Simulation time 115769812 ps
CPU time 1.91 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:22 PM PDT 24
Peak memory 214236 kb
Host smart-9c6823b1-0007-4c02-b51c-b85e43131c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294958837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.294958837
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.1838358762
Short name T901
Test name
Test status
Simulation time 37479829 ps
CPU time 2.6 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:21 PM PDT 24
Peak memory 214288 kb
Host smart-04bea5af-151a-421a-b6fb-bd83bbef2855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838358762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.1838358762
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.3127519565
Short name T4
Test name
Test status
Simulation time 175472458 ps
CPU time 3.84 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:23 PM PDT 24
Peak memory 220156 kb
Host smart-987ba356-22d2-49a1-ae33-61899767ebe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127519565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.3127519565
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.1139596950
Short name T216
Test name
Test status
Simulation time 621244123 ps
CPU time 5.52 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:26 PM PDT 24
Peak memory 207688 kb
Host smart-e9716be3-6652-4963-bf6e-f9dee7b2f4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139596950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1139596950
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.3750034911
Short name T353
Test name
Test status
Simulation time 859040506 ps
CPU time 21.49 seconds
Started Jul 17 07:06:10 PM PDT 24
Finished Jul 17 07:06:39 PM PDT 24
Peak memory 207808 kb
Host smart-12cc3d64-b7cb-4494-9a8a-f11557151297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750034911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.3750034911
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.3037944536
Short name T335
Test name
Test status
Simulation time 79200683 ps
CPU time 2.32 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:21 PM PDT 24
Peak memory 206936 kb
Host smart-2118af3f-e8ea-418e-8ecb-9da69786ecac
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037944536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.3037944536
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.2506007725
Short name T606
Test name
Test status
Simulation time 1318765357 ps
CPU time 39.62 seconds
Started Jul 17 07:06:12 PM PDT 24
Finished Jul 17 07:07:02 PM PDT 24
Peak memory 208672 kb
Host smart-424dd272-87ae-4840-b6c4-e94dea11f53a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506007725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.2506007725
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.116460646
Short name T539
Test name
Test status
Simulation time 100223714 ps
CPU time 2.6 seconds
Started Jul 17 07:06:06 PM PDT 24
Finished Jul 17 07:06:11 PM PDT 24
Peak memory 207024 kb
Host smart-fa4dddbb-de25-484f-818c-dcf57068b771
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116460646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.116460646
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.3273142230
Short name T585
Test name
Test status
Simulation time 848931107 ps
CPU time 8.53 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:29 PM PDT 24
Peak memory 218320 kb
Host smart-927fa0c8-80ba-47ae-94a0-d1566e1b1173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273142230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3273142230
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.2118082861
Short name T899
Test name
Test status
Simulation time 175943211 ps
CPU time 2.27 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:21 PM PDT 24
Peak memory 207244 kb
Host smart-7fc5c50b-6ace-494f-90e5-4d405d0650bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118082861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.2118082861
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.1833382568
Short name T465
Test name
Test status
Simulation time 2178622898 ps
CPU time 6.84 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:26 PM PDT 24
Peak memory 208680 kb
Host smart-9a1af14f-a76d-4a40-9c95-723fc36f8040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833382568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.1833382568
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.1421015658
Short name T882
Test name
Test status
Simulation time 35672008 ps
CPU time 1.74 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:22 PM PDT 24
Peak memory 209868 kb
Host smart-5f67ee6b-f0a1-485f-9dec-ad36ed94a582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421015658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1421015658
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.3699683415
Short name T738
Test name
Test status
Simulation time 10221279 ps
CPU time 0.82 seconds
Started Jul 17 07:06:18 PM PDT 24
Finished Jul 17 07:06:29 PM PDT 24
Peak memory 205984 kb
Host smart-2248ac2c-3edf-4ee4-aa45-c02733632afb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699683415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.3699683415
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.2471955291
Short name T440
Test name
Test status
Simulation time 81333071 ps
CPU time 3.32 seconds
Started Jul 17 07:06:18 PM PDT 24
Finished Jul 17 07:06:31 PM PDT 24
Peak memory 222584 kb
Host smart-73f9ec1c-1cf3-4784-bbb5-4653cb493f34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2471955291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.2471955291
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.823807059
Short name T38
Test name
Test status
Simulation time 468467453 ps
CPU time 4.11 seconds
Started Jul 17 07:06:15 PM PDT 24
Finished Jul 17 07:06:30 PM PDT 24
Peak memory 221972 kb
Host smart-c961939a-cbc9-42a8-abc3-bc0b29a54815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823807059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.823807059
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.2833575330
Short name T377
Test name
Test status
Simulation time 180465596 ps
CPU time 4.28 seconds
Started Jul 17 07:06:17 PM PDT 24
Finished Jul 17 07:06:32 PM PDT 24
Peak memory 222356 kb
Host smart-c411af74-c675-4a57-b3b6-c081f48758f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833575330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.2833575330
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1147706456
Short name T40
Test name
Test status
Simulation time 186151985 ps
CPU time 3.31 seconds
Started Jul 17 07:06:17 PM PDT 24
Finished Jul 17 07:06:31 PM PDT 24
Peak memory 208140 kb
Host smart-bb93bd3c-693c-41d9-867a-a5b7e403cef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147706456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1147706456
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.828998961
Short name T604
Test name
Test status
Simulation time 48256426 ps
CPU time 2.75 seconds
Started Jul 17 07:06:17 PM PDT 24
Finished Jul 17 07:06:31 PM PDT 24
Peak memory 208136 kb
Host smart-288e8884-6bb1-489c-a035-3b05988d6c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828998961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.828998961
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.2064701239
Short name T794
Test name
Test status
Simulation time 202911016 ps
CPU time 2.72 seconds
Started Jul 17 07:06:07 PM PDT 24
Finished Jul 17 07:06:12 PM PDT 24
Peak memory 207108 kb
Host smart-6cbad6b1-74de-4e03-9752-7284f19a52b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064701239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.2064701239
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.1111004552
Short name T292
Test name
Test status
Simulation time 220687580 ps
CPU time 4.58 seconds
Started Jul 17 07:06:12 PM PDT 24
Finished Jul 17 07:06:27 PM PDT 24
Peak memory 208504 kb
Host smart-3e28704b-86e2-4c1c-9377-8a5ee6299666
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111004552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1111004552
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.659394186
Short name T747
Test name
Test status
Simulation time 609748442 ps
CPU time 4.94 seconds
Started Jul 17 07:06:14 PM PDT 24
Finished Jul 17 07:06:30 PM PDT 24
Peak memory 208672 kb
Host smart-6285eaa2-37ab-4c8b-815d-829517dc1926
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659394186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.659394186
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.1207798573
Short name T814
Test name
Test status
Simulation time 521294828 ps
CPU time 15.62 seconds
Started Jul 17 07:06:15 PM PDT 24
Finished Jul 17 07:06:42 PM PDT 24
Peak memory 207972 kb
Host smart-b877d091-bd25-418e-8eea-a8221da132b6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207798573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.1207798573
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.556610901
Short name T225
Test name
Test status
Simulation time 87465110 ps
CPU time 2.9 seconds
Started Jul 17 07:06:15 PM PDT 24
Finished Jul 17 07:06:29 PM PDT 24
Peak memory 210140 kb
Host smart-d8eb7b98-7dc7-4098-86ef-529c04e302fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556610901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.556610901
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.2982134533
Short name T445
Test name
Test status
Simulation time 635564801 ps
CPU time 2.45 seconds
Started Jul 17 07:06:12 PM PDT 24
Finished Jul 17 07:06:25 PM PDT 24
Peak memory 206880 kb
Host smart-c6dceb8f-938d-4298-8542-188aca4dde63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982134533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.2982134533
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.3520944495
Short name T634
Test name
Test status
Simulation time 6328454657 ps
CPU time 28.51 seconds
Started Jul 17 07:06:14 PM PDT 24
Finished Jul 17 07:06:53 PM PDT 24
Peak memory 218412 kb
Host smart-e8ad88cd-9e5d-48b7-a549-2b6207b08f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520944495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.3520944495
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.3563480937
Short name T866
Test name
Test status
Simulation time 234984092 ps
CPU time 2.69 seconds
Started Jul 17 07:06:08 PM PDT 24
Finished Jul 17 07:06:14 PM PDT 24
Peak memory 209868 kb
Host smart-d7cf02a2-ef0a-4351-875f-b22b98f577f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563480937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.3563480937
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.2123962538
Short name T649
Test name
Test status
Simulation time 48101663 ps
CPU time 0.91 seconds
Started Jul 17 07:06:11 PM PDT 24
Finished Jul 17 07:06:21 PM PDT 24
Peak memory 206024 kb
Host smart-693d575d-18be-44ec-bbdd-d57d80520d78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123962538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.2123962538
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.3667778732
Short name T803
Test name
Test status
Simulation time 1639234926 ps
CPU time 15.86 seconds
Started Jul 17 07:06:17 PM PDT 24
Finished Jul 17 07:06:44 PM PDT 24
Peak memory 222844 kb
Host smart-b8c603e7-0eed-4b77-bc62-3f854bd0940b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667778732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.3667778732
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.2459839288
Short name T698
Test name
Test status
Simulation time 71761854 ps
CPU time 2.94 seconds
Started Jul 17 07:06:15 PM PDT 24
Finished Jul 17 07:06:29 PM PDT 24
Peak memory 214320 kb
Host smart-97406c83-dc42-4034-b6da-40e42f32b00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459839288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.2459839288
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.150658403
Short name T234
Test name
Test status
Simulation time 269657846 ps
CPU time 6.56 seconds
Started Jul 17 07:06:14 PM PDT 24
Finished Jul 17 07:06:31 PM PDT 24
Peak memory 209396 kb
Host smart-64c8db98-8bec-4b4f-961e-9139887c93c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150658403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.150658403
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.1163232586
Short name T756
Test name
Test status
Simulation time 34969944 ps
CPU time 2.06 seconds
Started Jul 17 07:06:10 PM PDT 24
Finished Jul 17 07:06:21 PM PDT 24
Peak memory 214260 kb
Host smart-0bc102db-c285-4532-8db0-535b32cd5c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163232586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.1163232586
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.2330023215
Short name T487
Test name
Test status
Simulation time 506968319 ps
CPU time 3.97 seconds
Started Jul 17 07:06:16 PM PDT 24
Finished Jul 17 07:06:31 PM PDT 24
Peak memory 210400 kb
Host smart-76e0f54d-4968-429a-8c2f-c4b9ca528c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330023215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.2330023215
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.3352608996
Short name T691
Test name
Test status
Simulation time 145736102 ps
CPU time 2.68 seconds
Started Jul 17 07:06:15 PM PDT 24
Finished Jul 17 07:06:29 PM PDT 24
Peak memory 207692 kb
Host smart-b115dc21-b5d4-4e6f-a971-c525b7546712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352608996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.3352608996
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.1025211780
Short name T904
Test name
Test status
Simulation time 178106013 ps
CPU time 1.75 seconds
Started Jul 17 07:06:19 PM PDT 24
Finished Jul 17 07:06:31 PM PDT 24
Peak memory 206872 kb
Host smart-e2105f7a-52ef-419f-a6a3-f025730a2a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025211780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1025211780
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.2754711478
Short name T869
Test name
Test status
Simulation time 119637739 ps
CPU time 5.21 seconds
Started Jul 17 07:06:20 PM PDT 24
Finished Jul 17 07:06:35 PM PDT 24
Peak memory 208872 kb
Host smart-aac2dc76-c4e3-44ac-a29a-dc8386207554
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754711478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.2754711478
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.539056147
Short name T687
Test name
Test status
Simulation time 249321689 ps
CPU time 3.43 seconds
Started Jul 17 07:06:09 PM PDT 24
Finished Jul 17 07:06:19 PM PDT 24
Peak memory 206872 kb
Host smart-1047221e-557b-4fec-b7a6-6c6c1949ffa3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539056147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.539056147
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.1749596514
Short name T451
Test name
Test status
Simulation time 128416245 ps
CPU time 2.32 seconds
Started Jul 17 07:06:17 PM PDT 24
Finished Jul 17 07:06:30 PM PDT 24
Peak memory 206800 kb
Host smart-720e7a01-d9b3-42af-81a0-5954a164c2f3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749596514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.1749596514
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.2611891412
Short name T494
Test name
Test status
Simulation time 50182825 ps
CPU time 2.46 seconds
Started Jul 17 07:06:17 PM PDT 24
Finished Jul 17 07:06:30 PM PDT 24
Peak memory 215224 kb
Host smart-acd687ce-efd3-4a57-815b-69a2c1cfd8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611891412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.2611891412
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.2191293212
Short name T618
Test name
Test status
Simulation time 224783006 ps
CPU time 3.72 seconds
Started Jul 17 07:06:20 PM PDT 24
Finished Jul 17 07:06:33 PM PDT 24
Peak memory 207064 kb
Host smart-a0728402-5e33-47bc-a771-49b75e6dd4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191293212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2191293212
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.1772010738
Short name T204
Test name
Test status
Simulation time 29289007908 ps
CPU time 162.87 seconds
Started Jul 17 07:06:07 PM PDT 24
Finished Jul 17 07:08:53 PM PDT 24
Peak memory 216960 kb
Host smart-e7e222fd-d222-44ec-9a7d-71231dcabd0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772010738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1772010738
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.4089402305
Short name T643
Test name
Test status
Simulation time 128691431 ps
CPU time 3.89 seconds
Started Jul 17 07:06:08 PM PDT 24
Finished Jul 17 07:06:15 PM PDT 24
Peak memory 207988 kb
Host smart-d3fb8ec1-25a0-4830-b3c0-a7fe9e2369c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089402305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.4089402305
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.2567481797
Short name T425
Test name
Test status
Simulation time 463583364 ps
CPU time 2.03 seconds
Started Jul 17 07:06:08 PM PDT 24
Finished Jul 17 07:06:13 PM PDT 24
Peak memory 210700 kb
Host smart-2820bbc4-eaa6-4e53-b643-6607c8776ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567481797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.2567481797
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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