Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.84	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	73	257	77.88

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	54	226	80.71	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4764

1

T1

13

T3

11

T4

6

auto[1]

486

1

T5

1

T19

1

T26

1

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4764

1

T1

13

T3

11

T4

6

auto[1]

486

1

T5

1

T19

1

T26

1

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4726

1

T1

8

T3

7

T4

6

auto[1]

524

1

T1

5

T3

4

T5

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4726

1

T1

8

T3

7

T4

6

auto[1]

524

1

T1

5

T3

4

T5

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	411	1			T17	1		T18	1		T49	3
auto[OpGenId]	1138	1			T4	2		T5	3		T6	1
auto[OpGenSwOut]	1160	1			T4	3		T18	2		T19	7
auto[OpGenHwOut]	2481	1			T1	13		T3	11		T4	1
auto[OpDisable]	60	1			T52	1		T53	1		T66	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	411	1			T17	1		T18	1		T49	3
auto[OpGenId]	1138	1			T4	2		T5	3		T6	1
auto[OpGenSwOut]	1160	1			T4	3		T18	2		T19	7
auto[OpGenHwOut]	2481	1			T1	13		T3	11		T4	1
auto[OpDisable]	60	1			T52	1		T53	1		T66	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4718

1

T1

13

T3

11

T4

6

auto[1]

532

1

T5

1

T18

1

T95

1

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4718

1

T1

13

T3

11

T4

6

auto[1]

532

1

T5

1

T18

1

T95

1

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4974

1

T1

13

T3

11

T4

6

auto[1]

276

1

T124

7

T125

2

T151

5

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1837	1			T1	8		T3	3		T4	2
auto[1]	694	1			T1	1		T3	1		T4	1
auto[2]	662	1			T1	1		T3	2		T4	1
auto[3]	678	1			T1	1		T3	3		T4	1
auto[4]	357	1			T3	1		T26	1		T119	1
auto[5]	321	1			T1	2		T94	1		T119	1
auto[6]	337	1			T3	1		T94	1		T150	1
auto[7]	364	1			T4	1		T5	1		T18	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1379	1			T1	2		T3	2		T4	1
clear_one[1]	694	1			T1	1		T3	1		T4	1
clear_one[2]	662	1			T1	1		T3	2		T4	1
clear_one[3]	678	1			T1	1		T3	3		T4	1
clear_none	1837	1			T1	8		T3	3		T4	2

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	979	1			T1	5		T3	3		T4	1
auto[StInit]	660	1			T1	1		T3	1		T4	1
auto[StCreatorRootKey]	560	1			T1	1		T3	1		T4	1
auto[StOwnerIntKey]	515	1			T1	1		T3	1		T5	1
auto[StOwnerKey]	481	1			T1	1		T3	1		T19	2
auto[StDisabled]	1795	1			T1	4		T3	4		T4	3
auto[StInvalid]	260	1			T17	4		T43	1		T55	4

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	979	1			T1	5		T3	3		T4	1
auto[StInit]	660	1			T1	1		T3	1		T4	1
auto[StCreatorRootKey]	560	1			T1	1		T3	1		T4	1
auto[StOwnerIntKey]	515	1			T1	1		T3	1		T5	1
auto[StOwnerKey]	481	1			T1	1		T3	1		T19	2
auto[StDisabled]	1795	1			T1	4		T3	4		T4	3
auto[StInvalid]	260	1			T17	4		T43	1		T55	4

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	54	226	80.71	54

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	10
[auto[0] - auto[1]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[2]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[2]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[2]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[2]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[3]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[4] - auto[6]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	3
[auto[4] - auto[6]]	[auto[StReset]]	[auto[OpDisable]]	--	--	3
[auto[4] - auto[6]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	12
[auto[4] - auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3
[auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[7]]	[auto[StInvalid]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	5	1			T139	1		T140	1		T260	1
auto[0]	auto[StReset]	auto[OpGenId]	150	1			T4	1		T6	1		T19	2
auto[0]	auto[StReset]	auto[OpGenSwOut]	198	1			T39	1		T50	1		T138	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	246	1			T1	4		T3	1		T18	2
auto[0]	auto[StInit]	auto[OpAdvance]	38	1			T124	1		T112	1		T44	1
auto[0]	auto[StInit]	auto[OpGenId]	109	1			T19	1		T138	1		T65	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	97	1			T18	1		T19	2		T218	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	173	1			T1	1		T3	1		T135	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	23	1			T151	1		T62	1		T261	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	53	1			T5	1		T26	1		T43	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	47	1			T95	1		T27	1		T88	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	71	1			T228	1		T230	1		T229	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	15	1			T132	1		T262	1		T82	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	33	1			T43	1		T7	1		T136	2
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	29	1			T114	1		T263	1		T70	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	43	1			T1	1		T94	1		T149	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	10	1			T264	2		T265	1		T247	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	27	1			T125	1		T60	1		T192	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	25	1			T112	1		T51	1		T266	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	50	1			T1	1		T119	1		T150	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	17	1			T226	1		T62	1		T267	1
auto[0]	auto[StDisabled]	auto[OpGenId]	63	1			T5	1		T218	1		T62	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	61	1			T4	1		T75	1		T92	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	160	1			T1	1		T3	1		T52	1
auto[0]	auto[StDisabled]	auto[OpDisable]	15	1			T52	1		T61	1		T82	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	12	1			T17	1		T101	1		T268	1
auto[0]	auto[StInvalid]	auto[OpGenId]	21	1			T99	1		T269	1		T270	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	27	1			T55	2		T99	2		T270	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	19	1			T17	1		T98	1		T100	1
auto[1]	auto[StReset]	auto[OpAdvance]	1	1			T271	1		-	-		-	-
auto[1]	auto[StReset]	auto[OpGenId]	15	1			T244	1		T240	1		T272	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	16	1			T18	1		T225	1		T134	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	39	1			T119	1		T273	2		T274	2
auto[1]	auto[StInit]	auto[OpAdvance]	4	1			T23	1		T253	1		T275	1
auto[1]	auto[StInit]	auto[OpGenId]	4	1			T62	1		T213	1		T246	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	14	1			T71	1		T62	1		T189	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	26	1			T94	1		T119	1		T50	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T226	1		T213	1		T276	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T61	1		T277	1		T81	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T225	1		T60	1		T77	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	29	1			T278	1		T279	1		T193	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	11	1			T280	1		T281	1		T77	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	19	1			T226	1		T112	1		T118	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	15	1			T60	1		T64	1		T82	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	39	1			T150	1		T90	1		T65	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	19	1			T228	1		T151	1		T77	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	18	1			T62	1		T103	1		T70	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	11	1			T88	1		T227	1		T64	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	34	1			T232	1		T219	1		T60	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	37	1			T60	1		T132	1		T282	1
auto[1]	auto[StDisabled]	auto[OpGenId]	67	1			T226	1		T125	1		T221	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	53	1			T4	1		T19	1		T26	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	153	1			T1	1		T3	1		T19	1
auto[1]	auto[StDisabled]	auto[OpDisable]	14	1			T81	1		T283	1		T199	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	5	1			T268	1		T284	1		T285	1
auto[1]	auto[StInvalid]	auto[OpGenId]	10	1			T286	1		T285	1		T287	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T44	1		T99	1		T101	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T98	1		T288	1		T289	1
auto[2]	auto[StReset]	auto[OpGenId]	15	1			T64	1		T73	1		T134	2
auto[2]	auto[StReset]	auto[OpGenSwOut]	21	1			T118	1		T57	1		T189	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	33	1			T150	1		T290	1		T60	1
auto[2]	auto[StInit]	auto[OpAdvance]	5	1			T112	1		T97	1		T291	1
auto[2]	auto[StInit]	auto[OpGenId]	12	1			T292	1		T191	1		T293	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	6	1			T291	1		T294	1		T295	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	23	1			T150	1		T296	1		T81	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T31	1		T41	1		T297	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T70	1		T298	1		T299	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	22	1			T19	1		T60	1		T23	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	45	1			T4	1		T149	1		T300	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T140	1		T291	1		T301	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	15	1			T302	1		T247	1		T303	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	16	1			T138	1		T249	1		T247	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	49	1			T232	1		T112	1		T66	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	10	1			T125	1		T139	1		T304	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	15	1			T140	1		T82	2		T136	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	20	1			T19	1		T60	1		T82	2
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	32	1			T3	1		T137	1		T231	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	21	1			T18	1		T49	2		T218	1
auto[2]	auto[StDisabled]	auto[OpGenId]	41	1			T19	2		T95	1		T75	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	58	1			T26	1		T125	1		T151	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	127	1			T1	1		T3	1		T149	1
auto[2]	auto[StDisabled]	auto[OpDisable]	7	1			T60	1		T246	1		T305	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	3	1			T306	1		T307	1		T308	1
auto[2]	auto[StInvalid]	auto[OpGenId]	14	1			T17	1		T269	1		T309	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	15	1			T56	1		T310	1		T311	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	13	1			T17	1		T56	1		T98	1
auto[3]	auto[StReset]	auto[OpAdvance]	1	1			T312	1		-	-		-	-
auto[3]	auto[StReset]	auto[OpGenId]	30	1			T50	1		T60	1		T140	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	13	1			T112	1		T140	1		T249	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	51	1			T3	1		T19	1		T119	2
auto[3]	auto[StInit]	auto[OpAdvance]	5	1			T105	1		T109	1		T12	1
auto[3]	auto[StInit]	auto[OpGenId]	10	1			T304	1		T189	1		T109	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	13	1			T60	1		T23	1		T313	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	16	1			T24	1		T314	1		T282	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	11	1			T49	1		T69	1		T60	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T62	1		T82	2		T77	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	20	1			T19	1		T313	1		T134	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	39	1			T3	1		T150	1		T90	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T82	1		T294	1		T246	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	21	1			T18	1		T88	1		T62	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T218	1		T73	1		T265	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	32	1			T3	1		T5	1		T225	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T218	1		T92	1		T225	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	12	1			T315	1		T316	1		T317	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	11	1			T82	1		T77	1		T299	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	30	1			T19	1		T94	1		T149	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	25	1			T124	2		T60	1		T318	1
auto[3]	auto[StDisabled]	auto[OpGenId]	63	1			T4	1		T53	1		T138	2
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	59	1			T138	1		T124	1		T112	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	138	1			T1	1		T119	2		T149	1
auto[3]	auto[StDisabled]	auto[OpDisable]	3	1			T53	1		T319	1		T255	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	5	1			T270	1		T214	1		T311	1
auto[3]	auto[StInvalid]	auto[OpGenId]	11	1			T55	1		T98	1		T100	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T44	1		T320	1		T179	2
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T99	1		T270	1		T268	1
auto[4]	auto[StReset]	auto[OpGenId]	12	1			T246	2		T321	1		T253	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	5	1			T322	1		T191	1		T242	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	20	1			T3	1		T323	1		T313	1
auto[4]	auto[StInit]	auto[OpAdvance]	6	1			T280	1		T324	1		T305	1
auto[4]	auto[StInit]	auto[OpGenId]	3	1			T109	1		T292	1		T325	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	4	1			T23	1		T105	1		T174	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	12	1			T326	1		T189	1		T105	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T114	1		T327	1		T328	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	1	1			T329	1		-	-		-	-
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T77	1		T247	1		T174	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	19	1			T137	1		T232	1		T273	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T241	1		T330	1		T189	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	1	1			T331	1		-	-		-	-
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	15	1			T112	1		T151	1		T51	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	23	1			T332	1		T296	1		T333	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	1	1			T334	1		-	-		-	-
auto[4]	auto[StOwnerKey]	auto[OpGenId]	9	1			T335	1		T70	1		T77	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T336	1		T305	2		T337	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	23	1			T26	1		T193	1		T194	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	14	1			T27	1		T151	2		T338	1
auto[4]	auto[StDisabled]	auto[OpGenId]	31	1			T151	1		T62	1		T335	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	21	1			T225	1		T112	1		T140	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	85	1			T119	1		T150	1		T193	1
auto[4]	auto[StDisabled]	auto[OpDisable]	8	1			T339	1		T340	1		T246	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	2	1			T99	1		T341	1		-	-
auto[4]	auto[StInvalid]	auto[OpGenId]	5	1			T180	1		T342	1		T343	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T98	1		T309	1		T285	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T55	1		T269	1		T309	1
auto[5]	auto[StReset]	auto[OpGenId]	10	1			T125	1		T82	1		T190	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	6	1			T247	1		T246	1		T344	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	21	1			T1	1		T149	1		T345	1
auto[5]	auto[StInit]	auto[OpAdvance]	2	1			T319	1		T346	1		-	-
auto[5]	auto[StInit]	auto[OpGenId]	4	1			T110	1		T347	1		T348	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	6	1			T112	1		T338	1		T97	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	15	1			T149	1		T117	1		T349	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T253	1		T350	1		T87	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T22	1		T303	1		T292	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	3	1			T191	1		T351	1		T352	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	17	1			T1	1		T333	1		T353	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T213	1		T354	1		T355	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T288	1		T356	1		T357	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T112	1		T79	1		T358	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	20	1			T119	1		T359	1		T360	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T213	1		T291	1		-	-
auto[5]	auto[StOwnerKey]	auto[OpGenId]	5	1			T282	1		T212	1		T242	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T136	1		T213	1		T361	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	12	1			T278	1		T279	1		T209	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	12	1			T213	1		T190	1		T362	1
auto[5]	auto[StDisabled]	auto[OpGenId]	27	1			T112	1		T60	1		T363	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	29	1			T112	1		T192	1		T81	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	71	1			T94	1		T150	1		T90	1
auto[5]	auto[StDisabled]	auto[OpDisable]	2	1			T253	1		T354	1		-	-
auto[5]	auto[StInvalid]	auto[OpAdvance]	1	1			T364	1		-	-		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	4	1			T269	1		T321	1		T365	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T96	1		T285	1		T366	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T179	1		T367	1		T364	1
auto[6]	auto[StReset]	auto[OpGenId]	5	1			T189	1		T368	1		T234	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	6	1			T153	1		T140	1		T64	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	31	1			T56	1		T290	1		T323	1
auto[6]	auto[StInit]	auto[OpAdvance]	1	1			T334	1		-	-		-	-
auto[6]	auto[StInit]	auto[OpGenId]	7	1			T369	1		T24	1		T82	2
auto[6]	auto[StInit]	auto[OpGenSwOut]	8	1			T189	1		T339	1		T370	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	11	1			T137	1		T194	1		T371	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	1	1			T218	1		-	-		-	-
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T54	1		T71	1		T82	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T189	1		T109	1		T253	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	14	1			T231	1		T210	1		T372	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T182	1		T373	1		-	-
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T134	1		T374	1		T242	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	4	1			T375	1		T376	1		T334	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T137	1		T282	1		T377	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T378	1		T331	1		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenId]	3	1			T136	1		T247	1		T191	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T189	1		T379	1		T380	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	25	1			T75	1		T381	1		T382	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	14	1			T383	1		T384	1		T189	1
auto[6]	auto[StDisabled]	auto[OpGenId]	25	1			T27	1		T62	1		T61	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	18	1			T112	1		T221	1		T136	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	88	1			T3	1		T94	1		T150	1
auto[6]	auto[StDisabled]	auto[OpDisable]	5	1			T80	1		T77	1		T246	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	1	1			T343	1		-	-		-	-
auto[6]	auto[StInvalid]	auto[OpGenId]	6	1			T96	1		T320	1		T287	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T44	1		T100	1		T366	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T214	1		T385	1		T287	1
auto[7]	auto[StReset]	auto[OpGenId]	4	1			T311	1		T386	1		T387	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	8	1			T39	1		T60	1		T23	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	17	1			T71	1		T62	1		T8	1
auto[7]	auto[StInit]	auto[OpAdvance]	1	1			T153	1		-	-		-	-
auto[7]	auto[StInit]	auto[OpGenId]	6	1			T188	1		T303	1		T388	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	6	1			T4	1		T110	1		T374	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	13	1			T37	1		T345	1		T24	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T92	1		T76	1		T254	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T19	1		T112	1		T118	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T335	1		T389	1		T386	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	26	1			T94	1		T119	1		T194	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T213	1		T58	1		-	-
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T75	1		T7	1		T247	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T92	1		T71	1		T390	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	22	1			T290	1		T273	1		T391	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T392	1		T373	1		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenId]	7	1			T221	1		T60	2		T61	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T71	1		T393	1		T136	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	33	1			T229	1		T300	1		T153	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	11	1			T77	1		T336	1		T190	1
auto[7]	auto[StDisabled]	auto[OpGenId]	30	1			T5	1		T18	1		T124	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	26	1			T19	1		T112	1		T153	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	90	1			T94	1		T119	1		T149	1
auto[7]	auto[StDisabled]	auto[OpDisable]	6	1			T66	1		T77	1		T189	1
auto[7]	auto[StInvalid]	auto[OpGenId]	3	1			T43	1		T310	1		T284	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T56	1		T101	1		T287	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T309	1		T100	1		T310	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1379

1

T1

2

T3

2

T4

1

clear_one[1]

auto[0]

auto[0]

auto[0]

409

1

T4

1

T18

1

T19

2

clear_one[1]

auto[0]

auto[0]

auto[1]

116

1

T95

1

T138

1

T90

2

clear_one[1]

auto[0]

auto[1]

auto[0]

132

1

T1

1

T3

1

T94

1

clear_one[1]

auto[0]

auto[1]

auto[1]

37

1

T358

1

T134

1

T102

2

clear_one[2]

auto[0]

auto[0]

auto[0]

412

1

T1

1

T3

2

T4

1

clear_one[2]

auto[0]

auto[0]

auto[1]

108

1

T18

1

T138

1

T232

1

clear_one[2]

auto[1]

auto[0]

auto[0]

114

1

T19

1

T26

1

T149

2

clear_one[2]

auto[1]

auto[0]

auto[1]

28

1

T66

1

T222

1

T393

1

clear_one[3]

auto[0]

auto[0]

auto[0]

401

1

T3

1

T4

1

T18

1

clear_one[3]

auto[0]

auto[1]

auto[0]

123

1

T1

1

T3

2

T94

1

clear_one[3]

auto[1]

auto[0]

auto[0]

128

1

T5

1

T149

2

T150

1

clear_one[3]

auto[1]

auto[1]

auto[0]

26

1

T88

1

T92

1

T112

2

clear_none

auto[0]

auto[0]

auto[0]

1356

1

T1

5

T3

2

T4

2

clear_none

auto[0]

auto[0]

auto[1]

131

1

T5

1

T119

1

T27

2

clear_none

auto[0]

auto[1]

auto[0]

110

1

T1

3

T3

1

T5

1

clear_none

auto[0]

auto[1]

auto[1]

50

1

T52

1

T153

2

T64

1

clear_none

auto[1]

auto[0]

auto[0]

103

1

T149

2

T150

1

T137

1

clear_none

auto[1]

auto[0]

auto[1]

41

1

T61

1

T73

1

T116

1

clear_none

auto[1]

auto[1]

auto[0]

25

1

T93

1

T223

1

T112

1

clear_none

auto[1]

auto[1]

auto[1]

21

1

T112

1

T61

1

T103

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1327	1			T1	2		T3	2		T4	1
clear_all	auto[1]	52	1			T124	1		T151	2		T153	2
clear_one[1]	auto[0]	637	1			T1	1		T3	1		T4	1
clear_one[1]	auto[1]	57	1			T141	1		T277	2		T271	4
clear_one[2]	auto[0]	624	1			T1	1		T3	2		T4	1
clear_one[2]	auto[1]	38	1			T125	1		T151	3		T139	1
clear_one[3]	auto[0]	645	1			T1	1		T3	3		T4	1
clear_one[3]	auto[1]	33	1			T124	3		T139	2		T141	1
clear_none	auto[0]	1741	1			T1	8		T3	3		T4	2
clear_none	auto[1]	96	1			T124	3		T125	1		T153	3