Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11008

1

T1

19

T3

10

T4

10

auto[Attestation]

7425

1

T1

5

T3

7

T4

2

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2702	1			T4	1		T5	3		T6	2
auto[Aes]	3222	1			T4	3		T5	2		T18	5
auto[Kmac]	3344	1			T1	24		T3	17		T4	3
auto[Otbn]	3289	1			T4	1		T5	4		T6	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7570	1			T1	8		T3	8		T4	8
auto[OpGenId]	5876	1			T4	4		T5	9		T6	3
auto[OpGenSwOut]	5779	1			T4	4		T5	6		T6	1
auto[OpGenHwOut]	6778	1			T1	24		T3	17		T4	4
auto[OpDisable]	132	1			T52	1		T53	1		T54	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10377

1

T1

8

T3

8

T4

8

auto[OpDoneFail]

15758

1

T1

24

T3

17

T4

12

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6449	1			T1	17		T3	10		T4	5
auto[StInit]	3733	1			T1	2		T3	2		T4	2
auto[StCreatorRootKey]	3123	1			T1	2		T3	2		T4	2
auto[StOwnerIntKey]	2721	1			T1	2		T3	2		T4	2
auto[StOwnerKey]	2346	1			T1	2		T3	2		T4	2
auto[StDisabled]	7763	1			T1	7		T3	7		T4	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	341	1			T18	1		T19	1		T39	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	114	1			T6	1		T19	1		T37	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	87	1			T88	1		T89	1		T30	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	83	1			T5	1		T35	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	52	1			T5	1		T217	1		T112	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	210	1			T5	1		T19	1		T54	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	338	1			T18	2		T19	3		T36	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	82	1			T26	1		T138	1		T218	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	72	1			T18	1		T95	1		T135	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	66	1			T112	3		T7	1		T60	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	65	1			T35	1		T26	1		T219	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	211	1			T4	1		T26	4		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	324	1			T18	1		T19	1		T36	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	103	1			T4	1		T36	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	81	1			T19	2		T37	1		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	69	1			T36	1		T37	1		T65	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	57	1			T36	1		T112	1		T220	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	196	1			T4	1		T36	1		T26	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	343	1			T36	2		T39	1		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	98	1			T35	1		T26	1		T95	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	76	1			T124	1		T221	1		T222	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	62	1			T19	1		T112	1		T67	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	44	1			T88	1		T64	1		T61	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	219	1			T4	1		T53	1		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	63	1			T112	4		T60	2		T51	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	99	1			T19	1		T27	1		T30	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	89	1			T135	1		T30	1		T62	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	78	1			T72	1		T223	1		T60	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	49	1			T93	2		T125	1		T224	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	225	1			T26	1		T53	1		T138	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	50	1			T112	3		T60	2		T132	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	88	1			T37	1		T75	1		T93	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	81	1			T88	1		T225	1		T112	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	71	1			T218	1		T226	1		T125	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	64	1			T35	1		T112	1		T227	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	205	1			T5	1		T18	1		T26	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	73	1			T60	3		T132	1		T134	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	92	1			T18	1		T72	1		T138	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	82	1			T19	1		T72	1		T221	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	69	1			T35	2		T26	1		T151	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	63	1			T19	1		T93	1		T71	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	231	1			T19	1		T53	1		T138	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	64	1			T112	1		T60	3		T134	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	108	1			T19	1		T27	1		T38	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	88	1			T54	1		T228	1		T225	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	67	1			T138	1		T228	3		T62	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	52	1			T62	1		T60	2		T31	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	235	1			T5	2		T18	1		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	266	1			T6	1		T18	1		T19	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	88	1			T49	1		T38	1		T124	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	90	1			T4	1		T135	1		T53	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	66	1			T138	1		T221	1		T60	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	45	1			T49	1		T27	1		T75	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	175	1			T88	1		T92	2		T228	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	440	1			T18	1		T19	1		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	106	1			T149	1		T137	1		T229	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	101	1			T150	1		T137	1		T72	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	88	1			T4	1		T5	1		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	84	1			T149	1		T75	1		T230	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	290	1			T19	1		T26	1		T149	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	508	1			T1	16		T3	9		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	108	1			T37	1		T49	1		T50	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	98	1			T37	1		T93	1		T231	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	91	1			T1	1		T94	1		T135	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	88	1			T18	1		T135	1		T231	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	281	1			T1	2		T3	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	432	1			T6	1		T18	2		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	121	1			T52	1		T38	1		T54	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	114	1			T5	1		T37	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	93	1			T37	1		T232	1		T125	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	86	1			T35	1		T26	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	273	1			T18	1		T95	1		T52	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	56	1			T112	1		T60	2		T132	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	98	1			T19	1		T135	1		T43	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	50	1			T19	1		T72	1		T138	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	56	1			T95	1		T65	1		T125	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	54	1			T19	1		T26	1		T88	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	168	1			T95	1		T49	1		T138	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	57	1			T60	3		T132	2		T118	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	119	1			T150	1		T92	1		T93	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	101	1			T135	1		T149	1		T53	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	98	1			T37	3		T26	1		T149	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	85	1			T4	1		T135	1		T150	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	260	1			T19	1		T26	1		T149	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	64	1			T112	2		T60	3		T132	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	118	1			T1	1		T3	1		T94	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	120	1			T1	1		T3	1		T94	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	92	1			T3	1		T37	1		T218	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	83	1			T1	1		T3	1		T94	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	253	1			T1	2		T3	3		T94	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	55	1			T112	1		T60	2		T134	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	135	1			T26	1		T119	1		T53	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	110	1			T119	1		T38	1		T90	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	81	1			T19	1		T37	1		T119	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	79	1			T5	1		T119	1		T135	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	254	1			T119	2		T90	1		T232	3

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	207	1			T5	1		T35	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	680	1			T5	2		T6	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	190	1			T18	1		T35	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	644	1			T4	1		T18	2		T19	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	193	1			T19	2		T36	2		T37	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	637	1			T4	2		T18	1		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	165	1			T19	1		T88	1		T124	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	677	1			T4	1		T35	1		T36	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	197	1			T135	1		T72	1		T30	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	406	1			T19	1		T26	1		T53	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	195	1			T35	1		T225	1		T226	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	364	1			T5	1		T18	1		T37	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	201	1			T19	2		T35	2		T72	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	409	1			T18	1		T19	1		T26	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	194	1			T138	1		T54	1		T228	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	420	1			T5	2		T18	1		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	187	1			T4	1		T135	1		T49	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	543	1			T6	1		T18	1		T19	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	259	1			T4	1		T5	1		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	850	1			T18	1		T19	2		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	261	1			T1	1		T18	1		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	913	1			T1	18		T3	10		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	281	1			T5	1		T35	1		T37	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	838	1			T6	1		T18	3		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	146	1			T19	2		T95	1		T72	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	336	1			T19	1		T26	1		T95	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	273	1			T4	1		T37	3		T26	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	447	1			T19	1		T26	1		T149	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	280	1			T1	2		T3	3		T37	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	450	1			T1	3		T3	4		T94	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	250	1			T5	1		T19	1		T37	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	464	1			T26	1		T119	3		T53	1