Unified Coverage Report :: Group Instance : salt_7

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2817

1

T5

1

T6

1

T17

3

auto[1]

294

1

T124

2

T125

2

T151

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	92	1			T17	1		T135	1		T138	1
auto[134217728:268435455]	88	1			T219	1		T55	1		T151	1
auto[268435456:402653183]	97	1			T17	1		T138	1		T88	1
auto[402653184:536870911]	95	1			T37	1		T92	1		T93	1
auto[536870912:671088639]	104	1			T37	1		T49	2		T43	1
auto[671088640:805306367]	99	1			T6	1		T26	1		T39	1
auto[805306368:939524095]	90	1			T17	1		T93	1		T112	1
auto[939524096:1073741823]	94	1			T138	2		T55	1		T222	1
auto[1073741824:1207959551]	98	1			T27	2		T112	1		T71	1
auto[1207959552:1342177279]	87	1			T26	1		T53	1		T125	1
auto[1342177280:1476395007]	99	1			T19	1		T125	1		T60	1
auto[1476395008:1610612735]	96	1			T27	1		T65	1		T226	1
auto[1610612736:1744830463]	100	1			T43	1		T228	1		T225	1
auto[1744830464:1879048191]	82	1			T5	1		T50	1		T218	1
auto[1879048192:2013265919]	93	1			T112	1		T60	2		T51	2
auto[2013265920:2147483647]	102	1			T18	1		T27	1		T75	1
auto[2147483648:2281701375]	113	1			T43	2		T93	1		T44	1
auto[2281701376:2415919103]	91	1			T18	1		T19	1		T26	1
auto[2415919104:2550136831]	95	1			T19	1		T218	1		T92	1
auto[2550136832:2684354559]	111	1			T65	1		T228	1		T226	1
auto[2684354560:2818572287]	104	1			T26	1		T52	1		T135	1
auto[2818572288:2952790015]	91	1			T18	1		T19	1		T65	1
auto[2952790016:3087007743]	110	1			T18	1		T50	1		T75	1
auto[3087007744:3221225471]	97	1			T19	1		T50	1		T125	1
auto[3221225472:3355443199]	104	1			T27	1		T138	1		T225	1
auto[3355443200:3489660927]	96	1			T50	1		T218	1		T223	1
auto[3489660928:3623878655]	105	1			T19	1		T218	1		T219	1
auto[3623878656:3758096383]	104	1			T39	1		T138	1		T93	1
auto[3758096384:3892314111]	99	1			T18	1		T88	1		T219	1
auto[3892314112:4026531839]	108	1			T124	1		T226	1		T125	1
auto[4026531840:4160749567]	90	1			T225	1		T112	1		T56	2
auto[4160749568:4294967295]	77	1			T39	1		T27	1		T56	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	79	1			T17	1		T135	1		T138	1
auto[0:134217727]	auto[1]	13	1			T153	1		T139	1		T422	1
auto[134217728:268435455]	auto[0]	79	1			T219	1		T55	1		T79	1
auto[134217728:268435455]	auto[1]	9	1			T151	1		T153	1		T260	1
auto[268435456:402653183]	auto[0]	90	1			T17	1		T138	1		T88	1
auto[268435456:402653183]	auto[1]	7	1			T264	2		T422	1		T421	1
auto[402653184:536870911]	auto[0]	87	1			T37	1		T92	1		T93	1
auto[402653184:536870911]	auto[1]	8	1			T262	1		T213	2		T427	1
auto[536870912:671088639]	auto[0]	97	1			T37	1		T49	2		T43	1
auto[536870912:671088639]	auto[1]	7	1			T140	1		T141	1		T213	1
auto[671088640:805306367]	auto[0]	86	1			T6	1		T26	1		T39	1
auto[671088640:805306367]	auto[1]	13	1			T151	1		T153	1		T140	1
auto[805306368:939524095]	auto[0]	83	1			T17	1		T93	1		T112	1
auto[805306368:939524095]	auto[1]	7	1			T151	1		T262	1		T418	1
auto[939524096:1073741823]	auto[0]	89	1			T138	2		T55	1		T222	1
auto[939524096:1073741823]	auto[1]	5	1			T301	1		T436	1		T435	1
auto[1073741824:1207959551]	auto[0]	85	1			T27	2		T112	1		T71	1
auto[1073741824:1207959551]	auto[1]	13	1			T140	1		T264	3		T420	1
auto[1207959552:1342177279]	auto[0]	81	1			T26	1		T53	1		T125	1
auto[1207959552:1342177279]	auto[1]	6	1			T139	1		T262	1		T431	1
auto[1342177280:1476395007]	auto[0]	92	1			T19	1		T125	1		T60	1
auto[1342177280:1476395007]	auto[1]	7	1			T140	2		T431	1		T334	1
auto[1476395008:1610612735]	auto[0]	91	1			T27	1		T65	1		T226	1
auto[1476395008:1610612735]	auto[1]	5	1			T271	1		T213	1		T418	1
auto[1610612736:1744830463]	auto[0]	88	1			T43	1		T228	1		T225	1
auto[1610612736:1744830463]	auto[1]	12	1			T141	1		T271	1		T264	2
auto[1744830464:1879048191]	auto[0]	77	1			T5	1		T50	1		T218	1
auto[1744830464:1879048191]	auto[1]	5	1			T140	1		T264	1		T355	1
auto[1879048192:2013265919]	auto[0]	91	1			T112	1		T60	2		T51	2
auto[1879048192:2013265919]	auto[1]	2	1			T421	1		T437	1		-	-
auto[2013265920:2147483647]	auto[0]	87	1			T18	1		T27	1		T75	1
auto[2013265920:2147483647]	auto[1]	15	1			T125	1		T153	2		T277	1
auto[2147483648:2281701375]	auto[0]	104	1			T43	2		T93	1		T44	1
auto[2147483648:2281701375]	auto[1]	9	1			T264	1		T275	2		T301	1
auto[2281701376:2415919103]	auto[0]	80	1			T18	1		T19	1		T26	1
auto[2281701376:2415919103]	auto[1]	11	1			T260	2		T423	1		T351	2
auto[2415919104:2550136831]	auto[0]	87	1			T19	1		T218	1		T92	1
auto[2415919104:2550136831]	auto[1]	8	1			T151	1		T262	1		T213	1
auto[2550136832:2684354559]	auto[0]	99	1			T65	1		T228	1		T226	1
auto[2550136832:2684354559]	auto[1]	12	1			T139	2		T277	1		T213	1
auto[2684354560:2818572287]	auto[0]	93	1			T26	1		T52	1		T135	1
auto[2684354560:2818572287]	auto[1]	11	1			T153	3		T141	1		T277	1
auto[2818572288:2952790015]	auto[0]	84	1			T18	1		T19	1		T65	1
auto[2818572288:2952790015]	auto[1]	7	1			T124	1		T141	1		T383	1
auto[2952790016:3087007743]	auto[0]	98	1			T18	1		T50	1		T75	1
auto[2952790016:3087007743]	auto[1]	12	1			T213	1		T260	1		T402	1
auto[3087007744:3221225471]	auto[0]	83	1			T19	1		T50	1		T125	1
auto[3087007744:3221225471]	auto[1]	14	1			T153	1		T139	1		T141	1
auto[3221225472:3355443199]	auto[0]	96	1			T27	1		T138	1		T225	1
auto[3221225472:3355443199]	auto[1]	8	1			T151	1		T264	1		T419	1
auto[3355443200:3489660927]	auto[0]	86	1			T50	1		T218	1		T223	1
auto[3355443200:3489660927]	auto[1]	10	1			T140	1		T262	1		T264	1
auto[3489660928:3623878655]	auto[0]	94	1			T19	1		T218	1		T219	1
auto[3489660928:3623878655]	auto[1]	11	1			T141	1		T213	2		T260	2
auto[3623878656:3758096383]	auto[0]	97	1			T39	1		T138	1		T93	1
auto[3623878656:3758096383]	auto[1]	7	1			T124	1		T153	1		T213	1
auto[3758096384:3892314111]	auto[0]	82	1			T18	1		T88	1		T219	1
auto[3758096384:3892314111]	auto[1]	17	1			T153	1		T139	1		T140	2
auto[3892314112:4026531839]	auto[0]	99	1			T124	1		T226	1		T112	2
auto[3892314112:4026531839]	auto[1]	9	1			T125	1		T213	1		T272	2
auto[4026531840:4160749567]	auto[0]	83	1			T225	1		T112	1		T56	2
auto[4026531840:4160749567]	auto[1]	7	1			T260	1		T419	1		T421	1
auto[4160749568:4294967295]	auto[0]	70	1			T39	1		T27	1		T56	1
auto[4160749568:4294967295]	auto[1]	7	1			T141	1		T264	1		T403	1