Unified Coverage Report :: Group Instance : sealing_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1563

1

T17

2

T18

4

T19

2

auto[1]

1673

1

T5

1

T6

1

T17

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	105	1			T6	1		T18	1		T19	1
auto[134217728:268435455]	80	1			T19	1		T27	1		T44	1
auto[268435456:402653183]	93	1			T19	1		T49	1		T27	1
auto[402653184:536870911]	102	1			T138	1		T225	1		T112	1
auto[536870912:671088639]	112	1			T218	1		T152	1		T60	3
auto[671088640:805306367]	111	1			T17	1		T19	1		T53	1
auto[805306368:939524095]	101	1			T19	1		T228	1		T55	1
auto[939524096:1073741823]	106	1			T218	1		T88	1		T112	1
auto[1073741824:1207959551]	86	1			T125	1		T55	1		T62	1
auto[1207959552:1342177279]	100	1			T37	1		T43	1		T228	1
auto[1342177280:1476395007]	97	1			T19	1		T39	1		T27	1
auto[1476395008:1610612735]	95	1			T26	1		T39	1		T50	1
auto[1610612736:1744830463]	91	1			T49	1		T27	1		T75	1
auto[1744830464:1879048191]	112	1			T27	1		T138	1		T218	1
auto[1879048192:2013265919]	98	1			T37	1		T50	1		T218	1
auto[2013265920:2147483647]	95	1			T44	1		T56	1		T60	2
auto[2147483648:2281701375]	111	1			T43	1		T92	1		T124	1
auto[2281701376:2415919103]	109	1			T17	1		T65	1		T79	2
auto[2415919104:2550136831]	112	1			T88	1		T93	1		T228	2
auto[2550136832:2684354559]	98	1			T5	1		T226	1		T112	1
auto[2684354560:2818572287]	91	1			T17	1		T54	1		T226	1
auto[2818572288:2952790015]	99	1			T52	1		T27	1		T151	1
auto[2952790016:3087007743]	101	1			T18	2		T39	1		T65	1
auto[3087007744:3221225471]	111	1			T135	1		T88	1		T93	1
auto[3221225472:3355443199]	100	1			T75	1		T92	1		T124	1
auto[3355443200:3489660927]	111	1			T30	1		T225	1		T112	1
auto[3489660928:3623878655]	96	1			T18	1		T26	1		T75	1
auto[3623878656:3758096383]	97	1			T26	1		T138	1		T65	1
auto[3758096384:3892314111]	111	1			T135	1		T138	1		T226	1
auto[3892314112:4026531839]	94	1			T18	1		T50	1		T43	1
auto[4026531840:4160749567]	93	1			T26	1		T50	1		T55	1
auto[4160749568:4294967295]	118	1			T39	1		T50	1		T124	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	47	1			T50	1		T56	1		T60	1
auto[0:134217727]	auto[1]	58	1			T6	1		T18	1		T19	1
auto[134217728:268435455]	auto[0]	39	1			T19	1		T44	1		T309	1
auto[134217728:268435455]	auto[1]	41	1			T27	1		T62	1		T141	1
auto[268435456:402653183]	auto[0]	43	1			T49	1		T27	1		T140	1
auto[268435456:402653183]	auto[1]	50	1			T19	1		T92	1		T225	1
auto[402653184:536870911]	auto[0]	46	1			T60	1		T424	1		T64	1
auto[402653184:536870911]	auto[1]	56	1			T138	1		T225	1		T112	1
auto[536870912:671088639]	auto[0]	57	1			T218	1		T152	1		T60	2
auto[536870912:671088639]	auto[1]	55	1			T60	1		T224	1		T132	1
auto[671088640:805306367]	auto[0]	52	1			T19	1		T125	1		T222	1
auto[671088640:805306367]	auto[1]	59	1			T17	1		T53	1		T43	1
auto[805306368:939524095]	auto[0]	50	1			T55	1		T369	1		T60	2
auto[805306368:939524095]	auto[1]	51	1			T19	1		T228	1		T223	1
auto[939524096:1073741823]	auto[0]	46	1			T88	1		T369	1		T99	1
auto[939524096:1073741823]	auto[1]	60	1			T218	1		T112	1		T152	1
auto[1073741824:1207959551]	auto[0]	40	1			T125	1		T98	1		T99	1
auto[1073741824:1207959551]	auto[1]	46	1			T55	1		T62	1		T393	1
auto[1207959552:1342177279]	auto[0]	50	1			T152	1		T44	1		T51	1
auto[1207959552:1342177279]	auto[1]	50	1			T37	1		T43	1		T228	1
auto[1342177280:1476395007]	auto[0]	58	1			T39	1		T50	1		T112	1
auto[1342177280:1476395007]	auto[1]	39	1			T19	1		T27	1		T415	1
auto[1476395008:1610612735]	auto[0]	40	1			T39	1		T50	1		T425	1
auto[1476395008:1610612735]	auto[1]	55	1			T26	1		T60	1		T141	1
auto[1610612736:1744830463]	auto[0]	49	1			T49	1		T27	1		T75	1
auto[1610612736:1744830463]	auto[1]	42	1			T79	1		T101	1		T118	1
auto[1744830464:1879048191]	auto[0]	60	1			T60	2		T64	1		T8	1
auto[1744830464:1879048191]	auto[1]	52	1			T27	1		T138	1		T218	1
auto[1879048192:2013265919]	auto[0]	46	1			T37	1		T50	1		T153	1
auto[1879048192:2013265919]	auto[1]	52	1			T218	1		T75	1		T79	1
auto[2013265920:2147483647]	auto[0]	40	1			T44	1		T56	1		T60	1
auto[2013265920:2147483647]	auto[1]	55	1			T60	1		T100	1		T188	1
auto[2147483648:2281701375]	auto[0]	50	1			T124	1		T125	1		T44	1
auto[2147483648:2281701375]	auto[1]	61	1			T43	1		T92	1		T125	1
auto[2281701376:2415919103]	auto[0]	54	1			T17	1		T65	1		T79	1
auto[2281701376:2415919103]	auto[1]	55	1			T79	1		T51	2		T31	1
auto[2415919104:2550136831]	auto[0]	56	1			T228	1		T112	1		T152	1
auto[2415919104:2550136831]	auto[1]	56	1			T88	1		T93	1		T228	1
auto[2550136832:2684354559]	auto[0]	54	1			T226	1		T221	1		T426	1
auto[2550136832:2684354559]	auto[1]	44	1			T5	1		T112	1		T51	1
auto[2684354560:2818572287]	auto[0]	46	1			T17	1		T64	1		T132	1
auto[2684354560:2818572287]	auto[1]	45	1			T54	1		T226	1		T60	2
auto[2818572288:2952790015]	auto[0]	44	1			T52	1		T151	1		T222	1
auto[2818572288:2952790015]	auto[1]	55	1			T27	1		T153	1		T220	1
auto[2952790016:3087007743]	auto[0]	46	1			T18	2		T39	1		T65	1
auto[2952790016:3087007743]	auto[1]	55	1			T225	1		T62	2		T153	1
auto[3087007744:3221225471]	auto[0]	52	1			T93	1		T62	1		T98	1
auto[3087007744:3221225471]	auto[1]	59	1			T135	1		T88	1		T62	1
auto[3221225472:3355443199]	auto[0]	58	1			T75	1		T92	1		T112	3
auto[3221225472:3355443199]	auto[1]	42	1			T124	1		T112	1		T66	1
auto[3355443200:3489660927]	auto[0]	42	1			T221	1		T62	1		T60	1
auto[3355443200:3489660927]	auto[1]	69	1			T30	1		T225	1		T112	1
auto[3489660928:3623878655]	auto[0]	43	1			T18	1		T75	1		T30	1
auto[3489660928:3623878655]	auto[1]	53	1			T26	1		T93	1		T219	1
auto[3623878656:3758096383]	auto[0]	57	1			T138	1		T228	1		T62	1
auto[3623878656:3758096383]	auto[1]	40	1			T26	1		T65	1		T93	1
auto[3758096384:3892314111]	auto[0]	56	1			T138	1		T62	2		T56	1
auto[3758096384:3892314111]	auto[1]	55	1			T135	1		T226	1		T62	1
auto[3892314112:4026531839]	auto[0]	39	1			T18	1		T50	1		T138	1
auto[3892314112:4026531839]	auto[1]	55	1			T43	1		T93	1		T226	1
auto[4026531840:4160749567]	auto[0]	46	1			T50	1		T112	1		T60	1
auto[4026531840:4160749567]	auto[1]	47	1			T26	1		T55	1		T220	1
auto[4160749568:4294967295]	auto[0]	57	1			T39	1		T50	1		T151	1
auto[4160749568:4294967295]	auto[1]	61	1			T124	1		T219	1		T151	1