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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6609 1 T5 9 T6 2 T17 7
auto[1] 270 1 T124 7 T125 1 T151 9


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 2773 1 T5 4 T6 1 T17 3
auto[134217728:268435455] 154 1 T5 1 T19 1 T53 1
auto[268435456:402653183] 159 1 T218 2 T30 1 T93 1
auto[402653184:536870911] 155 1 T6 1 T19 1 T26 1
auto[536870912:671088639] 129 1 T39 1 T27 2 T50 1
auto[671088640:805306367] 133 1 T17 2 T18 1 T219 2
auto[805306368:939524095] 136 1 T52 1 T27 2 T218 1
auto[939524096:1073741823] 154 1 T39 1 T27 1 T138 1
auto[1073741824:1207959551] 142 1 T50 1 T75 1 T65 1
auto[1207959552:1342177279] 148 1 T138 1 T88 1 T228 2
auto[1342177280:1476395007] 141 1 T43 1 T228 1 T225 2
auto[1476395008:1610612735] 111 1 T37 1 T26 1 T75 2
auto[1610612736:1744830463] 113 1 T18 1 T37 1 T65 1
auto[1744830464:1879048191] 129 1 T5 1 T18 1 T26 1
auto[1879048192:2013265919] 104 1 T39 1 T138 1 T228 1
auto[2013265920:2147483647] 121 1 T5 1 T19 1 T27 1
auto[2147483648:2281701375] 151 1 T5 1 T135 2 T138 1
auto[2281701376:2415919103] 119 1 T27 1 T112 2 T44 1
auto[2415919104:2550136831] 118 1 T19 1 T88 1 T153 1
auto[2550136832:2684354559] 128 1 T26 1 T226 1 T55 1
auto[2684354560:2818572287] 141 1 T18 1 T19 1 T50 1
auto[2818572288:2952790015] 136 1 T18 1 T19 1 T27 1
auto[2952790016:3087007743] 118 1 T27 1 T65 1 T92 1
auto[3087007744:3221225471] 110 1 T92 1 T225 2 T62 1
auto[3221225472:3355443199] 146 1 T17 1 T49 1 T92 2
auto[3355443200:3489660927] 111 1 T26 1 T124 1 T219 1
auto[3489660928:3623878655] 119 1 T18 1 T49 1 T27 1
auto[3623878656:3758096383] 124 1 T19 1 T218 3 T124 1
auto[3758096384:3892314111] 138 1 T5 1 T138 1 T88 1
auto[3892314112:4026531839] 134 1 T19 1 T218 1 T228 1
auto[4026531840:4160749567] 152 1 T17 1 T19 1 T26 1
auto[4160749568:4294967295] 132 1 T26 1 T228 2 T225 2


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 2765 1 T5 4 T6 1 T17 3
auto[0:134217727] auto[1] 8 1 T151 1 T139 1 T422 1
auto[134217728:268435455] auto[0] 146 1 T5 1 T19 1 T53 1
auto[134217728:268435455] auto[1] 8 1 T124 2 T151 1 T141 1
auto[268435456:402653183] auto[0] 154 1 T218 2 T30 1 T93 1
auto[268435456:402653183] auto[1] 5 1 T151 2 T351 1 T427 1
auto[402653184:536870911] auto[0] 146 1 T6 1 T19 1 T26 1
auto[402653184:536870911] auto[1] 9 1 T153 1 T140 1 T213 1
auto[536870912:671088639] auto[0] 122 1 T39 1 T27 2 T50 1
auto[536870912:671088639] auto[1] 7 1 T153 1 T264 1 T291 1
auto[671088640:805306367] auto[0] 122 1 T17 2 T18 1 T219 2
auto[671088640:805306367] auto[1] 11 1 T151 1 T277 1 T264 1
auto[805306368:939524095] auto[0] 130 1 T52 1 T27 2 T218 1
auto[805306368:939524095] auto[1] 6 1 T153 1 T264 1 T272 2
auto[939524096:1073741823] auto[0] 148 1 T39 1 T27 1 T138 1
auto[939524096:1073741823] auto[1] 6 1 T151 1 T277 1 T419 2
auto[1073741824:1207959551] auto[0] 131 1 T50 1 T75 1 T65 1
auto[1073741824:1207959551] auto[1] 11 1 T277 1 T264 1 T213 1
auto[1207959552:1342177279] auto[0] 136 1 T138 1 T88 1 T228 2
auto[1207959552:1342177279] auto[1] 12 1 T139 1 T271 1 T213 2
auto[1342177280:1476395007] auto[0] 129 1 T43 1 T228 1 T225 2
auto[1342177280:1476395007] auto[1] 12 1 T213 1 T272 1 T401 1
auto[1476395008:1610612735] auto[0] 102 1 T37 1 T26 1 T75 2
auto[1476395008:1610612735] auto[1] 9 1 T264 1 T337 1 T419 1
auto[1610612736:1744830463] auto[0] 107 1 T18 1 T37 1 T65 1
auto[1610612736:1744830463] auto[1] 6 1 T141 1 T423 1 T422 1
auto[1744830464:1879048191] auto[0] 117 1 T5 1 T18 1 T26 1
auto[1744830464:1879048191] auto[1] 12 1 T124 1 T153 1 T139 1
auto[1879048192:2013265919] auto[0] 96 1 T39 1 T138 1 T228 1
auto[1879048192:2013265919] auto[1] 8 1 T260 1 T418 1 T291 1
auto[2013265920:2147483647] auto[0] 111 1 T5 1 T19 1 T27 1
auto[2013265920:2147483647] auto[1] 10 1 T264 1 T213 1 T401 1
auto[2147483648:2281701375] auto[0] 145 1 T5 1 T135 2 T138 1
auto[2147483648:2281701375] auto[1] 6 1 T125 1 T153 1 T264 1
auto[2281701376:2415919103] auto[0] 113 1 T27 1 T112 2 T44 1
auto[2281701376:2415919103] auto[1] 6 1 T422 1 T351 1 T301 2
auto[2415919104:2550136831] auto[0] 109 1 T19 1 T88 1 T51 2
auto[2415919104:2550136831] auto[1] 9 1 T153 1 T262 1 T264 1
auto[2550136832:2684354559] auto[0] 126 1 T26 1 T226 1 T55 1
auto[2550136832:2684354559] auto[1] 2 1 T351 1 T428 1 - -
auto[2684354560:2818572287] auto[0] 130 1 T18 1 T19 1 T50 1
auto[2684354560:2818572287] auto[1] 11 1 T151 1 T140 1 T141 1
auto[2818572288:2952790015] auto[0] 133 1 T18 1 T19 1 T27 1
auto[2818572288:2952790015] auto[1] 3 1 T402 1 T337 1 T403 1
auto[2952790016:3087007743] auto[0] 109 1 T27 1 T65 1 T92 1
auto[2952790016:3087007743] auto[1] 9 1 T262 1 T264 1 T422 1
auto[3087007744:3221225471] auto[0] 100 1 T92 1 T225 2 T62 1
auto[3087007744:3221225471] auto[1] 10 1 T139 1 T140 1 T262 1
auto[3221225472:3355443199] auto[0] 133 1 T17 1 T49 1 T92 2
auto[3221225472:3355443199] auto[1] 13 1 T124 1 T264 1 T351 1
auto[3355443200:3489660927] auto[0] 105 1 T26 1 T124 1 T219 1
auto[3355443200:3489660927] auto[1] 6 1 T423 1 T337 1 T429 2
auto[3489660928:3623878655] auto[0] 110 1 T18 1 T49 1 T27 1
auto[3489660928:3623878655] auto[1] 9 1 T140 3 T277 1 T271 1
auto[3623878656:3758096383] auto[0] 114 1 T19 1 T218 3 T55 3
auto[3623878656:3758096383] auto[1] 10 1 T124 1 T139 1 T262 1
auto[3758096384:3892314111] auto[0] 134 1 T5 1 T138 1 T88 1
auto[3758096384:3892314111] auto[1] 4 1 T140 1 T418 1 T275 1
auto[3892314112:4026531839] auto[0] 124 1 T19 1 T218 1 T228 1
auto[3892314112:4026531839] auto[1] 10 1 T124 1 T140 1 T141 2
auto[4026531840:4160749567] auto[0] 140 1 T17 1 T19 1 T26 1
auto[4026531840:4160749567] auto[1] 12 1 T124 1 T151 2 T139 1
auto[4160749568:4294967295] auto[0] 122 1 T26 1 T228 2 T225 2
auto[4160749568:4294967295] auto[1] 10 1 T140 1 T337 1 T403 1

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