Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.67 99.04 97.91 98.14 100.00 99.02 98.41 91.19


Total test records in report: 1083
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T1006 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.2731113789 Jul 18 06:25:54 PM PDT 24 Jul 18 06:25:57 PM PDT 24 38753698 ps
T1007 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3705525086 Jul 18 06:24:51 PM PDT 24 Jul 18 06:24:55 PM PDT 24 90738895 ps
T1008 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1060436263 Jul 18 06:25:54 PM PDT 24 Jul 18 06:25:57 PM PDT 24 12331732 ps
T1009 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1431065611 Jul 18 06:25:10 PM PDT 24 Jul 18 06:25:13 PM PDT 24 468317114 ps
T1010 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.3893279192 Jul 18 06:25:53 PM PDT 24 Jul 18 06:25:55 PM PDT 24 33749979 ps
T1011 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2478407877 Jul 18 06:24:45 PM PDT 24 Jul 18 06:24:48 PM PDT 24 29170819 ps
T1012 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3251651388 Jul 18 06:25:13 PM PDT 24 Jul 18 06:25:19 PM PDT 24 1121489006 ps
T1013 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3082790457 Jul 18 06:25:54 PM PDT 24 Jul 18 06:25:58 PM PDT 24 52251243 ps
T1014 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.678313074 Jul 18 06:25:56 PM PDT 24 Jul 18 06:26:00 PM PDT 24 10815760 ps
T1015 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1815196601 Jul 18 06:24:51 PM PDT 24 Jul 18 06:24:54 PM PDT 24 75859557 ps
T1016 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2117098123 Jul 18 06:25:38 PM PDT 24 Jul 18 06:25:50 PM PDT 24 231177134 ps
T169 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2976877310 Jul 18 06:25:35 PM PDT 24 Jul 18 06:25:42 PM PDT 24 257775498 ps
T1017 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3263426589 Jul 18 06:25:35 PM PDT 24 Jul 18 06:25:39 PM PDT 24 181578855 ps
T1018 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.2732130621 Jul 18 06:24:27 PM PDT 24 Jul 18 06:24:34 PM PDT 24 1033281431 ps
T1019 /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2427635663 Jul 18 06:25:35 PM PDT 24 Jul 18 06:25:41 PM PDT 24 120855032 ps
T1020 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2902268929 Jul 18 06:25:53 PM PDT 24 Jul 18 06:25:55 PM PDT 24 34105563 ps
T1021 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.231598894 Jul 18 06:24:31 PM PDT 24 Jul 18 06:24:35 PM PDT 24 58594872 ps
T1022 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2735321351 Jul 18 06:24:45 PM PDT 24 Jul 18 06:24:52 PM PDT 24 631138404 ps
T1023 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1616778327 Jul 18 06:24:45 PM PDT 24 Jul 18 06:24:49 PM PDT 24 50546963 ps
T1024 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.2772013633 Jul 18 06:25:35 PM PDT 24 Jul 18 06:25:39 PM PDT 24 15775064 ps
T1025 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.705962390 Jul 18 06:24:43 PM PDT 24 Jul 18 06:24:46 PM PDT 24 43110913 ps
T1026 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.569131260 Jul 18 06:25:13 PM PDT 24 Jul 18 06:25:18 PM PDT 24 324597341 ps
T1027 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2232491751 Jul 18 06:25:35 PM PDT 24 Jul 18 06:25:47 PM PDT 24 357076050 ps
T1028 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.1100655789 Jul 18 06:24:32 PM PDT 24 Jul 18 06:24:41 PM PDT 24 1000642154 ps
T1029 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1516836972 Jul 18 06:25:13 PM PDT 24 Jul 18 06:25:15 PM PDT 24 90419763 ps
T1030 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.246216317 Jul 18 06:25:54 PM PDT 24 Jul 18 06:25:59 PM PDT 24 225021830 ps
T1031 /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.540925557 Jul 18 06:25:37 PM PDT 24 Jul 18 06:25:43 PM PDT 24 14465668 ps
T1032 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1250180691 Jul 18 06:25:53 PM PDT 24 Jul 18 06:25:56 PM PDT 24 100894149 ps
T1033 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.4174944984 Jul 18 06:25:33 PM PDT 24 Jul 18 06:25:39 PM PDT 24 245389323 ps
T1034 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.1440730386 Jul 18 06:24:49 PM PDT 24 Jul 18 06:24:51 PM PDT 24 39702160 ps
T1035 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3562441046 Jul 18 06:25:52 PM PDT 24 Jul 18 06:26:01 PM PDT 24 615464956 ps
T1036 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.3319752390 Jul 18 06:25:38 PM PDT 24 Jul 18 06:25:45 PM PDT 24 88498123 ps
T1037 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1040846827 Jul 18 06:25:57 PM PDT 24 Jul 18 06:26:00 PM PDT 24 19749526 ps
T159 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.3025413940 Jul 18 06:25:22 PM PDT 24 Jul 18 06:25:29 PM PDT 24 419641469 ps
T1038 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2090078011 Jul 18 06:25:14 PM PDT 24 Jul 18 06:25:17 PM PDT 24 225812681 ps
T1039 /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3717550154 Jul 18 06:25:38 PM PDT 24 Jul 18 06:25:44 PM PDT 24 44621310 ps
T1040 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.1856653270 Jul 18 06:24:28 PM PDT 24 Jul 18 06:24:31 PM PDT 24 16187880 ps
T1041 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.4047138227 Jul 18 06:25:12 PM PDT 24 Jul 18 06:25:17 PM PDT 24 409638105 ps
T1042 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.4044374903 Jul 18 06:24:46 PM PDT 24 Jul 18 06:24:49 PM PDT 24 42748026 ps
T1043 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.2270702078 Jul 18 06:24:47 PM PDT 24 Jul 18 06:24:50 PM PDT 24 33032732 ps
T1044 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.3366240090 Jul 18 06:25:53 PM PDT 24 Jul 18 06:25:55 PM PDT 24 54165097 ps
T1045 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2204996645 Jul 18 06:25:57 PM PDT 24 Jul 18 06:26:00 PM PDT 24 20535047 ps
T1046 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2657075242 Jul 18 06:25:37 PM PDT 24 Jul 18 06:25:51 PM PDT 24 843843466 ps
T1047 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2031523152 Jul 18 06:25:52 PM PDT 24 Jul 18 06:25:54 PM PDT 24 13674158 ps
T1048 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1427485486 Jul 18 06:24:51 PM PDT 24 Jul 18 06:25:05 PM PDT 24 660331304 ps
T1049 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.848537189 Jul 18 06:25:35 PM PDT 24 Jul 18 06:25:51 PM PDT 24 349960668 ps
T1050 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.345208896 Jul 18 06:25:12 PM PDT 24 Jul 18 06:25:19 PM PDT 24 435377148 ps
T1051 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.2024230540 Jul 18 06:25:59 PM PDT 24 Jul 18 06:26:02 PM PDT 24 14625700 ps
T1052 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.1695353703 Jul 18 06:25:38 PM PDT 24 Jul 18 06:25:45 PM PDT 24 142299420 ps
T171 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.191019052 Jul 18 06:25:36 PM PDT 24 Jul 18 06:25:45 PM PDT 24 900723224 ps
T1053 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2631653361 Jul 18 06:25:53 PM PDT 24 Jul 18 06:25:55 PM PDT 24 9409100 ps
T1054 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3241381578 Jul 18 06:25:11 PM PDT 24 Jul 18 06:25:14 PM PDT 24 65937238 ps
T1055 /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.4093775678 Jul 18 06:25:56 PM PDT 24 Jul 18 06:26:02 PM PDT 24 943895336 ps
T1056 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.649659524 Jul 18 06:25:57 PM PDT 24 Jul 18 06:26:01 PM PDT 24 13706476 ps
T1057 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.81933814 Jul 18 06:25:54 PM PDT 24 Jul 18 06:25:57 PM PDT 24 10135611 ps
T1058 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1922549707 Jul 18 06:25:53 PM PDT 24 Jul 18 06:25:56 PM PDT 24 12177889 ps
T1059 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1316292863 Jul 18 06:24:49 PM PDT 24 Jul 18 06:24:51 PM PDT 24 13854160 ps
T1060 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2155132266 Jul 18 06:25:35 PM PDT 24 Jul 18 06:25:45 PM PDT 24 1566637062 ps
T1061 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1735370991 Jul 18 06:25:52 PM PDT 24 Jul 18 06:25:54 PM PDT 24 127943321 ps
T1062 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2802805948 Jul 18 06:24:29 PM PDT 24 Jul 18 06:24:36 PM PDT 24 651622368 ps
T1063 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.605261506 Jul 18 06:25:36 PM PDT 24 Jul 18 06:25:41 PM PDT 24 54605665 ps
T1064 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.167411681 Jul 18 06:24:51 PM PDT 24 Jul 18 06:24:53 PM PDT 24 170686428 ps
T1065 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.884386260 Jul 18 06:25:33 PM PDT 24 Jul 18 06:25:38 PM PDT 24 276202314 ps
T1066 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3347692004 Jul 18 06:24:52 PM PDT 24 Jul 18 06:24:54 PM PDT 24 23847147 ps
T1067 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.3102804527 Jul 18 06:25:34 PM PDT 24 Jul 18 06:25:36 PM PDT 24 112276331 ps
T155 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2870072762 Jul 18 06:25:37 PM PDT 24 Jul 18 06:25:47 PM PDT 24 186264419 ps
T1068 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.3754765213 Jul 18 06:25:36 PM PDT 24 Jul 18 06:25:44 PM PDT 24 253885532 ps
T1069 /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2784464678 Jul 18 06:24:26 PM PDT 24 Jul 18 06:24:28 PM PDT 24 72192170 ps
T1070 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3502201774 Jul 18 06:25:35 PM PDT 24 Jul 18 06:25:39 PM PDT 24 71555673 ps
T1071 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3938901742 Jul 18 06:25:38 PM PDT 24 Jul 18 06:25:44 PM PDT 24 96766191 ps
T1072 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1003064872 Jul 18 06:24:46 PM PDT 24 Jul 18 06:24:49 PM PDT 24 23494875 ps
T1073 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.1212047882 Jul 18 06:25:55 PM PDT 24 Jul 18 06:25:58 PM PDT 24 19939826 ps
T1074 /workspace/coverage/cover_reg_top/38.keymgr_intr_test.1030488642 Jul 18 06:25:57 PM PDT 24 Jul 18 06:26:00 PM PDT 24 42838022 ps
T1075 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2854259780 Jul 18 06:25:36 PM PDT 24 Jul 18 06:25:41 PM PDT 24 151117630 ps
T1076 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.250392416 Jul 18 06:25:34 PM PDT 24 Jul 18 06:25:40 PM PDT 24 109552515 ps
T1077 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2043980687 Jul 18 06:25:34 PM PDT 24 Jul 18 06:25:38 PM PDT 24 237364771 ps
T1078 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1128176365 Jul 18 06:24:43 PM PDT 24 Jul 18 06:24:51 PM PDT 24 149930893 ps
T1079 /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.1816050783 Jul 18 06:25:57 PM PDT 24 Jul 18 06:26:05 PM PDT 24 327767714 ps
T1080 /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.2062273949 Jul 18 06:24:45 PM PDT 24 Jul 18 06:24:48 PM PDT 24 119938127 ps
T1081 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2591145383 Jul 18 06:25:11 PM PDT 24 Jul 18 06:25:14 PM PDT 24 287548182 ps
T157 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.648082069 Jul 18 06:25:37 PM PDT 24 Jul 18 06:25:44 PM PDT 24 56342295 ps
T1082 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2322125085 Jul 18 06:25:35 PM PDT 24 Jul 18 06:25:40 PM PDT 24 699447615 ps
T1083 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.569122335 Jul 18 06:25:54 PM PDT 24 Jul 18 06:25:57 PM PDT 24 8458370 ps

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.1219749799
Short name T19
Test name
Test status
Simulation time 177315167 ps
CPU time 6.94 seconds
Started Jul 18 06:27:10 PM PDT 24
Finished Jul 18 06:27:19 PM PDT 24
Peak memory 222296 kb
Host smart-b1dafca1-2be7-4b16-a824-d29544549a71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219749799 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.1219749799
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.1558446415
Short name T60
Test name
Test status
Simulation time 1712210555 ps
CPU time 43.32 seconds
Started Jul 18 06:30:35 PM PDT 24
Finished Jul 18 06:31:25 PM PDT 24
Peak memory 214912 kb
Host smart-a5e53cee-0118-4987-a10b-5bf57a235ac3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558446415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.1558446415
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.3184725592
Short name T6
Test name
Test status
Simulation time 94420599 ps
CPU time 2.25 seconds
Started Jul 18 06:28:02 PM PDT 24
Finished Jul 18 06:28:08 PM PDT 24
Peak memory 222360 kb
Host smart-fb6dac70-feb9-4508-a7a9-a2159744641b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184725592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.3184725592
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.472301312
Short name T77
Test name
Test status
Simulation time 8550323888 ps
CPU time 86.31 seconds
Started Jul 18 06:29:42 PM PDT 24
Finished Jul 18 06:31:13 PM PDT 24
Peak memory 222288 kb
Host smart-3c352da0-05bf-4eab-8de2-50559ca88fd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472301312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.472301312
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.2202657390
Short name T13
Test name
Test status
Simulation time 428160212 ps
CPU time 9.76 seconds
Started Jul 18 06:26:52 PM PDT 24
Finished Jul 18 06:27:07 PM PDT 24
Peak memory 229352 kb
Host smart-cdfe7288-3029-411f-af74-7fce91b9561b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202657390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.2202657390
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3809611215
Short name T121
Test name
Test status
Simulation time 204528167 ps
CPU time 4.96 seconds
Started Jul 18 06:25:38 PM PDT 24
Finished Jul 18 06:25:48 PM PDT 24
Peak memory 214760 kb
Host smart-f8555f3a-8234-4e55-9486-50a920dbf55d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809611215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3809611215
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.1334391904
Short name T62
Test name
Test status
Simulation time 931221360 ps
CPU time 18.29 seconds
Started Jul 18 06:27:09 PM PDT 24
Finished Jul 18 06:27:29 PM PDT 24
Peak memory 214948 kb
Host smart-6a2b6c3c-c091-4ee8-a8d9-d77b242350d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334391904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.1334391904
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.3001864815
Short name T26
Test name
Test status
Simulation time 43591431 ps
CPU time 2.98 seconds
Started Jul 18 06:29:49 PM PDT 24
Finished Jul 18 06:29:54 PM PDT 24
Peak memory 208960 kb
Host smart-ca53be0b-db73-4b43-9ca2-f468008088e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001864815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.3001864815
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.2268065979
Short name T61
Test name
Test status
Simulation time 682084243 ps
CPU time 19.18 seconds
Started Jul 18 06:27:10 PM PDT 24
Finished Jul 18 06:27:31 PM PDT 24
Peak memory 222364 kb
Host smart-fa26d9d5-68a5-4560-9461-ca8b45830f22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268065979 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.2268065979
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.767032745
Short name T56
Test name
Test status
Simulation time 186050624 ps
CPU time 3.03 seconds
Started Jul 18 06:28:29 PM PDT 24
Finished Jul 18 06:28:39 PM PDT 24
Peak memory 213996 kb
Host smart-1eac5f59-e5c5-437d-8d5c-1a809da94fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767032745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.767032745
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.1616689886
Short name T153
Test name
Test status
Simulation time 6938796312 ps
CPU time 89.4 seconds
Started Jul 18 06:28:59 PM PDT 24
Finished Jul 18 06:30:31 PM PDT 24
Peak memory 215308 kb
Host smart-02b36c4c-5299-47d0-a886-756545837f5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1616689886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.1616689886
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.2225644497
Short name T10
Test name
Test status
Simulation time 137460078 ps
CPU time 4.33 seconds
Started Jul 18 06:28:16 PM PDT 24
Finished Jul 18 06:28:24 PM PDT 24
Peak memory 214368 kb
Host smart-93448702-ec00-403b-aad7-4e17b898d7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225644497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2225644497
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.2435236164
Short name T191
Test name
Test status
Simulation time 4962703942 ps
CPU time 50.95 seconds
Started Jul 18 06:28:29 PM PDT 24
Finished Jul 18 06:29:27 PM PDT 24
Peak memory 222368 kb
Host smart-e910e3e6-7936-44f8-95a0-793f7207d19e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435236164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.2435236164
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.2592160321
Short name T433
Test name
Test status
Simulation time 1110428669 ps
CPU time 15.68 seconds
Started Jul 18 06:28:15 PM PDT 24
Finished Jul 18 06:28:34 PM PDT 24
Peak memory 214072 kb
Host smart-ad199bf1-523e-4b04-981c-fd49190c2f91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2592160321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.2592160321
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.331164477
Short name T24
Test name
Test status
Simulation time 653585302 ps
CPU time 7.57 seconds
Started Jul 18 06:29:40 PM PDT 24
Finished Jul 18 06:29:52 PM PDT 24
Peak memory 214336 kb
Host smart-9ecb2076-4e19-4e1b-8d93-25bc8a53cf9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331164477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.331164477
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.4193885971
Short name T140
Test name
Test status
Simulation time 668812374 ps
CPU time 17.93 seconds
Started Jul 18 06:30:13 PM PDT 24
Finished Jul 18 06:30:35 PM PDT 24
Peak memory 215500 kb
Host smart-8c0b2c90-32bf-4781-8e73-fedd5c237cc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4193885971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.4193885971
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.984051262
Short name T38
Test name
Test status
Simulation time 186025611 ps
CPU time 6.05 seconds
Started Jul 18 06:28:03 PM PDT 24
Finished Jul 18 06:28:14 PM PDT 24
Peak memory 210648 kb
Host smart-34442863-8877-4c7b-8852-e05f21a2923f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984051262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.984051262
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.3488199021
Short name T112
Test name
Test status
Simulation time 1002811878 ps
CPU time 19.91 seconds
Started Jul 18 06:28:28 PM PDT 24
Finished Jul 18 06:28:55 PM PDT 24
Peak memory 222280 kb
Host smart-96c547a2-81ab-4815-9d32-099e86dae7a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488199021 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.3488199021
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.2313616418
Short name T402
Test name
Test status
Simulation time 318022530 ps
CPU time 5.2 seconds
Started Jul 18 06:27:22 PM PDT 24
Finished Jul 18 06:27:30 PM PDT 24
Peak memory 214456 kb
Host smart-a4bf9572-0f8a-4086-9b59-b8b78c5f1d53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2313616418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.2313616418
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.3120596527
Short name T977
Test name
Test status
Simulation time 771173324 ps
CPU time 3.71 seconds
Started Jul 18 06:24:45 PM PDT 24
Finished Jul 18 06:24:50 PM PDT 24
Peak memory 214668 kb
Host smart-01e0ed35-c1d7-4bb2-800d-7f9994a5d327
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120596527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.3120596527
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.454912929
Short name T82
Test name
Test status
Simulation time 2140700151 ps
CPU time 30.01 seconds
Started Jul 18 06:29:18 PM PDT 24
Finished Jul 18 06:29:51 PM PDT 24
Peak memory 221944 kb
Host smart-9913666a-aa50-4283-be7c-fa6142bc4630
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454912929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.454912929
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.3217660023
Short name T213
Test name
Test status
Simulation time 578203678 ps
CPU time 8.37 seconds
Started Jul 18 06:30:38 PM PDT 24
Finished Jul 18 06:30:55 PM PDT 24
Peak memory 215472 kb
Host smart-f997568a-5022-4135-a564-7beaf32ad09b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3217660023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.3217660023
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.538572361
Short name T39
Test name
Test status
Simulation time 225813883 ps
CPU time 7.28 seconds
Started Jul 18 06:29:53 PM PDT 24
Finished Jul 18 06:30:03 PM PDT 24
Peak memory 213692 kb
Host smart-5ff6b0e1-99ad-41ab-8916-d5e755a26dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538572361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.538572361
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.1592851096
Short name T264
Test name
Test status
Simulation time 4199079705 ps
CPU time 17.35 seconds
Started Jul 18 06:26:53 PM PDT 24
Finished Jul 18 06:27:16 PM PDT 24
Peak memory 214468 kb
Host smart-85b34d75-d682-4908-b85b-6b97de01b62b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1592851096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.1592851096
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.616899184
Short name T51
Test name
Test status
Simulation time 4031835952 ps
CPU time 26.47 seconds
Started Jul 18 06:26:50 PM PDT 24
Finished Jul 18 06:27:20 PM PDT 24
Peak memory 216236 kb
Host smart-346199b0-f49e-4f07-bb07-f6a2ea359399
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616899184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.616899184
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.3147970790
Short name T172
Test name
Test status
Simulation time 595971903 ps
CPU time 3.99 seconds
Started Jul 18 06:27:38 PM PDT 24
Finished Jul 18 06:27:44 PM PDT 24
Peak memory 220876 kb
Host smart-968c4ad7-482f-4429-abe1-be3910b7b82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147970790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.3147970790
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.2836086217
Short name T419
Test name
Test status
Simulation time 479559773 ps
CPU time 8.13 seconds
Started Jul 18 06:29:52 PM PDT 24
Finished Jul 18 06:30:04 PM PDT 24
Peak memory 222164 kb
Host smart-a1637911-6cf8-4ee4-a8a8-61437c46f93c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2836086217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.2836086217
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.2341406742
Short name T22
Test name
Test status
Simulation time 1061514959 ps
CPU time 20.74 seconds
Started Jul 18 06:30:34 PM PDT 24
Finished Jul 18 06:31:00 PM PDT 24
Peak memory 214100 kb
Host smart-3e3139c9-1624-4dac-b020-bc76ab2c4c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341406742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.2341406742
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.2049272626
Short name T31
Test name
Test status
Simulation time 95832145 ps
CPU time 4.61 seconds
Started Jul 18 06:28:58 PM PDT 24
Finished Jul 18 06:29:05 PM PDT 24
Peak memory 209204 kb
Host smart-41bf2c7c-6243-4abe-a727-fcf2d490dbf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049272626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.2049272626
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.1269705886
Short name T253
Test name
Test status
Simulation time 3346528525 ps
CPU time 52.26 seconds
Started Jul 18 06:26:51 PM PDT 24
Finished Jul 18 06:27:48 PM PDT 24
Peak memory 215752 kb
Host smart-d3bef022-aea5-4243-b8ff-55cb9d761c1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269705886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.1269705886
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.3984452553
Short name T99
Test name
Test status
Simulation time 344171037 ps
CPU time 3.09 seconds
Started Jul 18 06:27:11 PM PDT 24
Finished Jul 18 06:27:16 PM PDT 24
Peak memory 214260 kb
Host smart-8e248737-b155-403f-b1b5-c07624f6737e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984452553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.3984452553
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.442704690
Short name T421
Test name
Test status
Simulation time 1994859887 ps
CPU time 103.07 seconds
Started Jul 18 06:28:32 PM PDT 24
Finished Jul 18 06:30:20 PM PDT 24
Peak memory 214104 kb
Host smart-86e0e393-5c4f-47f8-a0a4-27612401a194
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=442704690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.442704690
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.3119402184
Short name T1
Test name
Test status
Simulation time 103444557 ps
CPU time 2.18 seconds
Started Jul 18 06:29:23 PM PDT 24
Finished Jul 18 06:29:29 PM PDT 24
Peak memory 208304 kb
Host smart-e957d2d7-10de-4af1-b92d-11dd56b7a45a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119402184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.3119402184
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.1315938794
Short name T189
Test name
Test status
Simulation time 1360505754 ps
CPU time 30.99 seconds
Started Jul 18 06:26:55 PM PDT 24
Finished Jul 18 06:27:32 PM PDT 24
Peak memory 214872 kb
Host smart-2e1af046-a514-4254-88ad-b99f6b3faff9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315938794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.1315938794
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.830824829
Short name T125
Test name
Test status
Simulation time 114877764 ps
CPU time 3.89 seconds
Started Jul 18 06:27:14 PM PDT 24
Finished Jul 18 06:27:20 PM PDT 24
Peak memory 222300 kb
Host smart-4cffaddb-5982-409d-8926-cad857001414
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=830824829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.830824829
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.180665622
Short name T120
Test name
Test status
Simulation time 287436238 ps
CPU time 6.48 seconds
Started Jul 18 06:25:12 PM PDT 24
Finished Jul 18 06:25:20 PM PDT 24
Peak memory 221316 kb
Host smart-70f1b4a9-11db-49ec-a29b-08738c7a1c5c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180665622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k
eymgr_shadow_reg_errors_with_csr_rw.180665622
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.4240611321
Short name T91
Test name
Test status
Simulation time 16334807 ps
CPU time 0.87 seconds
Started Jul 18 06:26:52 PM PDT 24
Finished Jul 18 06:26:58 PM PDT 24
Peak memory 206000 kb
Host smart-94876d0f-2153-4d52-9b40-eeb766059a40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240611321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.4240611321
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.3410023289
Short name T75
Test name
Test status
Simulation time 52962045 ps
CPU time 3.51 seconds
Started Jul 18 06:28:27 PM PDT 24
Finished Jul 18 06:28:38 PM PDT 24
Peak memory 208224 kb
Host smart-b6872f00-ef64-40f7-b033-7615e8c7b231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410023289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.3410023289
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.4258959955
Short name T58
Test name
Test status
Simulation time 2853241262 ps
CPU time 37.57 seconds
Started Jul 18 06:28:05 PM PDT 24
Finished Jul 18 06:28:46 PM PDT 24
Peak memory 215856 kb
Host smart-cc191ba5-b0b9-42fd-9a27-cfe17c9d53b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258959955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.4258959955
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3596268720
Short name T275
Test name
Test status
Simulation time 1422611545 ps
CPU time 62.04 seconds
Started Jul 18 06:27:58 PM PDT 24
Finished Jul 18 06:29:03 PM PDT 24
Peak memory 222384 kb
Host smart-1053c361-f0e6-4abc-8902-c452f80cbfc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3596268720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3596268720
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.2467572462
Short name T337
Test name
Test status
Simulation time 78771469 ps
CPU time 3.02 seconds
Started Jul 18 06:28:19 PM PDT 24
Finished Jul 18 06:28:29 PM PDT 24
Peak memory 214888 kb
Host smart-09ef74a3-ec94-4eed-b316-a221bce8288b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2467572462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.2467572462
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.2530954253
Short name T43
Test name
Test status
Simulation time 431576406 ps
CPU time 4.66 seconds
Started Jul 18 06:28:18 PM PDT 24
Finished Jul 18 06:28:28 PM PDT 24
Peak memory 222124 kb
Host smart-8eaf88c2-04a5-4a81-a46b-1b1da0632a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530954253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.2530954253
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.1108992224
Short name T96
Test name
Test status
Simulation time 55865483 ps
CPU time 2.07 seconds
Started Jul 18 06:28:27 PM PDT 24
Finished Jul 18 06:28:36 PM PDT 24
Peak memory 214064 kb
Host smart-7e389061-62e1-4378-a842-4d3c3a5b9e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108992224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.1108992224
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.1318683711
Short name T246
Test name
Test status
Simulation time 47919623777 ps
CPU time 311.3 seconds
Started Jul 18 06:29:41 PM PDT 24
Finished Jul 18 06:34:56 PM PDT 24
Peak memory 219152 kb
Host smart-cf67450f-a658-40b7-a994-3fbb8c0b9f0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318683711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.1318683711
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.1795730785
Short name T164
Test name
Test status
Simulation time 350308434 ps
CPU time 4.49 seconds
Started Jul 18 06:25:35 PM PDT 24
Finished Jul 18 06:25:42 PM PDT 24
Peak memory 206172 kb
Host smart-c1ca6a55-5d3a-4632-8192-0806cf216a29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795730785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.1795730785
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.1631358407
Short name T165
Test name
Test status
Simulation time 194096777 ps
CPU time 2.92 seconds
Started Jul 18 06:24:32 PM PDT 24
Finished Jul 18 06:24:36 PM PDT 24
Peak memory 214476 kb
Host smart-25628ff7-06f1-4332-aefa-0707ec3ba810
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631358407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.1631358407
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.199483170
Short name T309
Test name
Test status
Simulation time 104151729 ps
CPU time 5.06 seconds
Started Jul 18 06:28:13 PM PDT 24
Finished Jul 18 06:28:21 PM PDT 24
Peak memory 214028 kb
Host smart-cf4c37a5-103f-4d36-acea-8b15a34fca22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199483170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.199483170
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2870072762
Short name T155
Test name
Test status
Simulation time 186264419 ps
CPU time 5.35 seconds
Started Jul 18 06:25:37 PM PDT 24
Finished Jul 18 06:25:47 PM PDT 24
Peak memory 214492 kb
Host smart-922e7882-c87b-4eeb-8d23-543bf9e803bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870072762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.2870072762
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.1573690209
Short name T520
Test name
Test status
Simulation time 90689802 ps
CPU time 3.39 seconds
Started Jul 18 06:28:42 PM PDT 24
Finished Jul 18 06:28:47 PM PDT 24
Peak memory 209496 kb
Host smart-5f800c4e-431c-480e-95a5-aa0c04b3d3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573690209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1573690209
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.625913261
Short name T136
Test name
Test status
Simulation time 465600660 ps
CPU time 23.35 seconds
Started Jul 18 06:26:56 PM PDT 24
Finished Jul 18 06:27:25 PM PDT 24
Peak memory 222380 kb
Host smart-3f48977d-19e6-4452-867c-cfd6ccffc588
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625913261 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.625913261
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.4185726569
Short name T255
Test name
Test status
Simulation time 890250031 ps
CPU time 21.4 seconds
Started Jul 18 06:28:01 PM PDT 24
Finished Jul 18 06:28:26 PM PDT 24
Peak memory 216592 kb
Host smart-7c0600f9-bd81-4818-a3bb-8e80a4f750c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185726569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.4185726569
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.240552750
Short name T218
Test name
Test status
Simulation time 232854093 ps
CPU time 3.31 seconds
Started Jul 18 06:29:00 PM PDT 24
Finished Jul 18 06:29:06 PM PDT 24
Peak memory 208728 kb
Host smart-e4df6b02-f621-42d5-b4b0-585ea0050fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240552750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.240552750
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.2374932024
Short name T119
Test name
Test status
Simulation time 24438960 ps
CPU time 2.14 seconds
Started Jul 18 06:29:36 PM PDT 24
Finished Jul 18 06:29:42 PM PDT 24
Peak memory 208328 kb
Host smart-b7f5fa2e-b73a-4ea3-a717-b03a80bd84b4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374932024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.2374932024
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.21715820
Short name T47
Test name
Test status
Simulation time 294935634 ps
CPU time 3.79 seconds
Started Jul 18 06:28:12 PM PDT 24
Finished Jul 18 06:28:17 PM PDT 24
Peak memory 218208 kb
Host smart-24271251-1087-44d8-9c82-016a5f99867b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21715820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.21715820
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.3404626920
Short name T48
Test name
Test status
Simulation time 525259557 ps
CPU time 6.05 seconds
Started Jul 18 06:26:55 PM PDT 24
Finished Jul 18 06:27:07 PM PDT 24
Peak memory 218212 kb
Host smart-eb77071f-0353-420a-a02b-2d5ee13bd5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404626920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.3404626920
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.664557457
Short name T260
Test name
Test status
Simulation time 2781925150 ps
CPU time 35.77 seconds
Started Jul 18 06:27:23 PM PDT 24
Finished Jul 18 06:28:02 PM PDT 24
Peak memory 214496 kb
Host smart-79cd7bd9-df18-4bc7-b957-36e8b7e7e2ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=664557457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.664557457
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.1074318279
Short name T505
Test name
Test status
Simulation time 35087461 ps
CPU time 1.89 seconds
Started Jul 18 06:27:38 PM PDT 24
Finished Jul 18 06:27:43 PM PDT 24
Peak memory 209820 kb
Host smart-44c7d860-8016-46d7-af60-ceee3c213abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074318279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.1074318279
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.2867449072
Short name T331
Test name
Test status
Simulation time 3832482708 ps
CPU time 37.57 seconds
Started Jul 18 06:27:38 PM PDT 24
Finished Jul 18 06:28:18 PM PDT 24
Peak memory 221260 kb
Host smart-c447bdc9-7d30-4691-9d9b-4c6fba14609f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867449072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.2867449072
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.3632819464
Short name T288
Test name
Test status
Simulation time 140041838 ps
CPU time 2.94 seconds
Started Jul 18 06:27:58 PM PDT 24
Finished Jul 18 06:28:04 PM PDT 24
Peak memory 211828 kb
Host smart-5e538ea3-e898-41a2-aae9-7083f69e4d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632819464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.3632819464
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.1662832366
Short name T72
Test name
Test status
Simulation time 106638505 ps
CPU time 3 seconds
Started Jul 18 06:29:22 PM PDT 24
Finished Jul 18 06:29:29 PM PDT 24
Peak memory 210200 kb
Host smart-5534f28b-d9cb-4c33-b0e2-9cda272a5ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662832366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.1662832366
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.765270500
Short name T109
Test name
Test status
Simulation time 2319505419 ps
CPU time 5.95 seconds
Started Jul 18 06:29:34 PM PDT 24
Finished Jul 18 06:29:42 PM PDT 24
Peak memory 208728 kb
Host smart-257e8f46-dcff-41c9-9c84-9c3e54b840c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765270500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.765270500
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3687639476
Short name T231
Test name
Test status
Simulation time 43148964 ps
CPU time 2.41 seconds
Started Jul 18 06:30:16 PM PDT 24
Finished Jul 18 06:30:21 PM PDT 24
Peak memory 206776 kb
Host smart-5ed3352a-2c53-43e5-9f4b-d972452c1582
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687639476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3687639476
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.330642741
Short name T306
Test name
Test status
Simulation time 76861901 ps
CPU time 2.94 seconds
Started Jul 18 06:27:11 PM PDT 24
Finished Jul 18 06:27:17 PM PDT 24
Peak memory 214008 kb
Host smart-60e2d7a8-d759-42a8-b2c9-0213b3e09c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330642741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.330642741
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.1106527324
Short name T334
Test name
Test status
Simulation time 134659560 ps
CPU time 2.99 seconds
Started Jul 18 06:27:11 PM PDT 24
Finished Jul 18 06:27:16 PM PDT 24
Peak memory 214084 kb
Host smart-a2fab96d-8314-4173-b1d6-508cad7dc15b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1106527324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.1106527324
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.413538126
Short name T343
Test name
Test status
Simulation time 176617372 ps
CPU time 3.58 seconds
Started Jul 18 06:27:21 PM PDT 24
Finished Jul 18 06:27:26 PM PDT 24
Peak memory 214016 kb
Host smart-f5f7afe8-d4aa-4a6e-90ca-6d6de37e3f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413538126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.413538126
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.191019052
Short name T171
Test name
Test status
Simulation time 900723224 ps
CPU time 4.7 seconds
Started Jul 18 06:25:36 PM PDT 24
Finished Jul 18 06:25:45 PM PDT 24
Peak memory 214384 kb
Host smart-671090d7-d375-47d9-8160-37990a3488d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191019052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err
.191019052
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.2440486289
Short name T254
Test name
Test status
Simulation time 126632221 ps
CPU time 4.09 seconds
Started Jul 18 06:26:33 PM PDT 24
Finished Jul 18 06:26:42 PM PDT 24
Peak memory 222400 kb
Host smart-1b90ba62-12da-4645-97ec-06384c40aa31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440486289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.2440486289
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.2708235739
Short name T435
Test name
Test status
Simulation time 1639266071 ps
CPU time 23.18 seconds
Started Jul 18 06:26:50 PM PDT 24
Finished Jul 18 06:27:17 PM PDT 24
Peak memory 214936 kb
Host smart-89e34502-2a94-4f6c-aa99-9b2b84631f96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2708235739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.2708235739
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.3214496674
Short name T271
Test name
Test status
Simulation time 207928746 ps
CPU time 4.1 seconds
Started Jul 18 06:27:38 PM PDT 24
Finished Jul 18 06:27:44 PM PDT 24
Peak memory 215184 kb
Host smart-4e2bc54b-e153-4ba2-9da6-fbf6e1fc637b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3214496674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.3214496674
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.15806867
Short name T373
Test name
Test status
Simulation time 292469203 ps
CPU time 19.11 seconds
Started Jul 18 06:28:33 PM PDT 24
Finished Jul 18 06:28:56 PM PDT 24
Peak memory 222380 kb
Host smart-23375478-00e3-4a0e-8e30-5e85eb1076ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15806867 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.15806867
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.1759689714
Short name T81
Test name
Test status
Simulation time 978046099 ps
CPU time 7.6 seconds
Started Jul 18 06:29:04 PM PDT 24
Finished Jul 18 06:29:14 PM PDT 24
Peak memory 219520 kb
Host smart-44d4ca7f-ed68-4555-90b4-5076e9572f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759689714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.1759689714
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.1723415672
Short name T268
Test name
Test status
Simulation time 34392253 ps
CPU time 1.82 seconds
Started Jul 18 06:29:34 PM PDT 24
Finished Jul 18 06:29:38 PM PDT 24
Peak memory 214024 kb
Host smart-405f4d3c-8753-447f-99c4-3d03bf619be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723415672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.1723415672
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.1228557020
Short name T428
Test name
Test status
Simulation time 61610598 ps
CPU time 3.86 seconds
Started Jul 18 06:29:37 PM PDT 24
Finished Jul 18 06:29:46 PM PDT 24
Peak memory 214708 kb
Host smart-60e45abb-7a46-4017-ad18-e7839ec8a4bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1228557020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1228557020
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.1465862844
Short name T311
Test name
Test status
Simulation time 74729490 ps
CPU time 3.59 seconds
Started Jul 18 06:29:53 PM PDT 24
Finished Jul 18 06:30:00 PM PDT 24
Peak memory 222124 kb
Host smart-674f07ad-1021-4f9f-87a0-1f878ccefb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465862844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.1465862844
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.2103684522
Short name T242
Test name
Test status
Simulation time 1245195326 ps
CPU time 39.03 seconds
Started Jul 18 06:30:11 PM PDT 24
Finished Jul 18 06:30:53 PM PDT 24
Peak memory 216344 kb
Host smart-2337e609-d65d-4816-b2a9-28be41a98206
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103684522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.2103684522
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.2045074023
Short name T364
Test name
Test status
Simulation time 84929056 ps
CPU time 3.51 seconds
Started Jul 18 06:30:09 PM PDT 24
Finished Jul 18 06:30:13 PM PDT 24
Peak memory 214248 kb
Host smart-0f15510e-82ef-4de9-a3ba-d993f8cef890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045074023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.2045074023
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.2474324635
Short name T162
Test name
Test status
Simulation time 235907789 ps
CPU time 9.59 seconds
Started Jul 18 06:25:34 PM PDT 24
Finished Jul 18 06:25:46 PM PDT 24
Peak memory 214444 kb
Host smart-c32b6456-4891-4d3e-9e85-705f67e151ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474324635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.2474324635
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.3025413940
Short name T159
Test name
Test status
Simulation time 419641469 ps
CPU time 4.98 seconds
Started Jul 18 06:25:22 PM PDT 24
Finished Jul 18 06:25:29 PM PDT 24
Peak memory 214352 kb
Host smart-16ed0fb7-4c04-490a-a5b3-915d526ba716
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025413940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.3025413940
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2915264324
Short name T160
Test name
Test status
Simulation time 364338615 ps
CPU time 4.19 seconds
Started Jul 18 06:25:35 PM PDT 24
Finished Jul 18 06:25:43 PM PDT 24
Peak memory 215516 kb
Host smart-59183fc5-291c-416e-aef5-edf9d8ccc4dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915264324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.2915264324
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.648082069
Short name T157
Test name
Test status
Simulation time 56342295 ps
CPU time 2.72 seconds
Started Jul 18 06:25:37 PM PDT 24
Finished Jul 18 06:25:44 PM PDT 24
Peak memory 214496 kb
Host smart-03c90802-3669-459e-82ad-4e46949d09a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648082069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err
.648082069
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2394280349
Short name T170
Test name
Test status
Simulation time 407250639 ps
CPU time 7.27 seconds
Started Jul 18 06:25:14 PM PDT 24
Finished Jul 18 06:25:22 PM PDT 24
Peak memory 214512 kb
Host smart-874b8523-2679-4652-b4bc-fda13867fb84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394280349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.2394280349
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1355851360
Short name T163
Test name
Test status
Simulation time 272390452 ps
CPU time 7.84 seconds
Started Jul 18 06:25:15 PM PDT 24
Finished Jul 18 06:25:24 PM PDT 24
Peak memory 214424 kb
Host smart-8a80a2fb-1d2a-454b-8ff1-0f5662e9090e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355851360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.1355851360
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.3682427919
Short name T45
Test name
Test status
Simulation time 632598859 ps
CPU time 10.55 seconds
Started Jul 18 06:26:51 PM PDT 24
Finished Jul 18 06:27:06 PM PDT 24
Peak memory 231520 kb
Host smart-0daafccd-9dde-4d82-a98d-d074c4deb5e8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682427919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.3682427919
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.1785442991
Short name T15
Test name
Test status
Simulation time 1193087332 ps
CPU time 11.8 seconds
Started Jul 18 06:26:50 PM PDT 24
Finished Jul 18 06:27:06 PM PDT 24
Peak memory 231884 kb
Host smart-0a09b649-64ad-4667-865b-5f34aa5a6f4a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785442991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.1785442991
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.141760226
Short name T803
Test name
Test status
Simulation time 462448836 ps
CPU time 2.66 seconds
Started Jul 18 06:27:38 PM PDT 24
Finished Jul 18 06:27:43 PM PDT 24
Peak memory 222096 kb
Host smart-90912b4b-6bde-444e-b0bb-84ba4e0b71d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141760226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.141760226
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_random.3496158031
Short name T336
Test name
Test status
Simulation time 131013886 ps
CPU time 2.74 seconds
Started Jul 18 06:27:20 PM PDT 24
Finished Jul 18 06:27:24 PM PDT 24
Peak memory 214136 kb
Host smart-1dc3e627-e38e-45d6-9afa-a4f7eef6fe44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496158031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3496158031
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.3865381813
Short name T820
Test name
Test status
Simulation time 660419694 ps
CPU time 30.57 seconds
Started Jul 18 06:27:38 PM PDT 24
Finished Jul 18 06:28:11 PM PDT 24
Peak memory 222224 kb
Host smart-87f414c0-81f0-43af-af3f-54c6510172ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865381813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.3865381813
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_random.1244235581
Short name T220
Test name
Test status
Simulation time 92335911 ps
CPU time 4.15 seconds
Started Jul 18 06:27:35 PM PDT 24
Finished Jul 18 06:27:40 PM PDT 24
Peak memory 214064 kb
Host smart-1fdc7d0b-c9db-4cc8-bea5-ddc0c9c79c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244235581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.1244235581
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.1352599071
Short name T137
Test name
Test status
Simulation time 230158103 ps
CPU time 6.71 seconds
Started Jul 18 06:27:36 PM PDT 24
Finished Jul 18 06:27:44 PM PDT 24
Peak memory 208360 kb
Host smart-5a4439cf-33a4-4cde-9266-e99e36e098c3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352599071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.1352599071
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.4030596217
Short name T23
Test name
Test status
Simulation time 1549760445 ps
CPU time 5.35 seconds
Started Jul 18 06:27:59 PM PDT 24
Finished Jul 18 06:28:08 PM PDT 24
Peak memory 220964 kb
Host smart-4cdbb5cc-73f2-484c-b055-09f6f147cf28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030596217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.4030596217
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.3994258347
Short name T666
Test name
Test status
Simulation time 569157971 ps
CPU time 4.11 seconds
Started Jul 18 06:27:56 PM PDT 24
Finished Jul 18 06:28:01 PM PDT 24
Peak memory 222176 kb
Host smart-a1d95d3a-db7a-4210-966a-e5fccbfe8ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994258347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.3994258347
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.3050171295
Short name T763
Test name
Test status
Simulation time 1069379198 ps
CPU time 8.42 seconds
Started Jul 18 06:27:58 PM PDT 24
Finished Jul 18 06:28:08 PM PDT 24
Peak memory 214144 kb
Host smart-2ef38fbc-5bf6-463b-b316-9356c99fa8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050171295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3050171295
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.3873144927
Short name T429
Test name
Test status
Simulation time 417596165 ps
CPU time 7.19 seconds
Started Jul 18 06:28:00 PM PDT 24
Finished Jul 18 06:28:11 PM PDT 24
Peak memory 214976 kb
Host smart-adbc4824-afd6-4b69-bee0-1a835e642812
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3873144927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.3873144927
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.2274035567
Short name T239
Test name
Test status
Simulation time 186186754 ps
CPU time 4.37 seconds
Started Jul 18 06:26:49 PM PDT 24
Finished Jul 18 06:26:57 PM PDT 24
Peak memory 220364 kb
Host smart-4f6ae619-04ae-4604-8a74-4a42d52ed538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274035567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.2274035567
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.3954069044
Short name T324
Test name
Test status
Simulation time 55859171 ps
CPU time 3.21 seconds
Started Jul 18 06:26:49 PM PDT 24
Finished Jul 18 06:26:54 PM PDT 24
Peak memory 209288 kb
Host smart-664ad220-998f-40e4-8003-f1db555c90cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954069044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.3954069044
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.320277205
Short name T97
Test name
Test status
Simulation time 88752458 ps
CPU time 3.14 seconds
Started Jul 18 06:28:27 PM PDT 24
Finished Jul 18 06:28:37 PM PDT 24
Peak memory 219900 kb
Host smart-ae8b7b52-c4c0-44e8-ae4e-321bbe741d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320277205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.320277205
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.2785703289
Short name T110
Test name
Test status
Simulation time 135536598 ps
CPU time 2.96 seconds
Started Jul 18 06:28:56 PM PDT 24
Finished Jul 18 06:29:00 PM PDT 24
Peak memory 220208 kb
Host smart-aa941725-8d4c-4bdb-8bc1-9736ebf09a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785703289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.2785703289
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.1420834719
Short name T257
Test name
Test status
Simulation time 1214503855 ps
CPU time 6.11 seconds
Started Jul 18 06:26:51 PM PDT 24
Finished Jul 18 06:27:02 PM PDT 24
Peak memory 219888 kb
Host smart-6a9140d1-3cad-4875-ad0b-1dd1a79f23bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420834719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.1420834719
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.463150991
Short name T328
Test name
Test status
Simulation time 301289703 ps
CPU time 7.53 seconds
Started Jul 18 06:29:16 PM PDT 24
Finished Jul 18 06:29:26 PM PDT 24
Peak memory 214024 kb
Host smart-4ad65675-a4a0-4f2b-bee7-85f184a09a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463150991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.463150991
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.3126102412
Short name T9
Test name
Test status
Simulation time 617639908 ps
CPU time 17.74 seconds
Started Jul 18 06:29:19 PM PDT 24
Finished Jul 18 06:29:39 PM PDT 24
Peak memory 214064 kb
Host smart-c1d654de-460b-4c29-9a77-b08f53e90214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126102412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.3126102412
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.2336691301
Short name T329
Test name
Test status
Simulation time 1009350729 ps
CPU time 6.94 seconds
Started Jul 18 06:29:34 PM PDT 24
Finished Jul 18 06:29:44 PM PDT 24
Peak memory 207976 kb
Host smart-abc7c8ff-d5b4-4566-8b16-446519899b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336691301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.2336691301
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.2784788790
Short name T12
Test name
Test status
Simulation time 69793401 ps
CPU time 4.73 seconds
Started Jul 18 06:26:54 PM PDT 24
Finished Jul 18 06:27:05 PM PDT 24
Peak memory 210616 kb
Host smart-2c0033f8-9581-4a5b-ae56-dc57e01e0ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784788790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.2784788790
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.2770326922
Short name T346
Test name
Test status
Simulation time 99347422 ps
CPU time 3.5 seconds
Started Jul 18 06:29:50 PM PDT 24
Finished Jul 18 06:29:56 PM PDT 24
Peak memory 214092 kb
Host smart-3a636f46-9c82-476f-a70f-509160d0362a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2770326922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.2770326922
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.3189203985
Short name T312
Test name
Test status
Simulation time 155262307 ps
CPU time 3.62 seconds
Started Jul 18 06:27:09 PM PDT 24
Finished Jul 18 06:27:14 PM PDT 24
Peak memory 215060 kb
Host smart-12e58138-a304-4e3e-b655-bc03f088db35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3189203985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.3189203985
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.2732130621
Short name T1018
Test name
Test status
Simulation time 1033281431 ps
CPU time 4.9 seconds
Started Jul 18 06:24:27 PM PDT 24
Finished Jul 18 06:24:34 PM PDT 24
Peak memory 206244 kb
Host smart-c19f6056-7c75-40b6-9aad-7b2df64ac5ca
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732130621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.2
732130621
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.2753613965
Short name T948
Test name
Test status
Simulation time 882754593 ps
CPU time 7.78 seconds
Started Jul 18 06:24:28 PM PDT 24
Finished Jul 18 06:24:38 PM PDT 24
Peak memory 206244 kb
Host smart-bd7a5f58-07cd-45d3-ad60-8b65c858703e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753613965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.2
753613965
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2784464678
Short name T1069
Test name
Test status
Simulation time 72192170 ps
CPU time 1.22 seconds
Started Jul 18 06:24:26 PM PDT 24
Finished Jul 18 06:24:28 PM PDT 24
Peak memory 206232 kb
Host smart-a5e95ea0-9607-4229-b85c-c688e632e6a9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784464678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.2
784464678
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.525413512
Short name T981
Test name
Test status
Simulation time 42393852 ps
CPU time 2.05 seconds
Started Jul 18 06:24:28 PM PDT 24
Finished Jul 18 06:24:32 PM PDT 24
Peak memory 217948 kb
Host smart-999851eb-3070-4b4d-b1f1-80033a66b9f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525413512 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.525413512
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3703643323
Short name T144
Test name
Test status
Simulation time 17833537 ps
CPU time 0.99 seconds
Started Jul 18 06:24:28 PM PDT 24
Finished Jul 18 06:24:31 PM PDT 24
Peak memory 206080 kb
Host smart-bc785d3b-229b-45b4-8498-e1c4e73476dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703643323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.3703643323
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3461729155
Short name T997
Test name
Test status
Simulation time 12537308 ps
CPU time 0.88 seconds
Started Jul 18 06:24:27 PM PDT 24
Finished Jul 18 06:24:29 PM PDT 24
Peak memory 205952 kb
Host smart-5f6b2168-cee8-4513-aad7-bdf27fd5fa14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461729155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.3461729155
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.231598894
Short name T1021
Test name
Test status
Simulation time 58594872 ps
CPU time 2.15 seconds
Started Jul 18 06:24:31 PM PDT 24
Finished Jul 18 06:24:35 PM PDT 24
Peak memory 206164 kb
Host smart-359dbb01-3b81-47b5-b3cd-b2aa0dcc0456
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231598894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sam
e_csr_outstanding.231598894
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.703038966
Short name T123
Test name
Test status
Simulation time 561949527 ps
CPU time 2.76 seconds
Started Jul 18 06:24:33 PM PDT 24
Finished Jul 18 06:24:37 PM PDT 24
Peak memory 214684 kb
Host smart-9624d586-1cc7-4dc6-b633-416dcd42c63a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703038966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow
_reg_errors.703038966
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1490166756
Short name T131
Test name
Test status
Simulation time 403005574 ps
CPU time 7.32 seconds
Started Jul 18 06:24:26 PM PDT 24
Finished Jul 18 06:24:35 PM PDT 24
Peak memory 214664 kb
Host smart-90c9b0d6-0785-4f92-9195-225e33ab2140
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490166756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.1490166756
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.4152412171
Short name T993
Test name
Test status
Simulation time 47370404 ps
CPU time 2.06 seconds
Started Jul 18 06:24:28 PM PDT 24
Finished Jul 18 06:24:32 PM PDT 24
Peak memory 214500 kb
Host smart-3a5a23a8-82c7-4567-af74-18d7422a21db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152412171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.4152412171
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2033628225
Short name T989
Test name
Test status
Simulation time 2747678687 ps
CPU time 14.76 seconds
Started Jul 18 06:24:47 PM PDT 24
Finished Jul 18 06:25:03 PM PDT 24
Peak memory 206300 kb
Host smart-d92bd3c2-a54a-4dde-973b-fe14b301c792
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033628225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2
033628225
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.1100655789
Short name T1028
Test name
Test status
Simulation time 1000642154 ps
CPU time 8.37 seconds
Started Jul 18 06:24:32 PM PDT 24
Finished Jul 18 06:24:41 PM PDT 24
Peak memory 206224 kb
Host smart-d16f57ab-8c1a-4727-8576-75d88607f9f1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100655789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.1
100655789
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2886528920
Short name T955
Test name
Test status
Simulation time 91497797 ps
CPU time 1.47 seconds
Started Jul 18 06:24:36 PM PDT 24
Finished Jul 18 06:24:38 PM PDT 24
Peak memory 206180 kb
Host smart-69f607db-ef9f-4d7a-83c8-28e2a8e3e1ca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886528920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2
886528920
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2831223980
Short name T954
Test name
Test status
Simulation time 58747253 ps
CPU time 2.39 seconds
Started Jul 18 06:24:45 PM PDT 24
Finished Jul 18 06:24:48 PM PDT 24
Peak memory 214516 kb
Host smart-bc4cd085-fa37-4da8-bbdc-531a3c654960
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831223980 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.2831223980
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.1856653270
Short name T1040
Test name
Test status
Simulation time 16187880 ps
CPU time 0.95 seconds
Started Jul 18 06:24:28 PM PDT 24
Finished Jul 18 06:24:31 PM PDT 24
Peak memory 206080 kb
Host smart-edeadefb-2604-4881-8fce-c103ad64f5aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856653270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.1856653270
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.4051459752
Short name T920
Test name
Test status
Simulation time 27244159 ps
CPU time 0.79 seconds
Started Jul 18 06:24:27 PM PDT 24
Finished Jul 18 06:24:30 PM PDT 24
Peak memory 205968 kb
Host smart-f5571354-7719-4b14-87bc-faac47c3f776
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051459752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.4051459752
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2417714578
Short name T941
Test name
Test status
Simulation time 184648402 ps
CPU time 1.69 seconds
Started Jul 18 06:24:45 PM PDT 24
Finished Jul 18 06:24:48 PM PDT 24
Peak memory 206416 kb
Host smart-331ebff1-b0ec-4e88-9927-f6996abd344f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417714578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.2417714578
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.4154315492
Short name T128
Test name
Test status
Simulation time 280970628 ps
CPU time 2.13 seconds
Started Jul 18 06:24:27 PM PDT 24
Finished Jul 18 06:24:30 PM PDT 24
Peak memory 214668 kb
Host smart-224008c0-6c66-4365-9eed-9cb8dbe27316
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154315492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.4154315492
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2802805948
Short name T1062
Test name
Test status
Simulation time 651622368 ps
CPU time 5.04 seconds
Started Jul 18 06:24:29 PM PDT 24
Finished Jul 18 06:24:36 PM PDT 24
Peak memory 214700 kb
Host smart-d8220ddd-b174-4184-ac2a-fe3d0b68ec40
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802805948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.2802805948
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1866788489
Short name T984
Test name
Test status
Simulation time 1278388252 ps
CPU time 3.67 seconds
Started Jul 18 06:24:26 PM PDT 24
Finished Jul 18 06:24:30 PM PDT 24
Peak memory 216524 kb
Host smart-8059007e-808d-4c67-b065-70737a77dec5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866788489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1866788489
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.912451987
Short name T398
Test name
Test status
Simulation time 71519757 ps
CPU time 3.38 seconds
Started Jul 18 06:24:28 PM PDT 24
Finished Jul 18 06:24:33 PM PDT 24
Peak memory 206240 kb
Host smart-2a83eefb-0053-41ad-8d16-25957dd350ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912451987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.
912451987
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1592761290
Short name T932
Test name
Test status
Simulation time 23152447 ps
CPU time 1.74 seconds
Started Jul 18 06:25:32 PM PDT 24
Finished Jul 18 06:25:34 PM PDT 24
Peak memory 214504 kb
Host smart-755beb0d-3a80-41cb-acba-b07c13bff7b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592761290 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1592761290
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3699868347
Short name T1005
Test name
Test status
Simulation time 16899155 ps
CPU time 1.15 seconds
Started Jul 18 06:25:35 PM PDT 24
Finished Jul 18 06:25:40 PM PDT 24
Peak memory 206260 kb
Host smart-9b92b4de-ef8e-4fc8-9a3e-b0476240ddab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699868347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.3699868347
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.3199768892
Short name T936
Test name
Test status
Simulation time 35451265 ps
CPU time 0.79 seconds
Started Jul 18 06:25:34 PM PDT 24
Finished Jul 18 06:25:38 PM PDT 24
Peak memory 205944 kb
Host smart-5e1ca9da-8a57-420e-9499-35dd36b8efa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199768892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.3199768892
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.255011929
Short name T976
Test name
Test status
Simulation time 155912757 ps
CPU time 3.29 seconds
Started Jul 18 06:25:34 PM PDT 24
Finished Jul 18 06:25:39 PM PDT 24
Peak memory 206256 kb
Host smart-cbfd233a-ddca-4fc7-8d97-c71d40543767
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255011929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_sa
me_csr_outstanding.255011929
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.581149693
Short name T988
Test name
Test status
Simulation time 189678771 ps
CPU time 1.88 seconds
Started Jul 18 06:25:35 PM PDT 24
Finished Jul 18 06:25:41 PM PDT 24
Peak memory 214628 kb
Host smart-cbf2ceaa-1465-4332-ac1a-1d971017d5b3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581149693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado
w_reg_errors.581149693
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3733262009
Short name T986
Test name
Test status
Simulation time 2030526347 ps
CPU time 10.88 seconds
Started Jul 18 06:25:35 PM PDT 24
Finished Jul 18 06:25:50 PM PDT 24
Peak memory 220928 kb
Host smart-20718a08-dcef-4893-a1ad-40f0514439b9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733262009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.3733262009
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1428983984
Short name T949
Test name
Test status
Simulation time 104975977 ps
CPU time 2.09 seconds
Started Jul 18 06:25:34 PM PDT 24
Finished Jul 18 06:25:37 PM PDT 24
Peak memory 214356 kb
Host smart-63345918-ac44-4ce7-bd46-3ebda8b00af8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428983984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.1428983984
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3927712898
Short name T1000
Test name
Test status
Simulation time 85434087 ps
CPU time 1.85 seconds
Started Jul 18 06:25:38 PM PDT 24
Finished Jul 18 06:25:45 PM PDT 24
Peak memory 214576 kb
Host smart-c27d5838-36fa-493a-b5dc-37b422a3611d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927712898 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.3927712898
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.1295706196
Short name T146
Test name
Test status
Simulation time 14851724 ps
CPU time 0.93 seconds
Started Jul 18 06:25:38 PM PDT 24
Finished Jul 18 06:25:44 PM PDT 24
Peak memory 206024 kb
Host smart-60555d89-b475-4b8d-82c4-ea8ee37366e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295706196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.1295706196
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3734143280
Short name T974
Test name
Test status
Simulation time 12210175 ps
CPU time 0.74 seconds
Started Jul 18 06:25:34 PM PDT 24
Finished Jul 18 06:25:37 PM PDT 24
Peak memory 206024 kb
Host smart-215b1c1d-6b28-4c72-9332-d21200c51eac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734143280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3734143280
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.729420083
Short name T145
Test name
Test status
Simulation time 34615367 ps
CPU time 2.09 seconds
Started Jul 18 06:25:35 PM PDT 24
Finished Jul 18 06:25:40 PM PDT 24
Peak memory 206240 kb
Host smart-12bba2fc-9591-4519-a255-331badaa06d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729420083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_sa
me_csr_outstanding.729420083
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.3319752390
Short name T1036
Test name
Test status
Simulation time 88498123 ps
CPU time 2.82 seconds
Started Jul 18 06:25:38 PM PDT 24
Finished Jul 18 06:25:45 PM PDT 24
Peak memory 214668 kb
Host smart-a996ad54-52f0-49c4-a920-ede8cbb415bc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319752390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.3319752390
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2413131305
Short name T122
Test name
Test status
Simulation time 473583814 ps
CPU time 16.68 seconds
Started Jul 18 06:25:37 PM PDT 24
Finished Jul 18 06:25:58 PM PDT 24
Peak memory 214684 kb
Host smart-bf4d5bfa-35d3-4f23-a45b-88243113a6b9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413131305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.2413131305
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.3754765213
Short name T1068
Test name
Test status
Simulation time 253885532 ps
CPU time 3.69 seconds
Started Jul 18 06:25:36 PM PDT 24
Finished Jul 18 06:25:44 PM PDT 24
Peak memory 217440 kb
Host smart-925daf0d-733d-4a1e-8f91-24e54c96c26f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754765213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.3754765213
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2976877310
Short name T169
Test name
Test status
Simulation time 257775498 ps
CPU time 5.14 seconds
Started Jul 18 06:25:35 PM PDT 24
Finished Jul 18 06:25:42 PM PDT 24
Peak memory 214488 kb
Host smart-3473670a-7d19-43b9-9602-ee209143beee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976877310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.2976877310
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2404776603
Short name T983
Test name
Test status
Simulation time 48172266 ps
CPU time 1.54 seconds
Started Jul 18 06:25:36 PM PDT 24
Finished Jul 18 06:25:42 PM PDT 24
Peak memory 216856 kb
Host smart-e35a4817-7240-45dd-921c-9a25e72abce1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404776603 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.2404776603
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.130827182
Short name T960
Test name
Test status
Simulation time 168564788 ps
CPU time 1.14 seconds
Started Jul 18 06:25:34 PM PDT 24
Finished Jul 18 06:25:36 PM PDT 24
Peak memory 206192 kb
Host smart-ebe2339e-0497-4043-96b4-502539a02fc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130827182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.130827182
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.4180276482
Short name T999
Test name
Test status
Simulation time 27976702 ps
CPU time 0.71 seconds
Started Jul 18 06:25:33 PM PDT 24
Finished Jul 18 06:25:34 PM PDT 24
Peak memory 206012 kb
Host smart-442c29d7-958c-43f4-ab20-ab6ba969c708
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180276482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.4180276482
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2043980687
Short name T1077
Test name
Test status
Simulation time 237364771 ps
CPU time 2.75 seconds
Started Jul 18 06:25:34 PM PDT 24
Finished Jul 18 06:25:38 PM PDT 24
Peak memory 206220 kb
Host smart-05ea3d70-d4ec-44ed-95a5-eead8128cdcc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043980687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.2043980687
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.4174944984
Short name T1033
Test name
Test status
Simulation time 245389323 ps
CPU time 4.12 seconds
Started Jul 18 06:25:33 PM PDT 24
Finished Jul 18 06:25:39 PM PDT 24
Peak memory 214676 kb
Host smart-15a7c16f-89f2-4efb-bf82-67a683a94740
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174944984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.4174944984
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2657075242
Short name T1046
Test name
Test status
Simulation time 843843466 ps
CPU time 9.62 seconds
Started Jul 18 06:25:37 PM PDT 24
Finished Jul 18 06:25:51 PM PDT 24
Peak memory 214660 kb
Host smart-8141cd0c-5ad1-4c45-acb0-1077ad185dda
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657075242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.2657075242
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.884386260
Short name T1065
Test name
Test status
Simulation time 276202314 ps
CPU time 4.12 seconds
Started Jul 18 06:25:33 PM PDT 24
Finished Jul 18 06:25:38 PM PDT 24
Peak memory 214452 kb
Host smart-9bac5b2a-97c2-41e6-b41e-18ef024b083f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884386260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.884386260
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3654195218
Short name T978
Test name
Test status
Simulation time 166583645 ps
CPU time 1.59 seconds
Started Jul 18 06:25:34 PM PDT 24
Finished Jul 18 06:25:36 PM PDT 24
Peak memory 214424 kb
Host smart-28e4ac75-192d-4677-a9a8-b5e63ab84eb0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654195218 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.3654195218
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.3427331155
Short name T142
Test name
Test status
Simulation time 24795484 ps
CPU time 1.41 seconds
Started Jul 18 06:25:32 PM PDT 24
Finished Jul 18 06:25:34 PM PDT 24
Peak memory 206152 kb
Host smart-c73dab46-79e6-4830-92be-2b27fb36cc92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427331155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.3427331155
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.2772013633
Short name T1024
Test name
Test status
Simulation time 15775064 ps
CPU time 0.87 seconds
Started Jul 18 06:25:35 PM PDT 24
Finished Jul 18 06:25:39 PM PDT 24
Peak memory 206112 kb
Host smart-9ec9e3d5-e57b-48db-a48d-764188c7bc8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772013633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.2772013633
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1949384674
Short name T962
Test name
Test status
Simulation time 39294914 ps
CPU time 1.97 seconds
Started Jul 18 06:25:36 PM PDT 24
Finished Jul 18 06:25:43 PM PDT 24
Peak memory 206268 kb
Host smart-809e80f8-eb98-4281-a8f1-5e16b896f65a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949384674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.1949384674
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.3823815232
Short name T970
Test name
Test status
Simulation time 172430666 ps
CPU time 4.49 seconds
Started Jul 18 06:25:34 PM PDT 24
Finished Jul 18 06:25:40 PM PDT 24
Peak memory 214684 kb
Host smart-65672cff-23d5-477a-affd-64d130ed5024
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823815232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.3823815232
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.848537189
Short name T1049
Test name
Test status
Simulation time 349960668 ps
CPU time 12.8 seconds
Started Jul 18 06:25:35 PM PDT 24
Finished Jul 18 06:25:51 PM PDT 24
Peak memory 214672 kb
Host smart-e748c5a2-aa8e-48fa-9e99-d13190e90e2b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848537189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
keymgr_shadow_reg_errors_with_csr_rw.848537189
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3646302041
Short name T915
Test name
Test status
Simulation time 97662764 ps
CPU time 3.74 seconds
Started Jul 18 06:25:35 PM PDT 24
Finished Jul 18 06:25:41 PM PDT 24
Peak memory 214400 kb
Host smart-f5abd0c3-d129-4322-8dcc-2e97393e3bcf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646302041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.3646302041
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2427635663
Short name T1019
Test name
Test status
Simulation time 120855032 ps
CPU time 2.01 seconds
Started Jul 18 06:25:35 PM PDT 24
Finished Jul 18 06:25:41 PM PDT 24
Peak memory 214624 kb
Host smart-0783e8f3-6616-444c-9142-84fbe2c64da0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427635663 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.2427635663
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.393766385
Short name T143
Test name
Test status
Simulation time 44989066 ps
CPU time 1.05 seconds
Started Jul 18 06:25:36 PM PDT 24
Finished Jul 18 06:25:42 PM PDT 24
Peak memory 205944 kb
Host smart-ac0b1fba-79c0-4674-a760-da8cf5cec653
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393766385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.393766385
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2854259780
Short name T1075
Test name
Test status
Simulation time 151117630 ps
CPU time 0.89 seconds
Started Jul 18 06:25:36 PM PDT 24
Finished Jul 18 06:25:41 PM PDT 24
Peak memory 206024 kb
Host smart-8d681412-055c-4d3b-b4a6-1a080a830920
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854259780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2854259780
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.1695353703
Short name T1052
Test name
Test status
Simulation time 142299420 ps
CPU time 2.35 seconds
Started Jul 18 06:25:38 PM PDT 24
Finished Jul 18 06:25:45 PM PDT 24
Peak memory 206224 kb
Host smart-0f67e8e0-1b93-44bb-89bc-5595673488b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695353703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.1695353703
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1753660328
Short name T987
Test name
Test status
Simulation time 133919301 ps
CPU time 1.43 seconds
Started Jul 18 06:25:35 PM PDT 24
Finished Jul 18 06:25:40 PM PDT 24
Peak memory 214612 kb
Host smart-7b69a8bf-c922-4289-ab2f-0c8317201f89
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753660328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.1753660328
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2232491751
Short name T1027
Test name
Test status
Simulation time 357076050 ps
CPU time 9.21 seconds
Started Jul 18 06:25:35 PM PDT 24
Finished Jul 18 06:25:47 PM PDT 24
Peak memory 214692 kb
Host smart-56aada40-8d0f-4644-bef6-31222d774fed
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232491751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.2232491751
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.3615633104
Short name T921
Test name
Test status
Simulation time 112427011 ps
CPU time 2.85 seconds
Started Jul 18 06:25:35 PM PDT 24
Finished Jul 18 06:25:40 PM PDT 24
Peak memory 214448 kb
Host smart-f4b6d0fd-ca8a-4c38-b9ba-0b8aa63c52d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615633104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.3615633104
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.250392416
Short name T1076
Test name
Test status
Simulation time 109552515 ps
CPU time 3.83 seconds
Started Jul 18 06:25:34 PM PDT 24
Finished Jul 18 06:25:40 PM PDT 24
Peak memory 215484 kb
Host smart-6bc7983e-d762-4360-865e-96bb1d36dc06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250392416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_err
.250392416
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3502201774
Short name T1070
Test name
Test status
Simulation time 71555673 ps
CPU time 1.31 seconds
Started Jul 18 06:25:35 PM PDT 24
Finished Jul 18 06:25:39 PM PDT 24
Peak memory 214568 kb
Host smart-71def263-2cef-4681-a302-fef03b5d100b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502201774 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.3502201774
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.3057499875
Short name T952
Test name
Test status
Simulation time 71062339 ps
CPU time 1.16 seconds
Started Jul 18 06:25:37 PM PDT 24
Finished Jul 18 06:25:43 PM PDT 24
Peak memory 206224 kb
Host smart-2acbc04d-0ae7-4ead-9c79-47163580d1c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057499875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.3057499875
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.410777242
Short name T919
Test name
Test status
Simulation time 10400344 ps
CPU time 0.78 seconds
Started Jul 18 06:25:31 PM PDT 24
Finished Jul 18 06:25:33 PM PDT 24
Peak memory 205992 kb
Host smart-9030e126-1438-4677-ba40-c73d605d25c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410777242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.410777242
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.517369502
Short name T995
Test name
Test status
Simulation time 44279143 ps
CPU time 1.64 seconds
Started Jul 18 06:25:34 PM PDT 24
Finished Jul 18 06:25:39 PM PDT 24
Peak memory 206240 kb
Host smart-247dd0b1-839b-42c1-8777-26c975e38752
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517369502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_sa
me_csr_outstanding.517369502
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2322125085
Short name T1082
Test name
Test status
Simulation time 699447615 ps
CPU time 1.64 seconds
Started Jul 18 06:25:35 PM PDT 24
Finished Jul 18 06:25:40 PM PDT 24
Peak memory 214684 kb
Host smart-86e52594-1d62-4d9c-a8e5-91b523d7a785
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322125085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.2322125085
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3672109296
Short name T964
Test name
Test status
Simulation time 430837485 ps
CPU time 5.53 seconds
Started Jul 18 06:25:35 PM PDT 24
Finished Jul 18 06:25:44 PM PDT 24
Peak memory 220812 kb
Host smart-1ae68ae5-378d-44e7-b077-3f9439a6dac8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672109296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.3672109296
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.3039832747
Short name T1002
Test name
Test status
Simulation time 53476575 ps
CPU time 1.76 seconds
Started Jul 18 06:25:38 PM PDT 24
Finished Jul 18 06:25:45 PM PDT 24
Peak memory 214472 kb
Host smart-ab761cfd-d5a8-42ff-83bf-5ad92fe065d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039832747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.3039832747
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3938901742
Short name T1071
Test name
Test status
Simulation time 96766191 ps
CPU time 1.22 seconds
Started Jul 18 06:25:38 PM PDT 24
Finished Jul 18 06:25:44 PM PDT 24
Peak memory 206276 kb
Host smart-ad203465-83bf-49f8-ad46-d1184039f514
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938901742 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.3938901742
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.540925557
Short name T1031
Test name
Test status
Simulation time 14465668 ps
CPU time 1.3 seconds
Started Jul 18 06:25:37 PM PDT 24
Finished Jul 18 06:25:43 PM PDT 24
Peak memory 206432 kb
Host smart-a75f4872-671e-4c1c-9cc4-0cb301fab9fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540925557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.540925557
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.2376362531
Short name T918
Test name
Test status
Simulation time 14146123 ps
CPU time 0.76 seconds
Started Jul 18 06:25:36 PM PDT 24
Finished Jul 18 06:25:42 PM PDT 24
Peak memory 205932 kb
Host smart-91229065-fda2-411c-997a-225b1f6d711e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376362531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.2376362531
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3263426589
Short name T1017
Test name
Test status
Simulation time 181578855 ps
CPU time 1.48 seconds
Started Jul 18 06:25:35 PM PDT 24
Finished Jul 18 06:25:39 PM PDT 24
Peak memory 206164 kb
Host smart-d5a68785-a2f7-4bfb-a4e0-51976b604bbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263426589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.3263426589
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3969834155
Short name T129
Test name
Test status
Simulation time 326815407 ps
CPU time 1.94 seconds
Started Jul 18 06:25:36 PM PDT 24
Finished Jul 18 06:25:43 PM PDT 24
Peak memory 214592 kb
Host smart-cc22ad1b-c037-4eef-9426-01cbf7ca9698
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969834155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3969834155
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.3122041581
Short name T934
Test name
Test status
Simulation time 34245464 ps
CPU time 2.5 seconds
Started Jul 18 06:25:36 PM PDT 24
Finished Jul 18 06:25:43 PM PDT 24
Peak memory 214372 kb
Host smart-7fafa2f6-eb3a-4774-b19c-53d76ec52399
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122041581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.3122041581
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2733329743
Short name T939
Test name
Test status
Simulation time 52047330 ps
CPU time 1.43 seconds
Started Jul 18 06:25:38 PM PDT 24
Finished Jul 18 06:25:44 PM PDT 24
Peak memory 214556 kb
Host smart-8b8a72bc-34db-44de-8ac4-7a3743e2c678
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733329743 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.2733329743
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.3102804527
Short name T1067
Test name
Test status
Simulation time 112276331 ps
CPU time 1.34 seconds
Started Jul 18 06:25:34 PM PDT 24
Finished Jul 18 06:25:36 PM PDT 24
Peak memory 206212 kb
Host smart-6f44bb03-1d55-4452-9fd5-4be9770e318d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102804527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.3102804527
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.4227671077
Short name T968
Test name
Test status
Simulation time 19329744 ps
CPU time 0.71 seconds
Started Jul 18 06:25:37 PM PDT 24
Finished Jul 18 06:25:42 PM PDT 24
Peak memory 206020 kb
Host smart-ed18a70a-3cc1-47ef-afea-2f837cbf0901
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227671077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.4227671077
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3717550154
Short name T1039
Test name
Test status
Simulation time 44621310 ps
CPU time 1.6 seconds
Started Jul 18 06:25:38 PM PDT 24
Finished Jul 18 06:25:44 PM PDT 24
Peak memory 206320 kb
Host smart-cb158b17-6b67-42d4-a87c-3efa7869de72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717550154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.3717550154
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2265635240
Short name T127
Test name
Test status
Simulation time 321699672 ps
CPU time 1.75 seconds
Started Jul 18 06:25:35 PM PDT 24
Finished Jul 18 06:25:41 PM PDT 24
Peak memory 214656 kb
Host smart-b3be7bdd-9656-48eb-8aaf-f9cc19661dda
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265635240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.2265635240
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2970876487
Short name T992
Test name
Test status
Simulation time 105064971 ps
CPU time 3.98 seconds
Started Jul 18 06:25:38 PM PDT 24
Finished Jul 18 06:25:46 PM PDT 24
Peak memory 214692 kb
Host smart-81f6e905-2a7a-425a-8001-43dc6e69b878
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970876487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.2970876487
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.1954445180
Short name T980
Test name
Test status
Simulation time 58352032 ps
CPU time 2.57 seconds
Started Jul 18 06:25:36 PM PDT 24
Finished Jul 18 06:25:43 PM PDT 24
Peak memory 214452 kb
Host smart-a8792007-0126-4f8e-bb53-a409d5229e3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954445180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.1954445180
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.4154676619
Short name T938
Test name
Test status
Simulation time 52762308 ps
CPU time 2.17 seconds
Started Jul 18 06:25:38 PM PDT 24
Finished Jul 18 06:25:45 PM PDT 24
Peak memory 214496 kb
Host smart-70edc34c-2cec-4b0a-93bb-7e5a7a4595b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154676619 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.4154676619
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.1582059943
Short name T966
Test name
Test status
Simulation time 21026229 ps
CPU time 1.43 seconds
Started Jul 18 06:25:37 PM PDT 24
Finished Jul 18 06:25:43 PM PDT 24
Peak memory 206308 kb
Host smart-2811a09a-3f14-4020-b59c-322d5f066d1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582059943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.1582059943
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.1248649503
Short name T1003
Test name
Test status
Simulation time 39112368 ps
CPU time 0.81 seconds
Started Jul 18 06:25:37 PM PDT 24
Finished Jul 18 06:25:43 PM PDT 24
Peak memory 206100 kb
Host smart-fe30f47a-ee42-44b3-b29f-f82a2975ebf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248649503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.1248649503
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.592295948
Short name T996
Test name
Test status
Simulation time 35231646 ps
CPU time 2.52 seconds
Started Jul 18 06:25:38 PM PDT 24
Finished Jul 18 06:25:45 PM PDT 24
Peak memory 206292 kb
Host smart-be9e0fb5-00c3-4063-a572-0e256df1c30f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592295948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_sa
me_csr_outstanding.592295948
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.605261506
Short name T1063
Test name
Test status
Simulation time 54605665 ps
CPU time 1.7 seconds
Started Jul 18 06:25:36 PM PDT 24
Finished Jul 18 06:25:41 PM PDT 24
Peak memory 214584 kb
Host smart-b54fe221-c8e4-4be4-b8ea-ab9fa4c90111
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605261506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shado
w_reg_errors.605261506
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2155132266
Short name T1060
Test name
Test status
Simulation time 1566637062 ps
CPU time 6.09 seconds
Started Jul 18 06:25:35 PM PDT 24
Finished Jul 18 06:25:45 PM PDT 24
Peak memory 214728 kb
Host smart-e7f5de50-8079-42ac-82f6-1723a367d667
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155132266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2155132266
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2544866907
Short name T946
Test name
Test status
Simulation time 78152752 ps
CPU time 2.51 seconds
Started Jul 18 06:25:37 PM PDT 24
Finished Jul 18 06:25:44 PM PDT 24
Peak memory 214524 kb
Host smart-130ead69-7a4f-453f-a82d-861935da593a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544866907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.2544866907
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1735370991
Short name T1061
Test name
Test status
Simulation time 127943321 ps
CPU time 1.19 seconds
Started Jul 18 06:25:52 PM PDT 24
Finished Jul 18 06:25:54 PM PDT 24
Peak memory 214500 kb
Host smart-b4ed2e1b-7639-4816-9934-6c3d6c62ad0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735370991 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.1735370991
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1250180691
Short name T1032
Test name
Test status
Simulation time 100894149 ps
CPU time 1.3 seconds
Started Jul 18 06:25:53 PM PDT 24
Finished Jul 18 06:25:56 PM PDT 24
Peak memory 206272 kb
Host smart-4fe3a57b-b8c1-445b-b434-2a2ad66fb776
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250180691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.1250180691
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.1528457405
Short name T944
Test name
Test status
Simulation time 16743876 ps
CPU time 0.77 seconds
Started Jul 18 06:25:58 PM PDT 24
Finished Jul 18 06:26:01 PM PDT 24
Peak memory 205908 kb
Host smart-c2cc2ad2-2f33-49b7-8380-10bf64fc68f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528457405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.1528457405
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.246216317
Short name T1030
Test name
Test status
Simulation time 225021830 ps
CPU time 2.4 seconds
Started Jul 18 06:25:54 PM PDT 24
Finished Jul 18 06:25:59 PM PDT 24
Peak memory 206264 kb
Host smart-71e12f51-6b4e-47da-bcf9-616d99d7ac10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246216317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_sa
me_csr_outstanding.246216317
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2117098123
Short name T1016
Test name
Test status
Simulation time 231177134 ps
CPU time 6.26 seconds
Started Jul 18 06:25:38 PM PDT 24
Finished Jul 18 06:25:50 PM PDT 24
Peak memory 214688 kb
Host smart-9664c3a2-d0d2-471f-a6f4-403a41179160
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117098123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.2117098123
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3562441046
Short name T1035
Test name
Test status
Simulation time 615464956 ps
CPU time 8.51 seconds
Started Jul 18 06:25:52 PM PDT 24
Finished Jul 18 06:26:01 PM PDT 24
Peak memory 214684 kb
Host smart-38988a50-1761-4188-aeda-16c7b8835abe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562441046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.3562441046
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.4093775678
Short name T1055
Test name
Test status
Simulation time 943895336 ps
CPU time 2.88 seconds
Started Jul 18 06:25:56 PM PDT 24
Finished Jul 18 06:26:02 PM PDT 24
Peak memory 216780 kb
Host smart-ef19678e-bf90-4c04-b1d9-fea9ed979f92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093775678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.4093775678
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.1816050783
Short name T1079
Test name
Test status
Simulation time 327767714 ps
CPU time 4.81 seconds
Started Jul 18 06:25:57 PM PDT 24
Finished Jul 18 06:26:05 PM PDT 24
Peak memory 214308 kb
Host smart-6141922a-7602-49f3-a876-e8d7c2c8f69a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816050783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.1816050783
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.1853511351
Short name T967
Test name
Test status
Simulation time 749521863 ps
CPU time 10.55 seconds
Started Jul 18 06:24:49 PM PDT 24
Finished Jul 18 06:25:00 PM PDT 24
Peak memory 206280 kb
Host smart-6c6f3914-4821-4a3a-8d31-b9e2c4b380de
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853511351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.1
853511351
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.1851802358
Short name T979
Test name
Test status
Simulation time 1350044029 ps
CPU time 17.85 seconds
Started Jul 18 06:24:45 PM PDT 24
Finished Jul 18 06:25:04 PM PDT 24
Peak memory 206180 kb
Host smart-2618952d-fdf6-4b0b-835a-4695a940ac9c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851802358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.1
851802358
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.705962390
Short name T1025
Test name
Test status
Simulation time 43110913 ps
CPU time 1.21 seconds
Started Jul 18 06:24:43 PM PDT 24
Finished Jul 18 06:24:46 PM PDT 24
Peak memory 206220 kb
Host smart-8e55acaf-0bbc-4f2f-bd34-f0a6ca564eda
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705962390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.705962390
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.216417369
Short name T178
Test name
Test status
Simulation time 109026438 ps
CPU time 1.35 seconds
Started Jul 18 06:24:44 PM PDT 24
Finished Jul 18 06:24:46 PM PDT 24
Peak memory 206244 kb
Host smart-64a9b45d-65e0-4d3d-8107-b92e1be7e072
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216417369 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.216417369
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3347692004
Short name T1066
Test name
Test status
Simulation time 23847147 ps
CPU time 0.93 seconds
Started Jul 18 06:24:52 PM PDT 24
Finished Jul 18 06:24:54 PM PDT 24
Peak memory 206084 kb
Host smart-3e6ee1a4-9193-49c7-abb3-007d428fb241
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347692004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.3347692004
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.2270702078
Short name T1043
Test name
Test status
Simulation time 33032732 ps
CPU time 0.73 seconds
Started Jul 18 06:24:47 PM PDT 24
Finished Jul 18 06:24:50 PM PDT 24
Peak memory 205944 kb
Host smart-3a19f138-a48d-47cf-a242-274347d72f5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270702078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.2270702078
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1815196601
Short name T1015
Test name
Test status
Simulation time 75859557 ps
CPU time 1.7 seconds
Started Jul 18 06:24:51 PM PDT 24
Finished Jul 18 06:24:54 PM PDT 24
Peak memory 206260 kb
Host smart-d354db03-848d-4d2c-b6de-50c9560910f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815196601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.1815196601
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.167411681
Short name T1064
Test name
Test status
Simulation time 170686428 ps
CPU time 1.38 seconds
Started Jul 18 06:24:51 PM PDT 24
Finished Jul 18 06:24:53 PM PDT 24
Peak memory 214672 kb
Host smart-96dbd77c-6e24-4c42-8b91-82eebd24241d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167411681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow
_reg_errors.167411681
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.541885320
Short name T998
Test name
Test status
Simulation time 270001848 ps
CPU time 4.35 seconds
Started Jul 18 06:24:46 PM PDT 24
Finished Jul 18 06:24:51 PM PDT 24
Peak memory 214732 kb
Host smart-2dc155c9-c554-440d-8561-aea2d06059af
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541885320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_shadow_reg_errors_with_csr_rw.541885320
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.4044374903
Short name T1042
Test name
Test status
Simulation time 42748026 ps
CPU time 1.51 seconds
Started Jul 18 06:24:46 PM PDT 24
Finished Jul 18 06:24:49 PM PDT 24
Peak memory 214508 kb
Host smart-6f4919c0-5385-45f7-bfba-89f93cecb736
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044374903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.4044374903
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1186174262
Short name T975
Test name
Test status
Simulation time 205460895 ps
CPU time 3.44 seconds
Started Jul 18 06:24:49 PM PDT 24
Finished Jul 18 06:24:54 PM PDT 24
Peak memory 215316 kb
Host smart-21351cf0-821d-4eb4-835c-f939409a912a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186174262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.1186174262
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1453953916
Short name T956
Test name
Test status
Simulation time 39596300 ps
CPU time 0.77 seconds
Started Jul 18 06:25:55 PM PDT 24
Finished Jul 18 06:25:59 PM PDT 24
Peak memory 205948 kb
Host smart-5e078b31-55c8-41e3-a22b-cc5fdb665045
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453953916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.1453953916
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.4059760284
Short name T925
Test name
Test status
Simulation time 17776304 ps
CPU time 0.87 seconds
Started Jul 18 06:25:54 PM PDT 24
Finished Jul 18 06:25:58 PM PDT 24
Peak memory 205940 kb
Host smart-cea652c5-213d-4eed-921d-a583df027890
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059760284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.4059760284
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1257499090
Short name T930
Test name
Test status
Simulation time 39090735 ps
CPU time 0.85 seconds
Started Jul 18 06:25:54 PM PDT 24
Finished Jul 18 06:25:57 PM PDT 24
Peak memory 206028 kb
Host smart-eb7f8f19-a515-4166-96bf-f650b6e30253
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257499090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.1257499090
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.649659524
Short name T1056
Test name
Test status
Simulation time 13706476 ps
CPU time 0.81 seconds
Started Jul 18 06:25:57 PM PDT 24
Finished Jul 18 06:26:01 PM PDT 24
Peak memory 206024 kb
Host smart-a54ab122-405a-48b8-bb0f-cd40b5bf6e1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649659524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.649659524
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1922549707
Short name T1058
Test name
Test status
Simulation time 12177889 ps
CPU time 0.71 seconds
Started Jul 18 06:25:53 PM PDT 24
Finished Jul 18 06:25:56 PM PDT 24
Peak memory 206024 kb
Host smart-5f81b946-e243-4c93-9aad-061d20f82c79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922549707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.1922549707
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.2024230540
Short name T1051
Test name
Test status
Simulation time 14625700 ps
CPU time 0.74 seconds
Started Jul 18 06:25:59 PM PDT 24
Finished Jul 18 06:26:02 PM PDT 24
Peak memory 205984 kb
Host smart-4078c22d-2fa0-460a-bf28-37ac9f2d3a49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024230540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.2024230540
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3614363458
Short name T929
Test name
Test status
Simulation time 24163500 ps
CPU time 0.74 seconds
Started Jul 18 06:25:58 PM PDT 24
Finished Jul 18 06:26:01 PM PDT 24
Peak memory 206004 kb
Host smart-a52c674a-6b85-41ef-bf69-85febc781e76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614363458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.3614363458
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.109164480
Short name T950
Test name
Test status
Simulation time 7916438 ps
CPU time 0.81 seconds
Started Jul 18 06:25:52 PM PDT 24
Finished Jul 18 06:25:54 PM PDT 24
Peak memory 206004 kb
Host smart-85c8bb8b-fdd9-40c3-b22b-de4f5f49729d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109164480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.109164480
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2204996645
Short name T1045
Test name
Test status
Simulation time 20535047 ps
CPU time 0.82 seconds
Started Jul 18 06:25:57 PM PDT 24
Finished Jul 18 06:26:00 PM PDT 24
Peak memory 206028 kb
Host smart-b054c13f-cd3e-4c8c-bcae-9a1c260774ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204996645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2204996645
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.3893279192
Short name T1010
Test name
Test status
Simulation time 33749979 ps
CPU time 0.82 seconds
Started Jul 18 06:25:53 PM PDT 24
Finished Jul 18 06:25:55 PM PDT 24
Peak memory 206124 kb
Host smart-8c5a0fb6-2a2a-4923-be09-f828e31f166d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893279192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.3893279192
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.57798814
Short name T154
Test name
Test status
Simulation time 5708385086 ps
CPU time 18.38 seconds
Started Jul 18 06:24:49 PM PDT 24
Finished Jul 18 06:25:08 PM PDT 24
Peak memory 206292 kb
Host smart-f83a3e27-e0d4-44d8-8d34-cab12f551571
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57798814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.57798814
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1437396056
Short name T1001
Test name
Test status
Simulation time 450234697 ps
CPU time 12.38 seconds
Started Jul 18 06:24:45 PM PDT 24
Finished Jul 18 06:24:59 PM PDT 24
Peak memory 206332 kb
Host smart-ce7be9e1-5152-4774-9c26-f6bdc2fc6151
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437396056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.1
437396056
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2478407877
Short name T1011
Test name
Test status
Simulation time 29170819 ps
CPU time 1.45 seconds
Started Jul 18 06:24:45 PM PDT 24
Finished Jul 18 06:24:48 PM PDT 24
Peak memory 206232 kb
Host smart-f8bf9297-68de-4c5e-a1cc-c5739400f101
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478407877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.2
478407877
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.1440730386
Short name T1034
Test name
Test status
Simulation time 39702160 ps
CPU time 1.1 seconds
Started Jul 18 06:24:49 PM PDT 24
Finished Jul 18 06:24:51 PM PDT 24
Peak memory 214524 kb
Host smart-30253147-ee64-408e-ace9-b7290bc0dc64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440730386 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.1440730386
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1316292863
Short name T1059
Test name
Test status
Simulation time 13854160 ps
CPU time 1.05 seconds
Started Jul 18 06:24:49 PM PDT 24
Finished Jul 18 06:24:51 PM PDT 24
Peak memory 206224 kb
Host smart-d8fe00cb-7dad-4e30-808c-26ee4241c6f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316292863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.1316292863
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3590930841
Short name T945
Test name
Test status
Simulation time 8880021 ps
CPU time 0.67 seconds
Started Jul 18 06:24:50 PM PDT 24
Finished Jul 18 06:24:52 PM PDT 24
Peak memory 205928 kb
Host smart-6ef1551d-6848-41ae-bdfd-56d7c36f1e99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590930841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3590930841
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.1204689920
Short name T147
Test name
Test status
Simulation time 35262858 ps
CPU time 2.41 seconds
Started Jul 18 06:24:50 PM PDT 24
Finished Jul 18 06:24:54 PM PDT 24
Peak memory 206316 kb
Host smart-ecda9f91-a49e-43ba-b306-848ad3e4c37d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204689920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.1204689920
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3705525086
Short name T1007
Test name
Test status
Simulation time 90738895 ps
CPU time 2.87 seconds
Started Jul 18 06:24:51 PM PDT 24
Finished Jul 18 06:24:55 PM PDT 24
Peak memory 218796 kb
Host smart-6067ae77-2646-4a1f-8a29-9d345bf8f6af
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705525086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.3705525086
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1427485486
Short name T1048
Test name
Test status
Simulation time 660331304 ps
CPU time 12.17 seconds
Started Jul 18 06:24:51 PM PDT 24
Finished Jul 18 06:25:05 PM PDT 24
Peak memory 214676 kb
Host smart-326eb84a-5acf-4c63-9936-d07f6fc6d4ff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427485486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1427485486
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3236916061
Short name T972
Test name
Test status
Simulation time 129962678 ps
CPU time 2.96 seconds
Started Jul 18 06:24:47 PM PDT 24
Finished Jul 18 06:24:51 PM PDT 24
Peak memory 214492 kb
Host smart-c24d9690-a928-4fee-a76b-811d3b0cbf70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236916061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.3236916061
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.4197422357
Short name T161
Test name
Test status
Simulation time 1019422590 ps
CPU time 4.94 seconds
Started Jul 18 06:24:46 PM PDT 24
Finished Jul 18 06:24:53 PM PDT 24
Peak memory 214276 kb
Host smart-28138ec2-8dd2-4f4b-9810-464dc7cba340
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197422357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.4197422357
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.404568091
Short name T959
Test name
Test status
Simulation time 22072449 ps
CPU time 0.74 seconds
Started Jul 18 06:25:55 PM PDT 24
Finished Jul 18 06:25:58 PM PDT 24
Peak memory 205804 kb
Host smart-d2df5372-b2a3-4aa3-b82c-aa2c0cda115b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404568091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.404568091
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.678313074
Short name T1014
Test name
Test status
Simulation time 10815760 ps
CPU time 0.87 seconds
Started Jul 18 06:25:56 PM PDT 24
Finished Jul 18 06:26:00 PM PDT 24
Peak memory 205992 kb
Host smart-0e2b65b3-774d-4b1e-b2e8-2348c6e5e791
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678313074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.678313074
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.744267248
Short name T982
Test name
Test status
Simulation time 12669370 ps
CPU time 0.86 seconds
Started Jul 18 06:25:54 PM PDT 24
Finished Jul 18 06:25:57 PM PDT 24
Peak memory 205948 kb
Host smart-c45bfbbc-3223-41f2-aa54-7dbf925ba801
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744267248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.744267248
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.1212047882
Short name T1073
Test name
Test status
Simulation time 19939826 ps
CPU time 0.71 seconds
Started Jul 18 06:25:55 PM PDT 24
Finished Jul 18 06:25:58 PM PDT 24
Peak memory 205800 kb
Host smart-f8e56f15-8633-4322-90d2-6b4e43d91adc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212047882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.1212047882
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3497444536
Short name T928
Test name
Test status
Simulation time 17967604 ps
CPU time 0.73 seconds
Started Jul 18 06:25:53 PM PDT 24
Finished Jul 18 06:25:55 PM PDT 24
Peak memory 206012 kb
Host smart-fd8457fe-d5aa-4cbe-b856-79c17d10c733
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497444536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.3497444536
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.2731113789
Short name T1006
Test name
Test status
Simulation time 38753698 ps
CPU time 0.75 seconds
Started Jul 18 06:25:54 PM PDT 24
Finished Jul 18 06:25:57 PM PDT 24
Peak memory 205956 kb
Host smart-add31c65-632b-4e3a-b58d-9bd56515877c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731113789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.2731113789
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2631653361
Short name T1053
Test name
Test status
Simulation time 9409100 ps
CPU time 0.72 seconds
Started Jul 18 06:25:53 PM PDT 24
Finished Jul 18 06:25:55 PM PDT 24
Peak memory 206012 kb
Host smart-71aec731-3513-4bf2-a5a5-bb25851a97c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631653361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.2631653361
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2031523152
Short name T1047
Test name
Test status
Simulation time 13674158 ps
CPU time 0.68 seconds
Started Jul 18 06:25:52 PM PDT 24
Finished Jul 18 06:25:54 PM PDT 24
Peak memory 205932 kb
Host smart-a8638b89-a925-44ec-ac51-3b7a685ef278
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031523152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.2031523152
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.1030488642
Short name T1074
Test name
Test status
Simulation time 42838022 ps
CPU time 0.73 seconds
Started Jul 18 06:25:57 PM PDT 24
Finished Jul 18 06:26:00 PM PDT 24
Peak memory 205984 kb
Host smart-ede9a0ba-30a2-4ad3-8f88-749aa04c92b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030488642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.1030488642
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.569122335
Short name T1083
Test name
Test status
Simulation time 8458370 ps
CPU time 0.83 seconds
Started Jul 18 06:25:54 PM PDT 24
Finished Jul 18 06:25:57 PM PDT 24
Peak memory 205948 kb
Host smart-3584df6e-105d-4bae-8d76-389b1b2ecd46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569122335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.569122335
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.4226425711
Short name T991
Test name
Test status
Simulation time 1241401028 ps
CPU time 9.99 seconds
Started Jul 18 06:24:44 PM PDT 24
Finished Jul 18 06:24:55 PM PDT 24
Peak memory 206160 kb
Host smart-3ea6957d-3878-4062-a488-104ebddabb16
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226425711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.4
226425711
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1128176365
Short name T1078
Test name
Test status
Simulation time 149930893 ps
CPU time 6.68 seconds
Started Jul 18 06:24:43 PM PDT 24
Finished Jul 18 06:24:51 PM PDT 24
Peak memory 206212 kb
Host smart-001f5666-587a-4dc2-9ad9-d3e969d738ab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128176365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.1
128176365
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1003064872
Short name T1072
Test name
Test status
Simulation time 23494875 ps
CPU time 1.14 seconds
Started Jul 18 06:24:46 PM PDT 24
Finished Jul 18 06:24:49 PM PDT 24
Peak memory 206224 kb
Host smart-ea060474-a8aa-4f74-b7ab-69d1d3d93f6c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003064872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.1
003064872
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.355246797
Short name T933
Test name
Test status
Simulation time 76550965 ps
CPU time 1.39 seconds
Started Jul 18 06:24:51 PM PDT 24
Finished Jul 18 06:24:54 PM PDT 24
Peak memory 214496 kb
Host smart-9187bf6c-74de-4871-b7f1-8d3350d27fcd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355246797 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.355246797
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.2062273949
Short name T1080
Test name
Test status
Simulation time 119938127 ps
CPU time 0.89 seconds
Started Jul 18 06:24:45 PM PDT 24
Finished Jul 18 06:24:48 PM PDT 24
Peak memory 206092 kb
Host smart-d35a800b-7998-4057-9af8-0adda78b617a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062273949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.2062273949
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.1404905171
Short name T931
Test name
Test status
Simulation time 7453758 ps
CPU time 0.72 seconds
Started Jul 18 06:24:48 PM PDT 24
Finished Jul 18 06:24:50 PM PDT 24
Peak memory 206024 kb
Host smart-576a125e-b52a-4007-9d26-72e355788ab8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404905171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.1404905171
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1616778327
Short name T1023
Test name
Test status
Simulation time 50546963 ps
CPU time 2.48 seconds
Started Jul 18 06:24:45 PM PDT 24
Finished Jul 18 06:24:49 PM PDT 24
Peak memory 206160 kb
Host smart-23ec7845-2ba6-434c-a8d4-ff77bde41f6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616778327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.1616778327
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.389792101
Short name T130
Test name
Test status
Simulation time 297541970 ps
CPU time 4.59 seconds
Started Jul 18 06:24:49 PM PDT 24
Finished Jul 18 06:24:54 PM PDT 24
Peak memory 219504 kb
Host smart-ad5ac68a-9132-4b4a-8532-e61831d16569
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389792101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow
_reg_errors.389792101
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.3997920040
Short name T1004
Test name
Test status
Simulation time 235091350 ps
CPU time 9.4 seconds
Started Jul 18 06:24:45 PM PDT 24
Finished Jul 18 06:24:56 PM PDT 24
Peak memory 220664 kb
Host smart-90e01689-114d-4151-991a-ad3880d3a261
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997920040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.3997920040
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.3272350522
Short name T969
Test name
Test status
Simulation time 99522243 ps
CPU time 1.76 seconds
Started Jul 18 06:24:45 PM PDT 24
Finished Jul 18 06:24:48 PM PDT 24
Peak memory 214484 kb
Host smart-49f80aaf-9cf8-47be-80af-6050a908d080
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272350522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.3272350522
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.997610918
Short name T158
Test name
Test status
Simulation time 208618579 ps
CPU time 2.76 seconds
Started Jul 18 06:24:43 PM PDT 24
Finished Jul 18 06:24:47 PM PDT 24
Peak memory 214436 kb
Host smart-ea22f712-ebcd-42b0-bbb0-668fe76f38cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997610918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.
997610918
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.419290588
Short name T917
Test name
Test status
Simulation time 28086216 ps
CPU time 0.71 seconds
Started Jul 18 06:25:53 PM PDT 24
Finished Jul 18 06:25:55 PM PDT 24
Peak memory 206028 kb
Host smart-d4ca9a40-5ba1-40f7-99c6-c4cd334eedc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419290588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.419290588
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.2705538861
Short name T971
Test name
Test status
Simulation time 42581073 ps
CPU time 0.8 seconds
Started Jul 18 06:25:52 PM PDT 24
Finished Jul 18 06:25:54 PM PDT 24
Peak memory 206024 kb
Host smart-34204ae3-ec49-41ad-beaf-61334261266b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705538861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.2705538861
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2419755715
Short name T953
Test name
Test status
Simulation time 37670318 ps
CPU time 0.73 seconds
Started Jul 18 06:25:54 PM PDT 24
Finished Jul 18 06:25:57 PM PDT 24
Peak memory 206016 kb
Host smart-8c748fb5-4247-4cbf-8a08-dd5c1e30d7f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419755715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2419755715
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.3500014717
Short name T927
Test name
Test status
Simulation time 42252603 ps
CPU time 0.73 seconds
Started Jul 18 06:25:54 PM PDT 24
Finished Jul 18 06:25:58 PM PDT 24
Peak memory 206124 kb
Host smart-512d185a-ec03-4bf0-888e-3fc35bc10add
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500014717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.3500014717
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.3366240090
Short name T1044
Test name
Test status
Simulation time 54165097 ps
CPU time 0.75 seconds
Started Jul 18 06:25:53 PM PDT 24
Finished Jul 18 06:25:55 PM PDT 24
Peak memory 206048 kb
Host smart-1a93e5e7-2236-44f9-b0b1-5f2068212192
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366240090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.3366240090
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3082790457
Short name T1013
Test name
Test status
Simulation time 52251243 ps
CPU time 0.91 seconds
Started Jul 18 06:25:54 PM PDT 24
Finished Jul 18 06:25:58 PM PDT 24
Peak memory 206168 kb
Host smart-f9f92633-0db7-4621-9652-5f728696ca18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082790457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.3082790457
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2902268929
Short name T1020
Test name
Test status
Simulation time 34105563 ps
CPU time 0.8 seconds
Started Jul 18 06:25:53 PM PDT 24
Finished Jul 18 06:25:55 PM PDT 24
Peak memory 206024 kb
Host smart-18320d58-5be9-42fc-b747-30243449ebb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902268929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.2902268929
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.81933814
Short name T1057
Test name
Test status
Simulation time 10135611 ps
CPU time 0.89 seconds
Started Jul 18 06:25:54 PM PDT 24
Finished Jul 18 06:25:57 PM PDT 24
Peak memory 206020 kb
Host smart-5f9b898b-6f0d-4dd8-8bf7-196894f0324e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81933814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.81933814
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1040846827
Short name T1037
Test name
Test status
Simulation time 19749526 ps
CPU time 0.7 seconds
Started Jul 18 06:25:57 PM PDT 24
Finished Jul 18 06:26:00 PM PDT 24
Peak memory 205984 kb
Host smart-f7840738-e20f-4566-9e79-1f5d7d3eddd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040846827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.1040846827
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1060436263
Short name T1008
Test name
Test status
Simulation time 12331732 ps
CPU time 0.82 seconds
Started Jul 18 06:25:54 PM PDT 24
Finished Jul 18 06:25:57 PM PDT 24
Peak memory 206024 kb
Host smart-966a0e41-7677-416f-a094-da611751219e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060436263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.1060436263
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.889471526
Short name T926
Test name
Test status
Simulation time 48822857 ps
CPU time 2.24 seconds
Started Jul 18 06:25:16 PM PDT 24
Finished Jul 18 06:25:19 PM PDT 24
Peak memory 214504 kb
Host smart-957cbd6d-6133-489a-9123-473b3e7d4540
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889471526 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.889471526
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.1448343252
Short name T940
Test name
Test status
Simulation time 17511331 ps
CPU time 0.85 seconds
Started Jul 18 06:25:13 PM PDT 24
Finished Jul 18 06:25:16 PM PDT 24
Peak memory 206096 kb
Host smart-68470310-16d5-4ec0-87ec-ec09045ef79f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448343252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.1448343252
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.355585054
Short name T914
Test name
Test status
Simulation time 14170129 ps
CPU time 0.7 seconds
Started Jul 18 06:24:47 PM PDT 24
Finished Jul 18 06:24:49 PM PDT 24
Peak memory 206012 kb
Host smart-c3564aa4-5173-4328-8165-06a39db38ae7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355585054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.355585054
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1431065611
Short name T1009
Test name
Test status
Simulation time 468317114 ps
CPU time 2.55 seconds
Started Jul 18 06:25:10 PM PDT 24
Finished Jul 18 06:25:13 PM PDT 24
Peak memory 214420 kb
Host smart-b5281a03-9307-45e0-9651-71e3173dec47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431065611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.1431065611
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2735321351
Short name T1022
Test name
Test status
Simulation time 631138404 ps
CPU time 6.36 seconds
Started Jul 18 06:24:45 PM PDT 24
Finished Jul 18 06:24:52 PM PDT 24
Peak memory 214592 kb
Host smart-4eb7beb0-0225-4945-b08d-8dc605ccee0a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735321351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.2735321351
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3125076980
Short name T935
Test name
Test status
Simulation time 1408622014 ps
CPU time 3.93 seconds
Started Jul 18 06:24:51 PM PDT 24
Finished Jul 18 06:24:56 PM PDT 24
Peak memory 214480 kb
Host smart-66d3cd40-bf84-467b-b638-6271be744aaf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125076980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.3125076980
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1318022327
Short name T168
Test name
Test status
Simulation time 108654416 ps
CPU time 3.05 seconds
Started Jul 18 06:24:44 PM PDT 24
Finished Jul 18 06:24:49 PM PDT 24
Peak memory 214548 kb
Host smart-afafbbcb-cb51-47aa-8f71-024fdd141481
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318022327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.1318022327
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2608057063
Short name T957
Test name
Test status
Simulation time 77832192 ps
CPU time 2.09 seconds
Started Jul 18 06:25:13 PM PDT 24
Finished Jul 18 06:25:17 PM PDT 24
Peak memory 214592 kb
Host smart-96e6840d-6c57-49c8-81ab-2152139990de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608057063 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.2608057063
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1516836972
Short name T1029
Test name
Test status
Simulation time 90419763 ps
CPU time 0.98 seconds
Started Jul 18 06:25:13 PM PDT 24
Finished Jul 18 06:25:15 PM PDT 24
Peak memory 206000 kb
Host smart-0dc40754-6d36-4887-aba6-2afc5f2ae5eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516836972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1516836972
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2528301362
Short name T951
Test name
Test status
Simulation time 13360495 ps
CPU time 0.77 seconds
Started Jul 18 06:25:14 PM PDT 24
Finished Jul 18 06:25:16 PM PDT 24
Peak memory 206024 kb
Host smart-3d7b2544-ab05-4a41-90d7-045815cca800
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528301362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.2528301362
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.3957723633
Short name T148
Test name
Test status
Simulation time 92484856 ps
CPU time 1.74 seconds
Started Jul 18 06:25:13 PM PDT 24
Finished Jul 18 06:25:16 PM PDT 24
Peak memory 206176 kb
Host smart-27a32426-a0d4-4add-9eb8-2464e0fc42b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957723633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.3957723633
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.901609694
Short name T126
Test name
Test status
Simulation time 209772357 ps
CPU time 4.95 seconds
Started Jul 18 06:25:12 PM PDT 24
Finished Jul 18 06:25:18 PM PDT 24
Peak memory 219784 kb
Host smart-b8868f49-f1bb-47e7-b347-df3c48a8c643
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901609694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow
_reg_errors.901609694
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.345208896
Short name T1050
Test name
Test status
Simulation time 435377148 ps
CPU time 5.35 seconds
Started Jul 18 06:25:12 PM PDT 24
Finished Jul 18 06:25:19 PM PDT 24
Peak memory 214692 kb
Host smart-bf63404c-c21b-4372-8246-d50559b35db7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345208896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_shadow_reg_errors_with_csr_rw.345208896
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.4047138227
Short name T1041
Test name
Test status
Simulation time 409638105 ps
CPU time 3.04 seconds
Started Jul 18 06:25:12 PM PDT 24
Finished Jul 18 06:25:17 PM PDT 24
Peak memory 214360 kb
Host smart-8b843c34-8042-4fda-9ec8-1fe651109e78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047138227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.4047138227
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3396946430
Short name T156
Test name
Test status
Simulation time 2842418282 ps
CPU time 6.86 seconds
Started Jul 18 06:25:12 PM PDT 24
Finished Jul 18 06:25:20 PM PDT 24
Peak memory 214500 kb
Host smart-98705e6d-96a5-4741-872e-5df8d026a3e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396946430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.3396946430
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.74397655
Short name T961
Test name
Test status
Simulation time 44881267 ps
CPU time 1.67 seconds
Started Jul 18 06:25:10 PM PDT 24
Finished Jul 18 06:25:13 PM PDT 24
Peak memory 214524 kb
Host smart-5b3eaea1-bd8e-4c2e-b432-6cb65231d449
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74397655 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.74397655
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.4226531909
Short name T947
Test name
Test status
Simulation time 41637501 ps
CPU time 1.13 seconds
Started Jul 18 06:25:11 PM PDT 24
Finished Jul 18 06:25:13 PM PDT 24
Peak memory 206412 kb
Host smart-2ab9afda-f52c-4cdd-b9d7-503591632da2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226531909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.4226531909
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.433051994
Short name T922
Test name
Test status
Simulation time 10908739 ps
CPU time 0.84 seconds
Started Jul 18 06:25:15 PM PDT 24
Finished Jul 18 06:25:18 PM PDT 24
Peak memory 206020 kb
Host smart-458c2d0a-774d-4655-ac17-c4feee172289
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433051994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.433051994
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2090078011
Short name T1038
Test name
Test status
Simulation time 225812681 ps
CPU time 1.68 seconds
Started Jul 18 06:25:14 PM PDT 24
Finished Jul 18 06:25:17 PM PDT 24
Peak memory 206304 kb
Host smart-b0583271-99d0-49fa-9a70-9213c4597636
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090078011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.2090078011
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.569131260
Short name T1026
Test name
Test status
Simulation time 324597341 ps
CPU time 3.05 seconds
Started Jul 18 06:25:13 PM PDT 24
Finished Jul 18 06:25:18 PM PDT 24
Peak memory 214688 kb
Host smart-d6d3a2ec-3938-4600-b3c2-bafc7e300a24
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569131260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow
_reg_errors.569131260
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.528744915
Short name T973
Test name
Test status
Simulation time 337071144 ps
CPU time 9.17 seconds
Started Jul 18 06:25:13 PM PDT 24
Finished Jul 18 06:25:24 PM PDT 24
Peak memory 214708 kb
Host smart-4aea0ed3-c0ca-424e-af5b-ff2b24847348
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528744915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_shadow_reg_errors_with_csr_rw.528744915
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3749388102
Short name T985
Test name
Test status
Simulation time 54090675 ps
CPU time 2.29 seconds
Started Jul 18 06:25:11 PM PDT 24
Finished Jul 18 06:25:15 PM PDT 24
Peak memory 214400 kb
Host smart-3639f853-ce6e-4170-b695-48d9cd1ec695
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749388102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.3749388102
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.972536789
Short name T994
Test name
Test status
Simulation time 16209542 ps
CPU time 1.3 seconds
Started Jul 18 06:25:11 PM PDT 24
Finished Jul 18 06:25:14 PM PDT 24
Peak memory 217216 kb
Host smart-40c72ed2-0887-4cfa-9304-243934b5d2bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972536789 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.972536789
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.738590719
Short name T937
Test name
Test status
Simulation time 255680649 ps
CPU time 1.19 seconds
Started Jul 18 06:25:16 PM PDT 24
Finished Jul 18 06:25:18 PM PDT 24
Peak memory 206232 kb
Host smart-704a3b58-b5c0-49e5-9f4a-c7ebb958e0e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738590719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.738590719
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2640929233
Short name T916
Test name
Test status
Simulation time 11498364 ps
CPU time 0.85 seconds
Started Jul 18 06:25:10 PM PDT 24
Finished Jul 18 06:25:12 PM PDT 24
Peak memory 206008 kb
Host smart-9e387db9-d043-4330-b35c-9ea22b45fc23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640929233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.2640929233
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.2075681308
Short name T965
Test name
Test status
Simulation time 205886310 ps
CPU time 1.63 seconds
Started Jul 18 06:25:14 PM PDT 24
Finished Jul 18 06:25:17 PM PDT 24
Peak memory 206212 kb
Host smart-dba21fba-d773-423b-9653-3b7f887514c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075681308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.2075681308
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3241381578
Short name T1054
Test name
Test status
Simulation time 65937238 ps
CPU time 1.35 seconds
Started Jul 18 06:25:11 PM PDT 24
Finished Jul 18 06:25:14 PM PDT 24
Peak memory 214732 kb
Host smart-4e02572f-fcd4-4e26-909e-e7bbcaaf218d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241381578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.3241381578
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.3931063722
Short name T942
Test name
Test status
Simulation time 113702841 ps
CPU time 2.61 seconds
Started Jul 18 06:25:13 PM PDT 24
Finished Jul 18 06:25:17 PM PDT 24
Peak memory 214292 kb
Host smart-3eff1b2b-b260-4eeb-b43b-7e3827bbf1a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931063722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.3931063722
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.3426613915
Short name T963
Test name
Test status
Simulation time 177264632 ps
CPU time 5.04 seconds
Started Jul 18 06:25:12 PM PDT 24
Finished Jul 18 06:25:19 PM PDT 24
Peak memory 214256 kb
Host smart-696c10b6-9b8c-44f0-892f-4a311e330051
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426613915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.3426613915
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.4235673571
Short name T923
Test name
Test status
Simulation time 28550564 ps
CPU time 1.86 seconds
Started Jul 18 06:25:32 PM PDT 24
Finished Jul 18 06:25:35 PM PDT 24
Peak memory 214580 kb
Host smart-f245c5c9-06c4-48c2-a189-e1c65aefd054
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235673571 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.4235673571
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3899343042
Short name T958
Test name
Test status
Simulation time 26108297 ps
CPU time 1.19 seconds
Started Jul 18 06:25:12 PM PDT 24
Finished Jul 18 06:25:15 PM PDT 24
Peak memory 206424 kb
Host smart-6552c063-f626-458d-8985-bc23cd0b14bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899343042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.3899343042
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2257232029
Short name T924
Test name
Test status
Simulation time 19401313 ps
CPU time 0.89 seconds
Started Jul 18 06:25:13 PM PDT 24
Finished Jul 18 06:25:16 PM PDT 24
Peak memory 206024 kb
Host smart-18ddb042-965b-4f15-b7be-0d877a793f71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257232029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.2257232029
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.3143949711
Short name T943
Test name
Test status
Simulation time 69481250 ps
CPU time 2.28 seconds
Started Jul 18 06:25:36 PM PDT 24
Finished Jul 18 06:25:43 PM PDT 24
Peak memory 206236 kb
Host smart-a4bf7743-72a3-46ab-b857-dee092a7de93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143949711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.3143949711
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2591145383
Short name T1081
Test name
Test status
Simulation time 287548182 ps
CPU time 2.17 seconds
Started Jul 18 06:25:11 PM PDT 24
Finished Jul 18 06:25:14 PM PDT 24
Peak memory 214608 kb
Host smart-b14c8c1e-9a04-44ff-a572-fed717a8557d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591145383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.2591145383
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2354995131
Short name T990
Test name
Test status
Simulation time 180541140 ps
CPU time 7.64 seconds
Started Jul 18 06:25:11 PM PDT 24
Finished Jul 18 06:25:20 PM PDT 24
Peak memory 214684 kb
Host smart-fa93e42a-fa24-402a-886b-8f9cb675b78f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354995131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.2354995131
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3251651388
Short name T1012
Test name
Test status
Simulation time 1121489006 ps
CPU time 4.51 seconds
Started Jul 18 06:25:13 PM PDT 24
Finished Jul 18 06:25:19 PM PDT 24
Peak memory 216624 kb
Host smart-9a83be97-7366-4c5c-9f97-7afb8916a9fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251651388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3251651388
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.2255230268
Short name T506
Test name
Test status
Simulation time 12556224 ps
CPU time 0.79 seconds
Started Jul 18 06:26:53 PM PDT 24
Finished Jul 18 06:26:59 PM PDT 24
Peak memory 205860 kb
Host smart-5e5760ba-45b2-4192-9983-824aab4cc4c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255230268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.2255230268
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.1583363635
Short name T277
Test name
Test status
Simulation time 96461665 ps
CPU time 3.77 seconds
Started Jul 18 06:26:34 PM PDT 24
Finished Jul 18 06:26:43 PM PDT 24
Peak memory 214860 kb
Host smart-01d82ebd-a6e1-408e-bc3a-a85eccd24ce3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1583363635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.1583363635
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.1407549997
Short name T350
Test name
Test status
Simulation time 72660985 ps
CPU time 2.73 seconds
Started Jul 18 06:26:49 PM PDT 24
Finished Jul 18 06:26:54 PM PDT 24
Peak memory 209012 kb
Host smart-b806849b-e4c5-42e1-9e77-d6e2d405bdd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407549997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.1407549997
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.1495869464
Short name T84
Test name
Test status
Simulation time 30777514 ps
CPU time 2.23 seconds
Started Jul 18 06:26:35 PM PDT 24
Finished Jul 18 06:26:43 PM PDT 24
Peak memory 207548 kb
Host smart-b0c37598-15f1-42df-b590-902524c4e2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495869464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.1495869464
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.1624549996
Short name T204
Test name
Test status
Simulation time 645400484 ps
CPU time 23.41 seconds
Started Jul 18 06:26:34 PM PDT 24
Finished Jul 18 06:27:02 PM PDT 24
Peak memory 214144 kb
Host smart-c0fd78ed-2686-4f62-899e-68b45a295107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624549996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.1624549996
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.1570748419
Short name T269
Test name
Test status
Simulation time 135256670 ps
CPU time 2.86 seconds
Started Jul 18 06:26:51 PM PDT 24
Finished Jul 18 06:26:59 PM PDT 24
Peak memory 213968 kb
Host smart-af64292a-6d46-44c4-b89a-927a792f8c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570748419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.1570748419
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_random.165213164
Short name T568
Test name
Test status
Simulation time 34508890 ps
CPU time 2.45 seconds
Started Jul 18 06:26:34 PM PDT 24
Finished Jul 18 06:26:42 PM PDT 24
Peak memory 209580 kb
Host smart-ecfefcfd-c63b-4570-ae1c-3473262c8032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165213164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.165213164
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.1725071504
Short name T410
Test name
Test status
Simulation time 286781933 ps
CPU time 2.67 seconds
Started Jul 18 06:26:36 PM PDT 24
Finished Jul 18 06:26:44 PM PDT 24
Peak memory 207912 kb
Host smart-ed737bd2-ede9-4876-b9fb-11f1d138b362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725071504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.1725071504
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.2585206931
Short name T823
Test name
Test status
Simulation time 84326260 ps
CPU time 1.84 seconds
Started Jul 18 06:26:36 PM PDT 24
Finished Jul 18 06:26:43 PM PDT 24
Peak memory 206528 kb
Host smart-f7944d8f-799d-4386-a80a-09d83f364be5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585206931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.2585206931
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.267893582
Short name T274
Test name
Test status
Simulation time 280402952 ps
CPU time 4.55 seconds
Started Jul 18 06:26:37 PM PDT 24
Finished Jul 18 06:26:46 PM PDT 24
Peak memory 208160 kb
Host smart-d98f439a-121d-4f3c-93d9-55aa2a59bf80
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267893582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.267893582
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.3622346916
Short name T359
Test name
Test status
Simulation time 199594015 ps
CPU time 3.3 seconds
Started Jul 18 06:26:37 PM PDT 24
Finished Jul 18 06:26:44 PM PDT 24
Peak memory 208404 kb
Host smart-1f1e7e76-7374-48e6-8a41-973df5200735
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622346916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.3622346916
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.2132806132
Short name T645
Test name
Test status
Simulation time 1889649828 ps
CPU time 31.61 seconds
Started Jul 18 06:26:50 PM PDT 24
Finished Jul 18 06:27:26 PM PDT 24
Peak memory 214148 kb
Host smart-826d9fd3-a0cc-48e4-a80f-b3519741893e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132806132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2132806132
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.1864068791
Short name T700
Test name
Test status
Simulation time 371507868 ps
CPU time 3.92 seconds
Started Jul 18 06:26:35 PM PDT 24
Finished Jul 18 06:26:43 PM PDT 24
Peak memory 208080 kb
Host smart-5bd70d98-2c8f-457c-b772-e409e8944c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864068791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.1864068791
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.3096196880
Short name T224
Test name
Test status
Simulation time 389426570 ps
CPU time 4.49 seconds
Started Jul 18 06:26:51 PM PDT 24
Finished Jul 18 06:27:00 PM PDT 24
Peak memory 207344 kb
Host smart-604e37c4-aed9-4eca-8e4c-237efc7889f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096196880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.3096196880
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.894322643
Short name T263
Test name
Test status
Simulation time 193918659 ps
CPU time 6.45 seconds
Started Jul 18 06:26:35 PM PDT 24
Finished Jul 18 06:26:47 PM PDT 24
Peak memory 208812 kb
Host smart-063712dd-7789-4dc4-bd79-fbc6ac2f4f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894322643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.894322643
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.1253718694
Short name T35
Test name
Test status
Simulation time 1182000078 ps
CPU time 11.89 seconds
Started Jul 18 06:26:51 PM PDT 24
Finished Jul 18 06:27:07 PM PDT 24
Peak memory 210280 kb
Host smart-a3767d32-4a1f-49c8-91ad-b98c86c71df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253718694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.1253718694
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.2601846662
Short name T20
Test name
Test status
Simulation time 68499354 ps
CPU time 2.47 seconds
Started Jul 18 06:26:50 PM PDT 24
Finished Jul 18 06:26:56 PM PDT 24
Peak memory 216972 kb
Host smart-455a56a4-14a9-4035-a743-5a8f36af0a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601846662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2601846662
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.2842552631
Short name T53
Test name
Test status
Simulation time 432569060 ps
CPU time 5.29 seconds
Started Jul 18 06:26:50 PM PDT 24
Finished Jul 18 06:26:59 PM PDT 24
Peak memory 209432 kb
Host smart-7314a77c-ea29-46ce-ad40-1e028cc14d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842552631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.2842552631
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.2878445257
Short name T665
Test name
Test status
Simulation time 457922295 ps
CPU time 9.05 seconds
Started Jul 18 06:26:50 PM PDT 24
Finished Jul 18 06:27:02 PM PDT 24
Peak memory 208544 kb
Host smart-4088caa4-832e-4fd3-a87c-35d3ae513922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878445257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.2878445257
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.614759240
Short name T851
Test name
Test status
Simulation time 260287081 ps
CPU time 4.9 seconds
Started Jul 18 06:26:53 PM PDT 24
Finished Jul 18 06:27:03 PM PDT 24
Peak memory 214292 kb
Host smart-c6777fb6-50f9-44b0-91a0-9783a3a8b5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614759240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.614759240
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1205822437
Short name T202
Test name
Test status
Simulation time 149648159 ps
CPU time 3.53 seconds
Started Jul 18 06:26:50 PM PDT 24
Finished Jul 18 06:26:57 PM PDT 24
Peak memory 222220 kb
Host smart-f89e9862-9c88-4a05-a10e-29cf0d67efa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205822437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1205822437
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.3341439723
Short name T276
Test name
Test status
Simulation time 206908947 ps
CPU time 5.04 seconds
Started Jul 18 06:26:52 PM PDT 24
Finished Jul 18 06:27:03 PM PDT 24
Peak memory 207660 kb
Host smart-3d529b3d-324b-439c-9db2-3ba9459d1620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341439723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3341439723
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.1450636370
Short name T14
Test name
Test status
Simulation time 999531838 ps
CPU time 14.48 seconds
Started Jul 18 06:26:53 PM PDT 24
Finished Jul 18 06:27:13 PM PDT 24
Peak memory 231928 kb
Host smart-14f5f4a3-b0e4-4437-bb25-450dc9cf1857
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450636370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.1450636370
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.1321137143
Short name T298
Test name
Test status
Simulation time 839936619 ps
CPU time 19.75 seconds
Started Jul 18 06:26:49 PM PDT 24
Finished Jul 18 06:27:10 PM PDT 24
Peak memory 207980 kb
Host smart-76cf85d1-73e8-4333-8f93-9ae076ed5554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321137143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.1321137143
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.402171468
Short name T485
Test name
Test status
Simulation time 303580426 ps
CPU time 5.17 seconds
Started Jul 18 06:26:49 PM PDT 24
Finished Jul 18 06:26:58 PM PDT 24
Peak memory 207892 kb
Host smart-572767cd-b780-41d7-be11-d983dd828f5e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402171468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.402171468
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.3674596725
Short name T646
Test name
Test status
Simulation time 100149336 ps
CPU time 2.06 seconds
Started Jul 18 06:26:52 PM PDT 24
Finished Jul 18 06:27:00 PM PDT 24
Peak memory 208260 kb
Host smart-5c2b2e0e-3326-4aed-81a9-716ee7e4cc97
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674596725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.3674596725
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.4035191790
Short name T186
Test name
Test status
Simulation time 3199692418 ps
CPU time 41.36 seconds
Started Jul 18 06:26:49 PM PDT 24
Finished Jul 18 06:27:32 PM PDT 24
Peak memory 208196 kb
Host smart-6072a3dc-3ba7-4673-be5c-98868b81f097
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035191790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.4035191790
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.1264387705
Short name T409
Test name
Test status
Simulation time 295937619 ps
CPU time 5.58 seconds
Started Jul 18 06:26:53 PM PDT 24
Finished Jul 18 06:27:04 PM PDT 24
Peak memory 209548 kb
Host smart-48227c0e-6b8a-4b3a-8e0f-02deac4c5deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264387705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.1264387705
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.3044459660
Short name T601
Test name
Test status
Simulation time 600885769 ps
CPU time 5.06 seconds
Started Jul 18 06:26:49 PM PDT 24
Finished Jul 18 06:26:56 PM PDT 24
Peak memory 208140 kb
Host smart-a2e3d7b8-97f0-4ccb-9901-9682a59a0522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044459660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.3044459660
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.4168550566
Short name T266
Test name
Test status
Simulation time 1231891538 ps
CPU time 35.77 seconds
Started Jul 18 06:26:48 PM PDT 24
Finished Jul 18 06:27:26 PM PDT 24
Peak memory 218348 kb
Host smart-97b1dea1-3762-4088-a731-2b94a4c1f0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168550566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.4168550566
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.1412916844
Short name T469
Test name
Test status
Simulation time 378697690 ps
CPU time 4.04 seconds
Started Jul 18 06:26:51 PM PDT 24
Finished Jul 18 06:26:59 PM PDT 24
Peak memory 210232 kb
Host smart-a289b89e-51e6-492c-83cc-09615e3e4ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412916844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.1412916844
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.2835900690
Short name T440
Test name
Test status
Simulation time 25037939 ps
CPU time 0.87 seconds
Started Jul 18 06:27:38 PM PDT 24
Finished Jul 18 06:27:42 PM PDT 24
Peak memory 205880 kb
Host smart-40db0226-5226-4db3-987c-e2836eb76c8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835900690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.2835900690
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.2962902779
Short name T902
Test name
Test status
Simulation time 218813495 ps
CPU time 2.49 seconds
Started Jul 18 06:27:36 PM PDT 24
Finished Jul 18 06:27:39 PM PDT 24
Peak memory 207256 kb
Host smart-402aaa4d-980e-49ba-a5ad-c559ac2d29aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962902779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.2962902779
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.647690428
Short name T106
Test name
Test status
Simulation time 375693252 ps
CPU time 4.96 seconds
Started Jul 18 06:27:39 PM PDT 24
Finished Jul 18 06:27:46 PM PDT 24
Peak memory 214316 kb
Host smart-921b92b3-24cd-4d84-854f-49ed487532ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647690428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.647690428
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.1505334769
Short name T50
Test name
Test status
Simulation time 464565238 ps
CPU time 3.92 seconds
Started Jul 18 06:27:38 PM PDT 24
Finished Jul 18 06:27:44 PM PDT 24
Peak memory 222316 kb
Host smart-a8ed7374-5d1a-46f2-9302-8630e275750d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505334769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.1505334769
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_sideload.2958405120
Short name T515
Test name
Test status
Simulation time 21702197 ps
CPU time 1.84 seconds
Started Jul 18 06:27:21 PM PDT 24
Finished Jul 18 06:27:25 PM PDT 24
Peak memory 206568 kb
Host smart-228292aa-1f3e-4b80-8d37-576859c5ae8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958405120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.2958405120
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.4222259746
Short name T774
Test name
Test status
Simulation time 77362076 ps
CPU time 2.89 seconds
Started Jul 18 06:31:10 PM PDT 24
Finished Jul 18 06:31:18 PM PDT 24
Peak memory 208692 kb
Host smart-f40a4159-70eb-4e63-84b4-15333ba80bd5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222259746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.4222259746
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.1129797029
Short name T531
Test name
Test status
Simulation time 4010089010 ps
CPU time 6.63 seconds
Started Jul 18 06:27:23 PM PDT 24
Finished Jul 18 06:27:32 PM PDT 24
Peak memory 208696 kb
Host smart-5eba0149-872d-4b2b-b366-70987b2fa1b5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129797029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.1129797029
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.2592070622
Short name T671
Test name
Test status
Simulation time 250004451 ps
CPU time 2.93 seconds
Started Jul 18 06:27:24 PM PDT 24
Finished Jul 18 06:27:29 PM PDT 24
Peak memory 208396 kb
Host smart-d8e6a58f-ec6a-4e58-aae4-ce921896701f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592070622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.2592070622
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.3896261137
Short name T821
Test name
Test status
Simulation time 37642189 ps
CPU time 1.57 seconds
Started Jul 18 06:27:40 PM PDT 24
Finished Jul 18 06:27:43 PM PDT 24
Peak memory 207948 kb
Host smart-3ccfb6b5-df93-4fd6-9662-a58c59c352a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896261137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.3896261137
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.3162506520
Short name T636
Test name
Test status
Simulation time 291512494 ps
CPU time 2.52 seconds
Started Jul 18 06:27:21 PM PDT 24
Finished Jul 18 06:27:26 PM PDT 24
Peak memory 206752 kb
Host smart-4e525820-8c11-410a-ba5e-69d5d1665823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162506520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3162506520
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.1323735263
Short name T85
Test name
Test status
Simulation time 166906019 ps
CPU time 10.39 seconds
Started Jul 18 06:27:37 PM PDT 24
Finished Jul 18 06:27:50 PM PDT 24
Peak memory 220504 kb
Host smart-b3b9018d-77be-4817-b12f-c0f551fb1574
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323735263 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.1323735263
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3463828215
Short name T623
Test name
Test status
Simulation time 1185876750 ps
CPU time 13.85 seconds
Started Jul 18 06:27:38 PM PDT 24
Finished Jul 18 06:27:54 PM PDT 24
Peak memory 209124 kb
Host smart-397fb593-cafa-4e5b-b99a-1d379d22fa7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463828215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3463828215
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.1735481465
Short name T563
Test name
Test status
Simulation time 14071176 ps
CPU time 0.92 seconds
Started Jul 18 06:27:37 PM PDT 24
Finished Jul 18 06:27:40 PM PDT 24
Peak memory 206000 kb
Host smart-19a88e85-050c-473c-9f1a-ec7aacf193b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735481465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.1735481465
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.3670488526
Short name T25
Test name
Test status
Simulation time 48898547 ps
CPU time 2.76 seconds
Started Jul 18 06:27:38 PM PDT 24
Finished Jul 18 06:27:43 PM PDT 24
Peak memory 220992 kb
Host smart-20ea1e7d-7b95-4c5e-bd1d-1bc8914f2db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670488526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.3670488526
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.2665807617
Short name T596
Test name
Test status
Simulation time 175822820 ps
CPU time 5.26 seconds
Started Jul 18 06:27:34 PM PDT 24
Finished Jul 18 06:27:41 PM PDT 24
Peak memory 207780 kb
Host smart-12b615b1-528c-4c75-8e06-a4ad0a197690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665807617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.2665807617
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.154443701
Short name T766
Test name
Test status
Simulation time 418132354 ps
CPU time 4.79 seconds
Started Jul 18 06:27:41 PM PDT 24
Finished Jul 18 06:27:47 PM PDT 24
Peak memory 222232 kb
Host smart-f77e7ec1-2bbb-45a2-8b4f-4eae0cfe0d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154443701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.154443701
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.853346631
Short name T619
Test name
Test status
Simulation time 304682956 ps
CPU time 3.75 seconds
Started Jul 18 06:27:35 PM PDT 24
Finished Jul 18 06:27:40 PM PDT 24
Peak memory 213980 kb
Host smart-72bc8a7c-2572-4381-8916-3eab22b816a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853346631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.853346631
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.947362726
Short name T251
Test name
Test status
Simulation time 289718027 ps
CPU time 3.46 seconds
Started Jul 18 06:27:40 PM PDT 24
Finished Jul 18 06:27:45 PM PDT 24
Peak memory 219588 kb
Host smart-d7e51cdf-c106-4a8c-af8b-d275eabb3c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947362726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.947362726
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_sideload.4029639729
Short name T509
Test name
Test status
Simulation time 308222966 ps
CPU time 6.04 seconds
Started Jul 18 06:27:36 PM PDT 24
Finished Jul 18 06:27:44 PM PDT 24
Peak memory 208032 kb
Host smart-f0d7eccd-243d-4bf9-955c-cefc64bcd25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029639729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.4029639729
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.1553282207
Short name T903
Test name
Test status
Simulation time 484616813 ps
CPU time 3.85 seconds
Started Jul 18 06:27:35 PM PDT 24
Finished Jul 18 06:27:39 PM PDT 24
Peak memory 208608 kb
Host smart-c14c0a21-1ad4-442a-a986-c57d8e0399e6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553282207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.1553282207
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.3902873186
Short name T649
Test name
Test status
Simulation time 1123367225 ps
CPU time 5.11 seconds
Started Jul 18 06:27:41 PM PDT 24
Finished Jul 18 06:27:47 PM PDT 24
Peak memory 207844 kb
Host smart-0e9cb8ff-30c9-4bf7-8856-6f559807f37c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902873186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.3902873186
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.3006251284
Short name T313
Test name
Test status
Simulation time 65629030 ps
CPU time 2.4 seconds
Started Jul 18 06:27:38 PM PDT 24
Finished Jul 18 06:27:42 PM PDT 24
Peak memory 209684 kb
Host smart-428d4f24-08f1-45f7-a8b4-d9bb6e3d1289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006251284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3006251284
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.4106233918
Short name T448
Test name
Test status
Simulation time 265885346 ps
CPU time 3.32 seconds
Started Jul 18 06:27:36 PM PDT 24
Finished Jul 18 06:27:41 PM PDT 24
Peak memory 208272 kb
Host smart-95533702-d261-4524-b2c5-6091611ae24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106233918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.4106233918
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.3671516773
Short name T855
Test name
Test status
Simulation time 336041399 ps
CPU time 23.98 seconds
Started Jul 18 06:27:40 PM PDT 24
Finished Jul 18 06:28:05 PM PDT 24
Peak memory 222492 kb
Host smart-3b50b816-8144-4e2a-b2ea-b5e8bf7099e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671516773 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.3671516773
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.2509886053
Short name T219
Test name
Test status
Simulation time 1120999835 ps
CPU time 19.62 seconds
Started Jul 18 06:27:36 PM PDT 24
Finished Jul 18 06:27:57 PM PDT 24
Peak memory 209164 kb
Host smart-08081a2e-17f9-467e-8a69-60fb858abf83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509886053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2509886053
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.2263073024
Short name T453
Test name
Test status
Simulation time 30640667 ps
CPU time 1.63 seconds
Started Jul 18 06:27:38 PM PDT 24
Finished Jul 18 06:27:41 PM PDT 24
Peak memory 209884 kb
Host smart-4ea6890c-72e7-46df-ae01-68fba33839d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263073024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.2263073024
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.2842366069
Short name T446
Test name
Test status
Simulation time 37271203 ps
CPU time 0.84 seconds
Started Jul 18 06:27:57 PM PDT 24
Finished Jul 18 06:27:59 PM PDT 24
Peak memory 205852 kb
Host smart-f5848aae-99f9-4d0d-9ad3-52610e3a9099
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842366069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.2842366069
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.1567352187
Short name T351
Test name
Test status
Simulation time 87753319 ps
CPU time 4.96 seconds
Started Jul 18 06:27:39 PM PDT 24
Finished Jul 18 06:27:46 PM PDT 24
Peak memory 214040 kb
Host smart-2b934304-5cd5-45a9-be5e-93e7a4c4c743
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1567352187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.1567352187
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.3273170499
Short name T913
Test name
Test status
Simulation time 68460858 ps
CPU time 1.82 seconds
Started Jul 18 06:27:57 PM PDT 24
Finished Jul 18 06:28:01 PM PDT 24
Peak memory 215388 kb
Host smart-e9ab233e-8eda-4608-8278-e0a9f8a89952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273170499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.3273170499
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.3294341650
Short name T768
Test name
Test status
Simulation time 83717560 ps
CPU time 2.27 seconds
Started Jul 18 06:27:37 PM PDT 24
Finished Jul 18 06:27:40 PM PDT 24
Peak memory 214032 kb
Host smart-f77601f6-4e5e-4a0b-ad89-abd36744ff1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294341650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.3294341650
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.1196627930
Short name T241
Test name
Test status
Simulation time 508999072 ps
CPU time 5.65 seconds
Started Jul 18 06:27:37 PM PDT 24
Finished Jul 18 06:27:44 PM PDT 24
Peak memory 214080 kb
Host smart-323fd0bf-5a6f-4593-9743-e3ba05c5fad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196627930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1196627930
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.3820157464
Short name T211
Test name
Test status
Simulation time 971014081 ps
CPU time 11.38 seconds
Started Jul 18 06:27:37 PM PDT 24
Finished Jul 18 06:27:50 PM PDT 24
Peak memory 209256 kb
Host smart-092e12c1-0200-4cd8-b347-5820e02fee32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820157464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.3820157464
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.1340192920
Short name T389
Test name
Test status
Simulation time 167812892 ps
CPU time 3.06 seconds
Started Jul 18 06:27:39 PM PDT 24
Finished Jul 18 06:27:44 PM PDT 24
Peak memory 208404 kb
Host smart-16f06d17-3e66-44d8-abe2-7d9ddba5f27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340192920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.1340192920
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.1898590657
Short name T578
Test name
Test status
Simulation time 200140486 ps
CPU time 6 seconds
Started Jul 18 06:27:42 PM PDT 24
Finished Jul 18 06:27:49 PM PDT 24
Peak memory 208264 kb
Host smart-b2c738dd-cd2c-4d02-a3c1-d85b64610eaf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898590657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.1898590657
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.2512381871
Short name T905
Test name
Test status
Simulation time 134581053 ps
CPU time 2.86 seconds
Started Jul 18 06:27:38 PM PDT 24
Finished Jul 18 06:27:44 PM PDT 24
Peak memory 208304 kb
Host smart-ca7c8114-904c-427c-8d52-eb41ef327be2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512381871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.2512381871
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.5030181
Short name T290
Test name
Test status
Simulation time 57237331 ps
CPU time 3.06 seconds
Started Jul 18 06:27:39 PM PDT 24
Finished Jul 18 06:27:44 PM PDT 24
Peak memory 208620 kb
Host smart-23a7e8f7-7917-49ab-9d4c-91720ac9774b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5030181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.5030181
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.871111504
Short name T570
Test name
Test status
Simulation time 351034732 ps
CPU time 4.84 seconds
Started Jul 18 06:27:57 PM PDT 24
Finished Jul 18 06:28:03 PM PDT 24
Peak memory 214168 kb
Host smart-3991a8b3-9832-4d50-ae4f-ebe759727428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871111504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.871111504
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.608489283
Short name T808
Test name
Test status
Simulation time 305208977 ps
CPU time 4.05 seconds
Started Jul 18 06:27:37 PM PDT 24
Finished Jul 18 06:27:43 PM PDT 24
Peak memory 208420 kb
Host smart-5e46af82-a4e0-450e-83f3-9a0075501c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608489283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.608489283
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.4176307720
Short name T340
Test name
Test status
Simulation time 212431313 ps
CPU time 8.56 seconds
Started Jul 18 06:27:57 PM PDT 24
Finished Jul 18 06:28:06 PM PDT 24
Peak memory 216108 kb
Host smart-6acdd660-fc04-4997-b356-fb8854de6fbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176307720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.4176307720
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.3383415353
Short name T27
Test name
Test status
Simulation time 204456786 ps
CPU time 5.68 seconds
Started Jul 18 06:27:38 PM PDT 24
Finished Jul 18 06:27:46 PM PDT 24
Peak memory 218244 kb
Host smart-4a1b4e0d-1fc0-4cbe-8d4c-8d52d3633a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383415353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.3383415353
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.1202570942
Short name T759
Test name
Test status
Simulation time 83442908 ps
CPU time 3.67 seconds
Started Jul 18 06:27:59 PM PDT 24
Finished Jul 18 06:28:07 PM PDT 24
Peak memory 210176 kb
Host smart-5ec12b4c-ea56-4cec-a425-18d5d1f56032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202570942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.1202570942
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.1052215374
Short name T16
Test name
Test status
Simulation time 8781917 ps
CPU time 0.83 seconds
Started Jul 18 06:27:57 PM PDT 24
Finished Jul 18 06:28:00 PM PDT 24
Peak memory 205872 kb
Host smart-ba51fa59-f7fc-4f13-b056-deb47f4aaa86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052215374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1052215374
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.1882397584
Short name T418
Test name
Test status
Simulation time 20460719968 ps
CPU time 95.55 seconds
Started Jul 18 06:27:58 PM PDT 24
Finished Jul 18 06:29:36 PM PDT 24
Peak memory 214700 kb
Host smart-5b19bbe3-5883-49da-9661-2333216cd26b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1882397584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.1882397584
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.4278428944
Short name T743
Test name
Test status
Simulation time 494624676 ps
CPU time 1.85 seconds
Started Jul 18 06:27:58 PM PDT 24
Finished Jul 18 06:28:03 PM PDT 24
Peak memory 207512 kb
Host smart-03704323-2f67-42f0-b23e-eaa1eacee6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278428944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.4278428944
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_random.4223018601
Short name T554
Test name
Test status
Simulation time 54297235 ps
CPU time 2.18 seconds
Started Jul 18 06:28:00 PM PDT 24
Finished Jul 18 06:28:06 PM PDT 24
Peak memory 206976 kb
Host smart-66f614d0-de33-45f0-970f-6067cfbb08c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223018601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.4223018601
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.3665092103
Short name T498
Test name
Test status
Simulation time 1110402000 ps
CPU time 7.12 seconds
Started Jul 18 06:28:02 PM PDT 24
Finished Jul 18 06:28:13 PM PDT 24
Peak memory 207708 kb
Host smart-a8de6797-ca2f-42c9-9470-04040dbb94c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665092103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3665092103
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.1173742236
Short name T512
Test name
Test status
Simulation time 77019710 ps
CPU time 3.76 seconds
Started Jul 18 06:27:58 PM PDT 24
Finished Jul 18 06:28:05 PM PDT 24
Peak memory 208420 kb
Host smart-1ae10af1-2c8c-4bda-a898-e9f6d73d5afa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173742236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.1173742236
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.4055795903
Short name T620
Test name
Test status
Simulation time 658602048 ps
CPU time 5.69 seconds
Started Jul 18 06:27:58 PM PDT 24
Finished Jul 18 06:28:06 PM PDT 24
Peak memory 208436 kb
Host smart-4b3d7973-72b3-42c5-9120-be8cb73d6c9c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055795903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.4055795903
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.52108679
Short name T349
Test name
Test status
Simulation time 309260350 ps
CPU time 3.43 seconds
Started Jul 18 06:27:59 PM PDT 24
Finished Jul 18 06:28:06 PM PDT 24
Peak memory 208384 kb
Host smart-3bc74fa7-fb1f-4e47-892d-0e6be85b46ef
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52108679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.52108679
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.2899225257
Short name T718
Test name
Test status
Simulation time 17760186 ps
CPU time 1.61 seconds
Started Jul 18 06:27:57 PM PDT 24
Finished Jul 18 06:28:01 PM PDT 24
Peak memory 206704 kb
Host smart-6e2f859b-a3b7-488f-9a55-9321042a2e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899225257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2899225257
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.2868197587
Short name T36
Test name
Test status
Simulation time 80663391 ps
CPU time 3.52 seconds
Started Jul 18 06:27:58 PM PDT 24
Finished Jul 18 06:28:04 PM PDT 24
Peak memory 208604 kb
Host smart-0fff4ca7-d86b-42dd-b277-acb5b4910542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868197587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.2868197587
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.1879632928
Short name T846
Test name
Test status
Simulation time 530503936 ps
CPU time 8.28 seconds
Started Jul 18 06:27:59 PM PDT 24
Finished Jul 18 06:28:11 PM PDT 24
Peak memory 220628 kb
Host smart-6a38ffdf-47ce-467a-8535-0389908645a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879632928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.1879632928
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.1619425186
Short name T860
Test name
Test status
Simulation time 221279596 ps
CPU time 15.46 seconds
Started Jul 18 06:27:59 PM PDT 24
Finished Jul 18 06:28:19 PM PDT 24
Peak memory 222356 kb
Host smart-4a15a8c9-e764-43a6-803a-794671299dd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619425186 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.1619425186
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.720552585
Short name T225
Test name
Test status
Simulation time 688579722 ps
CPU time 6.77 seconds
Started Jul 18 06:28:00 PM PDT 24
Finished Jul 18 06:28:11 PM PDT 24
Peak memory 218232 kb
Host smart-b0c2ae96-7bdd-4283-bb72-72c8f1586bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720552585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.720552585
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.4103012838
Short name T187
Test name
Test status
Simulation time 67105704 ps
CPU time 2.16 seconds
Started Jul 18 06:27:58 PM PDT 24
Finished Jul 18 06:28:02 PM PDT 24
Peak memory 209432 kb
Host smart-9ed7848e-b07e-437c-a755-f76f93cd9349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103012838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.4103012838
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.1327326134
Short name T482
Test name
Test status
Simulation time 81951298 ps
CPU time 0.82 seconds
Started Jul 18 06:28:01 PM PDT 24
Finished Jul 18 06:28:06 PM PDT 24
Peak memory 205804 kb
Host smart-e7889e5d-02df-459e-877a-2bb0fc58552b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327326134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1327326134
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.2037638708
Short name T34
Test name
Test status
Simulation time 131018038 ps
CPU time 2.39 seconds
Started Jul 18 06:28:01 PM PDT 24
Finished Jul 18 06:28:07 PM PDT 24
Peak memory 221060 kb
Host smart-fa1383d0-21e9-4ca7-a852-54800fed11de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037638708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.2037638708
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.2844893837
Short name T199
Test name
Test status
Simulation time 423638468 ps
CPU time 14.81 seconds
Started Jul 18 06:27:58 PM PDT 24
Finished Jul 18 06:28:16 PM PDT 24
Peak memory 209228 kb
Host smart-845199d1-08f2-4bee-b992-11c6fc3fa95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844893837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.2844893837
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.1968758498
Short name T833
Test name
Test status
Simulation time 45358889 ps
CPU time 1.62 seconds
Started Jul 18 06:28:01 PM PDT 24
Finished Jul 18 06:28:07 PM PDT 24
Peak memory 214148 kb
Host smart-d9557f17-1ff4-4502-a8df-ea2f152180f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968758498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.1968758498
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.3039373047
Short name T877
Test name
Test status
Simulation time 197792512 ps
CPU time 2.74 seconds
Started Jul 18 06:28:01 PM PDT 24
Finished Jul 18 06:28:08 PM PDT 24
Peak memory 214080 kb
Host smart-f21f7d3b-daec-47a4-8e38-3a1da21005f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039373047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3039373047
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.1808654294
Short name T386
Test name
Test status
Simulation time 196328504 ps
CPU time 4.37 seconds
Started Jul 18 06:28:01 PM PDT 24
Finished Jul 18 06:28:10 PM PDT 24
Peak memory 210224 kb
Host smart-3ad11026-f12a-4148-b42e-3b17c7ea94fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808654294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.1808654294
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.1625489804
Short name T891
Test name
Test status
Simulation time 105345819 ps
CPU time 2.29 seconds
Started Jul 18 06:28:00 PM PDT 24
Finished Jul 18 06:28:06 PM PDT 24
Peak memory 206644 kb
Host smart-fc55dd94-c712-4221-aff4-f7d7a441f2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625489804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.1625489804
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.4024569669
Short name T477
Test name
Test status
Simulation time 49781757 ps
CPU time 2.6 seconds
Started Jul 18 06:28:01 PM PDT 24
Finished Jul 18 06:28:08 PM PDT 24
Peak memory 206612 kb
Host smart-b1c81477-5c98-402b-bc66-3203b530b777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024569669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.4024569669
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.3109790354
Short name T580
Test name
Test status
Simulation time 429518258 ps
CPU time 11.61 seconds
Started Jul 18 06:28:00 PM PDT 24
Finished Jul 18 06:28:16 PM PDT 24
Peak memory 208584 kb
Host smart-92cbe3b1-4fe3-4b0e-a1b4-88a914ecdb69
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109790354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3109790354
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.4142684587
Short name T455
Test name
Test status
Simulation time 1232127586 ps
CPU time 4.08 seconds
Started Jul 18 06:27:59 PM PDT 24
Finished Jul 18 06:28:07 PM PDT 24
Peak memory 208324 kb
Host smart-12d3c9cf-9a5d-4f65-9774-30979428a8c9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142684587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.4142684587
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.2289644741
Short name T232
Test name
Test status
Simulation time 88118661 ps
CPU time 2.48 seconds
Started Jul 18 06:28:01 PM PDT 24
Finished Jul 18 06:28:08 PM PDT 24
Peak memory 206624 kb
Host smart-f8f23727-394f-433e-9660-46f9992cbd2d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289644741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.2289644741
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.4235977454
Short name T426
Test name
Test status
Simulation time 40807414 ps
CPU time 2.25 seconds
Started Jul 18 06:28:01 PM PDT 24
Finished Jul 18 06:28:07 PM PDT 24
Peak memory 214168 kb
Host smart-06dcbb06-0e6a-4ace-96be-f5ec66d4d523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235977454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.4235977454
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.1976109746
Short name T558
Test name
Test status
Simulation time 110938979 ps
CPU time 3.11 seconds
Started Jul 18 06:28:02 PM PDT 24
Finished Jul 18 06:28:09 PM PDT 24
Peak memory 206552 kb
Host smart-e07722f8-8af4-4461-bbaf-9efbfc3ec0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976109746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.1976109746
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.4247612463
Short name T492
Test name
Test status
Simulation time 398051785 ps
CPU time 6.34 seconds
Started Jul 18 06:28:01 PM PDT 24
Finished Jul 18 06:28:13 PM PDT 24
Peak memory 214060 kb
Host smart-d94baaa4-7cc8-4072-8b2d-e5d688e3d64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247612463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.4247612463
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.1192913481
Short name T113
Test name
Test status
Simulation time 120566272 ps
CPU time 2.33 seconds
Started Jul 18 06:28:01 PM PDT 24
Finished Jul 18 06:28:07 PM PDT 24
Peak memory 209916 kb
Host smart-be76f612-7dbe-4c9a-a394-9abd690f4060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192913481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1192913481
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.1227789134
Short name T906
Test name
Test status
Simulation time 12957532 ps
CPU time 0.92 seconds
Started Jul 18 06:28:04 PM PDT 24
Finished Jul 18 06:28:10 PM PDT 24
Peak memory 205836 kb
Host smart-504db8bb-2fe3-42ab-bc33-400b665e6c5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227789134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.1227789134
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.1384287689
Short name T427
Test name
Test status
Simulation time 151199695 ps
CPU time 3.53 seconds
Started Jul 18 06:28:02 PM PDT 24
Finished Jul 18 06:28:10 PM PDT 24
Peak memory 215100 kb
Host smart-9ca18ddb-da49-4b1d-b60f-4404d84e4be0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1384287689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.1384287689
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.4225381965
Short name T42
Test name
Test status
Simulation time 772539535 ps
CPU time 24 seconds
Started Jul 18 06:28:03 PM PDT 24
Finished Jul 18 06:28:32 PM PDT 24
Peak memory 208924 kb
Host smart-dd069f99-e016-4ab9-9c0d-1762864401b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225381965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.4225381965
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.1720623797
Short name T845
Test name
Test status
Simulation time 54908822 ps
CPU time 2.11 seconds
Started Jul 18 06:27:58 PM PDT 24
Finished Jul 18 06:28:03 PM PDT 24
Peak memory 214060 kb
Host smart-dd70b5b3-cf94-484e-b9cd-59e02f30b41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720623797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.1720623797
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.3867423964
Short name T834
Test name
Test status
Simulation time 1336465316 ps
CPU time 7.76 seconds
Started Jul 18 06:28:02 PM PDT 24
Finished Jul 18 06:28:14 PM PDT 24
Peak memory 208944 kb
Host smart-87c867f5-a3f7-47cc-b1ec-8f61b4d9461f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867423964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.3867423964
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.2039078032
Short name T284
Test name
Test status
Simulation time 36646451 ps
CPU time 2.17 seconds
Started Jul 18 06:28:03 PM PDT 24
Finished Jul 18 06:28:09 PM PDT 24
Peak memory 214004 kb
Host smart-05323486-c533-4978-94b7-bc9b8e7e2cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039078032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.2039078032
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.1745001824
Short name T57
Test name
Test status
Simulation time 94679871 ps
CPU time 2.72 seconds
Started Jul 18 06:28:00 PM PDT 24
Finished Jul 18 06:28:07 PM PDT 24
Peak memory 214064 kb
Host smart-c248828c-3563-49ce-85d6-8684a11ac128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745001824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.1745001824
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.2260149635
Short name T294
Test name
Test status
Simulation time 636795370 ps
CPU time 7.23 seconds
Started Jul 18 06:28:02 PM PDT 24
Finished Jul 18 06:28:14 PM PDT 24
Peak memory 217748 kb
Host smart-1a95c166-8d46-41b1-a4e4-d8fe862990c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260149635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.2260149635
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.951601442
Short name T335
Test name
Test status
Simulation time 404119953 ps
CPU time 7.39 seconds
Started Jul 18 06:28:03 PM PDT 24
Finished Jul 18 06:28:14 PM PDT 24
Peak memory 208520 kb
Host smart-212af612-b448-4907-ad80-ed7ff110cbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951601442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.951601442
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.2014008742
Short name T571
Test name
Test status
Simulation time 56500120 ps
CPU time 2.98 seconds
Started Jul 18 06:28:02 PM PDT 24
Finished Jul 18 06:28:10 PM PDT 24
Peak memory 208248 kb
Host smart-ac90d1e8-deaf-4d64-afa9-23a5798bc9f4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014008742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.2014008742
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.560310277
Short name T600
Test name
Test status
Simulation time 601779434 ps
CPU time 4.16 seconds
Started Jul 18 06:28:06 PM PDT 24
Finished Jul 18 06:28:13 PM PDT 24
Peak memory 206572 kb
Host smart-eabcc284-16be-4271-9289-106468ce0a05
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560310277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.560310277
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.4280494545
Short name T593
Test name
Test status
Simulation time 3331244366 ps
CPU time 12.97 seconds
Started Jul 18 06:28:02 PM PDT 24
Finished Jul 18 06:28:19 PM PDT 24
Peak memory 208140 kb
Host smart-6ab5f0aa-fa79-4c10-9f19-c71c844af82c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280494545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.4280494545
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.3950078694
Short name T135
Test name
Test status
Simulation time 2543998692 ps
CPU time 10.06 seconds
Started Jul 18 06:28:04 PM PDT 24
Finished Jul 18 06:28:18 PM PDT 24
Peak memory 208124 kb
Host smart-db1010e5-5308-404e-98af-c9130ade5dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950078694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3950078694
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.1491260125
Short name T89
Test name
Test status
Simulation time 236244544 ps
CPU time 2.7 seconds
Started Jul 18 06:28:00 PM PDT 24
Finished Jul 18 06:28:07 PM PDT 24
Peak memory 208660 kb
Host smart-923b6f60-00a8-409e-972e-2179b7d9252f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491260125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.1491260125
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.1617258140
Short name T904
Test name
Test status
Simulation time 115323403 ps
CPU time 4.85 seconds
Started Jul 18 06:27:59 PM PDT 24
Finished Jul 18 06:28:07 PM PDT 24
Peak memory 222372 kb
Host smart-b601c39d-4095-42d7-bfc3-18478416b899
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617258140 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.1617258140
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.3613467662
Short name T88
Test name
Test status
Simulation time 60749045 ps
CPU time 3.42 seconds
Started Jul 18 06:28:02 PM PDT 24
Finished Jul 18 06:28:10 PM PDT 24
Peak memory 208736 kb
Host smart-2cb48ce4-b6c5-4d0a-8d34-f23b386bc213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613467662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.3613467662
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.1998848743
Short name T847
Test name
Test status
Simulation time 10115893 ps
CPU time 0.7 seconds
Started Jul 18 06:28:12 PM PDT 24
Finished Jul 18 06:28:14 PM PDT 24
Peak memory 205860 kb
Host smart-a508a4ac-8b74-4e9a-9dc3-ff10d26ec86a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998848743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1998848743
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.1090698236
Short name T283
Test name
Test status
Simulation time 90678709 ps
CPU time 2.77 seconds
Started Jul 18 06:27:59 PM PDT 24
Finished Jul 18 06:28:06 PM PDT 24
Peak memory 207340 kb
Host smart-21c94cc7-90ca-4f7a-889f-229d38b271ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090698236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.1090698236
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.962018526
Short name T797
Test name
Test status
Simulation time 69572457 ps
CPU time 3 seconds
Started Jul 18 06:28:12 PM PDT 24
Finished Jul 18 06:28:16 PM PDT 24
Peak memory 209428 kb
Host smart-87b97fb0-cd80-4928-a05d-55a6638bc5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962018526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.962018526
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.1638973804
Short name T744
Test name
Test status
Simulation time 500108926 ps
CPU time 4.52 seconds
Started Jul 18 06:28:11 PM PDT 24
Finished Jul 18 06:28:17 PM PDT 24
Peak memory 214064 kb
Host smart-66f13b66-c554-42f0-a0cc-89ca78099325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638973804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.1638973804
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.3485964306
Short name T777
Test name
Test status
Simulation time 379774282 ps
CPU time 9.39 seconds
Started Jul 18 06:28:05 PM PDT 24
Finished Jul 18 06:28:18 PM PDT 24
Peak memory 219012 kb
Host smart-f390756e-0b7f-47dd-9955-e7b7ce4bc3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485964306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3485964306
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.2138186968
Short name T476
Test name
Test status
Simulation time 448921191 ps
CPU time 4.4 seconds
Started Jul 18 06:28:03 PM PDT 24
Finished Jul 18 06:28:12 PM PDT 24
Peak memory 208556 kb
Host smart-56ce5c9c-e511-4b99-80e3-6b63e605434a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138186968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2138186968
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.1144311371
Short name T345
Test name
Test status
Simulation time 408078641 ps
CPU time 10.5 seconds
Started Jul 18 06:28:05 PM PDT 24
Finished Jul 18 06:28:19 PM PDT 24
Peak memory 208536 kb
Host smart-3196532c-503f-4994-aa2d-c631f0442355
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144311371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.1144311371
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.2205736228
Short name T696
Test name
Test status
Simulation time 35044959 ps
CPU time 2.51 seconds
Started Jul 18 06:28:04 PM PDT 24
Finished Jul 18 06:28:11 PM PDT 24
Peak memory 206712 kb
Host smart-c3e689e4-0b10-45a1-b62d-8a773c17931a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205736228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.2205736228
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.3349325153
Short name T507
Test name
Test status
Simulation time 4228732005 ps
CPU time 21.96 seconds
Started Jul 18 06:28:06 PM PDT 24
Finished Jul 18 06:28:31 PM PDT 24
Peak memory 208452 kb
Host smart-2cafd402-f061-43e0-b784-c83c4f3f4692
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349325153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.3349325153
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.695918275
Short name T745
Test name
Test status
Simulation time 55202336 ps
CPU time 2.82 seconds
Started Jul 18 06:28:11 PM PDT 24
Finished Jul 18 06:28:15 PM PDT 24
Peak memory 209924 kb
Host smart-f4353e62-f02b-4c89-ae8a-53d8a1c40a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695918275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.695918275
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.300418611
Short name T787
Test name
Test status
Simulation time 372929682 ps
CPU time 4.07 seconds
Started Jul 18 06:28:06 PM PDT 24
Finished Jul 18 06:28:13 PM PDT 24
Peak memory 206488 kb
Host smart-5398fb13-50ad-4882-9cad-9269f462d872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300418611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.300418611
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.1737754857
Short name T780
Test name
Test status
Simulation time 2984017526 ps
CPU time 40.85 seconds
Started Jul 18 06:28:11 PM PDT 24
Finished Jul 18 06:28:53 PM PDT 24
Peak memory 216944 kb
Host smart-f5a1b294-32ea-48ce-8692-67f58cc8c9b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737754857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.1737754857
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.4034633891
Short name T886
Test name
Test status
Simulation time 224717787 ps
CPU time 4.12 seconds
Started Jul 18 06:28:13 PM PDT 24
Finished Jul 18 06:28:20 PM PDT 24
Peak memory 214148 kb
Host smart-27608343-0d79-4fc5-a007-df647867a2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034633891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.4034633891
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.927589428
Short name T560
Test name
Test status
Simulation time 181502083 ps
CPU time 2.68 seconds
Started Jul 18 06:28:15 PM PDT 24
Finished Jul 18 06:28:20 PM PDT 24
Peak memory 209884 kb
Host smart-5f63b56f-0d5a-4bc2-b2b5-0547a78cc9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927589428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.927589428
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.4074405393
Short name T579
Test name
Test status
Simulation time 178608485 ps
CPU time 0.97 seconds
Started Jul 18 06:28:17 PM PDT 24
Finished Jul 18 06:28:23 PM PDT 24
Peak memory 205856 kb
Host smart-ae39a8eb-88f3-4ee0-9bc7-2aa74f6d4386
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074405393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.4074405393
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.293218119
Short name T151
Test name
Test status
Simulation time 541307910 ps
CPU time 8.25 seconds
Started Jul 18 06:28:16 PM PDT 24
Finished Jul 18 06:28:27 PM PDT 24
Peak memory 214080 kb
Host smart-912923f6-60c9-4e14-9109-bfc560c349f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=293218119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.293218119
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.1368142724
Short name T41
Test name
Test status
Simulation time 247133029 ps
CPU time 4.78 seconds
Started Jul 18 06:28:13 PM PDT 24
Finished Jul 18 06:28:20 PM PDT 24
Peak memory 217892 kb
Host smart-55c4c184-b6f1-480e-b105-863b95f9813d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368142724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.1368142724
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.981872262
Short name T525
Test name
Test status
Simulation time 66556079 ps
CPU time 2.73 seconds
Started Jul 18 06:28:14 PM PDT 24
Finished Jul 18 06:28:18 PM PDT 24
Peak memory 218176 kb
Host smart-733b5916-06fb-43ac-8660-34c5d4784507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981872262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.981872262
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2192534965
Short name T180
Test name
Test status
Simulation time 261847209 ps
CPU time 5.85 seconds
Started Jul 18 06:28:13 PM PDT 24
Finished Jul 18 06:28:20 PM PDT 24
Peak memory 206992 kb
Host smart-118ccab4-0ffc-427f-ad1e-db19cbdef004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192534965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2192534965
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.3794042028
Short name T742
Test name
Test status
Simulation time 209101902 ps
CPU time 2.39 seconds
Started Jul 18 06:28:16 PM PDT 24
Finished Jul 18 06:28:21 PM PDT 24
Peak memory 219568 kb
Host smart-6fe2b164-ba46-44e5-9b96-da257839426e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794042028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.3794042028
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.2572188982
Short name T252
Test name
Test status
Simulation time 536532283 ps
CPU time 4.03 seconds
Started Jul 18 06:28:12 PM PDT 24
Finished Jul 18 06:28:17 PM PDT 24
Peak memory 214108 kb
Host smart-a1bb3afb-b8ba-4de0-a412-79591928d426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572188982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.2572188982
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.3007195387
Short name T496
Test name
Test status
Simulation time 151568529 ps
CPU time 4.36 seconds
Started Jul 18 06:28:12 PM PDT 24
Finished Jul 18 06:28:18 PM PDT 24
Peak memory 209268 kb
Host smart-11e34483-e146-41a9-b13f-3067759d1d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007195387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.3007195387
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.3826621406
Short name T861
Test name
Test status
Simulation time 170937166 ps
CPU time 6.64 seconds
Started Jul 18 06:28:14 PM PDT 24
Finished Jul 18 06:28:23 PM PDT 24
Peak memory 208128 kb
Host smart-1ddb0caf-bc01-43bf-9ac1-8ac526192ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826621406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3826621406
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.2599505854
Short name T360
Test name
Test status
Simulation time 776098251 ps
CPU time 6.8 seconds
Started Jul 18 06:28:12 PM PDT 24
Finished Jul 18 06:28:20 PM PDT 24
Peak memory 207908 kb
Host smart-0d0e1bb2-f23f-473b-8808-296f25716a25
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599505854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.2599505854
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.2896189306
Short name T483
Test name
Test status
Simulation time 53327319 ps
CPU time 2.6 seconds
Started Jul 18 06:28:15 PM PDT 24
Finished Jul 18 06:28:20 PM PDT 24
Peak memory 206720 kb
Host smart-abbec379-25e1-44bd-a79d-51c3a4ebbb27
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896189306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2896189306
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.1231476332
Short name T720
Test name
Test status
Simulation time 364097229 ps
CPU time 5.14 seconds
Started Jul 18 06:28:14 PM PDT 24
Finished Jul 18 06:28:21 PM PDT 24
Peak memory 208504 kb
Host smart-c494314b-a9ac-4f89-850c-cb66b17d03ef
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231476332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.1231476332
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.3501597447
Short name T567
Test name
Test status
Simulation time 84939217 ps
CPU time 2.22 seconds
Started Jul 18 06:28:18 PM PDT 24
Finished Jul 18 06:28:26 PM PDT 24
Peak memory 215544 kb
Host smart-a7ffdcce-89aa-4207-9157-000e35314dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501597447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3501597447
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.715999847
Short name T748
Test name
Test status
Simulation time 414171591 ps
CPU time 2.4 seconds
Started Jul 18 06:28:12 PM PDT 24
Finished Jul 18 06:28:16 PM PDT 24
Peak memory 208056 kb
Host smart-8247aa3e-f7aa-4a21-89ea-0ba21a50efa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715999847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.715999847
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.507089770
Short name T582
Test name
Test status
Simulation time 2159258398 ps
CPU time 80.33 seconds
Started Jul 18 06:28:16 PM PDT 24
Finished Jul 18 06:29:39 PM PDT 24
Peak memory 222196 kb
Host smart-670649b6-0d4e-42d3-8ba0-b11d39979eae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507089770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.507089770
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.2647398510
Short name T464
Test name
Test status
Simulation time 264123916 ps
CPU time 9.76 seconds
Started Jul 18 06:28:18 PM PDT 24
Finished Jul 18 06:28:34 PM PDT 24
Peak memory 222364 kb
Host smart-81070eb4-a193-43b6-bc7d-0a8b2efcbfad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647398510 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.2647398510
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.3890414114
Short name T388
Test name
Test status
Simulation time 480250710 ps
CPU time 5.16 seconds
Started Jul 18 06:28:14 PM PDT 24
Finished Jul 18 06:28:21 PM PDT 24
Peak memory 210112 kb
Host smart-0de5e1f6-cd4d-4d64-88f8-1298e44d5b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890414114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.3890414114
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.4123100771
Short name T196
Test name
Test status
Simulation time 91075312 ps
CPU time 2.41 seconds
Started Jul 18 06:28:16 PM PDT 24
Finished Jul 18 06:28:22 PM PDT 24
Peak memory 209796 kb
Host smart-61553c84-49d3-497c-93ec-c01048e6ce2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123100771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.4123100771
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.3944826492
Short name T817
Test name
Test status
Simulation time 44651669 ps
CPU time 0.76 seconds
Started Jul 18 06:28:19 PM PDT 24
Finished Jul 18 06:28:27 PM PDT 24
Peak memory 205836 kb
Host smart-697ea704-c132-4ac1-9948-f96d1eb33eaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944826492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.3944826492
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.1625593461
Short name T436
Test name
Test status
Simulation time 174091017 ps
CPU time 3.51 seconds
Started Jul 18 06:28:17 PM PDT 24
Finished Jul 18 06:28:24 PM PDT 24
Peak memory 214144 kb
Host smart-87afe128-7e8f-450b-85c3-0f8ec7050f5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1625593461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.1625593461
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.264314524
Short name T856
Test name
Test status
Simulation time 166113376 ps
CPU time 3.68 seconds
Started Jul 18 06:28:17 PM PDT 24
Finished Jul 18 06:28:25 PM PDT 24
Peak memory 209708 kb
Host smart-e451312c-0e8b-4cbe-afde-35559c1494f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264314524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.264314524
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.1661379096
Short name T78
Test name
Test status
Simulation time 105935111 ps
CPU time 2.31 seconds
Started Jul 18 06:28:13 PM PDT 24
Finished Jul 18 06:28:18 PM PDT 24
Peak memory 219548 kb
Host smart-ba60bebf-d18e-464b-9458-71fab65480e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661379096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.1661379096
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.3707522456
Short name T102
Test name
Test status
Simulation time 1290290186 ps
CPU time 8.09 seconds
Started Jul 18 06:28:19 PM PDT 24
Finished Jul 18 06:28:34 PM PDT 24
Peak memory 208256 kb
Host smart-5ab1c11a-f64b-4c06-84a2-cecc6afcef97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707522456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.3707522456
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.1439219075
Short name T98
Test name
Test status
Simulation time 57233057 ps
CPU time 2.31 seconds
Started Jul 18 06:28:19 PM PDT 24
Finished Jul 18 06:28:28 PM PDT 24
Peak memory 212856 kb
Host smart-e35d956f-25c0-40ea-a5dd-2c8a13f39460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439219075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.1439219075
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.1338776141
Short name T809
Test name
Test status
Simulation time 314803774 ps
CPU time 4.53 seconds
Started Jul 18 06:28:17 PM PDT 24
Finished Jul 18 06:28:26 PM PDT 24
Peak memory 219992 kb
Host smart-08444b35-4548-48a1-a49e-2ae6c3b185a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338776141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.1338776141
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.435769515
Short name T736
Test name
Test status
Simulation time 110368322 ps
CPU time 4.72 seconds
Started Jul 18 06:28:13 PM PDT 24
Finished Jul 18 06:28:19 PM PDT 24
Peak memory 208264 kb
Host smart-eead0268-0e23-4760-a5be-0080042df62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435769515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.435769515
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.1784832351
Short name T590
Test name
Test status
Simulation time 47365476 ps
CPU time 2.43 seconds
Started Jul 18 06:28:17 PM PDT 24
Finished Jul 18 06:28:25 PM PDT 24
Peak memory 207912 kb
Host smart-9a0347e1-3547-4b12-8fce-7461d09a29c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784832351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.1784832351
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.2989110570
Short name T193
Test name
Test status
Simulation time 714713222 ps
CPU time 19.93 seconds
Started Jul 18 06:28:17 PM PDT 24
Finished Jul 18 06:28:42 PM PDT 24
Peak memory 208088 kb
Host smart-d75f9741-2126-4b28-9cab-71f1600f38c5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989110570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.2989110570
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.743907780
Short name T885
Test name
Test status
Simulation time 24843860 ps
CPU time 2.02 seconds
Started Jul 18 06:28:14 PM PDT 24
Finished Jul 18 06:28:18 PM PDT 24
Peak memory 206772 kb
Host smart-80736418-797e-48c0-8fa5-3b5afda8ff51
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743907780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.743907780
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.1566558538
Short name T732
Test name
Test status
Simulation time 69039497 ps
CPU time 2.57 seconds
Started Jul 18 06:28:14 PM PDT 24
Finished Jul 18 06:28:19 PM PDT 24
Peak memory 206696 kb
Host smart-4c1b6877-1d79-4910-8f6e-2756f3257ea1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566558538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.1566558538
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.1439903460
Short name T223
Test name
Test status
Simulation time 80061108 ps
CPU time 2.11 seconds
Started Jul 18 06:28:19 PM PDT 24
Finished Jul 18 06:28:28 PM PDT 24
Peak memory 208120 kb
Host smart-899e864b-80b6-4222-8f7b-2f33b83cf0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439903460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.1439903460
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.3051681789
Short name T654
Test name
Test status
Simulation time 517723338 ps
CPU time 2.88 seconds
Started Jul 18 06:28:12 PM PDT 24
Finished Jul 18 06:28:17 PM PDT 24
Peak memory 208248 kb
Host smart-dbb521a0-14c4-48cc-ab36-539bbc4e70fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051681789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.3051681789
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.1869636138
Short name T375
Test name
Test status
Simulation time 137785765 ps
CPU time 2.59 seconds
Started Jul 18 06:28:17 PM PDT 24
Finished Jul 18 06:28:24 PM PDT 24
Peak memory 206248 kb
Host smart-9d6c8829-ce9c-465c-aca6-0f56dcc96b70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869636138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.1869636138
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.1544760473
Short name T836
Test name
Test status
Simulation time 438185378 ps
CPU time 4.44 seconds
Started Jul 18 06:28:17 PM PDT 24
Finished Jul 18 06:28:27 PM PDT 24
Peak memory 214080 kb
Host smart-a1ba5b7d-b6bd-40d8-867f-b01fefef81bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544760473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.1544760473
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.1843716504
Short name T394
Test name
Test status
Simulation time 90936874 ps
CPU time 1.75 seconds
Started Jul 18 06:28:18 PM PDT 24
Finished Jul 18 06:28:25 PM PDT 24
Peak memory 209944 kb
Host smart-87423548-48da-4aec-a59d-6c6322b8bc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843716504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.1843716504
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.3258760099
Short name T881
Test name
Test status
Simulation time 10551166 ps
CPU time 0.75 seconds
Started Jul 18 06:28:19 PM PDT 24
Finished Jul 18 06:28:27 PM PDT 24
Peak memory 205876 kb
Host smart-0fdee49d-c4ba-43b7-b04a-ca40389b1662
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258760099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.3258760099
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.694428532
Short name T653
Test name
Test status
Simulation time 294511059 ps
CPU time 3.12 seconds
Started Jul 18 06:28:22 PM PDT 24
Finished Jul 18 06:28:32 PM PDT 24
Peak memory 220392 kb
Host smart-1a40b68f-8a37-4074-920a-efa1368fbb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694428532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.694428532
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.3668199986
Short name T407
Test name
Test status
Simulation time 3587907580 ps
CPU time 15.03 seconds
Started Jul 18 06:28:22 PM PDT 24
Finished Jul 18 06:28:44 PM PDT 24
Peak memory 214184 kb
Host smart-de62d35b-f3ca-486f-8b5e-82d758c41158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668199986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.3668199986
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.71687850
Short name T656
Test name
Test status
Simulation time 147602215 ps
CPU time 5.78 seconds
Started Jul 18 06:28:20 PM PDT 24
Finished Jul 18 06:28:32 PM PDT 24
Peak memory 220664 kb
Host smart-8eb32b35-fcf6-463b-b3be-c3d39c0dea25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71687850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.71687850
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.78280106
Short name T814
Test name
Test status
Simulation time 100696656 ps
CPU time 2.21 seconds
Started Jul 18 06:28:21 PM PDT 24
Finished Jul 18 06:28:30 PM PDT 24
Peak memory 214068 kb
Host smart-da3f6672-93ba-4890-989f-3d502f8caf2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78280106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.78280106
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.1113887918
Short name T588
Test name
Test status
Simulation time 500980812 ps
CPU time 5.25 seconds
Started Jul 18 06:28:23 PM PDT 24
Finished Jul 18 06:28:35 PM PDT 24
Peak memory 210020 kb
Host smart-0d0c5406-6a08-4b50-9638-61d6280991c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113887918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.1113887918
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.1103466278
Short name T462
Test name
Test status
Simulation time 1720367917 ps
CPU time 6.44 seconds
Started Jul 18 06:28:18 PM PDT 24
Finished Jul 18 06:28:31 PM PDT 24
Peak memory 209912 kb
Host smart-d5e42ae0-4205-45a6-9bf0-b3c0ae64909c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103466278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.1103466278
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.300679819
Short name T352
Test name
Test status
Simulation time 131530349 ps
CPU time 1.87 seconds
Started Jul 18 06:28:19 PM PDT 24
Finished Jul 18 06:28:28 PM PDT 24
Peak memory 205860 kb
Host smart-897b5299-a8b4-450d-950e-f927a2f950f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300679819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.300679819
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.2655354782
Short name T444
Test name
Test status
Simulation time 312948428 ps
CPU time 5.06 seconds
Started Jul 18 06:28:20 PM PDT 24
Finished Jul 18 06:28:32 PM PDT 24
Peak memory 207556 kb
Host smart-968c9c61-a751-43dc-9942-99aca557b513
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655354782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2655354782
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.319851709
Short name T504
Test name
Test status
Simulation time 251329803 ps
CPU time 2.83 seconds
Started Jul 18 06:28:19 PM PDT 24
Finished Jul 18 06:28:28 PM PDT 24
Peak memory 206704 kb
Host smart-38776a73-4524-4932-93d2-60dd5ceb3651
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319851709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.319851709
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.1072195243
Short name T610
Test name
Test status
Simulation time 4193764599 ps
CPU time 44.34 seconds
Started Jul 18 06:28:19 PM PDT 24
Finished Jul 18 06:29:09 PM PDT 24
Peak memory 208660 kb
Host smart-78964b6e-5b12-4758-a010-ff0beb10be81
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072195243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.1072195243
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.3539613203
Short name T832
Test name
Test status
Simulation time 235647799 ps
CPU time 2.92 seconds
Started Jul 18 06:28:22 PM PDT 24
Finished Jul 18 06:28:31 PM PDT 24
Peak memory 214116 kb
Host smart-88c2a749-0aba-44f2-961a-62885d99cb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539613203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.3539613203
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.21772926
Short name T910
Test name
Test status
Simulation time 31965182 ps
CPU time 2.47 seconds
Started Jul 18 06:28:20 PM PDT 24
Finished Jul 18 06:28:29 PM PDT 24
Peak memory 206704 kb
Host smart-9a02707d-c1da-4bf2-a590-6cca83e67c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21772926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.21772926
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.1672373594
Short name T87
Test name
Test status
Simulation time 2421620806 ps
CPU time 23.69 seconds
Started Jul 18 06:28:21 PM PDT 24
Finished Jul 18 06:28:51 PM PDT 24
Peak memory 222324 kb
Host smart-f9892424-92eb-4a36-83a3-a0837eb4a790
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672373594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.1672373594
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2072292000
Short name T267
Test name
Test status
Simulation time 154703085 ps
CPU time 3.59 seconds
Started Jul 18 06:28:22 PM PDT 24
Finished Jul 18 06:28:32 PM PDT 24
Peak memory 208420 kb
Host smart-614f84e0-f037-441a-baf1-734ac8c21e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072292000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2072292000
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.2662971047
Short name T714
Test name
Test status
Simulation time 295057635 ps
CPU time 1.97 seconds
Started Jul 18 06:28:22 PM PDT 24
Finished Jul 18 06:28:30 PM PDT 24
Peak memory 209552 kb
Host smart-b4967475-1456-4a9b-8035-451e314b598f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662971047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.2662971047
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.20108269
Short name T864
Test name
Test status
Simulation time 33885182 ps
CPU time 0.77 seconds
Started Jul 18 06:26:53 PM PDT 24
Finished Jul 18 06:26:59 PM PDT 24
Peak memory 205856 kb
Host smart-1702798d-d60b-4868-8fbb-f8102d1bc8f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20108269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.20108269
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.4171501868
Short name T873
Test name
Test status
Simulation time 873016828 ps
CPU time 22.11 seconds
Started Jul 18 06:26:53 PM PDT 24
Finished Jul 18 06:27:21 PM PDT 24
Peak memory 214064 kb
Host smart-0723d60b-c343-4ed0-be71-5e8653bf99b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4171501868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.4171501868
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.3722685211
Short name T741
Test name
Test status
Simulation time 691122917 ps
CPU time 14.78 seconds
Started Jul 18 06:26:51 PM PDT 24
Finished Jul 18 06:27:10 PM PDT 24
Peak memory 209400 kb
Host smart-66a506aa-9c84-4e6a-8f95-5297d29ed174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722685211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.3722685211
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.3973622086
Short name T711
Test name
Test status
Simulation time 147442817 ps
CPU time 6.33 seconds
Started Jul 18 06:26:50 PM PDT 24
Finished Jul 18 06:27:00 PM PDT 24
Peak memory 214908 kb
Host smart-5719d876-931c-4958-8fbe-f5ea83a1a5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973622086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.3973622086
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.13529216
Short name T310
Test name
Test status
Simulation time 80618169 ps
CPU time 3.56 seconds
Started Jul 18 06:26:49 PM PDT 24
Finished Jul 18 06:26:56 PM PDT 24
Peak memory 220516 kb
Host smart-4af12967-8581-40da-8d1e-82ff2fded364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13529216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.13529216
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_random.2711966079
Short name T295
Test name
Test status
Simulation time 10700686461 ps
CPU time 58.13 seconds
Started Jul 18 06:26:50 PM PDT 24
Finished Jul 18 06:27:52 PM PDT 24
Peak memory 214212 kb
Host smart-daceea6d-a148-4eb8-ade8-20e011055825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711966079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.2711966079
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sideload.1499773711
Short name T709
Test name
Test status
Simulation time 37630367 ps
CPU time 2.4 seconds
Started Jul 18 06:26:54 PM PDT 24
Finished Jul 18 06:27:02 PM PDT 24
Peak memory 206704 kb
Host smart-9d05cd4d-b614-495b-a48a-bc8cc58f291e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499773711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.1499773711
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.1071289716
Short name T896
Test name
Test status
Simulation time 36172730 ps
CPU time 2.23 seconds
Started Jul 18 06:26:49 PM PDT 24
Finished Jul 18 06:26:55 PM PDT 24
Peak memory 206732 kb
Host smart-c68b4b7b-43af-4b73-938d-df82588b01de
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071289716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1071289716
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.1284155346
Short name T547
Test name
Test status
Simulation time 40194314 ps
CPU time 2.36 seconds
Started Jul 18 06:26:50 PM PDT 24
Finished Jul 18 06:26:56 PM PDT 24
Peak memory 207828 kb
Host smart-fe3bc423-cff3-457f-9a60-a5d913ebccab
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284155346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.1284155346
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.3910196218
Short name T203
Test name
Test status
Simulation time 682860815 ps
CPU time 21.12 seconds
Started Jul 18 06:26:51 PM PDT 24
Finished Jul 18 06:27:16 PM PDT 24
Peak memory 208484 kb
Host smart-e6abd125-198f-43d3-958e-b41f8fe1eedc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910196218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.3910196218
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.2392914325
Short name T471
Test name
Test status
Simulation time 1545143692 ps
CPU time 3.02 seconds
Started Jul 18 06:26:52 PM PDT 24
Finished Jul 18 06:27:00 PM PDT 24
Peak memory 208864 kb
Host smart-9da8b430-1ee8-4abc-a620-e8464883c2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392914325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.2392914325
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.4287264801
Short name T811
Test name
Test status
Simulation time 214357331 ps
CPU time 4.26 seconds
Started Jul 18 06:26:49 PM PDT 24
Finished Jul 18 06:26:56 PM PDT 24
Peak memory 206588 kb
Host smart-791b4215-262c-4f64-ac29-509bbef14165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287264801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.4287264801
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.4037164670
Short name T773
Test name
Test status
Simulation time 2035161335 ps
CPU time 16.56 seconds
Started Jul 18 06:26:51 PM PDT 24
Finished Jul 18 06:27:12 PM PDT 24
Peak memory 222360 kb
Host smart-55bd77c3-41b8-4290-9092-39c1f160348f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037164670 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.4037164670
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.2784442238
Short name T884
Test name
Test status
Simulation time 894488749 ps
CPU time 5 seconds
Started Jul 18 06:26:49 PM PDT 24
Finished Jul 18 06:26:57 PM PDT 24
Peak memory 208308 kb
Host smart-959edd0b-e41e-434e-acc2-268144a9ff9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784442238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.2784442238
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.2485204591
Short name T528
Test name
Test status
Simulation time 87934585 ps
CPU time 3.08 seconds
Started Jul 18 06:26:53 PM PDT 24
Finished Jul 18 06:27:02 PM PDT 24
Peak memory 209744 kb
Host smart-557a0650-5a5b-48a9-b332-1f792c743012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485204591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.2485204591
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.1068999840
Short name T592
Test name
Test status
Simulation time 10655928 ps
CPU time 0.75 seconds
Started Jul 18 06:28:13 PM PDT 24
Finished Jul 18 06:28:16 PM PDT 24
Peak memory 205832 kb
Host smart-155b16c6-8db6-4061-a02b-82c702181798
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068999840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.1068999840
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.2399843526
Short name T52
Test name
Test status
Simulation time 24002603 ps
CPU time 1.39 seconds
Started Jul 18 06:28:17 PM PDT 24
Finished Jul 18 06:28:24 PM PDT 24
Peak memory 207500 kb
Host smart-62fc2911-2392-467e-98e0-c5f84c32690a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399843526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.2399843526
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.716396147
Short name T672
Test name
Test status
Simulation time 110281204 ps
CPU time 2.35 seconds
Started Jul 18 06:28:17 PM PDT 24
Finished Jul 18 06:28:24 PM PDT 24
Peak memory 217104 kb
Host smart-5e2eea1a-b41f-4da5-bd18-beaea334d229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716396147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.716396147
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.2964840573
Short name T296
Test name
Test status
Simulation time 219960543 ps
CPU time 3.74 seconds
Started Jul 18 06:28:14 PM PDT 24
Finished Jul 18 06:28:20 PM PDT 24
Peak memory 214184 kb
Host smart-233599e3-4222-4d33-87be-07f1f494d379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964840573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.2964840573
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.3692750270
Short name T733
Test name
Test status
Simulation time 9945216266 ps
CPU time 22.93 seconds
Started Jul 18 06:28:19 PM PDT 24
Finished Jul 18 06:28:48 PM PDT 24
Peak memory 209180 kb
Host smart-9ccb6263-abff-49ce-9ba8-30a30486481c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692750270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.3692750270
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.1113170631
Short name T603
Test name
Test status
Simulation time 230349109 ps
CPU time 4.09 seconds
Started Jul 18 06:28:19 PM PDT 24
Finished Jul 18 06:28:30 PM PDT 24
Peak memory 208148 kb
Host smart-f01011ac-54e2-45af-b39d-b07768135a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113170631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1113170631
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.1656369748
Short name T727
Test name
Test status
Simulation time 78726287 ps
CPU time 2.47 seconds
Started Jul 18 06:28:19 PM PDT 24
Finished Jul 18 06:28:27 PM PDT 24
Peak memory 206756 kb
Host smart-2035c378-5f9f-49bd-9746-3fb193e9b5f0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656369748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1656369748
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.4050655481
Short name T750
Test name
Test status
Simulation time 52381505 ps
CPU time 2.96 seconds
Started Jul 18 06:28:16 PM PDT 24
Finished Jul 18 06:28:22 PM PDT 24
Peak memory 206672 kb
Host smart-327a8fff-b944-4c52-95d5-81f18e880f7f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050655481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.4050655481
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.4089080728
Short name T687
Test name
Test status
Simulation time 311391934 ps
CPU time 3.58 seconds
Started Jul 18 06:28:20 PM PDT 24
Finished Jul 18 06:28:30 PM PDT 24
Peak memory 206652 kb
Host smart-856257e3-f8ab-4f5d-a01e-75345b790e97
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089080728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.4089080728
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.4270451514
Short name T369
Test name
Test status
Simulation time 242797806 ps
CPU time 3.21 seconds
Started Jul 18 06:28:14 PM PDT 24
Finished Jul 18 06:28:19 PM PDT 24
Peak memory 218228 kb
Host smart-e75d6de1-c7a9-4993-83a6-3c6ac88a27c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270451514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.4270451514
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.3707288437
Short name T472
Test name
Test status
Simulation time 138215046 ps
CPU time 2.18 seconds
Started Jul 18 06:28:20 PM PDT 24
Finished Jul 18 06:28:29 PM PDT 24
Peak memory 206608 kb
Host smart-df0c3d1b-2fdf-4048-bfc5-2435f6bda718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707288437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.3707288437
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.3321203708
Short name T265
Test name
Test status
Simulation time 582514868 ps
CPU time 5.03 seconds
Started Jul 18 06:28:15 PM PDT 24
Finished Jul 18 06:28:22 PM PDT 24
Peak memory 214820 kb
Host smart-62888657-169d-4dde-a907-9d953ab9fe46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321203708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.3321203708
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.2055882046
Short name T59
Test name
Test status
Simulation time 2462740510 ps
CPU time 21.34 seconds
Started Jul 18 06:28:14 PM PDT 24
Finished Jul 18 06:28:37 PM PDT 24
Peak memory 222584 kb
Host smart-c6697c03-e3f7-40fc-9e4a-2eab7ef5be6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055882046 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.2055882046
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.2308099017
Short name T390
Test name
Test status
Simulation time 275906097 ps
CPU time 3.78 seconds
Started Jul 18 06:28:14 PM PDT 24
Finished Jul 18 06:28:20 PM PDT 24
Peak memory 209176 kb
Host smart-2f7cc594-6c7e-4200-88f2-7f7c56e6cb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308099017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.2308099017
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.3910974135
Short name T400
Test name
Test status
Simulation time 60512267 ps
CPU time 2.29 seconds
Started Jul 18 06:28:14 PM PDT 24
Finished Jul 18 06:28:18 PM PDT 24
Peak memory 210212 kb
Host smart-8dee4f6b-d0bc-4a42-9851-43097ec4d93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910974135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3910974135
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.998484910
Short name T198
Test name
Test status
Simulation time 97584367 ps
CPU time 0.83 seconds
Started Jul 18 06:28:14 PM PDT 24
Finished Jul 18 06:28:17 PM PDT 24
Peak memory 205832 kb
Host smart-f8e2fc3f-3ee5-40d8-bebf-545a8421a6b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998484910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.998484910
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.1688960375
Short name T432
Test name
Test status
Simulation time 2533333589 ps
CPU time 33.97 seconds
Started Jul 18 06:28:19 PM PDT 24
Finished Jul 18 06:29:00 PM PDT 24
Peak memory 214888 kb
Host smart-5c69ded5-5f4a-441e-ab4d-a6d1523c3d34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1688960375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.1688960375
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.448108945
Short name T634
Test name
Test status
Simulation time 53746612 ps
CPU time 2.59 seconds
Started Jul 18 06:28:18 PM PDT 24
Finished Jul 18 06:28:26 PM PDT 24
Peak memory 220288 kb
Host smart-e721aac9-8349-437d-b5a0-996046d3eecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448108945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.448108945
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.119648381
Short name T679
Test name
Test status
Simulation time 231526046 ps
CPU time 3.45 seconds
Started Jul 18 06:28:19 PM PDT 24
Finished Jul 18 06:28:29 PM PDT 24
Peak memory 208392 kb
Host smart-4c0fa0cd-38c5-4378-89c4-35d95f6ffde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119648381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.119648381
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.1829948141
Short name T683
Test name
Test status
Simulation time 109767381 ps
CPU time 3.63 seconds
Started Jul 18 06:28:19 PM PDT 24
Finished Jul 18 06:28:29 PM PDT 24
Peak memory 214088 kb
Host smart-2ba6fcac-487c-49aa-a8c1-dc4e6bebbe72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829948141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.1829948141
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.4088369003
Short name T341
Test name
Test status
Simulation time 327085755 ps
CPU time 2.93 seconds
Started Jul 18 06:28:16 PM PDT 24
Finished Jul 18 06:28:23 PM PDT 24
Peak memory 214024 kb
Host smart-96fa255f-e415-466c-a7c3-febf6dc3e5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088369003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.4088369003
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.1959930959
Short name T534
Test name
Test status
Simulation time 196152415 ps
CPU time 3.64 seconds
Started Jul 18 06:28:17 PM PDT 24
Finished Jul 18 06:28:24 PM PDT 24
Peak memory 209236 kb
Host smart-8e9fb411-3ad8-4417-a0ab-68d70c01cd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959930959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.1959930959
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.1005469897
Short name T138
Test name
Test status
Simulation time 416743926 ps
CPU time 6.44 seconds
Started Jul 18 06:28:18 PM PDT 24
Finished Jul 18 06:28:30 PM PDT 24
Peak memory 208992 kb
Host smart-742b0f06-583d-4078-94d2-43111472d633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005469897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.1005469897
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.3353349257
Short name T681
Test name
Test status
Simulation time 112299358 ps
CPU time 3.2 seconds
Started Jul 18 06:28:16 PM PDT 24
Finished Jul 18 06:28:22 PM PDT 24
Peak memory 205864 kb
Host smart-668d8281-2a07-40cd-a3e3-95df21f6bcda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353349257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.3353349257
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.260719397
Short name T230
Test name
Test status
Simulation time 83411780 ps
CPU time 3.12 seconds
Started Jul 18 06:28:19 PM PDT 24
Finished Jul 18 06:28:29 PM PDT 24
Peak memory 205376 kb
Host smart-b3a991b7-b810-4e95-9af7-fa53af88ee47
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260719397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.260719397
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.1826001280
Short name T526
Test name
Test status
Simulation time 185132184 ps
CPU time 7.5 seconds
Started Jul 18 06:28:18 PM PDT 24
Finished Jul 18 06:28:31 PM PDT 24
Peak memory 207696 kb
Host smart-db30c0a9-0437-4dd9-93f9-50584ced90fb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826001280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.1826001280
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.2468587749
Short name T333
Test name
Test status
Simulation time 313928289 ps
CPU time 2.67 seconds
Started Jul 18 06:28:17 PM PDT 24
Finished Jul 18 06:28:23 PM PDT 24
Peak memory 206792 kb
Host smart-b15d4625-5186-4939-9255-bd425f2bf6cb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468587749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.2468587749
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.1346639322
Short name T551
Test name
Test status
Simulation time 32592113 ps
CPU time 2.28 seconds
Started Jul 18 06:28:18 PM PDT 24
Finished Jul 18 06:28:25 PM PDT 24
Peak memory 215036 kb
Host smart-9840768a-b574-4f31-92c8-fadacc6b79ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346639322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.1346639322
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.3470190207
Short name T648
Test name
Test status
Simulation time 281088226 ps
CPU time 3.13 seconds
Started Jul 18 06:28:18 PM PDT 24
Finished Jul 18 06:28:27 PM PDT 24
Peak memory 206656 kb
Host smart-51dfd90e-7722-4768-bd94-b932b28ea300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470190207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3470190207
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.850967214
Short name T132
Test name
Test status
Simulation time 146136203 ps
CPU time 10.91 seconds
Started Jul 18 06:28:21 PM PDT 24
Finished Jul 18 06:28:39 PM PDT 24
Peak memory 222336 kb
Host smart-02c99871-b9c1-442e-aacc-3a062a96656f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850967214 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.850967214
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.3768426786
Short name T713
Test name
Test status
Simulation time 2066696481 ps
CPU time 48.66 seconds
Started Jul 18 06:28:19 PM PDT 24
Finished Jul 18 06:29:15 PM PDT 24
Peak memory 209964 kb
Host smart-8db84057-f903-4d74-8175-00c94268a4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768426786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.3768426786
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.388037241
Short name T779
Test name
Test status
Simulation time 49858340 ps
CPU time 2.84 seconds
Started Jul 18 06:28:19 PM PDT 24
Finished Jul 18 06:28:29 PM PDT 24
Peak memory 209960 kb
Host smart-9b20234d-99b1-4843-9c82-4a33973eda3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388037241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.388037241
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.3604700513
Short name T566
Test name
Test status
Simulation time 10469905 ps
CPU time 0.85 seconds
Started Jul 18 06:28:28 PM PDT 24
Finished Jul 18 06:28:36 PM PDT 24
Peak memory 205852 kb
Host smart-e4233d18-0e70-4b1b-a37d-cf3049d285a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604700513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3604700513
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1047486592
Short name T423
Test name
Test status
Simulation time 82734983 ps
CPU time 3.35 seconds
Started Jul 18 06:28:30 PM PDT 24
Finished Jul 18 06:28:40 PM PDT 24
Peak memory 214860 kb
Host smart-dd56993c-d8ea-4464-b753-2a3655b1adfa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1047486592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1047486592
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2034792581
Short name T76
Test name
Test status
Simulation time 91379829 ps
CPU time 3.89 seconds
Started Jul 18 06:28:29 PM PDT 24
Finished Jul 18 06:28:40 PM PDT 24
Peak memory 210592 kb
Host smart-7bcaf2a9-75b2-4c01-9e57-39c138a1d18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034792581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2034792581
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.196782439
Short name T339
Test name
Test status
Simulation time 293410282 ps
CPU time 3.19 seconds
Started Jul 18 06:28:28 PM PDT 24
Finished Jul 18 06:28:38 PM PDT 24
Peak memory 214044 kb
Host smart-1b70d731-1b2c-4c52-9b66-26576a0e0d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196782439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.196782439
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.2172488001
Short name T101
Test name
Test status
Simulation time 53536770 ps
CPU time 2.42 seconds
Started Jul 18 06:28:28 PM PDT 24
Finished Jul 18 06:28:38 PM PDT 24
Peak memory 214024 kb
Host smart-221cce00-5d94-434d-94ce-18d6bd0df2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172488001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2172488001
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_random.2348122993
Short name T826
Test name
Test status
Simulation time 415188822 ps
CPU time 4.8 seconds
Started Jul 18 06:28:31 PM PDT 24
Finished Jul 18 06:28:42 PM PDT 24
Peak memory 208568 kb
Host smart-fea175e6-6519-4184-b779-de702bf49546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348122993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.2348122993
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.1846345731
Short name T781
Test name
Test status
Simulation time 29496610 ps
CPU time 1.88 seconds
Started Jul 18 06:28:19 PM PDT 24
Finished Jul 18 06:28:28 PM PDT 24
Peak memory 208312 kb
Host smart-b73f6ef7-c859-4659-9641-6350a85d692f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846345731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1846345731
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.789253069
Short name T612
Test name
Test status
Simulation time 78590740 ps
CPU time 2.4 seconds
Started Jul 18 06:28:16 PM PDT 24
Finished Jul 18 06:28:21 PM PDT 24
Peak memory 206788 kb
Host smart-24dac0e7-635c-4f40-874f-65f77bfb3384
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789253069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.789253069
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.2876401709
Short name T524
Test name
Test status
Simulation time 91209474 ps
CPU time 4.16 seconds
Started Jul 18 06:28:22 PM PDT 24
Finished Jul 18 06:28:33 PM PDT 24
Peak memory 206724 kb
Host smart-c9b4abba-28e7-4e10-8ce3-40f4112b5f61
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876401709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.2876401709
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.3666290757
Short name T416
Test name
Test status
Simulation time 55017916 ps
CPU time 2.76 seconds
Started Jul 18 06:28:23 PM PDT 24
Finished Jul 18 06:28:33 PM PDT 24
Peak memory 206708 kb
Host smart-eb59eb7f-c592-49da-a327-23df8ecbf735
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666290757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.3666290757
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.2165311416
Short name T790
Test name
Test status
Simulation time 31377580 ps
CPU time 1.98 seconds
Started Jul 18 06:28:32 PM PDT 24
Finished Jul 18 06:28:39 PM PDT 24
Peak memory 218104 kb
Host smart-efc18b3d-f1df-425c-9c10-87d922be6e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165311416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.2165311416
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.2310042548
Short name T724
Test name
Test status
Simulation time 80844764 ps
CPU time 3.23 seconds
Started Jul 18 06:28:18 PM PDT 24
Finished Jul 18 06:28:26 PM PDT 24
Peak memory 208144 kb
Host smart-fee6db93-02b3-422f-b0ea-26cea3ac027a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310042548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.2310042548
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.3968158379
Short name T761
Test name
Test status
Simulation time 97278849 ps
CPU time 4.48 seconds
Started Jul 18 06:28:32 PM PDT 24
Finished Jul 18 06:28:42 PM PDT 24
Peak memory 214064 kb
Host smart-3e9940e7-3664-4cbc-a4c6-83fa2eaf12be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968158379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.3968158379
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.1599824214
Short name T703
Test name
Test status
Simulation time 204985407 ps
CPU time 2.22 seconds
Started Jul 18 06:28:25 PM PDT 24
Finished Jul 18 06:28:35 PM PDT 24
Peak memory 209848 kb
Host smart-645b0db8-7ba1-46b9-b467-df1f7a72d44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599824214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.1599824214
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.3065258230
Short name T862
Test name
Test status
Simulation time 19110374 ps
CPU time 0.71 seconds
Started Jul 18 06:28:28 PM PDT 24
Finished Jul 18 06:28:36 PM PDT 24
Peak memory 205860 kb
Host smart-9e9a3620-0d6d-4505-9f47-767e15778ba9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065258230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.3065258230
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.627257353
Short name T871
Test name
Test status
Simulation time 63261804 ps
CPU time 3.14 seconds
Started Jul 18 06:28:33 PM PDT 24
Finished Jul 18 06:28:41 PM PDT 24
Peak memory 222540 kb
Host smart-333ace0a-3bbc-42a5-af86-63cc2d41fd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627257353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.627257353
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.3639222856
Short name T415
Test name
Test status
Simulation time 38243357 ps
CPU time 2.58 seconds
Started Jul 18 06:28:26 PM PDT 24
Finished Jul 18 06:28:36 PM PDT 24
Peak memory 210016 kb
Host smart-9ae2ce09-11fe-4f9a-9584-26f3516f48ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639222856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.3639222856
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.2345884392
Short name T819
Test name
Test status
Simulation time 340313911 ps
CPU time 4.17 seconds
Started Jul 18 06:28:28 PM PDT 24
Finished Jul 18 06:28:39 PM PDT 24
Peak memory 214108 kb
Host smart-0cab674c-b8bf-4329-91e1-50abaf5dfc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345884392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.2345884392
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.1941005041
Short name T557
Test name
Test status
Simulation time 104328826 ps
CPU time 3.13 seconds
Started Jul 18 06:28:26 PM PDT 24
Finished Jul 18 06:28:37 PM PDT 24
Peak memory 214004 kb
Host smart-08279af3-8b8e-495e-a165-1d20a944c36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941005041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1941005041
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.3971011785
Short name T604
Test name
Test status
Simulation time 882781194 ps
CPU time 6.23 seconds
Started Jul 18 06:28:26 PM PDT 24
Finished Jul 18 06:28:39 PM PDT 24
Peak memory 222204 kb
Host smart-657473fc-1b1f-49f5-bdf8-4546941f7d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971011785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.3971011785
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.1808118063
Short name T569
Test name
Test status
Simulation time 382820963 ps
CPU time 3.97 seconds
Started Jul 18 06:28:30 PM PDT 24
Finished Jul 18 06:28:40 PM PDT 24
Peak memory 207204 kb
Host smart-69e335cd-5dff-4de3-b702-77d8410ef960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808118063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.1808118063
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.475054002
Short name T192
Test name
Test status
Simulation time 152172767 ps
CPU time 2.33 seconds
Started Jul 18 06:28:27 PM PDT 24
Finished Jul 18 06:28:37 PM PDT 24
Peak memory 206664 kb
Host smart-2258d7a9-1fbf-44ab-8e3f-637f8d9d7c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475054002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.475054002
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1889676057
Short name T795
Test name
Test status
Simulation time 28241552 ps
CPU time 2.05 seconds
Started Jul 18 06:28:29 PM PDT 24
Finished Jul 18 06:28:38 PM PDT 24
Peak memory 208264 kb
Host smart-a61f9496-9697-43b4-a099-c274f7516a45
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889676057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1889676057
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.1566176332
Short name T565
Test name
Test status
Simulation time 114925881 ps
CPU time 3.06 seconds
Started Jul 18 06:28:30 PM PDT 24
Finished Jul 18 06:28:39 PM PDT 24
Peak memory 205868 kb
Host smart-7fa77bed-e57c-4418-a5a9-94ef02ffbdb9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566176332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.1566176332
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3922797459
Short name T326
Test name
Test status
Simulation time 32310441 ps
CPU time 2.4 seconds
Started Jul 18 06:28:28 PM PDT 24
Finished Jul 18 06:28:38 PM PDT 24
Peak memory 208624 kb
Host smart-47d9ba34-b64b-4496-9c63-075c88219a8a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922797459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3922797459
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.623021361
Short name T641
Test name
Test status
Simulation time 377334178 ps
CPU time 2.66 seconds
Started Jul 18 06:28:28 PM PDT 24
Finished Jul 18 06:28:38 PM PDT 24
Peak memory 206592 kb
Host smart-2ce7e7b2-00fb-4db1-b034-3f868476d416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623021361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.623021361
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.878376117
Short name T217
Test name
Test status
Simulation time 4293753057 ps
CPU time 23.63 seconds
Started Jul 18 06:28:29 PM PDT 24
Finished Jul 18 06:29:00 PM PDT 24
Peak memory 208004 kb
Host smart-60b69ade-c725-440c-be7a-bff82241ddab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878376117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.878376117
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.2781737424
Short name T190
Test name
Test status
Simulation time 9791268966 ps
CPU time 227.45 seconds
Started Jul 18 06:28:28 PM PDT 24
Finished Jul 18 06:32:23 PM PDT 24
Peak memory 216424 kb
Host smart-b9bcb512-4c5c-42c4-8ab8-74ee83619eee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781737424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.2781737424
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.1432634593
Short name T717
Test name
Test status
Simulation time 5947683127 ps
CPU time 64.78 seconds
Started Jul 18 06:28:27 PM PDT 24
Finished Jul 18 06:29:39 PM PDT 24
Peak memory 209232 kb
Host smart-d27ff038-c109-46ae-89ba-49b472ef8070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432634593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.1432634593
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.4272637044
Short name T184
Test name
Test status
Simulation time 156924592 ps
CPU time 3.31 seconds
Started Jul 18 06:28:27 PM PDT 24
Finished Jul 18 06:28:38 PM PDT 24
Peak memory 210508 kb
Host smart-0767b3fd-c9f4-4c1d-9b9f-306c926c503c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272637044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.4272637044
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.2012209640
Short name T111
Test name
Test status
Simulation time 22953192 ps
CPU time 0.77 seconds
Started Jul 18 06:28:43 PM PDT 24
Finished Jul 18 06:28:45 PM PDT 24
Peak memory 205788 kb
Host smart-a768df40-c1c0-4e1b-9a50-56b8afe97d35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012209640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.2012209640
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.1139580055
Short name T383
Test name
Test status
Simulation time 38296985 ps
CPU time 3.08 seconds
Started Jul 18 06:28:26 PM PDT 24
Finished Jul 18 06:28:36 PM PDT 24
Peak memory 215176 kb
Host smart-88919d25-157b-4c6c-b983-f1b134666fd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1139580055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.1139580055
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.1149613956
Short name T508
Test name
Test status
Simulation time 453403073 ps
CPU time 1.74 seconds
Started Jul 18 06:28:28 PM PDT 24
Finished Jul 18 06:28:36 PM PDT 24
Peak memory 208808 kb
Host smart-35bd45b3-b890-4f58-abce-f1cee1384e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149613956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.1149613956
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.1672037430
Short name T627
Test name
Test status
Simulation time 121333119 ps
CPU time 1.93 seconds
Started Jul 18 06:28:28 PM PDT 24
Finished Jul 18 06:28:37 PM PDT 24
Peak memory 207008 kb
Host smart-7c8fd91d-a16a-43a0-b602-555bb8d09c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672037430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.1672037430
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.1646144041
Short name T538
Test name
Test status
Simulation time 59737542 ps
CPU time 3.59 seconds
Started Jul 18 06:28:29 PM PDT 24
Finished Jul 18 06:28:39 PM PDT 24
Peak memory 208196 kb
Host smart-b88ff87c-c840-4690-a028-beedc41933af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646144041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.1646144041
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.1398109
Short name T643
Test name
Test status
Simulation time 186396025 ps
CPU time 5.38 seconds
Started Jul 18 06:28:32 PM PDT 24
Finished Jul 18 06:28:42 PM PDT 24
Peak memory 208852 kb
Host smart-5f3f6fb0-e671-49db-84af-b7328e962a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.1398109
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.1984137481
Short name T4
Test name
Test status
Simulation time 132207832 ps
CPU time 5.2 seconds
Started Jul 18 06:28:30 PM PDT 24
Finished Jul 18 06:28:42 PM PDT 24
Peak memory 207236 kb
Host smart-b68e128d-e266-4ff1-a13e-010e8bb05c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984137481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.1984137481
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.2490842179
Short name T674
Test name
Test status
Simulation time 7058298206 ps
CPU time 41.11 seconds
Started Jul 18 06:28:26 PM PDT 24
Finished Jul 18 06:29:14 PM PDT 24
Peak memory 208992 kb
Host smart-3026c9a2-ea89-4e9a-a10c-61b49103e99e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490842179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.2490842179
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.3009221885
Short name T699
Test name
Test status
Simulation time 39128568 ps
CPU time 2.86 seconds
Started Jul 18 06:28:27 PM PDT 24
Finished Jul 18 06:28:37 PM PDT 24
Peak memory 208460 kb
Host smart-ff5c3d3e-8164-4fa1-856d-bc225c388021
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009221885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.3009221885
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.2632294696
Short name T90
Test name
Test status
Simulation time 1857270520 ps
CPU time 9.81 seconds
Started Jul 18 06:28:30 PM PDT 24
Finished Jul 18 06:28:46 PM PDT 24
Peak memory 206736 kb
Host smart-2bfe2ddb-7a53-4832-a695-ad5d6f104389
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632294696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.2632294696
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.4053232258
Short name T630
Test name
Test status
Simulation time 34528540 ps
CPU time 2.14 seconds
Started Jul 18 06:28:27 PM PDT 24
Finished Jul 18 06:28:36 PM PDT 24
Peak memory 208464 kb
Host smart-146cb228-a16b-4877-a48d-c4cbcaee5c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053232258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.4053232258
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.490452235
Short name T879
Test name
Test status
Simulation time 125421774 ps
CPU time 2.85 seconds
Started Jul 18 06:28:28 PM PDT 24
Finished Jul 18 06:28:38 PM PDT 24
Peak memory 208304 kb
Host smart-06abba22-70cb-4fba-a30f-16b3e2334c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490452235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.490452235
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.279044883
Short name T655
Test name
Test status
Simulation time 533995380 ps
CPU time 5.17 seconds
Started Jul 18 06:28:44 PM PDT 24
Finished Jul 18 06:28:51 PM PDT 24
Peak memory 207640 kb
Host smart-f3d1ec4d-bc89-435d-9f76-842dabbf75fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279044883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.279044883
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.1042666337
Short name T754
Test name
Test status
Simulation time 1225128935 ps
CPU time 8.74 seconds
Started Jul 18 06:28:27 PM PDT 24
Finished Jul 18 06:28:43 PM PDT 24
Peak memory 208836 kb
Host smart-2a15bcc3-f46a-4993-812e-ac530d16482f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042666337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1042666337
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.2305181166
Short name T201
Test name
Test status
Simulation time 982257282 ps
CPU time 3.09 seconds
Started Jul 18 06:28:46 PM PDT 24
Finished Jul 18 06:28:51 PM PDT 24
Peak memory 210392 kb
Host smart-3f735942-89f4-49d7-a48b-2e061b76c706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305181166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.2305181166
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.820797788
Short name T561
Test name
Test status
Simulation time 100825271 ps
CPU time 0.72 seconds
Started Jul 18 06:28:42 PM PDT 24
Finished Jul 18 06:28:44 PM PDT 24
Peak memory 205856 kb
Host smart-63929255-7fce-4ddd-81e1-59818d9ba247
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820797788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.820797788
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.2429534511
Short name T139
Test name
Test status
Simulation time 688238696 ps
CPU time 9.79 seconds
Started Jul 18 06:28:41 PM PDT 24
Finished Jul 18 06:28:53 PM PDT 24
Peak memory 215312 kb
Host smart-779f6ceb-2c87-4c53-bd74-e38b0ecd5b34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2429534511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.2429534511
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.2341090664
Short name T86
Test name
Test status
Simulation time 340176293 ps
CPU time 1.96 seconds
Started Jul 18 06:28:41 PM PDT 24
Finished Jul 18 06:28:44 PM PDT 24
Peak memory 207240 kb
Host smart-8ae61ff6-0cb3-4e9f-8727-cf29c5003621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341090664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.2341090664
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.4029771154
Short name T536
Test name
Test status
Simulation time 102120798 ps
CPU time 3.63 seconds
Started Jul 18 06:28:44 PM PDT 24
Finished Jul 18 06:28:49 PM PDT 24
Peak memory 214012 kb
Host smart-f0c6673d-e9c3-4c41-9fd9-e877929ddfba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029771154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.4029771154
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.442943543
Short name T663
Test name
Test status
Simulation time 217407820 ps
CPU time 3.41 seconds
Started Jul 18 06:28:43 PM PDT 24
Finished Jul 18 06:28:48 PM PDT 24
Peak memory 213980 kb
Host smart-c753a261-5d3a-45e4-b0dc-125d5670ef21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442943543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.442943543
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.3738327195
Short name T258
Test name
Test status
Simulation time 621666509 ps
CPU time 5.38 seconds
Started Jul 18 06:28:43 PM PDT 24
Finished Jul 18 06:28:50 PM PDT 24
Peak memory 214232 kb
Host smart-302af52c-ce78-410c-a005-7aff40c4dcf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738327195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.3738327195
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.835350253
Short name T358
Test name
Test status
Simulation time 714931021 ps
CPU time 5.99 seconds
Started Jul 18 06:28:41 PM PDT 24
Finished Jul 18 06:28:49 PM PDT 24
Peak memory 207352 kb
Host smart-b42220bb-9af3-4aa9-8007-ca7d07b079fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835350253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.835350253
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.708269155
Short name T793
Test name
Test status
Simulation time 175597558 ps
CPU time 4.98 seconds
Started Jul 18 06:28:43 PM PDT 24
Finished Jul 18 06:28:49 PM PDT 24
Peak memory 208016 kb
Host smart-dfff12ff-ca2f-4a37-85a1-d59ec4a9588b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708269155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.708269155
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.2265851318
Short name T527
Test name
Test status
Simulation time 408391303 ps
CPU time 3.2 seconds
Started Jul 18 06:28:42 PM PDT 24
Finished Jul 18 06:28:47 PM PDT 24
Peak memory 206772 kb
Host smart-ab644559-2bda-4f0a-8c9a-bf630bff3bc0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265851318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.2265851318
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2089348378
Short name T447
Test name
Test status
Simulation time 24225325728 ps
CPU time 86.64 seconds
Started Jul 18 06:28:46 PM PDT 24
Finished Jul 18 06:30:14 PM PDT 24
Peak memory 208340 kb
Host smart-63695b49-f70f-4c9e-8aec-a7277efc4649
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089348378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2089348378
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1800972418
Short name T729
Test name
Test status
Simulation time 98020656 ps
CPU time 3.58 seconds
Started Jul 18 06:28:42 PM PDT 24
Finished Jul 18 06:28:47 PM PDT 24
Peak memory 206744 kb
Host smart-1a5a3072-59a8-4225-9305-c68904807844
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800972418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1800972418
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.3749508397
Short name T708
Test name
Test status
Simulation time 117731045 ps
CPU time 1.83 seconds
Started Jul 18 06:28:45 PM PDT 24
Finished Jul 18 06:28:48 PM PDT 24
Peak memory 207472 kb
Host smart-535529cc-d687-410d-ad2a-1604f3d890f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749508397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.3749508397
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.2246598713
Short name T746
Test name
Test status
Simulation time 109027376 ps
CPU time 4.08 seconds
Started Jul 18 06:28:43 PM PDT 24
Finished Jul 18 06:28:49 PM PDT 24
Peak memory 208404 kb
Host smart-7540ea9f-392d-4797-afb6-4897424796ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246598713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.2246598713
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.3820669936
Short name T247
Test name
Test status
Simulation time 2317729386 ps
CPU time 71.21 seconds
Started Jul 18 06:28:42 PM PDT 24
Finished Jul 18 06:29:55 PM PDT 24
Peak memory 220644 kb
Host smart-8cd66b29-6d67-43ab-8f46-323866fe60f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820669936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.3820669936
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.4066382373
Short name T380
Test name
Test status
Simulation time 663126816 ps
CPU time 5.01 seconds
Started Jul 18 06:28:44 PM PDT 24
Finished Jul 18 06:28:50 PM PDT 24
Peak memory 207928 kb
Host smart-8967f98c-a045-4115-826e-0c3552d0dd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066382373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.4066382373
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.2088927903
Short name T577
Test name
Test status
Simulation time 41821265 ps
CPU time 1.46 seconds
Started Jul 18 06:28:41 PM PDT 24
Finished Jul 18 06:28:44 PM PDT 24
Peak memory 209568 kb
Host smart-e63d5c0a-3e88-459d-b71d-c6713134e461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088927903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.2088927903
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.129091477
Short name T457
Test name
Test status
Simulation time 52435557 ps
CPU time 0.79 seconds
Started Jul 18 06:28:57 PM PDT 24
Finished Jul 18 06:28:59 PM PDT 24
Peak memory 205860 kb
Host smart-0eaf9ee9-129f-42e6-a9a0-d6e8273f23f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129091477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.129091477
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.3043546173
Short name T880
Test name
Test status
Simulation time 73194159 ps
CPU time 3.57 seconds
Started Jul 18 06:29:01 PM PDT 24
Finished Jul 18 06:29:07 PM PDT 24
Peak memory 217060 kb
Host smart-220a9b57-09f1-4144-9f2d-7c34d5f8fe36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043546173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.3043546173
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.2410867671
Short name T640
Test name
Test status
Simulation time 37868468 ps
CPU time 1.63 seconds
Started Jul 18 06:29:01 PM PDT 24
Finished Jul 18 06:29:06 PM PDT 24
Peak memory 218388 kb
Host smart-1bd7fc8d-da20-4448-919a-9f72b33bfddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410867671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2410867671
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.3582585123
Short name T321
Test name
Test status
Simulation time 189315329 ps
CPU time 7.32 seconds
Started Jul 18 06:28:59 PM PDT 24
Finished Jul 18 06:29:10 PM PDT 24
Peak memory 222188 kb
Host smart-8913dd3d-b6f2-41ee-bb1d-abdfb14500ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582585123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.3582585123
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.3908841332
Short name T614
Test name
Test status
Simulation time 257750346 ps
CPU time 3.3 seconds
Started Jul 18 06:29:02 PM PDT 24
Finished Jul 18 06:29:08 PM PDT 24
Peak memory 214060 kb
Host smart-836746f1-d057-451d-a2c8-ee9adaf67867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908841332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.3908841332
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.703826174
Short name T738
Test name
Test status
Simulation time 552416178 ps
CPU time 6.1 seconds
Started Jul 18 06:29:01 PM PDT 24
Finished Jul 18 06:29:10 PM PDT 24
Peak memory 207040 kb
Host smart-e95e2e01-63bc-499d-a2b7-13de82f77e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703826174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.703826174
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1052122835
Short name T95
Test name
Test status
Simulation time 135072060 ps
CPU time 3 seconds
Started Jul 18 06:28:43 PM PDT 24
Finished Jul 18 06:28:48 PM PDT 24
Peak memory 206496 kb
Host smart-00024e3e-4a00-4efe-a043-eb177123cd1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052122835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1052122835
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2621683291
Short name T273
Test name
Test status
Simulation time 219573770 ps
CPU time 3.19 seconds
Started Jul 18 06:29:00 PM PDT 24
Finished Jul 18 06:29:06 PM PDT 24
Peak memory 208628 kb
Host smart-b76bda7e-f549-4b80-88f2-c6b7d579e380
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621683291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2621683291
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.2468588035
Short name T728
Test name
Test status
Simulation time 1213857478 ps
CPU time 9.23 seconds
Started Jul 18 06:28:42 PM PDT 24
Finished Jul 18 06:28:53 PM PDT 24
Peak memory 208252 kb
Host smart-005c360d-9d9a-4387-9689-51c8c6cb15b9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468588035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.2468588035
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.2542033067
Short name T841
Test name
Test status
Simulation time 89868893 ps
CPU time 3.16 seconds
Started Jul 18 06:28:58 PM PDT 24
Finished Jul 18 06:29:04 PM PDT 24
Peak memory 206724 kb
Host smart-d11f42ea-fd42-4435-b4b9-2c8527e769e8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542033067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.2542033067
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.925156620
Short name T890
Test name
Test status
Simulation time 311360727 ps
CPU time 2.45 seconds
Started Jul 18 06:28:59 PM PDT 24
Finished Jul 18 06:29:05 PM PDT 24
Peak memory 215308 kb
Host smart-4cf01a03-c8e1-4d66-816f-753b7fac0d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925156620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.925156620
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.2028055615
Short name T734
Test name
Test status
Simulation time 112766253 ps
CPU time 3.39 seconds
Started Jul 18 06:28:45 PM PDT 24
Finished Jul 18 06:28:49 PM PDT 24
Peak memory 207200 kb
Host smart-a8ace4f2-247a-4aeb-a5af-bd1efd39d932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028055615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.2028055615
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.3031374068
Short name T889
Test name
Test status
Simulation time 250528542 ps
CPU time 12.98 seconds
Started Jul 18 06:28:57 PM PDT 24
Finished Jul 18 06:29:11 PM PDT 24
Peak memory 215704 kb
Host smart-94ed6f6a-2740-46a5-bbec-ad3b0bdd7305
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031374068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.3031374068
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.3663700175
Short name T7
Test name
Test status
Simulation time 273234041 ps
CPU time 12.27 seconds
Started Jul 18 06:28:59 PM PDT 24
Finished Jul 18 06:29:14 PM PDT 24
Peak memory 222352 kb
Host smart-8de520b7-7c62-4514-923e-3b0f0e13c1ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663700175 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.3663700175
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.4123297430
Short name T317
Test name
Test status
Simulation time 3861425030 ps
CPU time 48.09 seconds
Started Jul 18 06:29:00 PM PDT 24
Finished Jul 18 06:29:51 PM PDT 24
Peak memory 218352 kb
Host smart-eac8fd40-62f8-4ae9-9cb0-5a81f1286bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123297430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.4123297430
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.1551656731
Short name T489
Test name
Test status
Simulation time 35023552 ps
CPU time 1.79 seconds
Started Jul 18 06:28:58 PM PDT 24
Finished Jul 18 06:29:03 PM PDT 24
Peak memory 209728 kb
Host smart-58025d05-ff3d-49ac-96a2-23826c1ae51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551656731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.1551656731
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.1070219665
Short name T468
Test name
Test status
Simulation time 16279540 ps
CPU time 0.98 seconds
Started Jul 18 06:29:00 PM PDT 24
Finished Jul 18 06:29:04 PM PDT 24
Peak memory 205904 kb
Host smart-1fff13aa-aa67-49e9-9242-b499fa2e15c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070219665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.1070219665
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.2594852739
Short name T420
Test name
Test status
Simulation time 117329727 ps
CPU time 2.7 seconds
Started Jul 18 06:29:01 PM PDT 24
Finished Jul 18 06:29:07 PM PDT 24
Peak memory 214176 kb
Host smart-9f1222a0-fc81-46a1-a4ce-7d22dccb69a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2594852739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.2594852739
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.3216268077
Short name T755
Test name
Test status
Simulation time 158672046 ps
CPU time 3.25 seconds
Started Jul 18 06:28:59 PM PDT 24
Finished Jul 18 06:29:04 PM PDT 24
Peak memory 215936 kb
Host smart-5f686195-98d4-468e-ab2c-daa7c39d7402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216268077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.3216268077
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.3438076224
Short name T602
Test name
Test status
Simulation time 49482272 ps
CPU time 2.72 seconds
Started Jul 18 06:28:57 PM PDT 24
Finished Jul 18 06:29:01 PM PDT 24
Peak memory 207104 kb
Host smart-2e7f968c-0781-418d-bac7-dcdc52aa8b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438076224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3438076224
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.2703211657
Short name T638
Test name
Test status
Simulation time 124606281 ps
CPU time 4.11 seconds
Started Jul 18 06:28:59 PM PDT 24
Finished Jul 18 06:29:06 PM PDT 24
Peak memory 222036 kb
Host smart-5ca3b634-b297-4f82-bd44-c43b6b1c4981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703211657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.2703211657
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.1919222614
Short name T270
Test name
Test status
Simulation time 199426650 ps
CPU time 1.99 seconds
Started Jul 18 06:28:55 PM PDT 24
Finished Jul 18 06:28:58 PM PDT 24
Peak memory 214008 kb
Host smart-765aad23-0ad7-4a03-a90e-456ac79be067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919222614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.1919222614
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.3653987781
Short name T609
Test name
Test status
Simulation time 1753359456 ps
CPU time 4.25 seconds
Started Jul 18 06:29:00 PM PDT 24
Finished Jul 18 06:29:08 PM PDT 24
Peak memory 214076 kb
Host smart-26e65c56-b2db-41bb-9953-0d4c121145d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653987781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.3653987781
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.2189695190
Short name T384
Test name
Test status
Simulation time 535712859 ps
CPU time 4.16 seconds
Started Jul 18 06:29:01 PM PDT 24
Finished Jul 18 06:29:08 PM PDT 24
Peak memory 213920 kb
Host smart-85e144e4-615c-43ed-b79c-bc8611169193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189695190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.2189695190
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.4072754778
Short name T522
Test name
Test status
Simulation time 3127404145 ps
CPU time 19.47 seconds
Started Jul 18 06:28:55 PM PDT 24
Finished Jul 18 06:29:15 PM PDT 24
Peak memory 208616 kb
Host smart-726b6b4a-9630-4c4b-97f2-ce22db4e9be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072754778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.4072754778
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.3879248062
Short name T481
Test name
Test status
Simulation time 106444223 ps
CPU time 3.63 seconds
Started Jul 18 06:28:58 PM PDT 24
Finished Jul 18 06:29:04 PM PDT 24
Peak memory 206656 kb
Host smart-4b491a30-36b2-45bd-9d98-598067091402
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879248062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.3879248062
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.3572323776
Short name T650
Test name
Test status
Simulation time 3102835526 ps
CPU time 21.46 seconds
Started Jul 18 06:28:59 PM PDT 24
Finished Jul 18 06:29:24 PM PDT 24
Peak memory 208664 kb
Host smart-f5188886-4921-4182-98db-120722be0595
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572323776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.3572323776
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.3895289737
Short name T353
Test name
Test status
Simulation time 130422657 ps
CPU time 2.47 seconds
Started Jul 18 06:29:00 PM PDT 24
Finished Jul 18 06:29:05 PM PDT 24
Peak memory 206860 kb
Host smart-49464de8-825c-4477-8f29-2da97881e885
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895289737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.3895289737
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.1133901521
Short name T479
Test name
Test status
Simulation time 420692395 ps
CPU time 3.74 seconds
Started Jul 18 06:28:57 PM PDT 24
Finished Jul 18 06:29:03 PM PDT 24
Peak memory 215424 kb
Host smart-8f677e82-39b2-4f1c-bb4f-9408468cf077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133901521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.1133901521
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.3301508076
Short name T799
Test name
Test status
Simulation time 59518900 ps
CPU time 2.93 seconds
Started Jul 18 06:28:58 PM PDT 24
Finished Jul 18 06:29:03 PM PDT 24
Peak memory 207972 kb
Host smart-76cb3cab-1727-46c5-a2cd-3ae38e484080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301508076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.3301508076
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.209843816
Short name T374
Test name
Test status
Simulation time 321843307 ps
CPU time 12.56 seconds
Started Jul 18 06:28:59 PM PDT 24
Finished Jul 18 06:29:14 PM PDT 24
Peak memory 219524 kb
Host smart-b7f33fdd-9262-48f7-b75e-64419f0c0457
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209843816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.209843816
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.32406452
Short name T73
Test name
Test status
Simulation time 900816665 ps
CPU time 13.19 seconds
Started Jul 18 06:28:57 PM PDT 24
Finished Jul 18 06:29:12 PM PDT 24
Peak memory 222680 kb
Host smart-b8a558d8-db4e-4403-b931-c41c9121d851
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32406452 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.32406452
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.2536549855
Short name T789
Test name
Test status
Simulation time 668407515 ps
CPU time 4.01 seconds
Started Jul 18 06:28:56 PM PDT 24
Finished Jul 18 06:29:01 PM PDT 24
Peak memory 210944 kb
Host smart-b854f08c-7886-4c9e-92d0-e806374691d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536549855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.2536549855
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.3798108614
Short name T494
Test name
Test status
Simulation time 114337795 ps
CPU time 0.77 seconds
Started Jul 18 06:28:59 PM PDT 24
Finished Jul 18 06:29:02 PM PDT 24
Peak memory 205780 kb
Host smart-95fcf234-f022-40a8-93ba-a845809b3e98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798108614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.3798108614
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.603653897
Short name T301
Test name
Test status
Simulation time 252170981 ps
CPU time 12.42 seconds
Started Jul 18 06:29:00 PM PDT 24
Finished Jul 18 06:29:15 PM PDT 24
Peak memory 215212 kb
Host smart-9ef2bb52-8e49-40d0-a671-7ac3ebd5e5bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=603653897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.603653897
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.2344537693
Short name T104
Test name
Test status
Simulation time 1712408276 ps
CPU time 4.75 seconds
Started Jul 18 06:29:01 PM PDT 24
Finished Jul 18 06:29:08 PM PDT 24
Peak memory 208676 kb
Host smart-404bae86-0f65-4582-a3ed-0f3df393be3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344537693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.2344537693
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.2030283076
Short name T289
Test name
Test status
Simulation time 96184299 ps
CPU time 1.99 seconds
Started Jul 18 06:29:00 PM PDT 24
Finished Jul 18 06:29:05 PM PDT 24
Peak memory 214008 kb
Host smart-cd31a036-05d8-483a-80b0-195bfb205cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030283076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.2030283076
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.2169645940
Short name T677
Test name
Test status
Simulation time 367928094 ps
CPU time 3.93 seconds
Started Jul 18 06:28:57 PM PDT 24
Finished Jul 18 06:29:03 PM PDT 24
Peak memory 222288 kb
Host smart-eb4ceb0d-a58e-4d63-9f80-52270e1d2c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169645940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.2169645940
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.236265582
Short name T430
Test name
Test status
Simulation time 358969960 ps
CPU time 3.74 seconds
Started Jul 18 06:29:01 PM PDT 24
Finished Jul 18 06:29:07 PM PDT 24
Peak memory 209028 kb
Host smart-ce3f7680-3c28-492d-98f5-ff401e17dfd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236265582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.236265582
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.4117395706
Short name T767
Test name
Test status
Simulation time 205837240 ps
CPU time 3.08 seconds
Started Jul 18 06:28:57 PM PDT 24
Finished Jul 18 06:29:03 PM PDT 24
Peak memory 206584 kb
Host smart-b9ca80a7-7bd1-4ff8-b463-0c3069ee0698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117395706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.4117395706
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.727518809
Short name T149
Test name
Test status
Simulation time 224683287 ps
CPU time 3.23 seconds
Started Jul 18 06:28:58 PM PDT 24
Finished Jul 18 06:29:04 PM PDT 24
Peak memory 208180 kb
Host smart-94e2a9a7-150b-43f2-bf57-4f88cf95e509
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727518809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.727518809
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.2817018663
Short name T332
Test name
Test status
Simulation time 82727462 ps
CPU time 3.57 seconds
Started Jul 18 06:28:57 PM PDT 24
Finished Jul 18 06:29:02 PM PDT 24
Peak memory 207708 kb
Host smart-688111c7-2733-4f54-b5b2-0bdea19c3589
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817018663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.2817018663
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.1649914066
Short name T791
Test name
Test status
Simulation time 77974364 ps
CPU time 3.79 seconds
Started Jul 18 06:28:58 PM PDT 24
Finished Jul 18 06:29:04 PM PDT 24
Peak memory 208428 kb
Host smart-ec34d4e0-fdf8-4040-b0bd-2318924f168a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649914066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.1649914066
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.899805280
Short name T545
Test name
Test status
Simulation time 167276512 ps
CPU time 2.2 seconds
Started Jul 18 06:28:59 PM PDT 24
Finished Jul 18 06:29:03 PM PDT 24
Peak memory 208816 kb
Host smart-815a9d17-f4d9-408e-8be3-d31a251cd50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899805280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.899805280
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.2575569127
Short name T670
Test name
Test status
Simulation time 218118712 ps
CPU time 4.87 seconds
Started Jul 18 06:29:00 PM PDT 24
Finished Jul 18 06:29:07 PM PDT 24
Peak memory 206684 kb
Host smart-c7b6787d-1eeb-46ad-936b-ecad07225dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575569127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.2575569127
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.2046682835
Short name T188
Test name
Test status
Simulation time 284223833 ps
CPU time 6.61 seconds
Started Jul 18 06:29:00 PM PDT 24
Finished Jul 18 06:29:10 PM PDT 24
Peak memory 220068 kb
Host smart-58a8bb1c-293f-4611-bc9c-cdb57f9dc810
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046682835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.2046682835
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.1500036318
Short name T702
Test name
Test status
Simulation time 412773709 ps
CPU time 9.08 seconds
Started Jul 18 06:28:57 PM PDT 24
Finished Jul 18 06:29:07 PM PDT 24
Peak memory 208012 kb
Host smart-1cb36410-ab54-4f1c-9ed0-b05bc926ed0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500036318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1500036318
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.859744263
Short name T517
Test name
Test status
Simulation time 63627165 ps
CPU time 2.06 seconds
Started Jul 18 06:28:57 PM PDT 24
Finished Jul 18 06:29:00 PM PDT 24
Peak memory 209868 kb
Host smart-18268436-13ac-448c-9099-ae35073f0f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859744263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.859744263
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.2223099551
Short name T804
Test name
Test status
Simulation time 11172489 ps
CPU time 0.75 seconds
Started Jul 18 06:29:16 PM PDT 24
Finished Jul 18 06:29:18 PM PDT 24
Peak memory 205864 kb
Host smart-99cd57ab-4536-42fb-a6c6-9f12b3326039
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223099551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.2223099551
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.1878652452
Short name T422
Test name
Test status
Simulation time 2910187024 ps
CPU time 40.82 seconds
Started Jul 18 06:29:01 PM PDT 24
Finished Jul 18 06:29:45 PM PDT 24
Peak memory 215636 kb
Host smart-7edb4b3e-2d69-4f53-9b7f-c3160ab9c570
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1878652452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.1878652452
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.2720852572
Short name T716
Test name
Test status
Simulation time 295933164 ps
CPU time 5.08 seconds
Started Jul 18 06:29:04 PM PDT 24
Finished Jul 18 06:29:11 PM PDT 24
Peak memory 222464 kb
Host smart-dc8ef4b6-fd93-4f88-8fb8-66f8efe67c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720852572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.2720852572
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.1972726785
Short name T848
Test name
Test status
Simulation time 35902567 ps
CPU time 2.38 seconds
Started Jul 18 06:28:58 PM PDT 24
Finished Jul 18 06:29:03 PM PDT 24
Peak memory 208128 kb
Host smart-43e79b2f-2b42-4b6b-88bc-b78160dbd35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972726785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.1972726785
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.3936939790
Short name T801
Test name
Test status
Simulation time 103064310 ps
CPU time 2.25 seconds
Started Jul 18 06:29:02 PM PDT 24
Finished Jul 18 06:29:07 PM PDT 24
Peak memory 214104 kb
Host smart-b5b34d96-a071-4838-a950-322856a773a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936939790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.3936939790
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.1702272716
Short name T44
Test name
Test status
Simulation time 94662445 ps
CPU time 5.04 seconds
Started Jul 18 06:29:04 PM PDT 24
Finished Jul 18 06:29:11 PM PDT 24
Peak memory 214008 kb
Host smart-3a4d64fa-029f-49c9-8e9e-8c31d640f1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702272716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.1702272716
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.2566578072
Short name T208
Test name
Test status
Simulation time 43360050 ps
CPU time 2.85 seconds
Started Jul 18 06:29:04 PM PDT 24
Finished Jul 18 06:29:09 PM PDT 24
Peak memory 208120 kb
Host smart-5f95aa43-9e72-4364-bc3a-850a5daeea28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566578072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2566578072
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.4156322188
Short name T297
Test name
Test status
Simulation time 522381295 ps
CPU time 6.6 seconds
Started Jul 18 06:29:02 PM PDT 24
Finished Jul 18 06:29:11 PM PDT 24
Peak memory 208904 kb
Host smart-25542b62-8e55-4779-aee8-4d3814d023b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156322188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.4156322188
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.3223214544
Short name T363
Test name
Test status
Simulation time 177502091 ps
CPU time 4.91 seconds
Started Jul 18 06:29:01 PM PDT 24
Finished Jul 18 06:29:09 PM PDT 24
Peak memory 208268 kb
Host smart-5ed47ccb-ff26-4b0e-8634-b0350f808740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223214544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.3223214544
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.4149510538
Short name T454
Test name
Test status
Simulation time 577828210 ps
CPU time 7.3 seconds
Started Jul 18 06:29:01 PM PDT 24
Finished Jul 18 06:29:12 PM PDT 24
Peak memory 207928 kb
Host smart-0ce7b0b6-4323-4c74-a5f2-072862824b14
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149510538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.4149510538
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.4140217312
Short name T586
Test name
Test status
Simulation time 204291796 ps
CPU time 5.12 seconds
Started Jul 18 06:28:59 PM PDT 24
Finished Jul 18 06:29:07 PM PDT 24
Peak memory 208604 kb
Host smart-11899951-1e1b-415d-b977-98d057a39c03
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140217312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.4140217312
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.3871366774
Short name T549
Test name
Test status
Simulation time 53366878 ps
CPU time 2.78 seconds
Started Jul 18 06:29:01 PM PDT 24
Finished Jul 18 06:29:07 PM PDT 24
Peak memory 206676 kb
Host smart-8ed9fb6a-4979-43fc-b5dd-08105fb96aa8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871366774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.3871366774
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.2196121070
Short name T523
Test name
Test status
Simulation time 111536980 ps
CPU time 2.76 seconds
Started Jul 18 06:29:01 PM PDT 24
Finished Jul 18 06:29:07 PM PDT 24
Peak memory 217868 kb
Host smart-041949b5-9dd6-4c80-a0c7-c74a62fd5615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196121070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.2196121070
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.3536695461
Short name T911
Test name
Test status
Simulation time 107812506 ps
CPU time 4.11 seconds
Started Jul 18 06:28:58 PM PDT 24
Finished Jul 18 06:29:04 PM PDT 24
Peak memory 208672 kb
Host smart-972fdeba-024d-4c1d-84bf-10582b0f078c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536695461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3536695461
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.1712913974
Short name T354
Test name
Test status
Simulation time 2123612125 ps
CPU time 28.15 seconds
Started Jul 18 06:29:17 PM PDT 24
Finished Jul 18 06:29:47 PM PDT 24
Peak memory 219880 kb
Host smart-27a92bb3-e55c-494b-bffa-d37075ab137f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712913974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.1712913974
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.289176760
Short name T176
Test name
Test status
Simulation time 8939622062 ps
CPU time 19.99 seconds
Started Jul 18 06:29:23 PM PDT 24
Finished Jul 18 06:29:47 PM PDT 24
Peak memory 221076 kb
Host smart-489f61aa-7221-4603-be7e-04bd7f87fe2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289176760 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.289176760
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.1284476649
Short name T701
Test name
Test status
Simulation time 1107611808 ps
CPU time 4.18 seconds
Started Jul 18 06:29:01 PM PDT 24
Finished Jul 18 06:29:08 PM PDT 24
Peak memory 214080 kb
Host smart-1acd73c8-cc1e-4faa-8653-d01c4a88b555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284476649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.1284476649
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.111359908
Short name T166
Test name
Test status
Simulation time 292356065 ps
CPU time 3.01 seconds
Started Jul 18 06:29:16 PM PDT 24
Finished Jul 18 06:29:20 PM PDT 24
Peak memory 210604 kb
Host smart-d12f382b-66a1-4aa3-801b-6d195826e5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111359908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.111359908
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2973516228
Short name T459
Test name
Test status
Simulation time 46465216 ps
CPU time 0.91 seconds
Started Jul 18 06:26:54 PM PDT 24
Finished Jul 18 06:27:01 PM PDT 24
Peak memory 205860 kb
Host smart-faabed49-9f1a-49f7-aeee-aa12c28787c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973516228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2973516228
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.1647805812
Short name T83
Test name
Test status
Simulation time 149426087 ps
CPU time 3.11 seconds
Started Jul 18 06:26:55 PM PDT 24
Finished Jul 18 06:27:04 PM PDT 24
Peak memory 209824 kb
Host smart-f5098284-3332-47e3-87d2-6437891046e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647805812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.1647805812
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.4233538581
Short name T782
Test name
Test status
Simulation time 2831959158 ps
CPU time 6.79 seconds
Started Jul 18 06:26:56 PM PDT 24
Finished Jul 18 06:27:08 PM PDT 24
Peak memory 209868 kb
Host smart-b292787a-5945-4cf3-b021-3d937da7b3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233538581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.4233538581
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.2551073962
Short name T878
Test name
Test status
Simulation time 66624212 ps
CPU time 2.91 seconds
Started Jul 18 06:26:56 PM PDT 24
Finished Jul 18 06:27:04 PM PDT 24
Peak memory 221032 kb
Host smart-63a59dac-0858-45f0-9e75-f4a92ebf7345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551073962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.2551073962
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_random.244477317
Short name T315
Test name
Test status
Simulation time 57735228 ps
CPU time 4.05 seconds
Started Jul 18 06:26:52 PM PDT 24
Finished Jul 18 06:27:02 PM PDT 24
Peak memory 206712 kb
Host smart-dc4b9b10-d72c-4a41-8a36-ee91e4c19f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244477317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.244477317
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.579354957
Short name T46
Test name
Test status
Simulation time 1143386059 ps
CPU time 9.58 seconds
Started Jul 18 06:26:54 PM PDT 24
Finished Jul 18 06:27:09 PM PDT 24
Peak memory 237452 kb
Host smart-597780b1-0aa6-40df-b23f-a73c7658de1d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579354957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.579354957
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.4192634214
Short name T559
Test name
Test status
Simulation time 667895875 ps
CPU time 11.95 seconds
Started Jul 18 06:26:54 PM PDT 24
Finished Jul 18 06:27:12 PM PDT 24
Peak memory 207800 kb
Host smart-84dad6b7-f378-41ff-b34f-a2495b58fe4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192634214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.4192634214
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.2087203504
Short name T882
Test name
Test status
Simulation time 207459072 ps
CPU time 7.69 seconds
Started Jul 18 06:26:54 PM PDT 24
Finished Jul 18 06:27:07 PM PDT 24
Peak memory 208752 kb
Host smart-8532c88d-6ac0-49cb-8e77-f92c1f96465d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087203504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.2087203504
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.3897616164
Short name T869
Test name
Test status
Simulation time 301532789 ps
CPU time 2.77 seconds
Started Jul 18 06:26:51 PM PDT 24
Finished Jul 18 06:26:58 PM PDT 24
Peak memory 206624 kb
Host smart-438dbbc6-9025-4cb6-8402-d84e3d3bdab3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897616164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.3897616164
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.3221080757
Short name T684
Test name
Test status
Simulation time 3926564073 ps
CPU time 28.75 seconds
Started Jul 18 06:26:54 PM PDT 24
Finished Jul 18 06:27:28 PM PDT 24
Peak memory 208504 kb
Host smart-e5f208cf-ef1f-49b0-9f51-923b02f9a257
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221080757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.3221080757
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.1181788281
Short name T425
Test name
Test status
Simulation time 43435706 ps
CPU time 1.97 seconds
Started Jul 18 06:26:55 PM PDT 24
Finished Jul 18 06:27:03 PM PDT 24
Peak memory 209436 kb
Host smart-9b9924c5-8ca9-42b6-b130-e291334a72be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181788281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.1181788281
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.1198992972
Short name T460
Test name
Test status
Simulation time 386981804 ps
CPU time 6.87 seconds
Started Jul 18 06:26:53 PM PDT 24
Finished Jul 18 06:27:06 PM PDT 24
Peak memory 208344 kb
Host smart-53c92204-f0e4-4a94-aa80-2218ab85df13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198992972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.1198992972
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.3641288489
Short name T248
Test name
Test status
Simulation time 7017911002 ps
CPU time 78.82 seconds
Started Jul 18 06:26:54 PM PDT 24
Finished Jul 18 06:28:20 PM PDT 24
Peak memory 220424 kb
Host smart-d2371c15-89fa-406a-9efc-55de00e519f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641288489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.3641288489
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.162197990
Short name T652
Test name
Test status
Simulation time 364526889 ps
CPU time 13.47 seconds
Started Jul 18 06:26:54 PM PDT 24
Finished Jul 18 06:27:14 PM PDT 24
Peak memory 222440 kb
Host smart-621cd95b-a017-462d-aeb3-0cb806f9e6d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162197990 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.162197990
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.1176552014
Short name T632
Test name
Test status
Simulation time 593955131 ps
CPU time 4.66 seconds
Started Jul 18 06:26:52 PM PDT 24
Finished Jul 18 06:27:02 PM PDT 24
Peak memory 218404 kb
Host smart-acf6832d-e8b8-4878-8956-a19b54abc2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176552014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.1176552014
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.3214387333
Short name T730
Test name
Test status
Simulation time 271832618 ps
CPU time 5.63 seconds
Started Jul 18 06:26:54 PM PDT 24
Finished Jul 18 06:27:06 PM PDT 24
Peak memory 210744 kb
Host smart-d15ce3cf-f652-420f-bbb7-5d2d0d641ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214387333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.3214387333
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.3129061020
Short name T445
Test name
Test status
Simulation time 24615138 ps
CPU time 0.76 seconds
Started Jul 18 06:29:16 PM PDT 24
Finished Jul 18 06:29:18 PM PDT 24
Peak memory 205860 kb
Host smart-7489aa5b-83ca-4766-be12-d69a63895519
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129061020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.3129061020
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.3548704218
Short name T865
Test name
Test status
Simulation time 126689698 ps
CPU time 2.75 seconds
Started Jul 18 06:29:19 PM PDT 24
Finished Jul 18 06:29:26 PM PDT 24
Peak memory 214920 kb
Host smart-368ca116-f889-4576-9af4-ed9bfdd29f81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3548704218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.3548704218
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.3577820044
Short name T874
Test name
Test status
Simulation time 215429975 ps
CPU time 4.26 seconds
Started Jul 18 06:29:16 PM PDT 24
Finished Jul 18 06:29:22 PM PDT 24
Peak memory 215680 kb
Host smart-d80ec180-9478-4bef-90b8-3fad6973347e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577820044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.3577820044
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.3892333004
Short name T79
Test name
Test status
Simulation time 600731542 ps
CPU time 4.48 seconds
Started Jul 18 06:29:16 PM PDT 24
Finished Jul 18 06:29:22 PM PDT 24
Peak memory 209372 kb
Host smart-7d1f3126-bd24-4703-bd4c-b08f169f69e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892333004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.3892333004
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.1268966534
Short name T103
Test name
Test status
Simulation time 173239732 ps
CPU time 3.31 seconds
Started Jul 18 06:29:23 PM PDT 24
Finished Jul 18 06:29:30 PM PDT 24
Peak memory 208912 kb
Host smart-25e689ac-ca32-4c49-bb87-a11968d2d459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268966534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.1268966534
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.2624290363
Short name T843
Test name
Test status
Simulation time 694040477 ps
CPU time 3.97 seconds
Started Jul 18 06:29:18 PM PDT 24
Finished Jul 18 06:29:26 PM PDT 24
Peak memory 222168 kb
Host smart-206e39a0-b4e9-42f1-927c-0cc689a7c023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624290363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.2624290363
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.3733790857
Short name T183
Test name
Test status
Simulation time 66401727 ps
CPU time 2.97 seconds
Started Jul 18 06:29:18 PM PDT 24
Finished Jul 18 06:29:24 PM PDT 24
Peak memory 217124 kb
Host smart-7adfbe8b-22fb-4531-a5a5-3dd62b29b5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733790857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.3733790857
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.3857129514
Short name T93
Test name
Test status
Simulation time 119859368 ps
CPU time 4.28 seconds
Started Jul 18 06:29:20 PM PDT 24
Finished Jul 18 06:29:28 PM PDT 24
Peak memory 208392 kb
Host smart-68825543-53e8-4279-b9ba-6e4b0037aed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857129514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.3857129514
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.2919583053
Short name T200
Test name
Test status
Simulation time 2128140899 ps
CPU time 25.53 seconds
Started Jul 18 06:29:18 PM PDT 24
Finished Jul 18 06:29:47 PM PDT 24
Peak memory 207820 kb
Host smart-dfdede03-2d64-4e7a-ba9f-d9da40d30bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919583053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.2919583053
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.2467328133
Short name T466
Test name
Test status
Simulation time 2074719761 ps
CPU time 14.72 seconds
Started Jul 18 06:29:17 PM PDT 24
Finished Jul 18 06:29:34 PM PDT 24
Peak memory 207864 kb
Host smart-8f008caf-c580-47f3-9b55-70f8c714ab31
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467328133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2467328133
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.1450056781
Short name T371
Test name
Test status
Simulation time 854858021 ps
CPU time 14.55 seconds
Started Jul 18 06:29:23 PM PDT 24
Finished Jul 18 06:29:41 PM PDT 24
Peak memory 207956 kb
Host smart-a0d595ca-5712-4593-9cd6-03777d2d00af
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450056781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.1450056781
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.3242869585
Short name T516
Test name
Test status
Simulation time 243777737 ps
CPU time 3.19 seconds
Started Jul 18 06:29:14 PM PDT 24
Finished Jul 18 06:29:18 PM PDT 24
Peak memory 208740 kb
Host smart-6d6b05dd-45e3-4af7-af34-db4a887ae6cd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242869585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.3242869585
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_smoke.92139808
Short name T585
Test name
Test status
Simulation time 1675534487 ps
CPU time 10.49 seconds
Started Jul 18 06:29:18 PM PDT 24
Finished Jul 18 06:29:31 PM PDT 24
Peak memory 208124 kb
Host smart-dfe70679-dfe3-4432-9e93-3daf8613da01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92139808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.92139808
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.56872658
Short name T776
Test name
Test status
Simulation time 3114657230 ps
CPU time 32.33 seconds
Started Jul 18 06:29:15 PM PDT 24
Finished Jul 18 06:29:49 PM PDT 24
Peak memory 216508 kb
Host smart-78a403ab-0419-4a3a-810d-a664fce4f844
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56872658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.56872658
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.1146479871
Short name T338
Test name
Test status
Simulation time 138686060 ps
CPU time 5.75 seconds
Started Jul 18 06:29:19 PM PDT 24
Finished Jul 18 06:29:28 PM PDT 24
Peak memory 219508 kb
Host smart-8c5f735a-444e-4062-a777-9d2d97231fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146479871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1146479871
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.592749601
Short name T895
Test name
Test status
Simulation time 2881334062 ps
CPU time 14.9 seconds
Started Jul 18 06:29:18 PM PDT 24
Finished Jul 18 06:29:36 PM PDT 24
Peak memory 210624 kb
Host smart-8e0636f6-f9e4-4280-b0af-e1d343ca4355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592749601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.592749601
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.969921223
Short name T893
Test name
Test status
Simulation time 40415565 ps
CPU time 0.73 seconds
Started Jul 18 06:29:18 PM PDT 24
Finished Jul 18 06:29:21 PM PDT 24
Peak memory 205864 kb
Host smart-07907d99-1587-4a83-84a9-7fc9f491a8d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969921223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.969921223
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.1747516781
Short name T378
Test name
Test status
Simulation time 494264772 ps
CPU time 7.03 seconds
Started Jul 18 06:29:15 PM PDT 24
Finished Jul 18 06:29:23 PM PDT 24
Peak memory 215564 kb
Host smart-a5874209-3dcd-48cd-bb69-b592131d8748
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1747516781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.1747516781
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.891050843
Short name T595
Test name
Test status
Simulation time 350292832 ps
CPU time 7.05 seconds
Started Jul 18 06:29:18 PM PDT 24
Finished Jul 18 06:29:28 PM PDT 24
Peak memory 214012 kb
Host smart-3999d0f6-cf8c-4026-a404-52e19841a6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891050843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.891050843
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.3422738027
Short name T376
Test name
Test status
Simulation time 290763807 ps
CPU time 3.52 seconds
Started Jul 18 06:29:17 PM PDT 24
Finished Jul 18 06:29:23 PM PDT 24
Peak memory 209956 kb
Host smart-3a163033-3ac9-4d0d-8c69-d8e2230f6665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422738027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.3422738027
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.1098641929
Short name T689
Test name
Test status
Simulation time 363858774 ps
CPU time 4.68 seconds
Started Jul 18 06:29:17 PM PDT 24
Finished Jul 18 06:29:24 PM PDT 24
Peak memory 208964 kb
Host smart-fb427440-4cce-4a83-9c9f-f0e8171ae976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098641929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.1098641929
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.3388827676
Short name T17
Test name
Test status
Simulation time 203025257 ps
CPU time 1.94 seconds
Started Jul 18 06:29:16 PM PDT 24
Finished Jul 18 06:29:20 PM PDT 24
Peak memory 214004 kb
Host smart-9613d108-0df7-435a-876a-d8fe22899309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388827676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.3388827676
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.1662448090
Short name T236
Test name
Test status
Simulation time 1019458996 ps
CPU time 5.08 seconds
Started Jul 18 06:29:17 PM PDT 24
Finished Jul 18 06:29:25 PM PDT 24
Peak memory 210256 kb
Host smart-1420cc63-e03b-45be-88d1-a3b6b293335f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662448090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.1662448090
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.2428467395
Short name T633
Test name
Test status
Simulation time 146416943 ps
CPU time 6.56 seconds
Started Jul 18 06:29:16 PM PDT 24
Finished Jul 18 06:29:25 PM PDT 24
Peak memory 217960 kb
Host smart-c84f5d13-2c4e-4f6a-bb94-fa222c73ba85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428467395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.2428467395
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.1778828198
Short name T116
Test name
Test status
Simulation time 68160528 ps
CPU time 2.3 seconds
Started Jul 18 06:29:18 PM PDT 24
Finished Jul 18 06:29:23 PM PDT 24
Peak memory 206576 kb
Host smart-a70f8950-9a31-4edc-9195-48f5c8ec9f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778828198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.1778828198
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.3567341053
Short name T450
Test name
Test status
Simulation time 26122309 ps
CPU time 1.84 seconds
Started Jul 18 06:29:20 PM PDT 24
Finished Jul 18 06:29:26 PM PDT 24
Peak memory 206796 kb
Host smart-18307d20-6853-4e84-9adb-18452dee35f5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567341053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.3567341053
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.1869716687
Short name T541
Test name
Test status
Simulation time 587379976 ps
CPU time 6.62 seconds
Started Jul 18 06:29:17 PM PDT 24
Finished Jul 18 06:29:26 PM PDT 24
Peak memory 208584 kb
Host smart-0143f7b7-bf93-4d87-9b97-0451d755eb34
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869716687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.1869716687
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.1530676199
Short name T669
Test name
Test status
Simulation time 1991014257 ps
CPU time 13.13 seconds
Started Jul 18 06:29:20 PM PDT 24
Finished Jul 18 06:29:37 PM PDT 24
Peak memory 208152 kb
Host smart-2df09d0f-6f90-4d13-a0eb-ccf43cafe573
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530676199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.1530676199
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.3307776413
Short name T261
Test name
Test status
Simulation time 52375699 ps
CPU time 2.01 seconds
Started Jul 18 06:29:19 PM PDT 24
Finished Jul 18 06:29:25 PM PDT 24
Peak memory 208620 kb
Host smart-93d58241-1536-49e9-a18a-db069a9a053c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307776413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.3307776413
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.3905115975
Short name T642
Test name
Test status
Simulation time 60374959 ps
CPU time 2.12 seconds
Started Jul 18 06:29:16 PM PDT 24
Finished Jul 18 06:29:20 PM PDT 24
Peak memory 206988 kb
Host smart-e3e032b6-0f7a-4107-b134-9ca73e419f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905115975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.3905115975
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.156199786
Short name T5
Test name
Test status
Simulation time 166998942 ps
CPU time 4.32 seconds
Started Jul 18 06:29:22 PM PDT 24
Finished Jul 18 06:29:30 PM PDT 24
Peak memory 208096 kb
Host smart-827d035a-4582-4bce-944e-779176d218aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156199786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.156199786
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.760389122
Short name T399
Test name
Test status
Simulation time 998712803 ps
CPU time 5.71 seconds
Started Jul 18 06:29:18 PM PDT 24
Finished Jul 18 06:29:26 PM PDT 24
Peak memory 210368 kb
Host smart-6f79d90e-10ff-4a32-ae61-3ce4b7817d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760389122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.760389122
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.2821953143
Short name T606
Test name
Test status
Simulation time 62603355 ps
CPU time 0.79 seconds
Started Jul 18 06:29:20 PM PDT 24
Finished Jul 18 06:29:24 PM PDT 24
Peak memory 205812 kb
Host smart-2c37ba82-4988-4fc1-8da7-ce89c2ed0288
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821953143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2821953143
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.3759136389
Short name T182
Test name
Test status
Simulation time 120377258 ps
CPU time 2.6 seconds
Started Jul 18 06:29:19 PM PDT 24
Finished Jul 18 06:29:26 PM PDT 24
Peak memory 215184 kb
Host smart-76398cfa-bc26-4646-b7b9-93bd62e3e3df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3759136389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.3759136389
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.3995520563
Short name T33
Test name
Test status
Simulation time 369605189 ps
CPU time 4.44 seconds
Started Jul 18 06:29:21 PM PDT 24
Finished Jul 18 06:29:29 PM PDT 24
Peak memory 214448 kb
Host smart-8b12e561-379c-44f8-8486-ede9494fec2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995520563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.3995520563
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.2986165004
Short name T539
Test name
Test status
Simulation time 69479063 ps
CPU time 2.33 seconds
Started Jul 18 06:29:20 PM PDT 24
Finished Jul 18 06:29:26 PM PDT 24
Peak memory 207852 kb
Host smart-bbd4ca4b-d276-4f76-ad76-93e3df1b6c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986165004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.2986165004
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.1520538271
Short name T362
Test name
Test status
Simulation time 1506090572 ps
CPU time 46.21 seconds
Started Jul 18 06:29:23 PM PDT 24
Finished Jul 18 06:30:13 PM PDT 24
Peak memory 213936 kb
Host smart-b0832faa-cab4-4549-aa0e-181c5e8f1bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520538271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.1520538271
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_random.910502712
Short name T222
Test name
Test status
Simulation time 1324742393 ps
CPU time 28.76 seconds
Started Jul 18 06:29:16 PM PDT 24
Finished Jul 18 06:29:47 PM PDT 24
Peak memory 207676 kb
Host smart-7daaec70-ddb1-4ce1-8b0b-928f7a813f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910502712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.910502712
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.1443637686
Short name T735
Test name
Test status
Simulation time 654168478 ps
CPU time 18.78 seconds
Started Jul 18 06:29:19 PM PDT 24
Finished Jul 18 06:29:42 PM PDT 24
Peak memory 207868 kb
Host smart-e51b2678-f31d-4569-bc39-2c2e35eb938d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443637686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1443637686
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.4058934241
Short name T381
Test name
Test status
Simulation time 483888124 ps
CPU time 10.36 seconds
Started Jul 18 06:29:17 PM PDT 24
Finished Jul 18 06:29:30 PM PDT 24
Peak memory 207776 kb
Host smart-6a73a706-a7c6-46a2-a3c8-9380fed7a87e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058934241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.4058934241
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.3866641615
Short name T502
Test name
Test status
Simulation time 999135005 ps
CPU time 35.93 seconds
Started Jul 18 06:29:17 PM PDT 24
Finished Jul 18 06:29:56 PM PDT 24
Peak memory 208160 kb
Host smart-ec9ca268-b51d-4df7-a71b-de82cc00c1a6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866641615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3866641615
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.371118920
Short name T449
Test name
Test status
Simulation time 506168488 ps
CPU time 16.2 seconds
Started Jul 18 06:29:20 PM PDT 24
Finished Jul 18 06:29:40 PM PDT 24
Peak memory 207708 kb
Host smart-7d2ed4dd-afea-409f-9e5b-784c360b807b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371118920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.371118920
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.3018219401
Short name T822
Test name
Test status
Simulation time 134548908 ps
CPU time 4.55 seconds
Started Jul 18 06:29:19 PM PDT 24
Finished Jul 18 06:29:27 PM PDT 24
Peak memory 218148 kb
Host smart-9acd271f-3551-401e-a8dd-3eb3afb8e092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018219401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.3018219401
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.2529326598
Short name T775
Test name
Test status
Simulation time 82027082 ps
CPU time 2.28 seconds
Started Jul 18 06:29:21 PM PDT 24
Finished Jul 18 06:29:27 PM PDT 24
Peak memory 206728 kb
Host smart-837a619c-4737-4659-b258-1f4fa3de0632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529326598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.2529326598
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.191439126
Short name T348
Test name
Test status
Simulation time 11259216863 ps
CPU time 68.29 seconds
Started Jul 18 06:29:20 PM PDT 24
Finished Jul 18 06:30:32 PM PDT 24
Peak memory 215628 kb
Host smart-8d3079d3-c786-4ea2-8200-d12ec6b6d362
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191439126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.191439126
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.2799817196
Short name T594
Test name
Test status
Simulation time 126811884 ps
CPU time 5.91 seconds
Started Jul 18 06:29:20 PM PDT 24
Finished Jul 18 06:29:30 PM PDT 24
Peak memory 209068 kb
Host smart-50d015be-279f-4b5b-9696-93af1a3490ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799817196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.2799817196
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.202339059
Short name T825
Test name
Test status
Simulation time 10922339 ps
CPU time 0.85 seconds
Started Jul 18 06:29:23 PM PDT 24
Finished Jul 18 06:29:28 PM PDT 24
Peak memory 205832 kb
Host smart-4b84c03f-96d1-4d94-bb35-0e47870adf5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202339059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.202339059
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.1175162997
Short name T403
Test name
Test status
Simulation time 712858657 ps
CPU time 10.36 seconds
Started Jul 18 06:29:19 PM PDT 24
Finished Jul 18 06:29:32 PM PDT 24
Peak memory 214180 kb
Host smart-7256aa90-c1fd-4d4e-ad8f-264f8efd8c39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1175162997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.1175162997
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.1679824369
Short name T660
Test name
Test status
Simulation time 52292957 ps
CPU time 2.44 seconds
Started Jul 18 06:29:22 PM PDT 24
Finished Jul 18 06:29:28 PM PDT 24
Peak memory 207236 kb
Host smart-daaf3bfb-a9eb-4c5d-927a-639c809500bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679824369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1679824369
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.2441770920
Short name T65
Test name
Test status
Simulation time 120841716 ps
CPU time 2.27 seconds
Started Jul 18 06:29:19 PM PDT 24
Finished Jul 18 06:29:26 PM PDT 24
Peak memory 207944 kb
Host smart-80de036b-6b51-453e-aaf9-dfd16788fa34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441770920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.2441770920
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.1102565376
Short name T108
Test name
Test status
Simulation time 90702915 ps
CPU time 3.19 seconds
Started Jul 18 06:29:19 PM PDT 24
Finished Jul 18 06:29:26 PM PDT 24
Peak memory 209488 kb
Host smart-0dd0265c-b867-4bdd-a89b-1337e4f97e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102565376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.1102565376
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.1727883547
Short name T385
Test name
Test status
Simulation time 116223300 ps
CPU time 3.09 seconds
Started Jul 18 06:29:20 PM PDT 24
Finished Jul 18 06:29:27 PM PDT 24
Peak memory 214028 kb
Host smart-df73136b-a177-49e6-8d37-9fe823c430ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727883547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.1727883547
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.2913381658
Short name T237
Test name
Test status
Simulation time 198388865 ps
CPU time 1.99 seconds
Started Jul 18 06:29:19 PM PDT 24
Finished Jul 18 06:29:25 PM PDT 24
Peak memory 219568 kb
Host smart-25de1960-d818-4bec-86fe-d61c843d5e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913381658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.2913381658
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.64900527
Short name T771
Test name
Test status
Simulation time 208256006 ps
CPU time 4.38 seconds
Started Jul 18 06:29:20 PM PDT 24
Finished Jul 18 06:29:28 PM PDT 24
Peak memory 207252 kb
Host smart-ca00fdc3-fec7-4641-b6b3-3717ceb55c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64900527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.64900527
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.3189312356
Short name T765
Test name
Test status
Simulation time 500141610 ps
CPU time 3.08 seconds
Started Jul 18 06:29:22 PM PDT 24
Finished Jul 18 06:29:29 PM PDT 24
Peak memory 207804 kb
Host smart-04326bdb-3d4d-4523-824a-b58296f58873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189312356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.3189312356
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.1039669746
Short name T150
Test name
Test status
Simulation time 224727392 ps
CPU time 6.56 seconds
Started Jul 18 06:29:20 PM PDT 24
Finished Jul 18 06:29:30 PM PDT 24
Peak memory 208356 kb
Host smart-953d500d-fa03-4530-b1b8-1d3df48642fe
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039669746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.1039669746
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.3060556915
Short name T391
Test name
Test status
Simulation time 43528254 ps
CPU time 2.34 seconds
Started Jul 18 06:29:19 PM PDT 24
Finished Jul 18 06:29:25 PM PDT 24
Peak memory 208012 kb
Host smart-634f3fae-69af-41b0-9e03-8a26f61141ed
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060556915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.3060556915
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.226733698
Short name T278
Test name
Test status
Simulation time 36948568 ps
CPU time 1.82 seconds
Started Jul 18 06:29:22 PM PDT 24
Finished Jul 18 06:29:28 PM PDT 24
Peak memory 206672 kb
Host smart-91eaba85-eab0-46cd-833e-1875427e8e16
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226733698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.226733698
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.1190871108
Short name T490
Test name
Test status
Simulation time 189889631 ps
CPU time 2.45 seconds
Started Jul 18 06:29:19 PM PDT 24
Finished Jul 18 06:29:26 PM PDT 24
Peak memory 208452 kb
Host smart-b9e899e3-60df-43ca-9409-999e3fd9d637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190871108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1190871108
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.515304703
Short name T866
Test name
Test status
Simulation time 116029693 ps
CPU time 2.65 seconds
Started Jul 18 06:29:20 PM PDT 24
Finished Jul 18 06:29:26 PM PDT 24
Peak memory 207980 kb
Host smart-e9d27865-df84-43a0-b121-10b8583759fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515304703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.515304703
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.2614115816
Short name T249
Test name
Test status
Simulation time 738300122 ps
CPU time 21.05 seconds
Started Jul 18 06:29:19 PM PDT 24
Finished Jul 18 06:29:43 PM PDT 24
Peak memory 214972 kb
Host smart-758f4763-a053-4225-8713-0fa0a780409a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614115816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.2614115816
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.2288887750
Short name T228
Test name
Test status
Simulation time 240738267 ps
CPU time 3.92 seconds
Started Jul 18 06:29:19 PM PDT 24
Finished Jul 18 06:29:26 PM PDT 24
Peak memory 207300 kb
Host smart-e3be741d-1fec-4e59-83e4-2d3feed5a4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288887750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.2288887750
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.1470804298
Short name T195
Test name
Test status
Simulation time 33881188 ps
CPU time 1.76 seconds
Started Jul 18 06:29:20 PM PDT 24
Finished Jul 18 06:29:26 PM PDT 24
Peak memory 209564 kb
Host smart-9dbdd61a-ac0b-4d46-8d2d-bec96acd4b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470804298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.1470804298
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.3243976219
Short name T583
Test name
Test status
Simulation time 41156135 ps
CPU time 0.77 seconds
Started Jul 18 06:29:39 PM PDT 24
Finished Jul 18 06:29:45 PM PDT 24
Peak memory 205872 kb
Host smart-cfa55e73-b219-46de-a7dc-18c979084710
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243976219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.3243976219
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.3208449424
Short name T901
Test name
Test status
Simulation time 2064208372 ps
CPU time 27.31 seconds
Started Jul 18 06:29:21 PM PDT 24
Finished Jul 18 06:29:53 PM PDT 24
Peak memory 214876 kb
Host smart-4bae0ffc-7a4a-48ae-b2bd-673f511f3374
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3208449424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3208449424
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.2160957135
Short name T844
Test name
Test status
Simulation time 156300966 ps
CPU time 4.7 seconds
Started Jul 18 06:29:36 PM PDT 24
Finished Jul 18 06:29:45 PM PDT 24
Peak memory 209632 kb
Host smart-bcac89b7-b119-45d9-be85-22c09546b682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160957135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.2160957135
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.2677832710
Short name T618
Test name
Test status
Simulation time 211654130 ps
CPU time 2.5 seconds
Started Jul 18 06:29:21 PM PDT 24
Finished Jul 18 06:29:28 PM PDT 24
Peak memory 207640 kb
Host smart-961d2b83-be36-4f95-b80b-de81cef6f2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677832710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.2677832710
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.1753852078
Short name T676
Test name
Test status
Simulation time 46731271 ps
CPU time 1.98 seconds
Started Jul 18 06:29:34 PM PDT 24
Finished Jul 18 06:29:39 PM PDT 24
Peak memory 210712 kb
Host smart-ffc65710-b321-44a2-8ec4-025cd5e50ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753852078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.1753852078
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.318422001
Short name T451
Test name
Test status
Simulation time 118463543 ps
CPU time 3.17 seconds
Started Jul 18 06:29:19 PM PDT 24
Finished Jul 18 06:29:26 PM PDT 24
Peak memory 214172 kb
Host smart-092831e9-dda8-4ae6-9828-1a524219567a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318422001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.318422001
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.639617339
Short name T691
Test name
Test status
Simulation time 62959839 ps
CPU time 3.39 seconds
Started Jul 18 06:29:18 PM PDT 24
Finished Jul 18 06:29:24 PM PDT 24
Peak memory 207332 kb
Host smart-349382da-6468-4e6a-b6ba-aff4aae88592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639617339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.639617339
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.4009761963
Short name T405
Test name
Test status
Simulation time 104628580 ps
CPU time 2.84 seconds
Started Jul 18 06:29:23 PM PDT 24
Finished Jul 18 06:29:30 PM PDT 24
Peak memory 206548 kb
Host smart-8439b6a4-207a-4edb-a92d-cd90d843ba49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009761963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.4009761963
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.3737165740
Short name T209
Test name
Test status
Simulation time 233165194 ps
CPU time 3.15 seconds
Started Jul 18 06:29:23 PM PDT 24
Finished Jul 18 06:29:30 PM PDT 24
Peak memory 206496 kb
Host smart-333d3e02-c14e-4cc5-ac33-6763523b94dd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737165740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.3737165740
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.2240292737
Short name T488
Test name
Test status
Simulation time 32297286 ps
CPU time 2.31 seconds
Started Jul 18 06:29:23 PM PDT 24
Finished Jul 18 06:29:29 PM PDT 24
Peak memory 206692 kb
Host smart-c4b062e2-0fe0-4d72-a6c0-c1242188220e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240292737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2240292737
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.1344852496
Short name T206
Test name
Test status
Simulation time 79448145 ps
CPU time 2.05 seconds
Started Jul 18 06:29:34 PM PDT 24
Finished Jul 18 06:29:39 PM PDT 24
Peak memory 207660 kb
Host smart-39717c12-9bba-4ef7-9e0f-ee31ea17dd47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344852496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.1344852496
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.2513544800
Short name T546
Test name
Test status
Simulation time 406889077 ps
CPU time 4.28 seconds
Started Jul 18 06:29:17 PM PDT 24
Finished Jul 18 06:29:23 PM PDT 24
Peak memory 208404 kb
Host smart-1aece6d8-3c94-4032-bfd3-b67b5641be99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513544800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.2513544800
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.2233860807
Short name T292
Test name
Test status
Simulation time 37853077289 ps
CPU time 214.97 seconds
Started Jul 18 06:29:44 PM PDT 24
Finished Jul 18 06:33:22 PM PDT 24
Peak memory 217024 kb
Host smart-b4268a89-7bf8-4ba1-acb4-a721c0fb1fed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233860807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.2233860807
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.1478690949
Short name T173
Test name
Test status
Simulation time 1598072218 ps
CPU time 11.43 seconds
Started Jul 18 06:29:36 PM PDT 24
Finished Jul 18 06:29:52 PM PDT 24
Peak memory 222476 kb
Host smart-4433f92e-7139-4d81-b6f6-248954ac8593
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478690949 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.1478690949
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.213156327
Short name T647
Test name
Test status
Simulation time 829785211 ps
CPU time 4.52 seconds
Started Jul 18 06:29:19 PM PDT 24
Finished Jul 18 06:29:27 PM PDT 24
Peak memory 207936 kb
Host smart-88563dc2-1bad-4dea-a078-5c2217c3392f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213156327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.213156327
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.909074301
Short name T564
Test name
Test status
Simulation time 26840115 ps
CPU time 1.17 seconds
Started Jul 18 06:29:40 PM PDT 24
Finished Jul 18 06:29:45 PM PDT 24
Peak memory 209516 kb
Host smart-9c718ca9-567c-44ff-a1f3-2b2926d16569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909074301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.909074301
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.2188481747
Short name T651
Test name
Test status
Simulation time 16262130 ps
CPU time 0.94 seconds
Started Jul 18 06:29:37 PM PDT 24
Finished Jul 18 06:29:42 PM PDT 24
Peak memory 205920 kb
Host smart-5255b350-8350-40fe-bb40-f25baa636460
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188481747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.2188481747
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.830686186
Short name T434
Test name
Test status
Simulation time 108502709 ps
CPU time 6.37 seconds
Started Jul 18 06:29:41 PM PDT 24
Finished Jul 18 06:29:52 PM PDT 24
Peak memory 214068 kb
Host smart-a385728b-8346-488a-a34c-8a80d85157b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=830686186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.830686186
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.2636970021
Short name T205
Test name
Test status
Simulation time 862984763 ps
CPU time 4.74 seconds
Started Jul 18 06:29:36 PM PDT 24
Finished Jul 18 06:29:45 PM PDT 24
Peak memory 209728 kb
Host smart-1b8d70ef-aa68-4a14-930c-ac25cc9910e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636970021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.2636970021
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.1221615461
Short name T54
Test name
Test status
Simulation time 212143770 ps
CPU time 2.75 seconds
Started Jul 18 06:29:39 PM PDT 24
Finished Jul 18 06:29:47 PM PDT 24
Peak memory 208472 kb
Host smart-c4aa7b31-4ed0-4a99-8f5b-b776bd2a4d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221615461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.1221615461
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1647423588
Short name T179
Test name
Test status
Simulation time 285096517 ps
CPU time 2.92 seconds
Started Jul 18 06:29:33 PM PDT 24
Finished Jul 18 06:29:37 PM PDT 24
Peak memory 214048 kb
Host smart-9214d165-15b9-486d-b141-95932e6fa15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647423588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1647423588
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.1151371563
Short name T240
Test name
Test status
Simulation time 653886036 ps
CPU time 5.62 seconds
Started Jul 18 06:29:35 PM PDT 24
Finished Jul 18 06:29:45 PM PDT 24
Peak memory 222112 kb
Host smart-e5ef8d90-4e51-4e16-8b87-20c1c3d27b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151371563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.1151371563
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.56943162
Short name T221
Test name
Test status
Simulation time 302626057 ps
CPU time 3.77 seconds
Started Jul 18 06:29:38 PM PDT 24
Finished Jul 18 06:29:46 PM PDT 24
Peak memory 208380 kb
Host smart-24641610-1a31-43b5-a6f6-623a3cc6943c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56943162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.56943162
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.1150158957
Short name T533
Test name
Test status
Simulation time 69269471 ps
CPU time 2.64 seconds
Started Jul 18 06:29:33 PM PDT 24
Finished Jul 18 06:29:37 PM PDT 24
Peak memory 208272 kb
Host smart-01e608e1-4012-4ffc-8339-e427094bc7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150158957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.1150158957
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.4108068566
Short name T838
Test name
Test status
Simulation time 114104772 ps
CPU time 3.53 seconds
Started Jul 18 06:29:33 PM PDT 24
Finished Jul 18 06:29:38 PM PDT 24
Peak memory 208516 kb
Host smart-d95f756e-72e6-49b9-9677-a568340294ed
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108068566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.4108068566
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.3384450084
Short name T707
Test name
Test status
Simulation time 92085706 ps
CPU time 2.14 seconds
Started Jul 18 06:29:37 PM PDT 24
Finished Jul 18 06:29:44 PM PDT 24
Peak memory 208532 kb
Host smart-79f66777-fded-40fe-a1b4-3a085b43d1ae
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384450084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.3384450084
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.994997721
Short name T377
Test name
Test status
Simulation time 42369854 ps
CPU time 1.99 seconds
Started Jul 18 06:29:33 PM PDT 24
Finished Jul 18 06:29:37 PM PDT 24
Peak memory 208376 kb
Host smart-e4b034e4-8f70-4513-aa8b-e3b0a8f6d8be
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994997721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.994997721
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_smoke.1963111142
Short name T442
Test name
Test status
Simulation time 43756388 ps
CPU time 1.93 seconds
Started Jul 18 06:29:42 PM PDT 24
Finished Jul 18 06:29:49 PM PDT 24
Peak memory 208296 kb
Host smart-ca121ebe-81bf-42e7-8063-c21f6e94fa01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963111142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1963111142
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.1640028293
Short name T731
Test name
Test status
Simulation time 859515254 ps
CPU time 3.87 seconds
Started Jul 18 06:29:34 PM PDT 24
Finished Jul 18 06:29:40 PM PDT 24
Peak memory 219476 kb
Host smart-1795f992-863e-4cf8-838c-b6448e8d834a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640028293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.1640028293
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.3639637773
Short name T414
Test name
Test status
Simulation time 4743329342 ps
CPU time 47.42 seconds
Started Jul 18 06:29:40 PM PDT 24
Finished Jul 18 06:30:32 PM PDT 24
Peak memory 208460 kb
Host smart-c452af5f-7874-4933-a650-6f62a52b1449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639637773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.3639637773
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.3898631153
Short name T411
Test name
Test status
Simulation time 81370259 ps
CPU time 2.38 seconds
Started Jul 18 06:29:33 PM PDT 24
Finished Jul 18 06:29:37 PM PDT 24
Peak memory 209732 kb
Host smart-0e8446c2-a580-4732-b26d-a05136730f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898631153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.3898631153
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.1572835630
Short name T185
Test name
Test status
Simulation time 10364128 ps
CPU time 0.83 seconds
Started Jul 18 06:29:41 PM PDT 24
Finished Jul 18 06:29:47 PM PDT 24
Peak memory 205872 kb
Host smart-b7bf5988-a71e-478d-a51a-393cc071d56b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572835630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.1572835630
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.1527306719
Short name T272
Test name
Test status
Simulation time 156825395 ps
CPU time 3.45 seconds
Started Jul 18 06:29:35 PM PDT 24
Finished Jul 18 06:29:41 PM PDT 24
Peak memory 215340 kb
Host smart-6bcbc107-cb38-47d6-9a62-d91ee2594647
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1527306719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.1527306719
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.2416742889
Short name T898
Test name
Test status
Simulation time 883710391 ps
CPU time 4.14 seconds
Started Jul 18 06:29:34 PM PDT 24
Finished Jul 18 06:29:40 PM PDT 24
Peak memory 220036 kb
Host smart-59eaf3a5-9ed3-4111-acb8-87f0e3c0f0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416742889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2416742889
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.582872985
Short name T511
Test name
Test status
Simulation time 189219843 ps
CPU time 2.47 seconds
Started Jul 18 06:29:39 PM PDT 24
Finished Jul 18 06:29:46 PM PDT 24
Peak memory 208944 kb
Host smart-84dc4ab6-2c42-4d6b-b201-e09ec45d9bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582872985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.582872985
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.3772518109
Short name T107
Test name
Test status
Simulation time 230750700 ps
CPU time 4.95 seconds
Started Jul 18 06:29:34 PM PDT 24
Finished Jul 18 06:29:42 PM PDT 24
Peak memory 218056 kb
Host smart-27413901-3d84-4b1b-8e7c-c738ed716e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772518109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.3772518109
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.1578532436
Short name T367
Test name
Test status
Simulation time 239222994 ps
CPU time 3.31 seconds
Started Jul 18 06:29:35 PM PDT 24
Finished Jul 18 06:29:41 PM PDT 24
Peak memory 205976 kb
Host smart-d45ffa29-0635-42f0-9b6a-d18db34edf8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578532436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.1578532436
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.97749398
Short name T244
Test name
Test status
Simulation time 319470454 ps
CPU time 3.69 seconds
Started Jul 18 06:29:42 PM PDT 24
Finished Jul 18 06:29:50 PM PDT 24
Peak memory 214824 kb
Host smart-8fecf518-7b86-4427-9748-4d3765e23563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97749398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.97749398
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.1078267416
Short name T576
Test name
Test status
Simulation time 1699171210 ps
CPU time 13.79 seconds
Started Jul 18 06:29:37 PM PDT 24
Finished Jul 18 06:29:55 PM PDT 24
Peak memory 208600 kb
Host smart-4722f6db-dfa3-487f-af27-97640dbf52e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078267416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1078267416
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.3972575846
Short name T693
Test name
Test status
Simulation time 37573660 ps
CPU time 2.56 seconds
Started Jul 18 06:29:41 PM PDT 24
Finished Jul 18 06:29:48 PM PDT 24
Peak memory 208204 kb
Host smart-1ed092ac-e382-4dbc-b990-4163019fb7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972575846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.3972575846
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.2169236437
Short name T452
Test name
Test status
Simulation time 124257329 ps
CPU time 3.33 seconds
Started Jul 18 06:29:36 PM PDT 24
Finished Jul 18 06:29:43 PM PDT 24
Peak memory 206716 kb
Host smart-6b043741-8b82-4b9c-9d6d-6b9572cbb2cf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169236437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2169236437
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.2083468709
Short name T704
Test name
Test status
Simulation time 213852540 ps
CPU time 3.09 seconds
Started Jul 18 06:29:39 PM PDT 24
Finished Jul 18 06:29:47 PM PDT 24
Peak memory 206748 kb
Host smart-f5257956-f249-4e4a-820b-fb0d8e352021
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083468709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.2083468709
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.1982125708
Short name T800
Test name
Test status
Simulation time 411643482 ps
CPU time 2.34 seconds
Started Jul 18 06:29:37 PM PDT 24
Finished Jul 18 06:29:43 PM PDT 24
Peak memory 207308 kb
Host smart-2e0316ad-0a18-4e16-aad3-91abd88e89b6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982125708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.1982125708
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.3664158449
Short name T887
Test name
Test status
Simulation time 25249181 ps
CPU time 2.11 seconds
Started Jul 18 06:29:38 PM PDT 24
Finished Jul 18 06:29:45 PM PDT 24
Peak memory 208216 kb
Host smart-bc49bbd9-c9a6-424e-a0aa-8cb802ed099e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664158449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.3664158449
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.1468080801
Short name T456
Test name
Test status
Simulation time 114683313 ps
CPU time 2.52 seconds
Started Jul 18 06:29:32 PM PDT 24
Finished Jul 18 06:29:36 PM PDT 24
Peak memory 208204 kb
Host smart-68c6fc3f-9c2a-499f-931c-c192bb1e729c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468080801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.1468080801
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.2040592502
Short name T850
Test name
Test status
Simulation time 2220975420 ps
CPU time 36.3 seconds
Started Jul 18 06:29:37 PM PDT 24
Finished Jul 18 06:30:17 PM PDT 24
Peak memory 216252 kb
Host smart-92cf4787-0527-44cb-9c8c-d28cc51c388d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040592502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.2040592502
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.2123636986
Short name T667
Test name
Test status
Simulation time 281301896 ps
CPU time 19.11 seconds
Started Jul 18 06:29:38 PM PDT 24
Finished Jul 18 06:30:02 PM PDT 24
Peak memory 222412 kb
Host smart-4a58b868-debb-42af-92d2-cb47591fa96d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123636986 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.2123636986
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.1166098141
Short name T897
Test name
Test status
Simulation time 1660166039 ps
CPU time 20.13 seconds
Started Jul 18 06:29:42 PM PDT 24
Finished Jul 18 06:30:07 PM PDT 24
Peak memory 210232 kb
Host smart-5800496a-c9d2-435f-9b2a-3961fc0aeb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166098141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.1166098141
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.3187183130
Short name T167
Test name
Test status
Simulation time 59813954 ps
CPU time 2.6 seconds
Started Jul 18 06:29:38 PM PDT 24
Finished Jul 18 06:29:45 PM PDT 24
Peak memory 209616 kb
Host smart-fc072d7c-fbf6-4e82-af8a-305bd39ca788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187183130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.3187183130
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.1280404833
Short name T635
Test name
Test status
Simulation time 13910410 ps
CPU time 0.8 seconds
Started Jul 18 06:29:41 PM PDT 24
Finished Jul 18 06:29:47 PM PDT 24
Peak memory 205840 kb
Host smart-740dcf44-3df2-479e-b4ae-444ba29b5e25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280404833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.1280404833
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.3698776371
Short name T900
Test name
Test status
Simulation time 95284969 ps
CPU time 2.59 seconds
Started Jul 18 06:29:42 PM PDT 24
Finished Jul 18 06:29:49 PM PDT 24
Peak memory 222532 kb
Host smart-22fd4e94-a881-40a1-95e4-ced55f40e68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698776371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.3698776371
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.2097813182
Short name T463
Test name
Test status
Simulation time 259186712 ps
CPU time 2.09 seconds
Started Jul 18 06:29:35 PM PDT 24
Finished Jul 18 06:29:40 PM PDT 24
Peak memory 207308 kb
Host smart-78a013b7-b4c2-4b4b-8626-04e857271756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097813182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.2097813182
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.2697633434
Short name T233
Test name
Test status
Simulation time 898505029 ps
CPU time 6.55 seconds
Started Jul 18 06:29:42 PM PDT 24
Finished Jul 18 06:29:53 PM PDT 24
Peak memory 219772 kb
Host smart-7fb26f3c-0ebe-4aee-966f-054fda3a0418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697633434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.2697633434
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.1693750974
Short name T55
Test name
Test status
Simulation time 973122695 ps
CPU time 3.06 seconds
Started Jul 18 06:29:42 PM PDT 24
Finished Jul 18 06:29:50 PM PDT 24
Peak memory 214028 kb
Host smart-fcb9494a-0855-4737-ad78-501150529f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693750974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.1693750974
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.3164931688
Short name T8
Test name
Test status
Simulation time 235782769 ps
CPU time 3.64 seconds
Started Jul 18 06:29:35 PM PDT 24
Finished Jul 18 06:29:42 PM PDT 24
Peak memory 222396 kb
Host smart-d5a3e031-54b2-4303-8f21-1656475f54a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164931688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3164931688
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.3619845000
Short name T18
Test name
Test status
Simulation time 215830969 ps
CPU time 7.54 seconds
Started Jul 18 06:29:36 PM PDT 24
Finished Jul 18 06:29:47 PM PDT 24
Peak memory 219420 kb
Host smart-a8d0a74a-9546-4b29-b650-0b8473f3456f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619845000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.3619845000
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.2889769612
Short name T379
Test name
Test status
Simulation time 230553824 ps
CPU time 6.82 seconds
Started Jul 18 06:29:40 PM PDT 24
Finished Jul 18 06:29:51 PM PDT 24
Peak memory 208492 kb
Host smart-ee72872e-73b8-4887-8804-97c8e7694660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889769612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2889769612
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.1372004288
Short name T840
Test name
Test status
Simulation time 33057669 ps
CPU time 2.35 seconds
Started Jul 18 06:29:35 PM PDT 24
Finished Jul 18 06:29:40 PM PDT 24
Peak memory 206540 kb
Host smart-31d91bd6-2bcc-4e4c-8e55-6d50eca4c264
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372004288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.1372004288
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.2282531319
Short name T608
Test name
Test status
Simulation time 3722385008 ps
CPU time 24.53 seconds
Started Jul 18 06:29:36 PM PDT 24
Finished Jul 18 06:30:04 PM PDT 24
Peak memory 209044 kb
Host smart-8e58fcfb-dd5d-4db1-a436-5ef5e9487982
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282531319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.2282531319
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.2260397853
Short name T408
Test name
Test status
Simulation time 964958524 ps
CPU time 3.41 seconds
Started Jul 18 06:29:38 PM PDT 24
Finished Jul 18 06:29:46 PM PDT 24
Peak memory 208748 kb
Host smart-b352cbef-9ff4-44b3-aa32-a7f7f3f8c29a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260397853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.2260397853
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.733069352
Short name T327
Test name
Test status
Simulation time 295643478 ps
CPU time 5.95 seconds
Started Jul 18 06:29:35 PM PDT 24
Finished Jul 18 06:29:44 PM PDT 24
Peak memory 208696 kb
Host smart-4860c2da-9383-48b6-af3e-0bd3895567ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733069352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.733069352
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.2209017293
Short name T835
Test name
Test status
Simulation time 161778903 ps
CPU time 2.7 seconds
Started Jul 18 06:29:39 PM PDT 24
Finished Jul 18 06:29:46 PM PDT 24
Peak memory 208000 kb
Host smart-a82750a5-7606-4ab0-86bc-3bed37a03593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209017293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.2209017293
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.3534726183
Short name T118
Test name
Test status
Simulation time 352795591 ps
CPU time 8.44 seconds
Started Jul 18 06:29:41 PM PDT 24
Finished Jul 18 06:29:54 PM PDT 24
Peak memory 222412 kb
Host smart-238b56bc-d488-413b-bc99-3f46b8f2d4f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534726183 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.3534726183
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.2623173345
Short name T226
Test name
Test status
Simulation time 52039386 ps
CPU time 3.08 seconds
Started Jul 18 06:29:42 PM PDT 24
Finished Jul 18 06:29:50 PM PDT 24
Peak memory 208852 kb
Host smart-e3e8ff0a-6358-47f1-95ec-443336f9b816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623173345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.2623173345
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.3528252789
Short name T68
Test name
Test status
Simulation time 900893011 ps
CPU time 20.07 seconds
Started Jul 18 06:29:40 PM PDT 24
Finished Jul 18 06:30:05 PM PDT 24
Peak memory 210496 kb
Host smart-aabdf0fe-21ea-4a04-a32e-57ed41fafec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528252789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.3528252789
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.4270972679
Short name T475
Test name
Test status
Simulation time 73234053 ps
CPU time 0.81 seconds
Started Jul 18 06:29:37 PM PDT 24
Finished Jul 18 06:29:43 PM PDT 24
Peak memory 205812 kb
Host smart-db9468ac-e08f-44fc-ac2d-136d27b38bea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270972679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.4270972679
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.518320843
Short name T361
Test name
Test status
Simulation time 55608077 ps
CPU time 4.37 seconds
Started Jul 18 06:29:41 PM PDT 24
Finished Jul 18 06:29:50 PM PDT 24
Peak memory 214072 kb
Host smart-6c972f39-d906-4d1e-8410-f38a72f25fa9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=518320843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.518320843
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.523467258
Short name T256
Test name
Test status
Simulation time 103455250 ps
CPU time 2.88 seconds
Started Jul 18 06:29:41 PM PDT 24
Finished Jul 18 06:29:49 PM PDT 24
Peak memory 208696 kb
Host smart-f1840a60-543c-40ab-a577-6e5d991a2954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523467258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.523467258
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.3396981101
Short name T812
Test name
Test status
Simulation time 175826424 ps
CPU time 4.3 seconds
Started Jul 18 06:29:41 PM PDT 24
Finished Jul 18 06:29:50 PM PDT 24
Peak memory 209784 kb
Host smart-720cb9a5-cbc3-4fee-8064-879472728375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396981101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.3396981101
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.3438316942
Short name T616
Test name
Test status
Simulation time 53563384 ps
CPU time 2.03 seconds
Started Jul 18 06:29:42 PM PDT 24
Finished Jul 18 06:29:48 PM PDT 24
Peak memory 214024 kb
Host smart-617f7d39-9d84-4989-9123-f016481c2c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438316942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.3438316942
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.786228459
Short name T584
Test name
Test status
Simulation time 80536755 ps
CPU time 2.88 seconds
Started Jul 18 06:29:41 PM PDT 24
Finished Jul 18 06:29:48 PM PDT 24
Peak memory 214040 kb
Host smart-7170a966-30e1-46e3-983b-24820e4d974d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786228459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.786228459
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.284950834
Short name T392
Test name
Test status
Simulation time 144178189 ps
CPU time 4.7 seconds
Started Jul 18 06:29:40 PM PDT 24
Finished Jul 18 06:29:49 PM PDT 24
Peak memory 207336 kb
Host smart-4060ff2c-6c8b-4da5-a8b7-e43bf790810d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284950834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.284950834
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.1003909937
Short name T216
Test name
Test status
Simulation time 112883834 ps
CPU time 4.05 seconds
Started Jul 18 06:29:41 PM PDT 24
Finished Jul 18 06:29:50 PM PDT 24
Peak memory 208216 kb
Host smart-ca2ad051-811b-4a07-afcf-0bec66eac034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003909937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.1003909937
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2807381237
Short name T694
Test name
Test status
Simulation time 56129701 ps
CPU time 3.01 seconds
Started Jul 18 06:29:40 PM PDT 24
Finished Jul 18 06:29:48 PM PDT 24
Peak memory 206696 kb
Host smart-e30cdacc-e34e-4adb-a348-c34c23822bce
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807381237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2807381237
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.1930359764
Short name T94
Test name
Test status
Simulation time 1227991887 ps
CPU time 9.39 seconds
Started Jul 18 06:29:36 PM PDT 24
Finished Jul 18 06:29:49 PM PDT 24
Peak memory 208464 kb
Host smart-49f813e4-e065-4fee-ba43-2b9e112400c8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930359764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.1930359764
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.10902420
Short name T859
Test name
Test status
Simulation time 214388622 ps
CPU time 5.94 seconds
Started Jul 18 06:29:42 PM PDT 24
Finished Jul 18 06:29:53 PM PDT 24
Peak memory 207616 kb
Host smart-3755fa76-196d-448b-abe4-55b4c61e9741
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10902420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.10902420
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.4013275578
Short name T698
Test name
Test status
Simulation time 130228402 ps
CPU time 2.09 seconds
Started Jul 18 06:29:41 PM PDT 24
Finished Jul 18 06:29:48 PM PDT 24
Peak memory 209128 kb
Host smart-6342bdb0-d213-41f3-b94d-c360b7616239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013275578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.4013275578
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.1005748512
Short name T484
Test name
Test status
Simulation time 148947905 ps
CPU time 3.34 seconds
Started Jul 18 06:29:41 PM PDT 24
Finished Jul 18 06:29:49 PM PDT 24
Peak memory 207624 kb
Host smart-5ecf22ea-7425-4e05-8f26-8fda82a62323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005748512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.1005748512
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.2451142009
Short name T805
Test name
Test status
Simulation time 781755163 ps
CPU time 19.6 seconds
Started Jul 18 06:29:34 PM PDT 24
Finished Jul 18 06:29:55 PM PDT 24
Peak memory 208224 kb
Host smart-f03e8c00-c712-42eb-be00-14f22ba55da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451142009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.2451142009
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.2307244648
Short name T207
Test name
Test status
Simulation time 253324391 ps
CPU time 2.93 seconds
Started Jul 18 06:29:40 PM PDT 24
Finished Jul 18 06:29:48 PM PDT 24
Peak memory 209764 kb
Host smart-7a7759f5-d9aa-4a5c-8428-979d8e26b2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307244648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.2307244648
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.1572032698
Short name T626
Test name
Test status
Simulation time 169869750 ps
CPU time 0.8 seconds
Started Jul 18 06:29:54 PM PDT 24
Finished Jul 18 06:29:58 PM PDT 24
Peak memory 205860 kb
Host smart-3b983657-d87e-4a56-9775-6a6548bcbfc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572032698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1572032698
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.4116004589
Short name T291
Test name
Test status
Simulation time 62775009 ps
CPU time 4.09 seconds
Started Jul 18 06:29:51 PM PDT 24
Finished Jul 18 06:29:58 PM PDT 24
Peak memory 214968 kb
Host smart-9ddc5d0d-3ad8-4960-9e83-9491e2ca520b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4116004589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.4116004589
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.1758925750
Short name T752
Test name
Test status
Simulation time 208321248 ps
CPU time 3.09 seconds
Started Jul 18 06:29:55 PM PDT 24
Finished Jul 18 06:30:01 PM PDT 24
Peak memory 214052 kb
Host smart-7bebeb7d-5c20-48c0-ace6-865f6fe2482c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758925750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.1758925750
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.2449273815
Short name T756
Test name
Test status
Simulation time 288270480 ps
CPU time 7.27 seconds
Started Jul 18 06:29:53 PM PDT 24
Finished Jul 18 06:30:03 PM PDT 24
Peak memory 208688 kb
Host smart-4d000168-46cf-422f-a0d0-9ea2ba48f231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449273815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.2449273815
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.1693292259
Short name T304
Test name
Test status
Simulation time 178319646 ps
CPU time 5.62 seconds
Started Jul 18 06:29:51 PM PDT 24
Finished Jul 18 06:29:59 PM PDT 24
Peak memory 214096 kb
Host smart-ef835a07-0d90-4f7f-85d2-c89cd66aaca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693292259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.1693292259
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.210502093
Short name T152
Test name
Test status
Simulation time 71315676 ps
CPU time 1.8 seconds
Started Jul 18 06:29:51 PM PDT 24
Finished Jul 18 06:29:55 PM PDT 24
Peak memory 205948 kb
Host smart-1ac2bd15-10f3-43ab-976b-18332838f980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210502093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.210502093
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.1572735143
Short name T828
Test name
Test status
Simulation time 123629264 ps
CPU time 5.24 seconds
Started Jul 18 06:29:38 PM PDT 24
Finished Jul 18 06:29:48 PM PDT 24
Peak memory 218208 kb
Host smart-ac6759bf-4049-46c1-a4f5-fe99d3e217ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572735143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.1572735143
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.995293512
Short name T212
Test name
Test status
Simulation time 139910968 ps
CPU time 3.07 seconds
Started Jul 18 06:29:37 PM PDT 24
Finished Jul 18 06:29:45 PM PDT 24
Peak memory 206636 kb
Host smart-2d7b638f-0425-4ada-99d5-ab9398eead96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995293512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.995293512
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.665452761
Short name T624
Test name
Test status
Simulation time 77164023 ps
CPU time 3.69 seconds
Started Jul 18 06:29:37 PM PDT 24
Finished Jul 18 06:29:45 PM PDT 24
Peak memory 208856 kb
Host smart-6203beba-0352-487d-b43d-a84f9326a39b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665452761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.665452761
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.1543647923
Short name T706
Test name
Test status
Simulation time 226736151 ps
CPU time 3 seconds
Started Jul 18 06:29:37 PM PDT 24
Finished Jul 18 06:29:44 PM PDT 24
Peak memory 206692 kb
Host smart-1f0edc92-7996-4491-85f5-7947af876d64
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543647923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.1543647923
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.1367112013
Short name T37
Test name
Test status
Simulation time 117137026 ps
CPU time 4.65 seconds
Started Jul 18 06:29:50 PM PDT 24
Finished Jul 18 06:29:56 PM PDT 24
Peak memory 209880 kb
Host smart-42f807c7-982c-45d8-892c-5c12c98dd89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367112013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.1367112013
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.2524351114
Short name T535
Test name
Test status
Simulation time 312931970 ps
CPU time 5.92 seconds
Started Jul 18 06:29:38 PM PDT 24
Finished Jul 18 06:29:49 PM PDT 24
Peak memory 206548 kb
Host smart-c29a8cd7-dc6b-4c87-ad09-17e951599c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524351114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.2524351114
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.473852198
Short name T387
Test name
Test status
Simulation time 21057867053 ps
CPU time 360.35 seconds
Started Jul 18 06:29:49 PM PDT 24
Finished Jul 18 06:35:51 PM PDT 24
Peak memory 222364 kb
Host smart-db8d8d02-8e0c-4b46-87b1-1c7c898424ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473852198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.473852198
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.3478705885
Short name T769
Test name
Test status
Simulation time 514187943 ps
CPU time 10.89 seconds
Started Jul 18 06:29:51 PM PDT 24
Finished Jul 18 06:30:05 PM PDT 24
Peak memory 214132 kb
Host smart-04d55802-5d88-4869-927f-c5f7d3e5803a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478705885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.3478705885
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.302917231
Short name T607
Test name
Test status
Simulation time 33337085 ps
CPU time 1.14 seconds
Started Jul 18 06:29:51 PM PDT 24
Finished Jul 18 06:29:55 PM PDT 24
Peak memory 209460 kb
Host smart-f2adbcc5-c940-4d14-831a-6af0e6bdc02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302917231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.302917231
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.4239309175
Short name T500
Test name
Test status
Simulation time 13796895 ps
CPU time 0.9 seconds
Started Jul 18 06:26:51 PM PDT 24
Finished Jul 18 06:26:57 PM PDT 24
Peak memory 205836 kb
Host smart-e4cd1e51-9c60-4cf5-bd68-285d30bca951
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239309175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.4239309175
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.1203066792
Short name T431
Test name
Test status
Simulation time 97044418 ps
CPU time 4.83 seconds
Started Jul 18 06:26:50 PM PDT 24
Finished Jul 18 06:27:00 PM PDT 24
Peak memory 222248 kb
Host smart-37ceae47-54d8-4d04-81d2-659d2000a757
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1203066792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1203066792
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.3304162339
Short name T325
Test name
Test status
Simulation time 4282170879 ps
CPU time 48.8 seconds
Started Jul 18 06:26:55 PM PDT 24
Finished Jul 18 06:27:49 PM PDT 24
Peak memory 219076 kb
Host smart-5e03e7ba-a292-4b65-86c0-2fa834ae14f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304162339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.3304162339
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.94291303
Short name T764
Test name
Test status
Simulation time 832658364 ps
CPU time 8 seconds
Started Jul 18 06:26:51 PM PDT 24
Finished Jul 18 06:27:03 PM PDT 24
Peak memory 219376 kb
Host smart-69ca33c7-8195-44ae-8b85-1e3fc83c073d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94291303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.94291303
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.3707013240
Short name T342
Test name
Test status
Simulation time 377358774 ps
CPU time 5.27 seconds
Started Jul 18 06:26:54 PM PDT 24
Finished Jul 18 06:27:05 PM PDT 24
Peak memory 221084 kb
Host smart-d7d1f3ad-29a0-4dbe-93f7-8c141243fefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707013240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.3707013240
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.824419086
Short name T344
Test name
Test status
Simulation time 143456444 ps
CPU time 4.24 seconds
Started Jul 18 06:26:50 PM PDT 24
Finished Jul 18 06:26:58 PM PDT 24
Peak memory 222276 kb
Host smart-f8e81edd-44d8-4b36-9362-3d7c3443c6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824419086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.824419086
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.1444109028
Short name T356
Test name
Test status
Simulation time 59106900 ps
CPU time 3.52 seconds
Started Jul 18 06:26:55 PM PDT 24
Finished Jul 18 06:27:04 PM PDT 24
Peak memory 217976 kb
Host smart-3f85c9e4-2c34-404e-bc24-2339f60973b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444109028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.1444109028
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sideload.924893610
Short name T556
Test name
Test status
Simulation time 278102018 ps
CPU time 4.39 seconds
Started Jul 18 06:26:49 PM PDT 24
Finished Jul 18 06:26:57 PM PDT 24
Peak memory 208632 kb
Host smart-3c6256ed-22f9-418f-9292-d9a38f6b7c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924893610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.924893610
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.2483039421
Short name T210
Test name
Test status
Simulation time 2738985620 ps
CPU time 32.6 seconds
Started Jul 18 06:26:56 PM PDT 24
Finished Jul 18 06:27:34 PM PDT 24
Peak memory 208680 kb
Host smart-ba1e1ce6-614e-4c84-9c20-f66b3593f1bd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483039421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.2483039421
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.1618886573
Short name T458
Test name
Test status
Simulation time 102975740 ps
CPU time 2.75 seconds
Started Jul 18 06:26:49 PM PDT 24
Finished Jul 18 06:26:55 PM PDT 24
Peak memory 206652 kb
Host smart-381738ff-7bab-4b87-8d5b-5a5c79e31cb6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618886573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.1618886573
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.4260225747
Short name T762
Test name
Test status
Simulation time 534984077 ps
CPU time 4.93 seconds
Started Jul 18 06:26:55 PM PDT 24
Finished Jul 18 06:27:05 PM PDT 24
Peak memory 206692 kb
Host smart-5a085c0d-ee07-413e-803b-4c7a2b3e674b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260225747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.4260225747
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.1525820769
Short name T372
Test name
Test status
Simulation time 1248639518 ps
CPU time 15.91 seconds
Started Jul 18 06:26:55 PM PDT 24
Finished Jul 18 06:27:17 PM PDT 24
Peak memory 208780 kb
Host smart-79a5e0d6-7165-441f-a357-899bf3761804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525820769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.1525820769
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.709268364
Short name T721
Test name
Test status
Simulation time 67542151 ps
CPU time 3.21 seconds
Started Jul 18 06:26:56 PM PDT 24
Finished Jul 18 06:27:05 PM PDT 24
Peak memory 207860 kb
Host smart-466ff969-921f-4403-bbc9-9180f6f1b262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709268364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.709268364
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.4053760712
Short name T605
Test name
Test status
Simulation time 107114597 ps
CPU time 5.85 seconds
Started Jul 18 06:26:53 PM PDT 24
Finished Jul 18 06:27:04 PM PDT 24
Peak memory 222400 kb
Host smart-89b7344b-bb17-4dae-ae21-9ea4ef8cafb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053760712 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.4053760712
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.3723707968
Short name T115
Test name
Test status
Simulation time 919310999 ps
CPU time 11.54 seconds
Started Jul 18 06:26:50 PM PDT 24
Finished Jul 18 06:27:05 PM PDT 24
Peak memory 209976 kb
Host smart-72fe34ea-af6e-47e4-b1e7-aadb249ff35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723707968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.3723707968
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.4197156306
Short name T749
Test name
Test status
Simulation time 338191079 ps
CPU time 3.45 seconds
Started Jul 18 06:26:55 PM PDT 24
Finished Jul 18 06:27:04 PM PDT 24
Peak memory 210312 kb
Host smart-292ff366-38cf-48d2-9fa3-ed5df6ded45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197156306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.4197156306
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.166127811
Short name T486
Test name
Test status
Simulation time 13713136 ps
CPU time 0.77 seconds
Started Jul 18 06:29:52 PM PDT 24
Finished Jul 18 06:29:56 PM PDT 24
Peak memory 205816 kb
Host smart-641d6ecb-2f73-4d96-a417-0e38a225ac07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166127811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.166127811
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.3640790124
Short name T29
Test name
Test status
Simulation time 38134525 ps
CPU time 2.43 seconds
Started Jul 18 06:29:53 PM PDT 24
Finished Jul 18 06:29:59 PM PDT 24
Peak memory 214464 kb
Host smart-532486ff-4c28-41b9-9a7d-8e94f32b59af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640790124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.3640790124
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.3101543395
Short name T912
Test name
Test status
Simulation time 29169987 ps
CPU time 1.68 seconds
Started Jul 18 06:29:51 PM PDT 24
Finished Jul 18 06:29:56 PM PDT 24
Peak memory 207140 kb
Host smart-467ebb3c-df7c-4bdc-9b56-9d59328b70cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101543395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3101543395
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.3466246627
Short name T286
Test name
Test status
Simulation time 101069164 ps
CPU time 2.47 seconds
Started Jul 18 06:29:50 PM PDT 24
Finished Jul 18 06:29:55 PM PDT 24
Peak memory 214716 kb
Host smart-9f35754c-eba7-4177-aabe-3906713ea14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466246627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3466246627
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.3519022513
Short name T293
Test name
Test status
Simulation time 129791457 ps
CPU time 3.73 seconds
Started Jul 18 06:29:49 PM PDT 24
Finished Jul 18 06:29:55 PM PDT 24
Peak memory 214080 kb
Host smart-972bb5bd-6e66-4110-b11e-4cc4ec7708d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519022513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.3519022513
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.1796882483
Short name T868
Test name
Test status
Simulation time 32787297 ps
CPU time 2.48 seconds
Started Jul 18 06:29:49 PM PDT 24
Finished Jul 18 06:29:54 PM PDT 24
Peak memory 208900 kb
Host smart-88355318-a4de-4a87-a237-57a3202f6fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796882483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1796882483
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.2137071667
Short name T227
Test name
Test status
Simulation time 60858042 ps
CPU time 3.01 seconds
Started Jul 18 06:29:51 PM PDT 24
Finished Jul 18 06:29:57 PM PDT 24
Peak memory 207728 kb
Host smart-83fa0774-e119-47c8-bc93-9967654ca5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137071667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.2137071667
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.3914174680
Short name T229
Test name
Test status
Simulation time 176951936 ps
CPU time 2.51 seconds
Started Jul 18 06:29:54 PM PDT 24
Finished Jul 18 06:29:59 PM PDT 24
Peak memory 206672 kb
Host smart-3b771613-1ec6-4354-8fee-2062be53ee6d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914174680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.3914174680
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.1612596263
Short name T543
Test name
Test status
Simulation time 182486384 ps
CPU time 5.62 seconds
Started Jul 18 06:29:49 PM PDT 24
Finished Jul 18 06:29:57 PM PDT 24
Peak memory 207976 kb
Host smart-45628586-d4a5-4770-b5c3-6606cc144e2d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612596263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.1612596263
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.2761403904
Short name T480
Test name
Test status
Simulation time 26436591 ps
CPU time 2.2 seconds
Started Jul 18 06:29:53 PM PDT 24
Finished Jul 18 06:29:58 PM PDT 24
Peak memory 208480 kb
Host smart-b4712bfd-c591-4f03-9c88-fd8f8b77ee28
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761403904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.2761403904
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.2218784790
Short name T572
Test name
Test status
Simulation time 84449633 ps
CPU time 2.06 seconds
Started Jul 18 06:29:55 PM PDT 24
Finished Jul 18 06:30:00 PM PDT 24
Peak memory 209388 kb
Host smart-dccf62d7-2f68-4915-996e-481f341b0cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218784790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.2218784790
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.213157918
Short name T467
Test name
Test status
Simulation time 362682241 ps
CPU time 4.56 seconds
Started Jul 18 06:29:51 PM PDT 24
Finished Jul 18 06:29:58 PM PDT 24
Peak memory 206648 kb
Host smart-b96b5a46-8d77-4426-85b6-cc0a2dc3846f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213157918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.213157918
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.839230240
Short name T368
Test name
Test status
Simulation time 169309908 ps
CPU time 4.09 seconds
Started Jul 18 06:29:51 PM PDT 24
Finished Jul 18 06:29:58 PM PDT 24
Peak memory 220076 kb
Host smart-94a9bca3-d435-4421-b838-168068fac20d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839230240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.839230240
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.21476194
Short name T712
Test name
Test status
Simulation time 111248441 ps
CPU time 4.81 seconds
Started Jul 18 06:29:50 PM PDT 24
Finished Jul 18 06:29:57 PM PDT 24
Peak memory 219500 kb
Host smart-7df7af80-d662-46b6-b85e-1c2b19d5c210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21476194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.21476194
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.891288609
Short name T397
Test name
Test status
Simulation time 37321249 ps
CPU time 2.29 seconds
Started Jul 18 06:29:49 PM PDT 24
Finished Jul 18 06:29:53 PM PDT 24
Peak memory 209980 kb
Host smart-3cb22c94-d624-4b4e-b081-7d166841fbad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891288609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.891288609
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.461074891
Short name T441
Test name
Test status
Simulation time 48958946 ps
CPU time 0.97 seconds
Started Jul 18 06:29:50 PM PDT 24
Finished Jul 18 06:29:53 PM PDT 24
Peak memory 205848 kb
Host smart-08a898f7-29d7-429d-831c-4d59cde59f17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461074891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.461074891
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.2661330790
Short name T80
Test name
Test status
Simulation time 52615618 ps
CPU time 2.76 seconds
Started Jul 18 06:29:53 PM PDT 24
Finished Jul 18 06:29:59 PM PDT 24
Peak memory 207444 kb
Host smart-00c9eea6-7900-4e5f-aa7c-022936e21c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661330790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.2661330790
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.1162507373
Short name T827
Test name
Test status
Simulation time 306853465 ps
CPU time 2.98 seconds
Started Jul 18 06:29:53 PM PDT 24
Finished Jul 18 06:29:59 PM PDT 24
Peak memory 214276 kb
Host smart-3eaf7f48-4236-4adf-9a47-22821e7c6162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162507373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.1162507373
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.3129463621
Short name T794
Test name
Test status
Simulation time 2033324138 ps
CPU time 5.82 seconds
Started Jul 18 06:29:50 PM PDT 24
Finished Jul 18 06:29:57 PM PDT 24
Peak memory 222148 kb
Host smart-412e0517-d8c3-488b-b6ea-8affbf51a575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129463621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.3129463621
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.180106338
Short name T907
Test name
Test status
Simulation time 55306756 ps
CPU time 2.67 seconds
Started Jul 18 06:29:51 PM PDT 24
Finished Jul 18 06:29:57 PM PDT 24
Peak memory 215168 kb
Host smart-bdf2041b-1ada-4264-bbdc-15ab4ab56aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180106338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.180106338
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.1201100760
Short name T357
Test name
Test status
Simulation time 7497465169 ps
CPU time 45.22 seconds
Started Jul 18 06:29:49 PM PDT 24
Finished Jul 18 06:30:36 PM PDT 24
Peak memory 218280 kb
Host smart-283c009e-1d76-4b59-997f-e2b74171cbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201100760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.1201100760
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.1818536409
Short name T181
Test name
Test status
Simulation time 76483231 ps
CPU time 2.68 seconds
Started Jul 18 06:29:48 PM PDT 24
Finished Jul 18 06:29:53 PM PDT 24
Peak memory 206660 kb
Host smart-a1bdfadc-27fd-4976-adbd-5686b7a69ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818536409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.1818536409
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.2502830991
Short name T573
Test name
Test status
Simulation time 233312961 ps
CPU time 6.55 seconds
Started Jul 18 06:29:54 PM PDT 24
Finished Jul 18 06:30:04 PM PDT 24
Peak memory 207836 kb
Host smart-92b5439a-b8f4-4aa4-b088-6467aa352c09
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502830991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.2502830991
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.636151933
Short name T314
Test name
Test status
Simulation time 76946432 ps
CPU time 3.59 seconds
Started Jul 18 06:29:52 PM PDT 24
Finished Jul 18 06:29:59 PM PDT 24
Peak memory 208696 kb
Host smart-4f4a3ac3-b170-4cf2-beb7-62cab4748a47
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636151933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.636151933
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.1536447412
Short name T300
Test name
Test status
Simulation time 29891146 ps
CPU time 2.19 seconds
Started Jul 18 06:29:54 PM PDT 24
Finished Jul 18 06:29:59 PM PDT 24
Peak memory 206688 kb
Host smart-1714d864-7a50-4448-91a9-c433d3ee98a7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536447412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.1536447412
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.1852644464
Short name T628
Test name
Test status
Simulation time 126838014 ps
CPU time 1.65 seconds
Started Jul 18 06:29:54 PM PDT 24
Finished Jul 18 06:29:58 PM PDT 24
Peak memory 207256 kb
Host smart-7d43d39b-a21c-41d1-b7aa-f90c0c5d2d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852644464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1852644464
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.2388686833
Short name T842
Test name
Test status
Simulation time 417554916 ps
CPU time 5.74 seconds
Started Jul 18 06:29:50 PM PDT 24
Finished Jul 18 06:29:59 PM PDT 24
Peak memory 207716 kb
Host smart-6d526e7e-92bc-48fd-8a9c-bdc9a18f8cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388686833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.2388686833
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.3673101332
Short name T319
Test name
Test status
Simulation time 2045818602 ps
CPU time 67.24 seconds
Started Jul 18 06:29:50 PM PDT 24
Finished Jul 18 06:31:00 PM PDT 24
Peak memory 222224 kb
Host smart-7911ab54-0852-42db-842f-17c7e541fa65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673101332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.3673101332
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.3452705108
Short name T92
Test name
Test status
Simulation time 1714724034 ps
CPU time 12.11 seconds
Started Jul 18 06:29:53 PM PDT 24
Finished Jul 18 06:30:08 PM PDT 24
Peak memory 207984 kb
Host smart-b4114860-4c46-4426-b576-cb6c5d5fdd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452705108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.3452705108
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.385609126
Short name T67
Test name
Test status
Simulation time 106828599 ps
CPU time 3.82 seconds
Started Jul 18 06:29:52 PM PDT 24
Finished Jul 18 06:29:59 PM PDT 24
Peak memory 209584 kb
Host smart-3923e96f-191c-4b44-ae4d-73c491686e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385609126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.385609126
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.1236424992
Short name T747
Test name
Test status
Simulation time 11064208 ps
CPU time 0.91 seconds
Started Jul 18 06:30:10 PM PDT 24
Finished Jul 18 06:30:12 PM PDT 24
Peak memory 205840 kb
Host smart-af858ccc-1f01-47dd-8910-a26da5b8956f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236424992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1236424992
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.3252938877
Short name T262
Test name
Test status
Simulation time 257745360 ps
CPU time 11.59 seconds
Started Jul 18 06:30:15 PM PDT 24
Finished Jul 18 06:30:29 PM PDT 24
Peak memory 214180 kb
Host smart-36b67c70-474a-4d5a-a76e-dd964860e3d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3252938877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.3252938877
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.2014319898
Short name T11
Test name
Test status
Simulation time 136929605 ps
CPU time 4.14 seconds
Started Jul 18 06:30:11 PM PDT 24
Finished Jul 18 06:30:18 PM PDT 24
Peak memory 209096 kb
Host smart-98466b2e-659f-47f3-aa21-d01d7a37c8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014319898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2014319898
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.840942188
Short name T322
Test name
Test status
Simulation time 161956976 ps
CPU time 5.89 seconds
Started Jul 18 06:30:11 PM PDT 24
Finished Jul 18 06:30:18 PM PDT 24
Peak memory 209084 kb
Host smart-7163a97e-0971-47bb-93f5-0c7baf910cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840942188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.840942188
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.708917766
Short name T100
Test name
Test status
Simulation time 34040750 ps
CPU time 2.34 seconds
Started Jul 18 06:30:11 PM PDT 24
Finished Jul 18 06:30:16 PM PDT 24
Peak memory 214096 kb
Host smart-886aecd9-f1c2-4e92-8a25-9338e6a47bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708917766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.708917766
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.1329585090
Short name T875
Test name
Test status
Simulation time 188172073 ps
CPU time 4.76 seconds
Started Jul 18 06:30:11 PM PDT 24
Finished Jul 18 06:30:17 PM PDT 24
Peak memory 214028 kb
Host smart-bdd21a84-c9f0-4bbb-b432-be5396288d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329585090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.1329585090
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.696064516
Short name T461
Test name
Test status
Simulation time 73130160 ps
CPU time 2.91 seconds
Started Jul 18 06:30:10 PM PDT 24
Finished Jul 18 06:30:14 PM PDT 24
Peak memory 219704 kb
Host smart-74ca2d63-503e-451f-a47d-d3e71c695e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696064516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.696064516
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2766137370
Short name T715
Test name
Test status
Simulation time 177108994 ps
CPU time 3.85 seconds
Started Jul 18 06:30:11 PM PDT 24
Finished Jul 18 06:30:17 PM PDT 24
Peak memory 214060 kb
Host smart-1a3f692c-3bf6-4ada-b115-37821abecf3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766137370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2766137370
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.3877840844
Short name T302
Test name
Test status
Simulation time 69562685 ps
CPU time 2.88 seconds
Started Jul 18 06:30:09 PM PDT 24
Finished Jul 18 06:30:13 PM PDT 24
Peak memory 208636 kb
Host smart-14e0bbf4-10f6-4aad-8e1b-711b8a2966b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877840844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.3877840844
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.2112443382
Short name T863
Test name
Test status
Simulation time 557392233 ps
CPU time 5.73 seconds
Started Jul 18 06:30:11 PM PDT 24
Finished Jul 18 06:30:19 PM PDT 24
Peak memory 208000 kb
Host smart-6593f0ab-c34f-49d1-9fa1-3cece30ff0a2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112443382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.2112443382
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.68895058
Short name T3
Test name
Test status
Simulation time 278959864 ps
CPU time 3.52 seconds
Started Jul 18 06:30:12 PM PDT 24
Finished Jul 18 06:30:19 PM PDT 24
Peak memory 208660 kb
Host smart-d75ddeb3-6057-4683-bec0-85ed35e61417
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68895058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.68895058
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.874573667
Short name T621
Test name
Test status
Simulation time 256500956 ps
CPU time 2.54 seconds
Started Jul 18 06:30:16 PM PDT 24
Finished Jul 18 06:30:21 PM PDT 24
Peak memory 206728 kb
Host smart-8c8713da-b6a6-46ad-9cc9-3a970da1b32a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874573667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.874573667
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.1459363426
Short name T813
Test name
Test status
Simulation time 105317919 ps
CPU time 2.46 seconds
Started Jul 18 06:30:15 PM PDT 24
Finished Jul 18 06:30:20 PM PDT 24
Peak memory 214060 kb
Host smart-ca3eb25d-0d2d-4519-87ad-65cd78dc7b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459363426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.1459363426
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.579402293
Short name T661
Test name
Test status
Simulation time 5595953172 ps
CPU time 25.07 seconds
Started Jul 18 06:29:52 PM PDT 24
Finished Jul 18 06:30:20 PM PDT 24
Peak memory 207724 kb
Host smart-62974c6b-8bf4-4bf9-a8e5-dd018daa18f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579402293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.579402293
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.2064686524
Short name T899
Test name
Test status
Simulation time 1191817393 ps
CPU time 44.88 seconds
Started Jul 18 06:30:12 PM PDT 24
Finished Jul 18 06:31:00 PM PDT 24
Peak memory 222240 kb
Host smart-9426e425-db4b-4111-8260-3d803b4df110
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064686524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.2064686524
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.1414166043
Short name T519
Test name
Test status
Simulation time 403206214 ps
CPU time 3.11 seconds
Started Jul 18 06:30:12 PM PDT 24
Finished Jul 18 06:30:19 PM PDT 24
Peak memory 218180 kb
Host smart-4088998f-7aa8-41cb-b9ce-b42e8c251642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414166043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.1414166043
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.2193163996
Short name T417
Test name
Test status
Simulation time 172694620 ps
CPU time 4.8 seconds
Started Jul 18 06:30:12 PM PDT 24
Finished Jul 18 06:30:21 PM PDT 24
Peak memory 210032 kb
Host smart-0aed81c5-8e6a-4e8c-b0ed-7a093fcf1546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193163996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.2193163996
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.3878658999
Short name T2
Test name
Test status
Simulation time 79276345 ps
CPU time 0.99 seconds
Started Jul 18 06:30:12 PM PDT 24
Finished Jul 18 06:30:17 PM PDT 24
Peak memory 205920 kb
Host smart-974f3889-0653-4278-b194-f016d4b8fe52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878658999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.3878658999
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.2895688578
Short name T32
Test name
Test status
Simulation time 264484270 ps
CPU time 2.87 seconds
Started Jul 18 06:30:11 PM PDT 24
Finished Jul 18 06:30:17 PM PDT 24
Peak memory 214964 kb
Host smart-0365df31-5827-4220-8c99-8f8d41d13678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895688578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.2895688578
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.2754376869
Short name T788
Test name
Test status
Simulation time 237327684 ps
CPU time 6.75 seconds
Started Jul 18 06:30:11 PM PDT 24
Finished Jul 18 06:30:19 PM PDT 24
Peak memory 208588 kb
Host smart-878f230e-be2c-4e34-bf1c-1436a7fcbc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754376869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.2754376869
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.1407255936
Short name T802
Test name
Test status
Simulation time 1541460927 ps
CPU time 5.94 seconds
Started Jul 18 06:30:11 PM PDT 24
Finished Jul 18 06:30:21 PM PDT 24
Peak memory 214064 kb
Host smart-4ae54ddb-e20b-4eb1-a01b-5cdfae8bdf49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407255936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.1407255936
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.3102858823
Short name T473
Test name
Test status
Simulation time 622477241 ps
CPU time 6.84 seconds
Started Jul 18 06:30:13 PM PDT 24
Finished Jul 18 06:30:23 PM PDT 24
Peak memory 209572 kb
Host smart-c6cba5e2-5566-42bd-9348-3c6b68032e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102858823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3102858823
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.4038472578
Short name T615
Test name
Test status
Simulation time 95465639 ps
CPU time 4.63 seconds
Started Jul 18 06:30:13 PM PDT 24
Finished Jul 18 06:30:21 PM PDT 24
Peak memory 207344 kb
Host smart-a6f4171e-dd12-4768-bffc-a2e3dc683056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038472578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.4038472578
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.2492632007
Short name T830
Test name
Test status
Simulation time 160485456 ps
CPU time 4.95 seconds
Started Jul 18 06:30:11 PM PDT 24
Finished Jul 18 06:30:17 PM PDT 24
Peak memory 207892 kb
Host smart-0016c062-191b-48da-9755-919b0da41a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492632007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.2492632007
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.1036762833
Short name T518
Test name
Test status
Simulation time 322932758 ps
CPU time 8.45 seconds
Started Jul 18 06:30:12 PM PDT 24
Finished Jul 18 06:30:24 PM PDT 24
Peak memory 207744 kb
Host smart-2c69eb31-cf46-4d3e-827a-e9427879b8e6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036762833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.1036762833
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.1468918884
Short name T631
Test name
Test status
Simulation time 3688188174 ps
CPU time 44.09 seconds
Started Jul 18 06:30:11 PM PDT 24
Finished Jul 18 06:30:57 PM PDT 24
Peak memory 208204 kb
Host smart-f4e238b8-251b-4eeb-b20c-f79b255a3d04
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468918884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.1468918884
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.1501986218
Short name T544
Test name
Test status
Simulation time 55925401 ps
CPU time 2.86 seconds
Started Jul 18 06:30:16 PM PDT 24
Finished Jul 18 06:30:22 PM PDT 24
Peak memory 207416 kb
Host smart-8191c901-b293-4bee-851e-7d3fcadc20bf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501986218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.1501986218
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.234944016
Short name T503
Test name
Test status
Simulation time 2655038155 ps
CPU time 16.18 seconds
Started Jul 18 06:30:13 PM PDT 24
Finished Jul 18 06:30:33 PM PDT 24
Peak memory 214272 kb
Host smart-bf311df4-5949-43d3-83c5-f8328e009a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234944016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.234944016
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.3479852451
Short name T909
Test name
Test status
Simulation time 907892593 ps
CPU time 3.29 seconds
Started Jul 18 06:30:13 PM PDT 24
Finished Jul 18 06:30:20 PM PDT 24
Peak memory 208292 kb
Host smart-2c636d64-dfaf-4ef1-95b3-b01235f865f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479852451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.3479852451
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.346830193
Short name T134
Test name
Test status
Simulation time 511422586 ps
CPU time 18.76 seconds
Started Jul 18 06:30:11 PM PDT 24
Finished Jul 18 06:30:31 PM PDT 24
Peak memory 222008 kb
Host smart-72b10395-9e78-42c9-99f3-c4d027fc7447
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346830193 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.346830193
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.883730926
Short name T678
Test name
Test status
Simulation time 104009267 ps
CPU time 2.8 seconds
Started Jul 18 06:30:14 PM PDT 24
Finished Jul 18 06:30:20 PM PDT 24
Peak memory 207760 kb
Host smart-4d5e0537-60e7-4c5f-ab37-9371a1608df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883730926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.883730926
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.1443834932
Short name T396
Test name
Test status
Simulation time 141153679 ps
CPU time 1.72 seconds
Started Jul 18 06:30:16 PM PDT 24
Finished Jul 18 06:30:21 PM PDT 24
Peak memory 209384 kb
Host smart-26734cbe-97ae-4395-8946-2190d9a88dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443834932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1443834932
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.2239266213
Short name T474
Test name
Test status
Simulation time 52701490 ps
CPU time 0.75 seconds
Started Jul 18 06:30:33 PM PDT 24
Finished Jul 18 06:30:39 PM PDT 24
Peak memory 205880 kb
Host smart-80e4ce67-ef60-4e7c-bfb4-c02243604d19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239266213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2239266213
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.2396713783
Short name T124
Test name
Test status
Simulation time 1527255538 ps
CPU time 5.02 seconds
Started Jul 18 06:30:12 PM PDT 24
Finished Jul 18 06:30:21 PM PDT 24
Peak memory 214144 kb
Host smart-1aec5b76-593c-4563-9553-ae6ca4210cbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2396713783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.2396713783
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.3493532951
Short name T21
Test name
Test status
Simulation time 274508686 ps
CPU time 2.92 seconds
Started Jul 18 06:30:11 PM PDT 24
Finished Jul 18 06:30:17 PM PDT 24
Peak memory 208624 kb
Host smart-d43cae4b-2b93-4968-b9bd-655c554974c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493532951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3493532951
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.2272071671
Short name T510
Test name
Test status
Simulation time 247921486 ps
CPU time 2.21 seconds
Started Jul 18 06:30:17 PM PDT 24
Finished Jul 18 06:30:22 PM PDT 24
Peak memory 213740 kb
Host smart-94954016-df8f-4075-a3f2-252107471179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272071671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.2272071671
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.3039993894
Short name T675
Test name
Test status
Simulation time 79947801 ps
CPU time 2.85 seconds
Started Jul 18 06:30:10 PM PDT 24
Finished Jul 18 06:30:13 PM PDT 24
Peak memory 214072 kb
Host smart-238448b2-ecb0-4674-94a0-617f8baba131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039993894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.3039993894
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.2841675433
Short name T49
Test name
Test status
Simulation time 33151116 ps
CPU time 2.53 seconds
Started Jul 18 06:30:12 PM PDT 24
Finished Jul 18 06:30:18 PM PDT 24
Peak memory 207404 kb
Host smart-72c49317-61d5-4100-ac53-1cb3f227dce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841675433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.2841675433
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.1538881677
Short name T753
Test name
Test status
Simulation time 1970792308 ps
CPU time 12.78 seconds
Started Jul 18 06:30:11 PM PDT 24
Finished Jul 18 06:30:28 PM PDT 24
Peak memory 218108 kb
Host smart-2325ecbd-12e4-4182-84a6-4966fb0e7da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538881677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1538881677
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.3433094893
Short name T908
Test name
Test status
Simulation time 177985097 ps
CPU time 2.54 seconds
Started Jul 18 06:30:10 PM PDT 24
Finished Jul 18 06:30:13 PM PDT 24
Peak memory 207180 kb
Host smart-a47d4a97-4564-4e79-b6bd-0171386b199e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433094893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.3433094893
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1905409871
Short name T589
Test name
Test status
Simulation time 43791795 ps
CPU time 2.59 seconds
Started Jul 18 06:30:12 PM PDT 24
Finished Jul 18 06:30:18 PM PDT 24
Peak memory 206720 kb
Host smart-62bcf422-b6f7-4dbb-b299-2a29a8e42e21
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905409871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1905409871
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.4236484304
Short name T695
Test name
Test status
Simulation time 42187336 ps
CPU time 1.77 seconds
Started Jul 18 06:30:11 PM PDT 24
Finished Jul 18 06:30:15 PM PDT 24
Peak memory 206688 kb
Host smart-63836030-db6b-4b35-b973-35813c9ab39d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236484304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.4236484304
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.3128902379
Short name T682
Test name
Test status
Simulation time 536905103 ps
CPU time 4.53 seconds
Started Jul 18 06:30:11 PM PDT 24
Finished Jul 18 06:30:19 PM PDT 24
Peak memory 208532 kb
Host smart-6338717a-73be-4d12-b604-cf99b0eba881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128902379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.3128902379
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.2389831160
Short name T858
Test name
Test status
Simulation time 587347993 ps
CPU time 7.58 seconds
Started Jul 18 06:30:16 PM PDT 24
Finished Jul 18 06:30:27 PM PDT 24
Peak memory 207180 kb
Host smart-69137698-6611-46bd-b33a-96f81aef441d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389831160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.2389831160
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.2785889851
Short name T259
Test name
Test status
Simulation time 169602799 ps
CPU time 8.37 seconds
Started Jul 18 06:30:12 PM PDT 24
Finished Jul 18 06:30:24 PM PDT 24
Peak memory 216284 kb
Host smart-ab63092b-64c6-4d35-a941-0189f8a9732b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785889851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.2785889851
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.4291309280
Short name T177
Test name
Test status
Simulation time 353388126 ps
CPU time 9.26 seconds
Started Jul 18 06:30:34 PM PDT 24
Finished Jul 18 06:30:49 PM PDT 24
Peak memory 222500 kb
Host smart-30f0b295-0644-4f9c-81f8-1f834f62f976
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291309280 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.4291309280
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.853291522
Short name T792
Test name
Test status
Simulation time 1598297316 ps
CPU time 11.79 seconds
Started Jul 18 06:30:17 PM PDT 24
Finished Jul 18 06:30:31 PM PDT 24
Peak memory 213972 kb
Host smart-a4e97be7-de0f-45f0-a2dc-162b96be6f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853291522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.853291522
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.251505453
Short name T63
Test name
Test status
Simulation time 86539421 ps
CPU time 1.63 seconds
Started Jul 18 06:30:13 PM PDT 24
Finished Jul 18 06:30:18 PM PDT 24
Peak memory 209748 kb
Host smart-8f4a1fb7-7e70-42e7-b557-743dc6e723b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251505453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.251505453
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.2931798369
Short name T443
Test name
Test status
Simulation time 22508390 ps
CPU time 0.7 seconds
Started Jul 18 06:30:34 PM PDT 24
Finished Jul 18 06:30:42 PM PDT 24
Peak memory 205856 kb
Host smart-9fde1ffa-e305-47c7-be89-ba3531c39911
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931798369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2931798369
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.600100443
Short name T141
Test name
Test status
Simulation time 594207238 ps
CPU time 7.95 seconds
Started Jul 18 06:30:36 PM PDT 24
Finished Jul 18 06:30:52 PM PDT 24
Peak memory 222160 kb
Host smart-db5a8bca-1c59-44ab-893d-63ff4838003b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=600100443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.600100443
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.2000945043
Short name T529
Test name
Test status
Simulation time 418677657 ps
CPU time 7.82 seconds
Started Jul 18 06:30:34 PM PDT 24
Finished Jul 18 06:30:49 PM PDT 24
Peak memory 215932 kb
Host smart-0905f123-d717-4905-ae29-d694d78032fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000945043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.2000945043
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.3510188011
Short name T658
Test name
Test status
Simulation time 1945924250 ps
CPU time 13.83 seconds
Started Jul 18 06:30:39 PM PDT 24
Finished Jul 18 06:31:01 PM PDT 24
Peak memory 214024 kb
Host smart-6841ca40-4df2-49b5-8826-f1a0d5cabc16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510188011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.3510188011
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.947350231
Short name T366
Test name
Test status
Simulation time 66840225 ps
CPU time 2.71 seconds
Started Jul 18 06:30:32 PM PDT 24
Finished Jul 18 06:30:38 PM PDT 24
Peak memory 214072 kb
Host smart-35646303-bb36-4d77-a34a-7e17588ffbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947350231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.947350231
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.3463512381
Short name T307
Test name
Test status
Simulation time 46048980 ps
CPU time 2.56 seconds
Started Jul 18 06:30:36 PM PDT 24
Finished Jul 18 06:30:47 PM PDT 24
Peak memory 214104 kb
Host smart-f13b3757-f0e2-487f-a0bc-2a57eb5659de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463512381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.3463512381
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1426970763
Short name T872
Test name
Test status
Simulation time 115712941 ps
CPU time 1.88 seconds
Started Jul 18 06:30:32 PM PDT 24
Finished Jul 18 06:30:36 PM PDT 24
Peak memory 208736 kb
Host smart-a4fa213c-260d-4d24-8da4-143bd977fff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426970763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1426970763
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.791676865
Short name T810
Test name
Test status
Simulation time 98491324 ps
CPU time 4.77 seconds
Started Jul 18 06:30:35 PM PDT 24
Finished Jul 18 06:30:47 PM PDT 24
Peak memory 209168 kb
Host smart-e9908523-e374-46a2-aa04-1b21f01e0f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791676865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.791676865
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.1045562783
Short name T673
Test name
Test status
Simulation time 6841225684 ps
CPU time 49.4 seconds
Started Jul 18 06:30:33 PM PDT 24
Finished Jul 18 06:31:28 PM PDT 24
Peak memory 208268 kb
Host smart-80205702-f3b4-44db-b148-5e96abd3e531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045562783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1045562783
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.3305519052
Short name T783
Test name
Test status
Simulation time 188181591 ps
CPU time 2.67 seconds
Started Jul 18 06:30:37 PM PDT 24
Finished Jul 18 06:30:48 PM PDT 24
Peak memory 206612 kb
Host smart-8416b45d-5556-4e02-9e2a-1701715dda27
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305519052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.3305519052
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.3568849293
Short name T892
Test name
Test status
Simulation time 310668674 ps
CPU time 5.02 seconds
Started Jul 18 06:30:33 PM PDT 24
Finished Jul 18 06:30:41 PM PDT 24
Peak memory 207868 kb
Host smart-5f02c95d-10a6-40b7-9115-c34de3a80d59
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568849293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.3568849293
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.2069405809
Short name T668
Test name
Test status
Simulation time 689197207 ps
CPU time 8.03 seconds
Started Jul 18 06:30:35 PM PDT 24
Finished Jul 18 06:30:51 PM PDT 24
Peak memory 208716 kb
Host smart-0350a59f-46b4-43b7-91c0-33d6edaa9413
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069405809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.2069405809
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.2395994460
Short name T758
Test name
Test status
Simulation time 1054321765 ps
CPU time 3.78 seconds
Started Jul 18 06:30:33 PM PDT 24
Finished Jul 18 06:30:42 PM PDT 24
Peak memory 218048 kb
Host smart-987117d9-2453-4c75-b8cc-0a1e75c5e279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395994460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2395994460
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.743746348
Short name T487
Test name
Test status
Simulation time 142365698 ps
CPU time 3.25 seconds
Started Jul 18 06:30:35 PM PDT 24
Finished Jul 18 06:30:45 PM PDT 24
Peak memory 207968 kb
Host smart-cb62be3b-dd26-4835-abb5-c67108506066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743746348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.743746348
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.423274263
Short name T785
Test name
Test status
Simulation time 1475511501 ps
CPU time 4.45 seconds
Started Jul 18 06:30:38 PM PDT 24
Finished Jul 18 06:30:51 PM PDT 24
Peak memory 214072 kb
Host smart-342951a1-2de5-401b-997c-1b7c14fb2178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423274263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.423274263
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.2773000227
Short name T806
Test name
Test status
Simulation time 197540782 ps
CPU time 2.53 seconds
Started Jul 18 06:30:34 PM PDT 24
Finished Jul 18 06:30:43 PM PDT 24
Peak memory 209824 kb
Host smart-bd8b1d5d-c6b8-4fe5-969e-a05cfec2bfb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773000227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.2773000227
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.2951797405
Short name T587
Test name
Test status
Simulation time 40663882 ps
CPU time 0.81 seconds
Started Jul 18 06:30:35 PM PDT 24
Finished Jul 18 06:30:43 PM PDT 24
Peak memory 206012 kb
Host smart-ca5b04a4-e31d-4df4-9a5c-5565259ea3df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951797405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.2951797405
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.532552069
Short name T849
Test name
Test status
Simulation time 110741644 ps
CPU time 4.13 seconds
Started Jul 18 06:30:38 PM PDT 24
Finished Jul 18 06:30:50 PM PDT 24
Peak memory 214148 kb
Host smart-0c74a120-11f4-4c55-9b9c-08f5ccd07089
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=532552069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.532552069
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.2654843910
Short name T796
Test name
Test status
Simulation time 277466826 ps
CPU time 2.14 seconds
Started Jul 18 06:30:34 PM PDT 24
Finished Jul 18 06:30:43 PM PDT 24
Peak memory 215892 kb
Host smart-d01bd196-dcc3-4317-97d1-4e7967d21d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654843910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2654843910
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.3964003811
Short name T719
Test name
Test status
Simulation time 415449689 ps
CPU time 2.49 seconds
Started Jul 18 06:30:34 PM PDT 24
Finished Jul 18 06:30:42 PM PDT 24
Peak memory 214060 kb
Host smart-248fc09f-e2ef-4f7e-8ca4-9c27adc95e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964003811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.3964003811
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.1325558238
Short name T105
Test name
Test status
Simulation time 269437031 ps
CPU time 6.95 seconds
Started Jul 18 06:30:34 PM PDT 24
Finished Jul 18 06:30:47 PM PDT 24
Peak memory 214144 kb
Host smart-9572e8eb-c08b-4552-ae8a-dba91f107433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325558238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.1325558238
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.2109230193
Short name T308
Test name
Test status
Simulation time 93457409 ps
CPU time 1.54 seconds
Started Jul 18 06:30:33 PM PDT 24
Finished Jul 18 06:30:38 PM PDT 24
Peak memory 214000 kb
Host smart-d695775a-0757-4064-8865-bb9cfdca1f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109230193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.2109230193
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.3343869387
Short name T243
Test name
Test status
Simulation time 414748394 ps
CPU time 3.68 seconds
Started Jul 18 06:30:33 PM PDT 24
Finished Jul 18 06:30:39 PM PDT 24
Peak memory 215144 kb
Host smart-2dbb8c6f-263d-478c-909b-092f3de7a8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343869387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3343869387
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.3293045055
Short name T710
Test name
Test status
Simulation time 698541459 ps
CPU time 8.57 seconds
Started Jul 18 06:30:34 PM PDT 24
Finished Jul 18 06:30:48 PM PDT 24
Peak memory 208052 kb
Host smart-181a50cb-8773-49c3-a2eb-23021501e27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293045055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.3293045055
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.3752935623
Short name T491
Test name
Test status
Simulation time 167830536 ps
CPU time 3.96 seconds
Started Jul 18 06:30:32 PM PDT 24
Finished Jul 18 06:30:39 PM PDT 24
Peak memory 208428 kb
Host smart-0dc99d0e-1e38-42e2-9109-04ea6dae128c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752935623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.3752935623
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.2267669136
Short name T412
Test name
Test status
Simulation time 69049501 ps
CPU time 3.44 seconds
Started Jul 18 06:30:37 PM PDT 24
Finished Jul 18 06:30:49 PM PDT 24
Peak memory 208592 kb
Host smart-d4b7fbcc-b3f1-44c9-9b09-46be4e147e3d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267669136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.2267669136
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1142839333
Short name T382
Test name
Test status
Simulation time 35379682 ps
CPU time 2.52 seconds
Started Jul 18 06:30:38 PM PDT 24
Finished Jul 18 06:30:49 PM PDT 24
Peak memory 208412 kb
Host smart-b4de7f52-6d8a-46df-ac43-b3fa3e8e1834
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142839333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1142839333
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.555146345
Short name T686
Test name
Test status
Simulation time 550655327 ps
CPU time 4.89 seconds
Started Jul 18 06:30:34 PM PDT 24
Finished Jul 18 06:30:45 PM PDT 24
Peak memory 208612 kb
Host smart-1d19f125-c5a2-4ca7-b4a4-bc0d48b9650e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555146345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.555146345
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.4021640855
Short name T739
Test name
Test status
Simulation time 285923454 ps
CPU time 8.9 seconds
Started Jul 18 06:30:39 PM PDT 24
Finished Jul 18 06:30:56 PM PDT 24
Peak memory 218072 kb
Host smart-e316e06c-beb2-4d7a-9845-0d9589d4b9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021640855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.4021640855
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.508591094
Short name T829
Test name
Test status
Simulation time 324026440 ps
CPU time 2.92 seconds
Started Jul 18 06:30:36 PM PDT 24
Finished Jul 18 06:30:46 PM PDT 24
Peak memory 208488 kb
Host smart-9e0828a5-3c5c-4619-9c5e-0ee9e85f6219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508591094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.508591094
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.1410406330
Short name T305
Test name
Test status
Simulation time 82437677444 ps
CPU time 481.14 seconds
Started Jul 18 06:30:36 PM PDT 24
Finished Jul 18 06:38:45 PM PDT 24
Peak memory 222600 kb
Host smart-21b8ddec-722c-4992-92c2-59517a457a35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410406330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.1410406330
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.1539552921
Short name T625
Test name
Test status
Simulation time 273552514 ps
CPU time 13.71 seconds
Started Jul 18 06:30:39 PM PDT 24
Finished Jul 18 06:31:02 PM PDT 24
Peak memory 221180 kb
Host smart-0b547475-43e9-4ba7-9ad5-1f85349b67c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539552921 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.1539552921
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.788161897
Short name T854
Test name
Test status
Simulation time 219084691 ps
CPU time 5.46 seconds
Started Jul 18 06:30:40 PM PDT 24
Finished Jul 18 06:30:54 PM PDT 24
Peak memory 214072 kb
Host smart-fb8a41bb-a745-4062-a773-501696e6725a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788161897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.788161897
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.862766723
Short name T197
Test name
Test status
Simulation time 190780590 ps
CPU time 1.83 seconds
Started Jul 18 06:30:37 PM PDT 24
Finished Jul 18 06:30:47 PM PDT 24
Peak memory 209496 kb
Host smart-1307fa71-77cb-4b86-8431-84b86af6ff45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862766723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.862766723
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.3955483991
Short name T778
Test name
Test status
Simulation time 116223776 ps
CPU time 0.75 seconds
Started Jul 18 06:30:37 PM PDT 24
Finished Jul 18 06:30:47 PM PDT 24
Peak memory 205852 kb
Host smart-7e40b3af-8bdb-49fb-8730-2273ee6f776f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955483991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.3955483991
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.4106714877
Short name T28
Test name
Test status
Simulation time 117160382 ps
CPU time 4.51 seconds
Started Jul 18 06:30:35 PM PDT 24
Finished Jul 18 06:30:48 PM PDT 24
Peak memory 210252 kb
Host smart-f101ba88-c583-4cb3-a2ed-f5cdbe1b4296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106714877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.4106714877
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.97611700
Short name T71
Test name
Test status
Simulation time 895960090 ps
CPU time 5.83 seconds
Started Jul 18 06:30:34 PM PDT 24
Finished Jul 18 06:30:45 PM PDT 24
Peak memory 214132 kb
Host smart-49bcadda-025a-4e87-b5cf-c27c26af38d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97611700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.97611700
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.3999328991
Short name T725
Test name
Test status
Simulation time 191034118 ps
CPU time 2.65 seconds
Started Jul 18 06:30:40 PM PDT 24
Finished Jul 18 06:30:51 PM PDT 24
Peak memory 214004 kb
Host smart-61a84c08-fa54-458a-9bec-2c559ed21fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999328991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.3999328991
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.462395148
Short name T770
Test name
Test status
Simulation time 338135956 ps
CPU time 2.64 seconds
Started Jul 18 06:30:36 PM PDT 24
Finished Jul 18 06:30:46 PM PDT 24
Peak memory 222220 kb
Host smart-f58fc9d1-78c3-42a6-a39a-be21f995a81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462395148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.462395148
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.1322092244
Short name T282
Test name
Test status
Simulation time 588998754 ps
CPU time 6.09 seconds
Started Jul 18 06:30:33 PM PDT 24
Finished Jul 18 06:30:42 PM PDT 24
Peak memory 210000 kb
Host smart-aca76c16-76a6-4f0d-9fcf-eccc5d8480da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322092244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1322092244
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.3944052912
Short name T815
Test name
Test status
Simulation time 289194163 ps
CPU time 4.41 seconds
Started Jul 18 06:30:39 PM PDT 24
Finished Jul 18 06:30:52 PM PDT 24
Peak memory 208280 kb
Host smart-3bab12bf-a718-44bd-bf74-eb343886df7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944052912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.3944052912
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.3615738187
Short name T323
Test name
Test status
Simulation time 2480192335 ps
CPU time 43.98 seconds
Started Jul 18 06:30:32 PM PDT 24
Finished Jul 18 06:31:18 PM PDT 24
Peak memory 209020 kb
Host smart-f7b12280-e5c2-4d30-8987-b66c1f3170e0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615738187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.3615738187
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.1664155096
Short name T644
Test name
Test status
Simulation time 555776876 ps
CPU time 5.92 seconds
Started Jul 18 06:30:35 PM PDT 24
Finished Jul 18 06:30:48 PM PDT 24
Peak memory 208704 kb
Host smart-cf33e912-5753-4ce5-b547-6efff4cfcbad
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664155096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.1664155096
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.2649385313
Short name T853
Test name
Test status
Simulation time 189841952 ps
CPU time 5.25 seconds
Started Jul 18 06:30:34 PM PDT 24
Finished Jul 18 06:30:45 PM PDT 24
Peak memory 207976 kb
Host smart-e0fc7033-e7d8-45ea-a62a-12c59bbc6e8c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649385313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2649385313
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.1671729251
Short name T465
Test name
Test status
Simulation time 85364857 ps
CPU time 2.21 seconds
Started Jul 18 06:30:33 PM PDT 24
Finished Jul 18 06:30:38 PM PDT 24
Peak memory 207820 kb
Host smart-d9cd8d94-6a86-44a5-af5b-8d8fd1a18974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671729251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.1671729251
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.677169715
Short name T786
Test name
Test status
Simulation time 204226716 ps
CPU time 2.86 seconds
Started Jul 18 06:30:32 PM PDT 24
Finished Jul 18 06:30:37 PM PDT 24
Peak memory 208524 kb
Host smart-e0052b04-bec0-456a-88bf-e16fdbb1def7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677169715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.677169715
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.3166077485
Short name T837
Test name
Test status
Simulation time 266468147 ps
CPU time 3.44 seconds
Started Jul 18 06:30:34 PM PDT 24
Finished Jul 18 06:30:44 PM PDT 24
Peak memory 207256 kb
Host smart-344cef9f-a0b4-47a7-9929-65cacc8ed307
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166077485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.3166077485
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.731026494
Short name T598
Test name
Test status
Simulation time 164315611 ps
CPU time 3.95 seconds
Started Jul 18 06:30:36 PM PDT 24
Finished Jul 18 06:30:48 PM PDT 24
Peak memory 209612 kb
Host smart-7ca2c952-c2f9-449e-b1d0-ce7253ee9f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731026494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.731026494
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.258787461
Short name T395
Test name
Test status
Simulation time 35606691 ps
CPU time 2.07 seconds
Started Jul 18 06:30:35 PM PDT 24
Finished Jul 18 06:30:44 PM PDT 24
Peak memory 209700 kb
Host smart-36a64105-9a24-43bf-bfa5-351710b85dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258787461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.258787461
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.2093495348
Short name T439
Test name
Test status
Simulation time 9533464 ps
CPU time 0.73 seconds
Started Jul 18 06:30:40 PM PDT 24
Finished Jul 18 06:30:49 PM PDT 24
Peak memory 205800 kb
Host smart-208362fb-6c31-4c21-996a-6be4e5763588
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093495348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2093495348
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.2342228221
Short name T437
Test name
Test status
Simulation time 61922374 ps
CPU time 4.39 seconds
Started Jul 18 06:30:34 PM PDT 24
Finished Jul 18 06:30:46 PM PDT 24
Peak memory 214056 kb
Host smart-46d99454-96cf-48f4-916b-6deb5d7e86da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2342228221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.2342228221
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.305052643
Short name T530
Test name
Test status
Simulation time 95581118 ps
CPU time 2.41 seconds
Started Jul 18 06:30:39 PM PDT 24
Finished Jul 18 06:30:50 PM PDT 24
Peak memory 213408 kb
Host smart-c4e9ebc4-d5aa-43cb-b5a7-53642c0fcce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305052643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.305052643
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.3141127098
Short name T501
Test name
Test status
Simulation time 98889256 ps
CPU time 1.76 seconds
Started Jul 18 06:30:37 PM PDT 24
Finished Jul 18 06:30:47 PM PDT 24
Peak memory 207156 kb
Host smart-2d950d79-84cb-436a-8d8f-1d175fe70589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141127098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.3141127098
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.1986428406
Short name T784
Test name
Test status
Simulation time 62599257 ps
CPU time 2.59 seconds
Started Jul 18 06:30:37 PM PDT 24
Finished Jul 18 06:30:47 PM PDT 24
Peak memory 214076 kb
Host smart-054f56c5-b21f-4f45-8eee-58a059e1aeb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986428406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.1986428406
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.202561682
Short name T831
Test name
Test status
Simulation time 208378127 ps
CPU time 3.25 seconds
Started Jul 18 06:30:33 PM PDT 24
Finished Jul 18 06:30:41 PM PDT 24
Peak memory 216360 kb
Host smart-2a8b78e5-e3b4-473b-9a3d-a7ccc1946fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202561682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.202561682
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.604375588
Short name T245
Test name
Test status
Simulation time 269666287 ps
CPU time 2.42 seconds
Started Jul 18 06:30:40 PM PDT 24
Finished Jul 18 06:30:51 PM PDT 24
Peak memory 215600 kb
Host smart-8461e353-111f-45ac-9b22-8bf424eff62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604375588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.604375588
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.2859738226
Short name T347
Test name
Test status
Simulation time 539640515 ps
CPU time 7.87 seconds
Started Jul 18 06:30:34 PM PDT 24
Finished Jul 18 06:30:49 PM PDT 24
Peak memory 209492 kb
Host smart-51ce09a6-028c-4bcc-9ba6-8b663002806f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859738226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.2859738226
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.1162668211
Short name T751
Test name
Test status
Simulation time 50868840 ps
CPU time 2.79 seconds
Started Jul 18 06:30:35 PM PDT 24
Finished Jul 18 06:30:45 PM PDT 24
Peak memory 206664 kb
Host smart-40994e38-ce87-4f9f-a775-bc15805a65c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162668211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1162668211
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1265780768
Short name T537
Test name
Test status
Simulation time 243960346 ps
CPU time 6.43 seconds
Started Jul 18 06:30:35 PM PDT 24
Finished Jul 18 06:30:49 PM PDT 24
Peak memory 208284 kb
Host smart-7d90946c-2ba1-401e-999d-7507754d3a28
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265780768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1265780768
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.2596605201
Short name T597
Test name
Test status
Simulation time 7892149004 ps
CPU time 29.56 seconds
Started Jul 18 06:30:35 PM PDT 24
Finished Jul 18 06:31:11 PM PDT 24
Peak memory 207720 kb
Host smart-07cb8c9b-7767-49b7-bc6f-2121cfb841de
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596605201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.2596605201
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.630316414
Short name T194
Test name
Test status
Simulation time 2327826563 ps
CPU time 21.35 seconds
Started Jul 18 06:30:36 PM PDT 24
Finished Jul 18 06:31:06 PM PDT 24
Peak memory 208640 kb
Host smart-cc97357b-a0db-4fa7-958a-83d381c5eaaa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630316414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.630316414
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.4100285420
Short name T574
Test name
Test status
Simulation time 1599232960 ps
CPU time 13.73 seconds
Started Jul 18 06:30:39 PM PDT 24
Finished Jul 18 06:31:02 PM PDT 24
Peak memory 208852 kb
Host smart-28e1a61a-60e8-407b-a75d-6b3a359d34cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100285420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.4100285420
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.1447372484
Short name T690
Test name
Test status
Simulation time 146762531 ps
CPU time 4.61 seconds
Started Jul 18 06:30:33 PM PDT 24
Finished Jul 18 06:30:42 PM PDT 24
Peak memory 206576 kb
Host smart-97a423ff-6e1f-4926-b065-716b5cb70597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447372484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.1447372484
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.3402355415
Short name T876
Test name
Test status
Simulation time 5798552437 ps
CPU time 68.42 seconds
Started Jul 18 06:30:40 PM PDT 24
Finished Jul 18 06:31:57 PM PDT 24
Peak memory 222324 kb
Host smart-8cf69c1d-aed5-45c4-b84f-56695ad111fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402355415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.3402355415
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.2376805262
Short name T174
Test name
Test status
Simulation time 863940102 ps
CPU time 16.47 seconds
Started Jul 18 06:30:33 PM PDT 24
Finished Jul 18 06:30:52 PM PDT 24
Peak memory 222368 kb
Host smart-7f0dc374-75c6-4c5c-a45c-7543c900223a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376805262 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.2376805262
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.2937579628
Short name T575
Test name
Test status
Simulation time 134402295 ps
CPU time 4.52 seconds
Started Jul 18 06:30:37 PM PDT 24
Finished Jul 18 06:30:49 PM PDT 24
Peak memory 209924 kb
Host smart-a97c007f-dea1-4e00-a1a1-4137273dc5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937579628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2937579628
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1987123724
Short name T499
Test name
Test status
Simulation time 71438879 ps
CPU time 1.37 seconds
Started Jul 18 06:30:40 PM PDT 24
Finished Jul 18 06:30:50 PM PDT 24
Peak memory 209292 kb
Host smart-8362e21f-c594-4e96-bf57-22c924dc611e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987123724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1987123724
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.3219523729
Short name T493
Test name
Test status
Simulation time 14168012 ps
CPU time 0.77 seconds
Started Jul 18 06:30:38 PM PDT 24
Finished Jul 18 06:30:47 PM PDT 24
Peak memory 205852 kb
Host smart-70044942-e542-45c5-a941-47ddd08aa9fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219523729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.3219523729
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.1482335900
Short name T401
Test name
Test status
Simulation time 70600485 ps
CPU time 2.94 seconds
Started Jul 18 06:30:35 PM PDT 24
Finished Jul 18 06:30:45 PM PDT 24
Peak memory 214096 kb
Host smart-f72cf353-cf8a-45de-8656-f2f719701c14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1482335900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1482335900
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.3816605365
Short name T74
Test name
Test status
Simulation time 76006593 ps
CPU time 3.34 seconds
Started Jul 18 06:30:39 PM PDT 24
Finished Jul 18 06:30:51 PM PDT 24
Peak memory 209352 kb
Host smart-76ffba09-a323-4a03-9971-db8c760cbd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816605365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.3816605365
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.2177985082
Short name T478
Test name
Test status
Simulation time 99769064 ps
CPU time 1.57 seconds
Started Jul 18 06:30:39 PM PDT 24
Finished Jul 18 06:30:49 PM PDT 24
Peak memory 208212 kb
Host smart-23695a2e-01d7-4b4f-bd02-5cdcca8d0b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177985082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.2177985082
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.337986869
Short name T234
Test name
Test status
Simulation time 3784065358 ps
CPU time 13.67 seconds
Started Jul 18 06:30:43 PM PDT 24
Finished Jul 18 06:31:04 PM PDT 24
Peak memory 222224 kb
Host smart-4cbc8c91-7a55-4bd5-b46c-d410d8b306f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337986869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.337986869
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.1141690599
Short name T664
Test name
Test status
Simulation time 85203742 ps
CPU time 4.13 seconds
Started Jul 18 06:30:39 PM PDT 24
Finished Jul 18 06:30:52 PM PDT 24
Peak memory 221228 kb
Host smart-754d15a9-d594-4cee-9339-ac2b83f79b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141690599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.1141690599
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.1919763783
Short name T215
Test name
Test status
Simulation time 1509679345 ps
CPU time 4.43 seconds
Started Jul 18 06:30:34 PM PDT 24
Finished Jul 18 06:30:44 PM PDT 24
Peak memory 215304 kb
Host smart-e4309218-bd97-4ae8-90ff-7ee275b5ebe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919763783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.1919763783
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.1236204929
Short name T316
Test name
Test status
Simulation time 346569073 ps
CPU time 9.79 seconds
Started Jul 18 06:30:38 PM PDT 24
Finished Jul 18 06:30:56 PM PDT 24
Peak memory 210096 kb
Host smart-56fceb3f-ecb1-4b17-8e86-41c399d05fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236204929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.1236204929
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.1297428091
Short name T370
Test name
Test status
Simulation time 146140800 ps
CPU time 3.48 seconds
Started Jul 18 06:30:38 PM PDT 24
Finished Jul 18 06:30:50 PM PDT 24
Peak memory 206976 kb
Host smart-f692cb60-8a96-4a5d-8253-df3b39e8d81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297428091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.1297428091
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.3500167424
Short name T722
Test name
Test status
Simulation time 3536251919 ps
CPU time 20.07 seconds
Started Jul 18 06:30:37 PM PDT 24
Finished Jul 18 06:31:06 PM PDT 24
Peak memory 207844 kb
Host smart-d0ba751e-8c60-4b3d-b5e5-bb59962ced54
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500167424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.3500167424
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.1167074922
Short name T839
Test name
Test status
Simulation time 74662039 ps
CPU time 3.59 seconds
Started Jul 18 06:30:35 PM PDT 24
Finished Jul 18 06:30:46 PM PDT 24
Peak memory 208628 kb
Host smart-4f80c072-1330-4f28-904c-e76054c4708a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167074922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.1167074922
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.2200821940
Short name T279
Test name
Test status
Simulation time 888851832 ps
CPU time 6.46 seconds
Started Jul 18 06:30:51 PM PDT 24
Finished Jul 18 06:31:00 PM PDT 24
Peak memory 207852 kb
Host smart-72ef7d3e-339f-4f75-b322-bae8abcf00b7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200821940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2200821940
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.3953362323
Short name T548
Test name
Test status
Simulation time 1189376763 ps
CPU time 11.19 seconds
Started Jul 18 06:30:46 PM PDT 24
Finished Jul 18 06:31:02 PM PDT 24
Peak memory 208224 kb
Host smart-1f8c6fcc-253c-4fa4-a0ad-51c0515407f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953362323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.3953362323
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.2808543867
Short name T562
Test name
Test status
Simulation time 140381161 ps
CPU time 2.17 seconds
Started Jul 18 06:30:38 PM PDT 24
Finished Jul 18 06:30:48 PM PDT 24
Peak memory 206684 kb
Host smart-8bac757f-a415-4864-9094-1baaca434014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808543867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.2808543867
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.3006984778
Short name T772
Test name
Test status
Simulation time 1402566926 ps
CPU time 11.98 seconds
Started Jul 18 06:30:42 PM PDT 24
Finished Jul 18 06:31:02 PM PDT 24
Peak memory 216556 kb
Host smart-437523fc-5ccd-46c2-a2f7-ddfe82b0903f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006984778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.3006984778
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.672564067
Short name T281
Test name
Test status
Simulation time 468693094 ps
CPU time 4.35 seconds
Started Jul 18 06:30:43 PM PDT 24
Finished Jul 18 06:30:54 PM PDT 24
Peak memory 208932 kb
Host smart-2020bd55-c381-4ddc-b21c-c032bc987d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672564067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.672564067
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.2807922202
Short name T685
Test name
Test status
Simulation time 59906614 ps
CPU time 2.59 seconds
Started Jul 18 06:30:43 PM PDT 24
Finished Jul 18 06:30:52 PM PDT 24
Peak memory 209356 kb
Host smart-8fdd7991-ce6e-4fda-827a-c7be340ec3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807922202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.2807922202
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.2255047726
Short name T870
Test name
Test status
Simulation time 10955844 ps
CPU time 0.77 seconds
Started Jul 18 06:27:05 PM PDT 24
Finished Jul 18 06:27:07 PM PDT 24
Peak memory 205748 kb
Host smart-3db8290e-a17c-4418-8fbc-6273e6a5a8ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255047726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.2255047726
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.1528640844
Short name T798
Test name
Test status
Simulation time 174568501 ps
CPU time 4.93 seconds
Started Jul 18 06:27:14 PM PDT 24
Finished Jul 18 06:27:21 PM PDT 24
Peak memory 218148 kb
Host smart-a7dab774-5c51-41f5-ac40-605cd9abe5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528640844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.1528640844
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.1239643772
Short name T66
Test name
Test status
Simulation time 529680169 ps
CPU time 2.71 seconds
Started Jul 18 06:27:14 PM PDT 24
Finished Jul 18 06:27:18 PM PDT 24
Peak memory 208152 kb
Host smart-1c39dbb8-9e4d-4bf8-a1f5-e99dcea940cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239643772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.1239643772
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.4066515098
Short name T818
Test name
Test status
Simulation time 201213059 ps
CPU time 6.21 seconds
Started Jul 18 06:27:09 PM PDT 24
Finished Jul 18 06:27:16 PM PDT 24
Peak memory 208488 kb
Host smart-7444118d-397f-4e04-a70e-855722698c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066515098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.4066515098
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.5764981
Short name T69
Test name
Test status
Simulation time 815331108 ps
CPU time 4.1 seconds
Started Jul 18 06:27:11 PM PDT 24
Finished Jul 18 06:27:17 PM PDT 24
Peak memory 219820 kb
Host smart-55b5ddb5-8990-435d-a549-c886bc3bac81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5764981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.5764981
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.701087438
Short name T318
Test name
Test status
Simulation time 415239490 ps
CPU time 14.79 seconds
Started Jul 18 06:27:07 PM PDT 24
Finished Jul 18 06:27:23 PM PDT 24
Peak memory 208456 kb
Host smart-a8f1d3ea-cf8d-4bac-8f50-fe9876e3b464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701087438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.701087438
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.4020263731
Short name T867
Test name
Test status
Simulation time 50698371 ps
CPU time 2.67 seconds
Started Jul 18 06:27:05 PM PDT 24
Finished Jul 18 06:27:09 PM PDT 24
Peak memory 206796 kb
Host smart-7945880e-0eb9-4878-afeb-bd7141049c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020263731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.4020263731
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.3635243550
Short name T117
Test name
Test status
Simulation time 15794910358 ps
CPU time 32.04 seconds
Started Jul 18 06:27:05 PM PDT 24
Finished Jul 18 06:27:39 PM PDT 24
Peak memory 208640 kb
Host smart-e1ad4f16-4775-4e45-ab51-496936569870
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635243550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.3635243550
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.637834350
Short name T521
Test name
Test status
Simulation time 115621071 ps
CPU time 2.95 seconds
Started Jul 18 06:27:04 PM PDT 24
Finished Jul 18 06:27:08 PM PDT 24
Peak memory 206640 kb
Host smart-b4a6d2ea-d9f2-41c8-b5e4-c9da55a30a0e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637834350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.637834350
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.3179044610
Short name T532
Test name
Test status
Simulation time 102187060 ps
CPU time 2.77 seconds
Started Jul 18 06:27:10 PM PDT 24
Finished Jul 18 06:27:14 PM PDT 24
Peak memory 206584 kb
Host smart-2df7917f-a454-4cbf-b9fa-6cc8b8f17798
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179044610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.3179044610
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.263957831
Short name T723
Test name
Test status
Simulation time 31737520 ps
CPU time 2.11 seconds
Started Jul 18 06:27:12 PM PDT 24
Finished Jul 18 06:27:17 PM PDT 24
Peak memory 213752 kb
Host smart-f542611b-d749-4c09-a719-48cfe9e01a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263957831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.263957831
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.2339728977
Short name T406
Test name
Test status
Simulation time 25269655 ps
CPU time 1.89 seconds
Started Jul 18 06:27:05 PM PDT 24
Finished Jul 18 06:27:08 PM PDT 24
Peak memory 206584 kb
Host smart-640bcaa4-da4c-496a-a0dd-4ddd7900cd53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339728977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.2339728977
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.3891908418
Short name T175
Test name
Test status
Simulation time 1157510522 ps
CPU time 9.86 seconds
Started Jul 18 06:27:06 PM PDT 24
Finished Jul 18 06:27:17 PM PDT 24
Peak memory 218292 kb
Host smart-66143e62-16cd-4f43-939c-cbe9721d826a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891908418 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.3891908418
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.31407608
Short name T553
Test name
Test status
Simulation time 532965339 ps
CPU time 11.9 seconds
Started Jul 18 06:27:11 PM PDT 24
Finished Jul 18 06:27:25 PM PDT 24
Peak memory 208360 kb
Host smart-77f8f09f-3003-4c82-aa2c-6e6589174cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31407608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.31407608
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.2575414873
Short name T133
Test name
Test status
Simulation time 311575650 ps
CPU time 2.47 seconds
Started Jul 18 06:27:05 PM PDT 24
Finished Jul 18 06:27:09 PM PDT 24
Peak memory 210252 kb
Host smart-b4d01e16-0bd4-41f7-a023-c1b6deb0687e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575414873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.2575414873
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.101925308
Short name T550
Test name
Test status
Simulation time 52080955 ps
CPU time 0.9 seconds
Started Jul 18 06:27:13 PM PDT 24
Finished Jul 18 06:27:16 PM PDT 24
Peak memory 205844 kb
Host smart-4b64abc2-1ae2-4c37-a7a6-e6a61c1c84cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101925308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.101925308
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2168530102
Short name T680
Test name
Test status
Simulation time 78953838 ps
CPU time 2.08 seconds
Started Jul 18 06:27:08 PM PDT 24
Finished Jul 18 06:27:12 PM PDT 24
Peak memory 221372 kb
Host smart-5cd4af3f-226e-4d4e-a507-394f90b5aca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168530102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2168530102
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.538739651
Short name T497
Test name
Test status
Simulation time 63710457 ps
CPU time 2.29 seconds
Started Jul 18 06:27:12 PM PDT 24
Finished Jul 18 06:27:17 PM PDT 24
Peak memory 208064 kb
Host smart-f4e530ee-202f-4b3a-8e9e-7d4cac3d2c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538739651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.538739651
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.1653209289
Short name T214
Test name
Test status
Simulation time 88742548 ps
CPU time 3.98 seconds
Started Jul 18 06:27:07 PM PDT 24
Finished Jul 18 06:27:12 PM PDT 24
Peak memory 214180 kb
Host smart-5c2903c7-458e-4d90-bb2e-c47100f252cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653209289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.1653209289
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.2008227306
Short name T238
Test name
Test status
Simulation time 84145178 ps
CPU time 3.42 seconds
Started Jul 18 06:27:11 PM PDT 24
Finished Jul 18 06:27:17 PM PDT 24
Peak memory 214084 kb
Host smart-1c3d7fac-6087-4188-95ae-0e8eed78b0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008227306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.2008227306
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.94152610
Short name T888
Test name
Test status
Simulation time 1299210884 ps
CPU time 6.98 seconds
Started Jul 18 06:27:09 PM PDT 24
Finished Jul 18 06:27:18 PM PDT 24
Peak memory 209864 kb
Host smart-5a8519f3-274b-4864-8827-cf439e1521f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94152610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.94152610
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.2681777964
Short name T299
Test name
Test status
Simulation time 122962294 ps
CPU time 3.26 seconds
Started Jul 18 06:27:12 PM PDT 24
Finished Jul 18 06:27:18 PM PDT 24
Peak memory 206640 kb
Host smart-177b825c-791b-49f3-99cd-d7264493051f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681777964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.2681777964
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.431926408
Short name T404
Test name
Test status
Simulation time 115544418 ps
CPU time 4.52 seconds
Started Jul 18 06:27:08 PM PDT 24
Finished Jul 18 06:27:13 PM PDT 24
Peak memory 207712 kb
Host smart-6a0f23f0-058f-4ccf-8ae5-e998dc9ca051
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431926408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.431926408
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.3922860678
Short name T613
Test name
Test status
Simulation time 124438265 ps
CPU time 3.15 seconds
Started Jul 18 06:27:07 PM PDT 24
Finished Jul 18 06:27:11 PM PDT 24
Peak memory 207932 kb
Host smart-dc7d76dd-b406-4e31-b1b0-81239b74c59e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922860678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.3922860678
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.469975751
Short name T514
Test name
Test status
Simulation time 2146885737 ps
CPU time 9.18 seconds
Started Jul 18 06:27:09 PM PDT 24
Finished Jul 18 06:27:19 PM PDT 24
Peak memory 208660 kb
Host smart-0890def3-d7c4-4529-a142-243500afaa36
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469975751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.469975751
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.2740620013
Short name T857
Test name
Test status
Simulation time 22978815 ps
CPU time 1.83 seconds
Started Jul 18 06:27:11 PM PDT 24
Finished Jul 18 06:27:15 PM PDT 24
Peak memory 207876 kb
Host smart-f168c072-5bf6-47bb-b2da-0a881f7ab7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740620013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.2740620013
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.2674979239
Short name T542
Test name
Test status
Simulation time 49857760 ps
CPU time 2.48 seconds
Started Jul 18 06:27:09 PM PDT 24
Finished Jul 18 06:27:12 PM PDT 24
Peak memory 206516 kb
Host smart-cffc8c3f-89a7-412a-a3dc-99249ded3549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674979239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2674979239
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2289697527
Short name T114
Test name
Test status
Simulation time 99759974 ps
CPU time 4.3 seconds
Started Jul 18 06:27:12 PM PDT 24
Finished Jul 18 06:27:19 PM PDT 24
Peak memory 217568 kb
Host smart-d0e39a39-9c7a-46a6-86aa-d7e372303f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289697527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2289697527
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.4028662375
Short name T40
Test name
Test status
Simulation time 59342712 ps
CPU time 1.92 seconds
Started Jul 18 06:27:09 PM PDT 24
Finished Jul 18 06:27:12 PM PDT 24
Peak memory 209608 kb
Host smart-0332a013-0d8c-4408-9113-c8adad2eff52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028662375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.4028662375
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.455802375
Short name T807
Test name
Test status
Simulation time 76867968 ps
CPU time 0.74 seconds
Started Jul 18 06:27:10 PM PDT 24
Finished Jul 18 06:27:13 PM PDT 24
Peak memory 205876 kb
Host smart-5f277842-8115-433a-b321-ee9fc2914526
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455802375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.455802375
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.627418982
Short name T824
Test name
Test status
Simulation time 126825673 ps
CPU time 3.06 seconds
Started Jul 18 06:27:11 PM PDT 24
Finished Jul 18 06:27:16 PM PDT 24
Peak memory 222528 kb
Host smart-5e2af625-b756-4fb3-b216-21aed9dea6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627418982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.627418982
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.1290243538
Short name T894
Test name
Test status
Simulation time 349392986 ps
CPU time 2.59 seconds
Started Jul 18 06:27:09 PM PDT 24
Finished Jul 18 06:27:13 PM PDT 24
Peak memory 207176 kb
Host smart-cc473973-7d5a-47b0-aab5-491bf618d169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290243538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.1290243538
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.680023329
Short name T285
Test name
Test status
Simulation time 59716809 ps
CPU time 2.68 seconds
Started Jul 18 06:27:11 PM PDT 24
Finished Jul 18 06:27:17 PM PDT 24
Peak memory 214120 kb
Host smart-e1c5fa39-5afc-4245-be6a-b89837fc5424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680023329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.680023329
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.1679751466
Short name T365
Test name
Test status
Simulation time 90505833 ps
CPU time 4.42 seconds
Started Jul 18 06:27:11 PM PDT 24
Finished Jul 18 06:27:17 PM PDT 24
Peak memory 210904 kb
Host smart-a0e39684-4035-4344-bd8d-30cc17a73e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679751466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.1679751466
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.1774963979
Short name T438
Test name
Test status
Simulation time 206678046 ps
CPU time 2.8 seconds
Started Jul 18 06:27:13 PM PDT 24
Finished Jul 18 06:27:18 PM PDT 24
Peak memory 208884 kb
Host smart-388d4f8b-92e3-46e6-8863-f3951b756e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774963979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.1774963979
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.3073565678
Short name T816
Test name
Test status
Simulation time 141344789 ps
CPU time 2.98 seconds
Started Jul 18 06:27:11 PM PDT 24
Finished Jul 18 06:27:16 PM PDT 24
Peak memory 207184 kb
Host smart-6110a874-0c58-406d-be6c-c79ca254c281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073565678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.3073565678
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.1526791550
Short name T740
Test name
Test status
Simulation time 195820333 ps
CPU time 2.79 seconds
Started Jul 18 06:27:05 PM PDT 24
Finished Jul 18 06:27:09 PM PDT 24
Peak memory 206504 kb
Host smart-345b05ed-1197-4c85-9714-581a82239021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526791550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1526791550
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.2614328569
Short name T413
Test name
Test status
Simulation time 228306493 ps
CPU time 2.82 seconds
Started Jul 18 06:27:09 PM PDT 24
Finished Jul 18 06:27:13 PM PDT 24
Peak memory 206628 kb
Host smart-0b43d69e-50a0-4404-bc80-388ef26b6275
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614328569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2614328569
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.1787931094
Short name T705
Test name
Test status
Simulation time 90546278 ps
CPU time 4.41 seconds
Started Jul 18 06:27:10 PM PDT 24
Finished Jul 18 06:27:17 PM PDT 24
Peak memory 208588 kb
Host smart-d1deb90f-5694-43bc-b86b-8398af0b0fce
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787931094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.1787931094
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.1417750958
Short name T495
Test name
Test status
Simulation time 56678333 ps
CPU time 3.16 seconds
Started Jul 18 06:27:11 PM PDT 24
Finished Jul 18 06:27:17 PM PDT 24
Peak memory 208700 kb
Host smart-fed0ea50-4f46-49e3-bac0-8394aa5a1499
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417750958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.1417750958
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.3202484440
Short name T599
Test name
Test status
Simulation time 86394728 ps
CPU time 2.26 seconds
Started Jul 18 06:27:11 PM PDT 24
Finished Jul 18 06:27:16 PM PDT 24
Peak memory 207764 kb
Host smart-c6e7be0b-d57b-4cdf-a4ed-deb7d2cfeb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202484440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3202484440
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.4158259656
Short name T639
Test name
Test status
Simulation time 93348909 ps
CPU time 3.87 seconds
Started Jul 18 06:27:08 PM PDT 24
Finished Jul 18 06:27:13 PM PDT 24
Peak memory 208412 kb
Host smart-a3bc4b4b-bbdb-4530-a5d2-d973babf7e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158259656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.4158259656
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.844415022
Short name T70
Test name
Test status
Simulation time 2184114462 ps
CPU time 19.78 seconds
Started Jul 18 06:27:11 PM PDT 24
Finished Jul 18 06:27:33 PM PDT 24
Peak memory 216928 kb
Host smart-35dceb13-37b0-4736-b8b3-13d742f0136c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844415022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.844415022
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2673205391
Short name T552
Test name
Test status
Simulation time 3275932490 ps
CPU time 43.73 seconds
Started Jul 18 06:27:08 PM PDT 24
Finished Jul 18 06:27:53 PM PDT 24
Peak memory 208820 kb
Host smart-2f7aad08-2709-474e-a205-654fda184ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673205391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2673205391
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.2867257851
Short name T470
Test name
Test status
Simulation time 76691626 ps
CPU time 3.15 seconds
Started Jul 18 06:27:14 PM PDT 24
Finished Jul 18 06:27:19 PM PDT 24
Peak memory 210364 kb
Host smart-1796aeb3-7a91-4cc2-a4ee-bb17b9a817c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867257851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.2867257851
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.485427411
Short name T852
Test name
Test status
Simulation time 48346814 ps
CPU time 0.81 seconds
Started Jul 18 06:27:21 PM PDT 24
Finished Jul 18 06:27:24 PM PDT 24
Peak memory 205856 kb
Host smart-a725ec73-bdd0-40a1-bd05-e253b55a5e9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485427411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.485427411
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.757206703
Short name T30
Test name
Test status
Simulation time 73683879 ps
CPU time 3.76 seconds
Started Jul 18 06:27:21 PM PDT 24
Finished Jul 18 06:27:27 PM PDT 24
Peak memory 209628 kb
Host smart-3bc89fbb-a577-4177-8ec5-467abb51a5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757206703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.757206703
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.1075862372
Short name T629
Test name
Test status
Simulation time 430331854 ps
CPU time 6.33 seconds
Started Jul 18 06:27:22 PM PDT 24
Finished Jul 18 06:27:31 PM PDT 24
Peak memory 217972 kb
Host smart-dc7b8868-6edf-4d77-8512-6ee8734dc1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075862372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.1075862372
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.3670921288
Short name T617
Test name
Test status
Simulation time 70684614 ps
CPU time 3.46 seconds
Started Jul 18 06:27:21 PM PDT 24
Finished Jul 18 06:27:26 PM PDT 24
Peak memory 214076 kb
Host smart-94988ac5-ca3a-41b1-ac3e-3fe052157bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670921288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.3670921288
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.2139770696
Short name T320
Test name
Test status
Simulation time 128134560 ps
CPU time 5.85 seconds
Started Jul 18 06:27:23 PM PDT 24
Finished Jul 18 06:27:32 PM PDT 24
Peak memory 214132 kb
Host smart-c4fd8f17-5a5c-4101-8fc4-811133fe592d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139770696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.2139770696
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.2576396124
Short name T235
Test name
Test status
Simulation time 70623831 ps
CPU time 3.21 seconds
Started Jul 18 06:27:20 PM PDT 24
Finished Jul 18 06:27:25 PM PDT 24
Peak memory 214108 kb
Host smart-aedda634-7e40-4ed8-bc95-34dc1506d0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576396124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.2576396124
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.2756073082
Short name T330
Test name
Test status
Simulation time 151970287 ps
CPU time 3.86 seconds
Started Jul 18 06:27:22 PM PDT 24
Finished Jul 18 06:27:29 PM PDT 24
Peak memory 214156 kb
Host smart-c8da3143-6e75-4cc2-b3b3-5bf313783c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756073082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2756073082
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.2778300445
Short name T659
Test name
Test status
Simulation time 545700767 ps
CPU time 4.32 seconds
Started Jul 18 06:27:10 PM PDT 24
Finished Jul 18 06:27:16 PM PDT 24
Peak memory 208252 kb
Host smart-5caf0489-d9fc-4e4d-808b-4d43622dd86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778300445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.2778300445
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.1716117954
Short name T697
Test name
Test status
Simulation time 1415439622 ps
CPU time 3.88 seconds
Started Jul 18 06:27:20 PM PDT 24
Finished Jul 18 06:27:26 PM PDT 24
Peak memory 207028 kb
Host smart-cb27bdf6-a436-4847-a39f-505fef730e36
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716117954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1716117954
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.2170610975
Short name T757
Test name
Test status
Simulation time 115384070 ps
CPU time 2.45 seconds
Started Jul 18 06:27:21 PM PDT 24
Finished Jul 18 06:27:25 PM PDT 24
Peak memory 206528 kb
Host smart-865bf5b3-8cdb-4591-973a-52162e7626dd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170610975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2170610975
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.4054103457
Short name T622
Test name
Test status
Simulation time 1448453059 ps
CPU time 6.25 seconds
Started Jul 18 06:27:20 PM PDT 24
Finished Jul 18 06:27:27 PM PDT 24
Peak memory 208664 kb
Host smart-e8c4d7c6-3d6f-4af8-93f6-442f05b6c9ba
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054103457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.4054103457
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.2484637371
Short name T555
Test name
Test status
Simulation time 118627108 ps
CPU time 4.39 seconds
Started Jul 18 06:27:21 PM PDT 24
Finished Jul 18 06:27:28 PM PDT 24
Peak memory 208424 kb
Host smart-de5d8459-bfb2-42bc-ab58-98d53acb9f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484637371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.2484637371
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.1735750598
Short name T540
Test name
Test status
Simulation time 40518724 ps
CPU time 2.28 seconds
Started Jul 18 06:27:04 PM PDT 24
Finished Jul 18 06:27:08 PM PDT 24
Peak memory 207684 kb
Host smart-04153519-7bb4-4bf1-828f-732a084b4cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735750598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.1735750598
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.683997738
Short name T657
Test name
Test status
Simulation time 185226434 ps
CPU time 8.61 seconds
Started Jul 18 06:27:22 PM PDT 24
Finished Jul 18 06:27:32 PM PDT 24
Peak memory 216236 kb
Host smart-1fa3002e-75a6-4f57-b89f-0778c8997941
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683997738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.683997738
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.3169359188
Short name T303
Test name
Test status
Simulation time 1393020308 ps
CPU time 11.92 seconds
Started Jul 18 06:27:22 PM PDT 24
Finished Jul 18 06:27:36 PM PDT 24
Peak memory 222468 kb
Host smart-5371c4eb-c7c5-482e-80df-f1ba3de8ee47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169359188 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.3169359188
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.3149153674
Short name T424
Test name
Test status
Simulation time 138762288 ps
CPU time 2.47 seconds
Started Jul 18 06:27:20 PM PDT 24
Finished Jul 18 06:27:24 PM PDT 24
Peak memory 207420 kb
Host smart-e2e08f8d-265f-4796-bf57-3bdf42336696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149153674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.3149153674
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.3245625918
Short name T513
Test name
Test status
Simulation time 67039131 ps
CPU time 3.01 seconds
Started Jul 18 06:27:22 PM PDT 24
Finished Jul 18 06:27:28 PM PDT 24
Peak memory 210168 kb
Host smart-d5e6f32b-b892-4a32-b2f5-cc3505f2acdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245625918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.3245625918
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.1318619978
Short name T581
Test name
Test status
Simulation time 11469964 ps
CPU time 0.74 seconds
Started Jul 18 06:27:24 PM PDT 24
Finished Jul 18 06:27:27 PM PDT 24
Peak memory 205872 kb
Host smart-45d829fa-e161-4e79-b0d9-73a9694c3304
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318619978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.1318619978
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.3906576024
Short name T355
Test name
Test status
Simulation time 94517408 ps
CPU time 3.72 seconds
Started Jul 18 06:27:23 PM PDT 24
Finished Jul 18 06:27:29 PM PDT 24
Peak memory 215024 kb
Host smart-90d43e32-cbae-4b3b-92c5-01fca82ab621
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3906576024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3906576024
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.636132781
Short name T692
Test name
Test status
Simulation time 308077552 ps
CPU time 3.35 seconds
Started Jul 18 06:27:24 PM PDT 24
Finished Jul 18 06:27:29 PM PDT 24
Peak memory 209812 kb
Host smart-3c1feafa-6ddf-4686-a2f2-0181816a1838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636132781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.636132781
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.1196287436
Short name T662
Test name
Test status
Simulation time 104209595 ps
CPU time 2.31 seconds
Started Jul 18 06:27:23 PM PDT 24
Finished Jul 18 06:27:28 PM PDT 24
Peak memory 218172 kb
Host smart-b8d3f726-cd96-4560-9e06-b09d5b0a21c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196287436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.1196287436
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.1347338101
Short name T287
Test name
Test status
Simulation time 57438095 ps
CPU time 1.91 seconds
Started Jul 18 06:27:23 PM PDT 24
Finished Jul 18 06:27:27 PM PDT 24
Peak memory 214172 kb
Host smart-9d4e8132-15ae-4ada-a7b5-b1a97687f193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347338101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.1347338101
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.4242467769
Short name T737
Test name
Test status
Simulation time 494481460 ps
CPU time 3.1 seconds
Started Jul 18 06:27:21 PM PDT 24
Finished Jul 18 06:27:26 PM PDT 24
Peak memory 214068 kb
Host smart-17e56ffd-b7cf-48cb-8ada-9bad3425e459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242467769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.4242467769
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.2017891703
Short name T393
Test name
Test status
Simulation time 322139772 ps
CPU time 4.24 seconds
Started Jul 18 06:27:24 PM PDT 24
Finished Jul 18 06:27:30 PM PDT 24
Peak memory 214144 kb
Host smart-19e65a37-47d4-4a7d-81c4-c6e97ead50b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017891703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2017891703
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.1258465703
Short name T688
Test name
Test status
Simulation time 22729586 ps
CPU time 1.96 seconds
Started Jul 18 06:27:23 PM PDT 24
Finished Jul 18 06:27:27 PM PDT 24
Peak memory 208560 kb
Host smart-7f78d540-ce81-4aee-a5ec-657aea40bada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258465703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1258465703
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.1529055253
Short name T883
Test name
Test status
Simulation time 133125115 ps
CPU time 4.19 seconds
Started Jul 18 06:27:22 PM PDT 24
Finished Jul 18 06:27:28 PM PDT 24
Peak memory 206660 kb
Host smart-4517c3ef-7c2f-49cc-a5a7-e631c55456f5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529055253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.1529055253
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.1932401985
Short name T726
Test name
Test status
Simulation time 214741320 ps
CPU time 4.56 seconds
Started Jul 18 06:27:23 PM PDT 24
Finished Jul 18 06:27:30 PM PDT 24
Peak memory 206564 kb
Host smart-20574081-b7d6-44a0-9194-1ea07027e3c6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932401985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.1932401985
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.591022357
Short name T591
Test name
Test status
Simulation time 63899081 ps
CPU time 2.97 seconds
Started Jul 18 06:27:24 PM PDT 24
Finished Jul 18 06:27:29 PM PDT 24
Peak memory 207248 kb
Host smart-3224612e-2983-4d1a-b389-75e6f762f5c3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591022357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.591022357
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.1853068065
Short name T280
Test name
Test status
Simulation time 371487834 ps
CPU time 4.33 seconds
Started Jul 18 06:27:21 PM PDT 24
Finished Jul 18 06:27:28 PM PDT 24
Peak memory 208644 kb
Host smart-e664dce2-75da-42b3-a844-7371366b0d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853068065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.1853068065
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.1241656217
Short name T637
Test name
Test status
Simulation time 143044733 ps
CPU time 4.59 seconds
Started Jul 18 06:27:24 PM PDT 24
Finished Jul 18 06:27:31 PM PDT 24
Peak memory 208440 kb
Host smart-a3815e34-e16e-4edb-b439-b2ddd27e76c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241656217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1241656217
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.579169802
Short name T250
Test name
Test status
Simulation time 2907185227 ps
CPU time 29.3 seconds
Started Jul 18 06:27:21 PM PDT 24
Finished Jul 18 06:27:52 PM PDT 24
Peak memory 216892 kb
Host smart-5e0c94d9-a9b9-43f6-866a-83b5bb377a8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579169802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.579169802
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.3597864236
Short name T64
Test name
Test status
Simulation time 165610355 ps
CPU time 10.23 seconds
Started Jul 18 06:27:22 PM PDT 24
Finished Jul 18 06:27:34 PM PDT 24
Peak memory 222288 kb
Host smart-d58a073b-80af-4cef-8941-cbf3a571eabb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597864236 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.3597864236
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.1445224413
Short name T611
Test name
Test status
Simulation time 15335211039 ps
CPU time 73.47 seconds
Started Jul 18 06:27:23 PM PDT 24
Finished Jul 18 06:28:39 PM PDT 24
Peak memory 209340 kb
Host smart-158e58f6-fed9-4d41-bd50-b6e572eafe13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445224413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.1445224413
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.812147224
Short name T760
Test name
Test status
Simulation time 42460368 ps
CPU time 2.07 seconds
Started Jul 18 06:27:23 PM PDT 24
Finished Jul 18 06:27:28 PM PDT 24
Peak memory 209572 kb
Host smart-bc1b0baf-d1be-418e-81f9-53329220e05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812147224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.812147224
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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