Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
55262 |
1 |
|
|
T2 |
51 |
|
T3 |
59 |
|
T4 |
132 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
32627 |
1 |
|
|
T2 |
44 |
|
T3 |
16 |
|
T4 |
75 |
auto[1] |
22635 |
1 |
|
|
T2 |
7 |
|
T3 |
43 |
|
T4 |
57 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
27376 |
1 |
|
|
T2 |
25 |
|
T3 |
30 |
|
T4 |
67 |
auto[1] |
27886 |
1 |
|
|
T2 |
26 |
|
T3 |
29 |
|
T4 |
65 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
16099 |
1 |
|
|
T2 |
22 |
|
T3 |
8 |
|
T4 |
40 |
all_values[0] |
auto[0] |
auto[1] |
16528 |
1 |
|
|
T2 |
22 |
|
T3 |
8 |
|
T4 |
35 |
all_values[0] |
auto[1] |
auto[0] |
11277 |
1 |
|
|
T2 |
3 |
|
T3 |
22 |
|
T4 |
27 |
all_values[0] |
auto[1] |
auto[1] |
11358 |
1 |
|
|
T2 |
4 |
|
T3 |
21 |
|
T4 |
30 |