Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10520

1

T2

4

T3

12

T4

15

auto[Attestation]

7522

1

T2

6

T3

9

T4

22

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2625	1			T2	2		T3	4		T4	6
auto[Aes]	3351	1			T2	2		T3	5		T4	4
auto[Kmac]	3251	1			T3	3		T4	4		T5	1
auto[Otbn]	3214	1			T2	2		T3	2		T4	4

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7356	1			T2	8		T3	8		T4	16
auto[OpGenId]	5601	1			T2	4		T3	7		T4	19
auto[OpGenSwOut]	5814	1			T2	6		T3	6		T4	14
auto[OpGenHwOut]	6627	1			T3	8		T4	4		T5	2
auto[OpDisable]	114	1			T15	1		T47	1		T48	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10311

1

T2

8

T3

8

T4

23

auto[OpDoneFail]

15201

1

T2

10

T3

21

T4

30

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6167	1			T2	3		T3	9		T4	17
auto[StInit]	3592	1			T2	2		T3	6		T4	13
auto[StCreatorRootKey]	3170	1			T2	2		T3	4		T4	12
auto[StOwnerIntKey]	2670	1			T2	2		T3	1		T4	2
auto[StOwnerKey]	2372	1			T2	2		T3	2		T4	2
auto[StDisabled]	7541	1			T2	7		T3	7		T4	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	297	1			T3	1		T4	2		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	93	1			T42	1		T69	1		T7	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	88	1			T4	1		T155	1		T139	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	92	1			T55	2		T199	1		T200	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	61	1			T15	1		T55	1		T49	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	227	1			T2	1		T17	1		T18	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	344	1			T2	1		T3	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	100	1			T3	1		T201	1		T134	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	82	1			T55	1		T69	1		T50	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	73	1			T202	1		T203	1		T204	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	67	1			T17	1		T18	1		T205	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	194	1			T43	2		T206	1		T205	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	329	1			T15	1		T43	1		T207	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	102	1			T43	3		T202	1		T69	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	88	1			T17	1		T206	1		T55	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	68	1			T202	1		T59	1		T208	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	64	1			T17	1		T43	1		T209	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	174	1			T34	1		T210	1		T206	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	314	1			T2	1		T5	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	112	1			T3	1		T17	1		T43	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	97	1			T18	1		T43	1		T210	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	59	1			T201	1		T139	1		T211	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	66	1			T4	1		T17	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	214	1			T42	1		T90	2		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	76	1			T4	1		T7	2		T60	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	94	1			T17	1		T155	1		T142	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	94	1			T2	1		T4	1		T90	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	61	1			T17	1		T42	2		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	42	1			T203	1		T6	1		T60	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	218	1			T15	1		T34	1		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	83	1			T6	1		T7	2		T60	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	117	1			T2	1		T4	2		T202	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	95	1			T4	1		T42	1		T202	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	76	1			T202	1		T47	1		T212	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	72	1			T210	1		T55	1		T199	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	193	1			T42	1		T43	1		T205	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	86	1			T7	5		T60	1		T72	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	98	1			T15	1		T43	1		T201	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	74	1			T4	1		T213	1		T69	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	63	1			T15	1		T34	1		T210	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	63	1			T3	1		T42	1		T207	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	190	1			T3	1		T4	1		T18	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	77	1			T4	1		T202	1		T7	5
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	87	1			T42	1		T214	1		T139	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	100	1			T4	1		T17	1		T207	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	85	1			T4	1		T210	1		T215	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	66	1			T55	1		T134	1		T156	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	199	1			T2	1		T17	2		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	266	1			T3	2		T15	1		T45	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	77	1			T55	1		T121	1		T138	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	61	1			T90	1		T48	1		T121	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	53	1			T48	1		T199	1		T46	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	37	1			T213	1		T46	1		T60	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	180	1			T3	1		T18	2		T215	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	446	1			T5	1		T15	1		T43	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	116	1			T138	1		T212	1		T70	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	119	1			T42	1		T210	1		T215	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	89	1			T136	1		T141	1		T212	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	77	1			T42	1		T43	1		T134	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	287	1			T90	2		T215	2		T55	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	429	1			T3	1		T18	2		T43	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	116	1			T5	1		T47	1		T215	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	109	1			T89	1		T216	1		T214	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	97	1			T43	1		T201	1		T55	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	86	1			T17	1		T201	3		T216	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	247	1			T17	1		T89	3		T210	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	377	1			T15	1		T43	1		T107	12
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	97	1			T217	1		T213	1		T138	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	102	1			T214	1		T217	1		T140	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	92	1			T107	1		T135	1		T140	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	72	1			T42	1		T201	1		T107	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	246	1			T16	2		T17	1		T18	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	62	1			T6	1		T7	1		T60	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	95	1			T139	1		T156	1		T218	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	61	1			T4	1		T44	1		T60	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	62	1			T201	1		T59	1		T46	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	59	1			T18	1		T215	1		T134	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	169	1			T90	2		T43	4		T219	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	57	1			T6	1		T7	2		T60	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	127	1			T3	2		T17	1		T201	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	107	1			T3	1		T4	1		T210	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	91	1			T215	1		T55	1		T212	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	85	1			T90	1		T55	1		T213	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	254	1			T43	2		T134	1		T136	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	48	1			T4	1		T7	1		T72	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	135	1			T4	1		T89	1		T201	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	114	1			T15	1		T17	1		T42	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	98	1			T17	1		T89	1		T43	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	86	1			T89	1		T201	2		T206	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	287	1			T15	1		T18	1		T89	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	56	1			T7	1		T60	2		T72	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	112	1			T15	1		T16	1		T43	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	123	1			T3	1		T16	1		T107	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	82	1			T16	1		T210	1		T215	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	87	1			T16	1		T42	1		T43	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	292	1			T16	2		T18	2		T42	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	223	1			T4	1		T15	1		T55	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	635	1			T2	1		T3	1		T4	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	207	1			T17	1		T18	1		T205	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	653	1			T2	1		T3	2		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	201	1			T17	1		T43	1		T206	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	624	1			T15	1		T17	1		T34	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	208	1			T4	1		T17	1		T18	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	654	1			T2	1		T3	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	181	1			T2	1		T4	1		T42	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	404	1			T4	1		T15	1		T17	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	232	1			T4	1		T42	1		T210	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	404	1			T2	1		T4	2		T42	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	181	1			T3	1		T15	1		T34	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	393	1			T3	1		T4	2		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	234	1			T4	2		T210	1		T207	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	380	1			T2	1		T4	1		T17	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	138	1			T90	1		T213	1		T48	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	536	1			T3	3		T15	1		T18	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	271	1			T42	2		T43	1		T210	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	863	1			T5	1		T15	1		T90	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	271	1			T17	1		T89	1		T43	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	813	1			T3	1		T5	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	258	1			T42	1		T201	1		T107	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	728	1			T15	1		T16	2		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	167	1			T18	1		T201	1		T215	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	341	1			T4	1		T90	2		T43	4
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	269	1			T4	1		T90	1		T210	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	452	1			T3	3		T17	1		T43	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	283	1			T15	1		T17	1		T42	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	485	1			T4	2		T15	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	282	1			T3	1		T16	3		T42	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	470	1			T15	1		T16	3		T18	2