Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31382

1

T2

21

T3

31

T4

61

auto[1]

299

1

T121

6

T134

2

T156

11

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	31393	1			T2	21		T3	31		T4	61
auto[134217728:268435455]	7	1			T156	1		T314	1		T144	1
auto[268435456:402653183]	4	1			T156	1		T408	1		T385	1
auto[402653184:536870911]	7	1			T134	1		T314	1		T302	1
auto[536870912:671088639]	4	1			T121	1		T395	1		T243	1
auto[671088640:805306367]	9	1			T294	1		T148	1		T351	1
auto[805306368:939524095]	14	1			T121	1		T314	2		T144	1
auto[939524096:1073741823]	5	1			T121	1		T294	1		T148	1
auto[1073741824:1207959551]	14	1			T314	1		T294	1		T148	1
auto[1207959552:1342177279]	8	1			T134	1		T147	1		T302	1
auto[1342177280:1476395007]	8	1			T156	1		T314	1		T353	2
auto[1476395008:1610612735]	9	1			T409	1		T408	1		T410	1
auto[1610612736:1744830463]	12	1			T156	1		T314	1		T256	1
auto[1744830464:1879048191]	14	1			T143	1		T148	2		T353	1
auto[1879048192:2013265919]	15	1			T314	2		T256	1		T294	1
auto[2013265920:2147483647]	11	1			T121	1		T156	3		T314	1
auto[2147483648:2281701375]	7	1			T314	1		T302	1		T298	1
auto[2281701376:2415919103]	12	1			T121	1		T156	1		T294	1
auto[2415919104:2550136831]	5	1			T256	1		T316	1		T411	1
auto[2550136832:2684354559]	15	1			T156	1		T144	1		T294	2
auto[2684354560:2818572287]	16	1			T121	1		T314	1		T256	1
auto[2818572288:2952790015]	7	1			T298	1		T299	1		T344	1
auto[2952790016:3087007743]	13	1			T156	1		T353	1		T243	1
auto[3087007744:3221225471]	9	1			T256	1		T144	1		T409	1
auto[3221225472:3355443199]	5	1			T314	1		T409	1		T333	1
auto[3355443200:3489660927]	9	1			T144	1		T145	1		T147	1
auto[3489660928:3623878655]	11	1			T294	1		T353	2		T409	1
auto[3623878656:3758096383]	7	1			T256	1		T294	1		T148	2
auto[3758096384:3892314111]	6	1			T302	1		T353	1		T412	1
auto[3892314112:4026531839]	8	1			T156	1		T314	1		T299	1
auto[4026531840:4160749567]	7	1			T314	1		T145	1		T353	1
auto[4160749568:4294967295]	10	1			T294	1		T243	1		T413	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	31382	1			T2	21		T3	31		T4	61
auto[0:134217727]	auto[1]	11	1			T144	1		T148	1		T412	1
auto[134217728:268435455]	auto[1]	7	1			T156	1		T314	1		T144	1
auto[268435456:402653183]	auto[1]	4	1			T156	1		T408	1		T385	1
auto[402653184:536870911]	auto[1]	7	1			T134	1		T314	1		T302	1
auto[536870912:671088639]	auto[1]	4	1			T121	1		T395	1		T243	1
auto[671088640:805306367]	auto[1]	9	1			T294	1		T148	1		T351	1
auto[805306368:939524095]	auto[1]	14	1			T121	1		T314	2		T144	1
auto[939524096:1073741823]	auto[1]	5	1			T121	1		T294	1		T148	1
auto[1073741824:1207959551]	auto[1]	14	1			T314	1		T294	1		T148	1
auto[1207959552:1342177279]	auto[1]	8	1			T134	1		T147	1		T302	1
auto[1342177280:1476395007]	auto[1]	8	1			T156	1		T314	1		T353	2
auto[1476395008:1610612735]	auto[1]	9	1			T409	1		T408	1		T410	1
auto[1610612736:1744830463]	auto[1]	12	1			T156	1		T314	1		T256	1
auto[1744830464:1879048191]	auto[1]	14	1			T143	1		T148	2		T353	1
auto[1879048192:2013265919]	auto[1]	15	1			T314	2		T256	1		T294	1
auto[2013265920:2147483647]	auto[1]	11	1			T121	1		T156	3		T314	1
auto[2147483648:2281701375]	auto[1]	7	1			T314	1		T302	1		T298	1
auto[2281701376:2415919103]	auto[1]	12	1			T121	1		T156	1		T294	1
auto[2415919104:2550136831]	auto[1]	5	1			T256	1		T316	1		T411	1
auto[2550136832:2684354559]	auto[1]	15	1			T156	1		T144	1		T294	2
auto[2684354560:2818572287]	auto[1]	16	1			T121	1		T314	1		T256	1
auto[2818572288:2952790015]	auto[1]	7	1			T298	1		T299	1		T344	1
auto[2952790016:3087007743]	auto[1]	13	1			T156	1		T353	1		T243	1
auto[3087007744:3221225471]	auto[1]	9	1			T256	1		T144	1		T409	1
auto[3221225472:3355443199]	auto[1]	5	1			T314	1		T409	1		T333	1
auto[3355443200:3489660927]	auto[1]	9	1			T144	1		T145	1		T147	1
auto[3489660928:3623878655]	auto[1]	11	1			T294	1		T353	2		T409	1
auto[3623878656:3758096383]	auto[1]	7	1			T256	1		T294	1		T148	2
auto[3758096384:3892314111]	auto[1]	6	1			T302	1		T353	1		T412	1
auto[3892314112:4026531839]	auto[1]	8	1			T156	1		T314	1		T299	1
auto[4026531840:4160749567]	auto[1]	7	1			T314	1		T145	1		T353	1
auto[4160749568:4294967295]	auto[1]	10	1			T294	1		T243	1		T413	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1519

1

T3

3

T4

2

T17

1

auto[1]

1665

1

T3

4

T4

5

T15

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	86	1			T90	1		T35	1		T45	1
auto[134217728:268435455]	114	1			T4	1		T15	2		T18	1
auto[268435456:402653183]	85	1			T3	1		T4	1		T18	1
auto[402653184:536870911]	78	1			T48	1		T134	1		T209	1
auto[536870912:671088639]	110	1			T17	1		T43	1		T134	1
auto[671088640:805306367]	101	1			T3	1		T43	1		T138	1
auto[805306368:939524095]	79	1			T42	1		T201	1		T213	1
auto[939524096:1073741823]	93	1			T3	1		T17	1		T55	1
auto[1073741824:1207959551]	89	1			T17	1		T55	1		T139	1
auto[1207959552:1342177279]	114	1			T4	1		T35	1		T55	1
auto[1342177280:1476395007]	104	1			T4	1		T42	1		T43	1
auto[1476395008:1610612735]	85	1			T3	1		T90	1		T215	1
auto[1610612736:1744830463]	103	1			T18	1		T19	1		T35	1
auto[1744830464:1879048191]	124	1			T42	1		T43	2		T215	1
auto[1879048192:2013265919]	111	1			T15	1		T45	1		T156	1
auto[2013265920:2147483647]	112	1			T18	1		T19	1		T45	1
auto[2147483648:2281701375]	101	1			T3	1		T44	1		T214	1
auto[2281701376:2415919103]	133	1			T3	1		T90	1		T215	1
auto[2415919104:2550136831]	82	1			T210	1		T215	1		T51	1
auto[2550136832:2684354559]	85	1			T55	1		T213	1		T69	1
auto[2684354560:2818572287]	107	1			T201	1		T49	1		T200	1
auto[2818572288:2952790015]	117	1			T4	1		T18	1		T19	1
auto[2952790016:3087007743]	98	1			T18	1		T210	1		T45	2
auto[3087007744:3221225471]	97	1			T18	1		T55	2		T48	2
auto[3221225472:3355443199]	81	1			T19	1		T55	1		T52	1
auto[3355443200:3489660927]	89	1			T17	1		T210	1		T156	1
auto[3489660928:3623878655]	112	1			T19	1		T210	1		T55	1
auto[3623878656:3758096383]	79	1			T104	1		T45	1		T138	1
auto[3758096384:3892314111]	102	1			T43	1		T104	1		T55	1
auto[3892314112:4026531839]	118	1			T17	1		T215	1		T51	1
auto[4026531840:4160749567]	89	1			T3	1		T4	1		T42	1
auto[4160749568:4294967295]	106	1			T4	1		T210	1		T139	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	44	1			T45	1		T48	1		T56	1
auto[0:134217727]	auto[1]	42	1			T90	1		T35	1		T134	1
auto[134217728:268435455]	auto[0]	56	1			T4	1		T44	1		T52	2
auto[134217728:268435455]	auto[1]	58	1			T15	2		T18	1		T85	1
auto[268435456:402653183]	auto[0]	40	1			T201	1		T47	1		T44	1
auto[268435456:402653183]	auto[1]	45	1			T3	1		T4	1		T18	1
auto[402653184:536870911]	auto[0]	37	1			T134	1		T56	1		T6	1
auto[402653184:536870911]	auto[1]	41	1			T48	1		T209	1		T94	1
auto[536870912:671088639]	auto[0]	48	1			T7	1		T71	1		T85	2
auto[536870912:671088639]	auto[1]	62	1			T17	1		T43	1		T134	1
auto[671088640:805306367]	auto[0]	44	1			T49	1		T84	1		T279	1
auto[671088640:805306367]	auto[1]	57	1			T3	1		T43	1		T138	1
auto[805306368:939524095]	auto[0]	34	1			T201	1		T6	1		T46	1
auto[805306368:939524095]	auto[1]	45	1			T42	1		T213	1		T156	1
auto[939524096:1073741823]	auto[0]	47	1			T20	1		T247	3		T315	1
auto[939524096:1073741823]	auto[1]	46	1			T3	1		T17	1		T55	1
auto[1073741824:1207959551]	auto[0]	44	1			T6	1		T46	1		T251	1
auto[1073741824:1207959551]	auto[1]	45	1			T17	1		T55	1		T139	1
auto[1207959552:1342177279]	auto[0]	57	1			T35	1		T55	1		T60	1
auto[1207959552:1342177279]	auto[1]	57	1			T4	1		T121	1		T156	1
auto[1342177280:1476395007]	auto[0]	51	1			T104	1		T121	1		T6	1
auto[1342177280:1476395007]	auto[1]	53	1			T4	1		T42	1		T43	1
auto[1476395008:1610612735]	auto[0]	44	1			T90	1		T6	2		T7	1
auto[1476395008:1610612735]	auto[1]	41	1			T3	1		T215	1		T94	1
auto[1610612736:1744830463]	auto[0]	45	1			T19	1		T35	1		T214	1
auto[1610612736:1744830463]	auto[1]	58	1			T18	1		T44	1		T209	1
auto[1744830464:1879048191]	auto[0]	60	1			T43	1		T215	1		T55	1
auto[1744830464:1879048191]	auto[1]	64	1			T42	1		T43	1		T55	1
auto[1879048192:2013265919]	auto[0]	46	1			T156	1		T69	1		T6	2
auto[1879048192:2013265919]	auto[1]	65	1			T15	1		T45	1		T60	1
auto[2013265920:2147483647]	auto[0]	59	1			T19	1		T45	1		T49	1
auto[2013265920:2147483647]	auto[1]	53	1			T18	1		T55	1		T213	3
auto[2147483648:2281701375]	auto[0]	54	1			T3	1		T44	1		T214	1
auto[2147483648:2281701375]	auto[1]	47	1			T139	1		T218	1		T70	1
auto[2281701376:2415919103]	auto[0]	64	1			T3	1		T215	1		T56	1
auto[2281701376:2415919103]	auto[1]	69	1			T90	1		T55	1		T138	2
auto[2415919104:2550136831]	auto[0]	44	1			T215	1		T51	1		T139	1
auto[2415919104:2550136831]	auto[1]	38	1			T210	1		T45	1		T6	1
auto[2550136832:2684354559]	auto[0]	48	1			T55	1		T213	1		T6	1
auto[2550136832:2684354559]	auto[1]	37	1			T69	1		T6	2		T414	1
auto[2684354560:2818572287]	auto[0]	56	1			T88	1		T248	1		T247	2
auto[2684354560:2818572287]	auto[1]	51	1			T201	1		T49	1		T200	1
auto[2818572288:2952790015]	auto[0]	54	1			T18	1		T19	1		T51	1
auto[2818572288:2952790015]	auto[1]	63	1			T4	1		T55	1		T204	1
auto[2952790016:3087007743]	auto[0]	46	1			T45	2		T48	1		T52	1
auto[2952790016:3087007743]	auto[1]	52	1			T18	1		T210	1		T6	1
auto[3087007744:3221225471]	auto[0]	36	1			T48	1		T69	1		T6	2
auto[3087007744:3221225471]	auto[1]	61	1			T18	1		T55	2		T48	1
auto[3221225472:3355443199]	auto[0]	42	1			T19	1		T52	1		T69	1
auto[3221225472:3355443199]	auto[1]	39	1			T55	1		T218	1		T68	1
auto[3355443200:3489660927]	auto[0]	51	1			T17	1		T210	1		T156	1
auto[3355443200:3489660927]	auto[1]	38	1			T209	1		T247	1		T415	1
auto[3489660928:3623878655]	auto[0]	46	1			T19	1		T55	1		T139	1
auto[3489660928:3623878655]	auto[1]	66	1			T210	1		T121	1		T46	1
auto[3623878656:3758096383]	auto[0]	30	1			T45	1		T156	1		T6	1
auto[3623878656:3758096383]	auto[1]	49	1			T104	1		T138	1		T139	1
auto[3758096384:3892314111]	auto[0]	47	1			T104	1		T60	1		T71	1
auto[3758096384:3892314111]	auto[1]	55	1			T43	1		T55	1		T53	1
auto[3892314112:4026531839]	auto[0]	59	1			T215	1		T51	1		T6	1
auto[3892314112:4026531839]	auto[1]	59	1			T17	1		T199	1		T6	2
auto[4026531840:4160749567]	auto[0]	43	1			T3	1		T56	2		T6	1
auto[4026531840:4160749567]	auto[1]	46	1			T4	1		T42	1		T210	1
auto[4160749568:4294967295]	auto[0]	43	1			T4	1		T139	1		T52	1
auto[4160749568:4294967295]	auto[1]	63	1			T210	1		T156	1		T10	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1514

1

T3

3

T4

2

T17

1

auto[1]

1669

1

T3

4

T4

5

T15

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	92	1			T19	1		T210	2		T52	1
auto[134217728:268435455]	83	1			T17	1		T201	1		T134	1
auto[268435456:402653183]	101	1			T17	1		T42	1		T45	1
auto[402653184:536870911]	102	1			T17	1		T43	1		T201	1
auto[536870912:671088639]	103	1			T15	1		T18	1		T6	1
auto[671088640:805306367]	106	1			T3	1		T215	1		T55	2
auto[805306368:939524095]	88	1			T15	1		T43	1		T210	1
auto[939524096:1073741823]	91	1			T134	1		T209	1		T6	1
auto[1073741824:1207959551]	101	1			T18	1		T90	1		T35	1
auto[1207959552:1342177279]	104	1			T43	1		T35	1		T51	1
auto[1342177280:1476395007]	126	1			T18	2		T19	1		T215	1
auto[1476395008:1610612735]	97	1			T4	2		T17	1		T42	2
auto[1610612736:1744830463]	95	1			T55	1		T121	1		T138	1
auto[1744830464:1879048191]	105	1			T4	1		T19	1		T35	1
auto[1879048192:2013265919]	104	1			T3	1		T18	1		T45	1
auto[2013265920:2147483647]	104	1			T55	1		T48	1		T156	1
auto[2147483648:2281701375]	81	1			T19	1		T43	1		T47	1
auto[2281701376:2415919103]	88	1			T4	1		T43	1		T44	1
auto[2415919104:2550136831]	106	1			T4	1		T138	1		T156	1
auto[2550136832:2684354559]	85	1			T156	1		T70	1		T46	1
auto[2684354560:2818572287]	105	1			T3	1		T17	1		T18	1
auto[2818572288:2952790015]	109	1			T45	1		T48	1		T121	1
auto[2952790016:3087007743]	90	1			T18	1		T213	1		T134	1
auto[3087007744:3221225471]	99	1			T3	1		T4	1		T210	1
auto[3221225472:3355443199]	111	1			T55	1		T49	1		T156	1
auto[3355443200:3489660927]	91	1			T210	1		T138	1		T56	2
auto[3489660928:3623878655]	93	1			T3	1		T15	1		T90	1
auto[3623878656:3758096383]	90	1			T3	1		T44	2		T45	1
auto[3758096384:3892314111]	118	1			T44	1		T55	1		T52	1
auto[3892314112:4026531839]	108	1			T4	1		T42	1		T90	1
auto[4026531840:4160749567]	105	1			T3	1		T104	1		T55	1
auto[4160749568:4294967295]	102	1			T210	1		T215	1		T134	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	38	1			T19	1		T210	1		T52	1
auto[0:134217727]	auto[1]	54	1			T210	1		T218	1		T6	2
auto[134217728:268435455]	auto[0]	44	1			T201	1		T49	1		T69	1
auto[134217728:268435455]	auto[1]	39	1			T17	1		T134	1		T209	1
auto[268435456:402653183]	auto[0]	51	1			T17	1		T42	1		T45	1
auto[268435456:402653183]	auto[1]	50	1			T6	1		T46	1		T60	1
auto[402653184:536870911]	auto[0]	48	1			T43	1		T45	2		T69	1
auto[402653184:536870911]	auto[1]	54	1			T17	1		T201	1		T213	1
auto[536870912:671088639]	auto[0]	41	1			T7	1		T21	1		T263	1
auto[536870912:671088639]	auto[1]	62	1			T15	1		T18	1		T6	1
auto[671088640:805306367]	auto[0]	47	1			T3	1		T215	1		T213	1
auto[671088640:805306367]	auto[1]	59	1			T55	2		T48	1		T69	1
auto[805306368:939524095]	auto[0]	42	1			T6	1		T60	1		T247	1
auto[805306368:939524095]	auto[1]	46	1			T15	1		T43	1		T210	1
auto[939524096:1073741823]	auto[0]	47	1			T6	1		T60	1		T68	1
auto[939524096:1073741823]	auto[1]	44	1			T134	1		T209	1		T60	1
auto[1073741824:1207959551]	auto[0]	47	1			T90	1		T35	1		T215	1
auto[1073741824:1207959551]	auto[1]	54	1			T18	1		T104	1		T55	1
auto[1207959552:1342177279]	auto[0]	47	1			T51	1		T104	1		T20	1
auto[1207959552:1342177279]	auto[1]	57	1			T43	1		T35	1		T213	1
auto[1342177280:1476395007]	auto[0]	67	1			T18	1		T19	1		T215	1
auto[1342177280:1476395007]	auto[1]	59	1			T18	1		T213	1		T56	1
auto[1476395008:1610612735]	auto[0]	41	1			T4	1		T200	1		T6	1
auto[1476395008:1610612735]	auto[1]	56	1			T4	1		T17	1		T42	2
auto[1610612736:1744830463]	auto[0]	41	1			T138	1		T52	1		T56	1
auto[1610612736:1744830463]	auto[1]	54	1			T55	1		T121	1		T6	2
auto[1744830464:1879048191]	auto[0]	55	1			T19	1		T215	1		T51	1
auto[1744830464:1879048191]	auto[1]	50	1			T4	1		T35	1		T139	1
auto[1879048192:2013265919]	auto[0]	50	1			T139	1		T69	1		T218	1
auto[1879048192:2013265919]	auto[1]	54	1			T3	1		T18	1		T45	1
auto[2013265920:2147483647]	auto[0]	50	1			T48	1		T156	1		T6	1
auto[2013265920:2147483647]	auto[1]	54	1			T55	1		T53	1		T70	1
auto[2147483648:2281701375]	auto[0]	43	1			T19	1		T47	1		T55	1
auto[2147483648:2281701375]	auto[1]	38	1			T43	1		T55	1		T250	1
auto[2281701376:2415919103]	auto[0]	49	1			T4	1		T214	1		T6	1
auto[2281701376:2415919103]	auto[1]	39	1			T43	1		T44	1		T87	1
auto[2415919104:2550136831]	auto[0]	50	1			T56	1		T6	1		T95	1
auto[2415919104:2550136831]	auto[1]	56	1			T4	1		T138	1		T156	1
auto[2550136832:2684354559]	auto[0]	45	1			T46	1		T62	1		T21	1
auto[2550136832:2684354559]	auto[1]	40	1			T156	1		T70	1		T7	1
auto[2684354560:2818572287]	auto[0]	56	1			T19	1		T56	1		T84	1
auto[2684354560:2818572287]	auto[1]	49	1			T3	1		T17	1		T18	1
auto[2818572288:2952790015]	auto[0]	42	1			T45	1		T48	1		T46	1
auto[2818572288:2952790015]	auto[1]	67	1			T121	1		T200	1		T46	1
auto[2952790016:3087007743]	auto[0]	45	1			T213	1		T139	1		T156	1
auto[2952790016:3087007743]	auto[1]	45	1			T18	1		T134	1		T7	2
auto[3087007744:3221225471]	auto[0]	51	1			T35	1		T51	1		T139	1
auto[3087007744:3221225471]	auto[1]	48	1			T3	1		T4	1		T210	1
auto[3221225472:3355443199]	auto[0]	48	1			T6	2		T11	1		T72	1
auto[3221225472:3355443199]	auto[1]	63	1			T55	1		T49	1		T156	1
auto[3355443200:3489660927]	auto[0]	43	1			T210	1		T56	2		T212	1
auto[3355443200:3489660927]	auto[1]	48	1			T138	1		T95	1		T46	1
auto[3489660928:3623878655]	auto[0]	38	1			T3	1		T48	1		T52	1
auto[3489660928:3623878655]	auto[1]	55	1			T15	1		T90	1		T43	1
auto[3623878656:3758096383]	auto[0]	46	1			T3	1		T44	1		T45	1
auto[3623878656:3758096383]	auto[1]	44	1			T44	1		T53	1		T60	1
auto[3758096384:3892314111]	auto[0]	60	1			T44	1		T6	2		T60	2
auto[3758096384:3892314111]	auto[1]	58	1			T55	1		T52	1		T6	1
auto[3892314112:4026531839]	auto[0]	42	1			T214	1		T95	1		T204	1
auto[3892314112:4026531839]	auto[1]	66	1			T4	1		T42	1		T90	1
auto[4026531840:4160749567]	auto[0]	48	1			T104	1		T53	1		T84	1
auto[4026531840:4160749567]	auto[1]	57	1			T3	1		T55	1		T52	1
auto[4160749568:4294967295]	auto[0]	52	1			T215	1		T52	1		T6	1
auto[4160749568:4294967295]	auto[1]	50	1			T210	1		T134	1		T139	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1513

1

T3

2

T4

2

T17

1

auto[1]

1672

1

T3

5

T4

5

T15

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	106	1			T18	1		T44	2		T45	1
auto[134217728:268435455]	95	1			T43	1		T210	1		T44	1
auto[268435456:402653183]	102	1			T18	1		T19	1		T55	1
auto[402653184:536870911]	96	1			T18	1		T19	1		T201	1
auto[536870912:671088639]	125	1			T3	2		T4	1		T210	1
auto[671088640:805306367]	86	1			T15	1		T210	1		T201	1
auto[805306368:939524095]	106	1			T3	1		T4	1		T17	1
auto[939524096:1073741823]	109	1			T18	1		T210	1		T215	1
auto[1073741824:1207959551]	105	1			T18	1		T90	1		T43	2
auto[1207959552:1342177279]	95	1			T19	1		T52	1		T6	1
auto[1342177280:1476395007]	107	1			T201	1		T55	1		T138	1
auto[1476395008:1610612735]	99	1			T213	1		T121	1		T156	1
auto[1610612736:1744830463]	92	1			T3	1		T17	1		T215	1
auto[1744830464:1879048191]	84	1			T139	2		T156	1		T69	1
auto[1879048192:2013265919]	106	1			T45	1		T121	1		T56	1
auto[2013265920:2147483647]	97	1			T4	1		T42	1		T53	1
auto[2147483648:2281701375]	102	1			T4	1		T43	1		T215	1
auto[2281701376:2415919103]	89	1			T17	1		T210	1		T35	1
auto[2415919104:2550136831]	107	1			T4	1		T90	1		T55	1
auto[2550136832:2684354559]	93	1			T17	1		T19	1		T35	1
auto[2684354560:2818572287]	96	1			T134	1		T138	1		T56	1
auto[2818572288:2952790015]	112	1			T15	1		T45	1		T48	2
auto[2952790016:3087007743]	82	1			T48	2		T134	1		T56	1
auto[3087007744:3221225471]	105	1			T3	1		T55	2		T134	1
auto[3221225472:3355443199]	85	1			T55	1		T52	1		T69	1
auto[3355443200:3489660927]	105	1			T42	1		T44	1		T209	1
auto[3489660928:3623878655]	110	1			T4	1		T51	1		T45	1
auto[3623878656:3758096383]	95	1			T19	1		T44	1		T45	1
auto[3758096384:3892314111]	106	1			T3	1		T4	1		T17	1
auto[3892314112:4026531839]	96	1			T3	1		T15	1		T18	2
auto[4026531840:4160749567]	100	1			T42	2		T43	1		T210	1
auto[4160749568:4294967295]	92	1			T215	1		T55	1		T48	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	48	1			T45	1		T139	1		T56	1
auto[0:134217727]	auto[1]	58	1			T18	1		T44	2		T213	1
auto[134217728:268435455]	auto[0]	49	1			T44	1		T204	2		T46	1
auto[134217728:268435455]	auto[1]	46	1			T43	1		T210	1		T121	1
auto[268435456:402653183]	auto[0]	55	1			T19	1		T138	1		T56	1
auto[268435456:402653183]	auto[1]	47	1			T18	1		T55	1		T46	1
auto[402653184:536870911]	auto[0]	39	1			T19	1		T52	2		T200	1
auto[402653184:536870911]	auto[1]	57	1			T18	1		T201	1		T55	1
auto[536870912:671088639]	auto[0]	71	1			T3	1		T51	1		T56	1
auto[536870912:671088639]	auto[1]	54	1			T3	1		T4	1		T210	1
auto[671088640:805306367]	auto[0]	37	1			T210	1		T201	1		T35	1
auto[671088640:805306367]	auto[1]	49	1			T15	1		T55	1		T121	1
auto[805306368:939524095]	auto[0]	41	1			T4	1		T17	1		T215	1
auto[805306368:939524095]	auto[1]	65	1			T3	1		T43	1		T35	1
auto[939524096:1073741823]	auto[0]	52	1			T215	1		T139	1		T52	1
auto[939524096:1073741823]	auto[1]	57	1			T18	1		T210	1		T209	1
auto[1073741824:1207959551]	auto[0]	46	1			T43	1		T6	2		T7	1
auto[1073741824:1207959551]	auto[1]	59	1			T18	1		T90	1		T43	1
auto[1207959552:1342177279]	auto[0]	56	1			T19	1		T20	1		T60	1
auto[1207959552:1342177279]	auto[1]	39	1			T52	1		T6	1		T46	1
auto[1342177280:1476395007]	auto[0]	48	1			T201	1		T49	1		T69	1
auto[1342177280:1476395007]	auto[1]	59	1			T55	1		T138	1		T6	2
auto[1476395008:1610612735]	auto[0]	48	1			T199	1		T6	1		T46	2
auto[1476395008:1610612735]	auto[1]	51	1			T213	1		T121	1		T156	1
auto[1610612736:1744830463]	auto[0]	46	1			T3	1		T215	1		T51	1
auto[1610612736:1744830463]	auto[1]	46	1			T17	1		T104	1		T45	1
auto[1744830464:1879048191]	auto[0]	45	1			T139	1		T156	1		T6	1
auto[1744830464:1879048191]	auto[1]	39	1			T139	1		T69	1		T87	1
auto[1879048192:2013265919]	auto[0]	51	1			T45	1		T6	1		T279	1
auto[1879048192:2013265919]	auto[1]	55	1			T121	1		T56	1		T95	1
auto[2013265920:2147483647]	auto[0]	55	1			T46	2		T60	1		T247	1
auto[2013265920:2147483647]	auto[1]	42	1			T4	1		T42	1		T53	1
auto[2147483648:2281701375]	auto[0]	47	1			T215	1		T214	1		T55	1
auto[2147483648:2281701375]	auto[1]	55	1			T4	1		T43	1		T55	1
auto[2281701376:2415919103]	auto[0]	40	1			T55	1		T84	1		T87	1
auto[2281701376:2415919103]	auto[1]	49	1			T17	1		T210	1		T35	1
auto[2415919104:2550136831]	auto[0]	47	1			T90	1		T69	1		T56	1
auto[2415919104:2550136831]	auto[1]	60	1			T4	1		T55	1		T213	1
auto[2550136832:2684354559]	auto[0]	48	1			T19	1		T53	1		T20	1
auto[2550136832:2684354559]	auto[1]	45	1			T17	1		T35	1		T156	1
auto[2684354560:2818572287]	auto[0]	47	1			T56	1		T6	1		T84	1
auto[2684354560:2818572287]	auto[1]	49	1			T134	1		T138	1		T70	1
auto[2818572288:2952790015]	auto[0]	46	1			T45	1		T48	1		T139	1
auto[2818572288:2952790015]	auto[1]	66	1			T15	1		T48	1		T46	1
auto[2952790016:3087007743]	auto[0]	36	1			T48	2		T56	1		T6	2
auto[2952790016:3087007743]	auto[1]	46	1			T134	1		T46	1		T87	1
auto[3087007744:3221225471]	auto[0]	44	1			T250	1		T72	1		T247	2
auto[3087007744:3221225471]	auto[1]	61	1			T3	1		T55	2		T134	1
auto[3221225472:3355443199]	auto[0]	38	1			T52	1		T69	1		T6	2
auto[3221225472:3355443199]	auto[1]	47	1			T55	1		T60	1		T414	1
auto[3355443200:3489660927]	auto[0]	53	1			T44	1		T6	1		T11	1
auto[3355443200:3489660927]	auto[1]	52	1			T42	1		T209	1		T416	1
auto[3489660928:3623878655]	auto[0]	55	1			T51	1		T45	1		T103	1
auto[3489660928:3623878655]	auto[1]	55	1			T4	1		T209	1		T6	1
auto[3623878656:3758096383]	auto[0]	46	1			T19	1		T44	1		T45	1
auto[3623878656:3758096383]	auto[1]	49	1			T55	1		T209	1		T10	1
auto[3758096384:3892314111]	auto[0]	56	1			T4	1		T55	1		T213	1
auto[3758096384:3892314111]	auto[1]	50	1			T3	1		T17	1		T94	1
auto[3892314112:4026531839]	auto[0]	39	1			T49	1		T95	1		T46	1
auto[3892314112:4026531839]	auto[1]	57	1			T3	1		T15	1		T18	2
auto[4026531840:4160749567]	auto[0]	44	1			T85	1		T253	1		T72	1
auto[4026531840:4160749567]	auto[1]	56	1			T42	2		T43	1		T210	1
auto[4160749568:4294967295]	auto[0]	40	1			T215	1		T69	1		T6	1
auto[4160749568:4294967295]	auto[1]	52	1			T55	1		T48	1		T134	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1522

1

T3

4

T4

3

T17

1

auto[1]

1663

1

T3

3

T4

4

T15

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	103	1			T17	1		T90	1		T210	1
auto[134217728:268435455]	110	1			T3	1		T42	1		T201	1
auto[268435456:402653183]	92	1			T4	1		T210	1		T55	1
auto[402653184:536870911]	107	1			T17	1		T55	1		T69	1
auto[536870912:671088639]	103	1			T18	1		T43	1		T210	1
auto[671088640:805306367]	101	1			T4	1		T18	1		T35	1
auto[805306368:939524095]	107	1			T35	1		T55	1		T134	1
auto[939524096:1073741823]	89	1			T215	1		T214	1		T139	1
auto[1073741824:1207959551]	98	1			T18	1		T44	1		T55	1
auto[1207959552:1342177279]	97	1			T3	1		T15	1		T18	1
auto[1342177280:1476395007]	86	1			T3	1		T95	1		T7	1
auto[1476395008:1610612735]	92	1			T45	1		T56	1		T200	1
auto[1610612736:1744830463]	94	1			T19	1		T214	1		T45	1
auto[1744830464:1879048191]	95	1			T4	1		T6	1		T46	1
auto[1879048192:2013265919]	103	1			T43	1		T44	1		T55	1
auto[2013265920:2147483647]	92	1			T3	1		T45	1		T134	1
auto[2147483648:2281701375]	102	1			T4	1		T19	1		T138	1
auto[2281701376:2415919103]	101	1			T3	1		T55	1		T156	1
auto[2415919104:2550136831]	104	1			T18	1		T42	1		T90	1
auto[2550136832:2684354559]	107	1			T43	1		T55	1		T213	1
auto[2684354560:2818572287]	104	1			T35	1		T215	1		T44	1
auto[2818572288:2952790015]	102	1			T4	1		T43	1		T47	1
auto[2952790016:3087007743]	108	1			T42	1		T44	1		T213	1
auto[3087007744:3221225471]	107	1			T43	1		T45	1		T48	1
auto[3221225472:3355443199]	98	1			T4	2		T19	1		T42	1
auto[3355443200:3489660927]	103	1			T17	2		T51	1		T55	1
auto[3489660928:3623878655]	113	1			T15	1		T17	1		T201	1
auto[3623878656:3758096383]	101	1			T3	1		T15	1		T19	1
auto[3758096384:3892314111]	91	1			T3	1		T90	1		T51	1
auto[3892314112:4026531839]	77	1			T210	1		T215	1		T104	1
auto[4026531840:4160749567]	113	1			T18	1		T19	1		T51	1
auto[4160749568:4294967295]	85	1			T18	1		T44	1		T45	1