Unified Coverage Report :: Group Instance : salt_4

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2781

1

T3

7

T4

6

T15

3

auto[1]

266

1

T121

5

T156

7

T143

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	105	1			T17	1		T18	1		T19	1
auto[134217728:268435455]	100	1			T3	1		T215	1		T55	1
auto[268435456:402653183]	89	1			T3	1		T121	1		T52	1
auto[402653184:536870911]	103	1			T4	2		T43	1		T215	1
auto[536870912:671088639]	101	1			T15	1		T43	1		T51	1
auto[671088640:805306367]	101	1			T138	1		T156	2		T209	1
auto[805306368:939524095]	95	1			T47	1		T213	1		T49	1
auto[939524096:1073741823]	107	1			T215	1		T55	1		T209	1
auto[1073741824:1207959551]	94	1			T18	1		T42	1		T90	1
auto[1207959552:1342177279]	91	1			T4	1		T15	1		T42	1
auto[1342177280:1476395007]	84	1			T15	1		T156	2		T52	1
auto[1476395008:1610612735]	109	1			T4	1		T210	1		T156	1
auto[1610612736:1744830463]	86	1			T35	2		T55	1		T121	1
auto[1744830464:1879048191]	103	1			T3	1		T19	1		T55	1
auto[1879048192:2013265919]	90	1			T43	1		T55	1		T134	1
auto[2013265920:2147483647]	91	1			T4	1		T210	1		T48	1
auto[2147483648:2281701375]	115	1			T3	2		T18	2		T19	1
auto[2281701376:2415919103]	84	1			T210	1		T35	1		T48	2
auto[2415919104:2550136831]	84	1			T42	1		T48	1		T121	1
auto[2550136832:2684354559]	95	1			T19	1		T43	1		T51	1
auto[2684354560:2818572287]	87	1			T3	1		T43	1		T215	1
auto[2818572288:2952790015]	93	1			T4	1		T17	1		T210	1
auto[2952790016:3087007743]	89	1			T104	1		T213	1		T52	1
auto[3087007744:3221225471]	75	1			T17	1		T52	1		T46	2
auto[3221225472:3355443199]	100	1			T104	1		T213	1		T121	1
auto[3355443200:3489660927]	66	1			T17	1		T213	1		T121	1
auto[3489660928:3623878655]	100	1			T18	1		T201	1		T49	1
auto[3623878656:3758096383]	98	1			T17	1		T18	1		T69	1
auto[3758096384:3892314111]	87	1			T215	1		T6	1		T46	1
auto[3892314112:4026531839]	107	1			T3	1		T43	1		T35	1
auto[4026531840:4160749567]	108	1			T90	1		T201	1		T104	1
auto[4160749568:4294967295]	110	1			T18	1		T19	1		T210	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	97	1			T17	1		T18	1		T19	1
auto[0:134217727]	auto[1]	8	1			T314	1		T145	1		T294	1
auto[134217728:268435455]	auto[0]	93	1			T3	1		T215	1		T55	1
auto[134217728:268435455]	auto[1]	7	1			T294	1		T351	1		T262	1
auto[268435456:402653183]	auto[0]	82	1			T3	1		T121	1		T52	1
auto[268435456:402653183]	auto[1]	7	1			T143	1		T256	1		T412	1
auto[402653184:536870911]	auto[0]	86	1			T4	2		T43	1		T215	1
auto[402653184:536870911]	auto[1]	17	1			T121	1		T314	1		T256	1
auto[536870912:671088639]	auto[0]	95	1			T15	1		T43	1		T51	1
auto[536870912:671088639]	auto[1]	6	1			T256	1		T353	1		T262	1
auto[671088640:805306367]	auto[0]	89	1			T138	1		T156	1		T209	1
auto[671088640:805306367]	auto[1]	12	1			T156	1		T314	1		T145	1
auto[805306368:939524095]	auto[0]	86	1			T47	1		T213	1		T49	1
auto[805306368:939524095]	auto[1]	9	1			T147	1		T353	1		T413	1
auto[939524096:1073741823]	auto[0]	98	1			T215	1		T55	1		T209	1
auto[939524096:1073741823]	auto[1]	9	1			T298	1		T316	1		T412	2
auto[1073741824:1207959551]	auto[0]	84	1			T18	1		T42	1		T90	1
auto[1073741824:1207959551]	auto[1]	10	1			T156	1		T314	1		T145	2
auto[1207959552:1342177279]	auto[0]	86	1			T4	1		T15	1		T42	1
auto[1207959552:1342177279]	auto[1]	5	1			T353	1		T243	1		T409	1
auto[1342177280:1476395007]	auto[0]	77	1			T15	1		T156	2		T52	1
auto[1342177280:1476395007]	auto[1]	7	1			T256	1		T148	1		T353	1
auto[1476395008:1610612735]	auto[0]	104	1			T4	1		T210	1		T70	1
auto[1476395008:1610612735]	auto[1]	5	1			T156	1		T353	1		T408	1
auto[1610612736:1744830463]	auto[0]	84	1			T35	2		T55	1		T121	1
auto[1610612736:1744830463]	auto[1]	2	1			T302	1		T262	1		-	-
auto[1744830464:1879048191]	auto[0]	95	1			T3	1		T19	1		T55	1
auto[1744830464:1879048191]	auto[1]	8	1			T145	1		T385	1		T334	1
auto[1879048192:2013265919]	auto[0]	80	1			T43	1		T55	1		T134	1
auto[1879048192:2013265919]	auto[1]	10	1			T144	1		T145	1		T412	1
auto[2013265920:2147483647]	auto[0]	83	1			T4	1		T210	1		T48	1
auto[2013265920:2147483647]	auto[1]	8	1			T156	1		T144	1		T294	1
auto[2147483648:2281701375]	auto[0]	106	1			T3	2		T18	2		T19	1
auto[2147483648:2281701375]	auto[1]	9	1			T145	1		T148	2		T421	1
auto[2281701376:2415919103]	auto[0]	75	1			T210	1		T35	1		T48	2
auto[2281701376:2415919103]	auto[1]	9	1			T395	1		T410	1		T385	1
auto[2415919104:2550136831]	auto[0]	74	1			T42	1		T48	1		T139	1
auto[2415919104:2550136831]	auto[1]	10	1			T121	1		T302	1		T353	1
auto[2550136832:2684354559]	auto[0]	91	1			T19	1		T43	1		T51	1
auto[2550136832:2684354559]	auto[1]	4	1			T302	1		T299	1		T344	1
auto[2684354560:2818572287]	auto[0]	78	1			T3	1		T43	1		T215	1
auto[2684354560:2818572287]	auto[1]	9	1			T314	3		T145	1		T353	1
auto[2818572288:2952790015]	auto[0]	85	1			T4	1		T17	1		T210	1
auto[2818572288:2952790015]	auto[1]	8	1			T156	1		T421	1		T385	1
auto[2952790016:3087007743]	auto[0]	87	1			T104	1		T213	1		T52	1
auto[2952790016:3087007743]	auto[1]	2	1			T145	1		T410	1		-	-
auto[3087007744:3221225471]	auto[0]	65	1			T17	1		T52	1		T46	2
auto[3087007744:3221225471]	auto[1]	10	1			T145	2		T294	1		T302	1
auto[3221225472:3355443199]	auto[0]	92	1			T104	1		T213	1		T69	1
auto[3221225472:3355443199]	auto[1]	8	1			T121	1		T148	1		T298	1
auto[3355443200:3489660927]	auto[0]	59	1			T17	1		T213	1		T139	1
auto[3355443200:3489660927]	auto[1]	7	1			T121	1		T314	1		T413	1
auto[3489660928:3623878655]	auto[0]	91	1			T18	1		T201	1		T49	1
auto[3489660928:3623878655]	auto[1]	9	1			T314	2		T256	1		T395	1
auto[3623878656:3758096383]	auto[0]	86	1			T17	1		T18	1		T69	1
auto[3623878656:3758096383]	auto[1]	12	1			T144	1		T316	1		T412	1
auto[3758096384:3892314111]	auto[0]	75	1			T215	1		T6	1		T46	1
auto[3758096384:3892314111]	auto[1]	12	1			T256	1		T147	1		T408	1
auto[3892314112:4026531839]	auto[0]	100	1			T3	1		T43	1		T35	1
auto[3892314112:4026531839]	auto[1]	7	1			T121	1		T156	1		T302	1
auto[4026531840:4160749567]	auto[0]	96	1			T90	1		T201	1		T104	1
auto[4026531840:4160749567]	auto[1]	12	1			T145	1		T294	1		T302	1
auto[4160749568:4294967295]	auto[0]	102	1			T18	1		T19	1		T210	1
auto[4160749568:4294967295]	auto[1]	8	1			T156	1		T145	1		T148	1