Unified Coverage Report :: Group Instance : attest_sw_binding_7

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1509

1

T3

3

T4

3

T17

2

auto[1]

1675

1

T3

4

T4

4

T15

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	113	1			T18	1		T210	2		T35	1
auto[134217728:268435455]	111	1			T43	1		T134	1		T49	1
auto[268435456:402653183]	115	1			T19	2		T55	1		T213	1
auto[402653184:536870911]	79	1			T3	1		T90	1		T44	1
auto[536870912:671088639]	110	1			T3	1		T215	1		T104	1
auto[671088640:805306367]	112	1			T18	1		T90	1		T210	1
auto[805306368:939524095]	96	1			T17	1		T43	1		T56	1
auto[939524096:1073741823]	103	1			T17	1		T18	1		T210	1
auto[1073741824:1207959551]	111	1			T15	1		T18	1		T55	1
auto[1207959552:1342177279]	105	1			T3	1		T51	1		T48	1
auto[1342177280:1476395007]	109	1			T42	1		T35	1		T104	1
auto[1476395008:1610612735]	93	1			T3	1		T4	1		T104	1
auto[1610612736:1744830463]	105	1			T4	1		T90	1		T210	1
auto[1744830464:1879048191]	103	1			T214	1		T45	1		T213	1
auto[1879048192:2013265919]	94	1			T17	1		T51	1		T52	2
auto[2013265920:2147483647]	118	1			T4	1		T18	1		T47	1
auto[2147483648:2281701375]	99	1			T19	1		T42	1		T43	1
auto[2281701376:2415919103]	95	1			T43	1		T44	1		T45	1
auto[2415919104:2550136831]	90	1			T15	1		T17	1		T201	1
auto[2550136832:2684354559]	107	1			T35	1		T55	1		T134	1
auto[2684354560:2818572287]	88	1			T139	2		T49	1		T69	1
auto[2818572288:2952790015]	100	1			T3	1		T4	2		T19	1
auto[2952790016:3087007743]	86	1			T17	1		T43	1		T55	2
auto[3087007744:3221225471]	94	1			T215	1		T45	1		T49	1
auto[3221225472:3355443199]	97	1			T45	1		T209	1		T69	1
auto[3355443200:3489660927]	104	1			T4	1		T15	1		T210	1
auto[3489660928:3623878655]	101	1			T42	1		T55	1		T48	2
auto[3623878656:3758096383]	99	1			T3	1		T35	1		T69	2
auto[3758096384:3892314111]	99	1			T18	1		T55	2		T139	1
auto[3892314112:4026531839]	82	1			T3	1		T4	1		T18	1
auto[4026531840:4160749567]	91	1			T19	1		T43	1		T215	1
auto[4160749568:4294967295]	75	1			T215	1		T44	1		T45	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	55	1			T210	1		T215	1		T213	1
auto[0:134217727]	auto[1]	58	1			T18	1		T210	1		T35	1
auto[134217728:268435455]	auto[0]	59	1			T49	1		T95	1		T7	1
auto[134217728:268435455]	auto[1]	52	1			T43	1		T134	1		T6	1
auto[268435456:402653183]	auto[0]	56	1			T19	2		T69	1		T199	1
auto[268435456:402653183]	auto[1]	59	1			T55	1		T213	1		T48	1
auto[402653184:536870911]	auto[0]	36	1			T90	1		T44	1		T6	1
auto[402653184:536870911]	auto[1]	43	1			T3	1		T85	1		T272	1
auto[536870912:671088639]	auto[0]	55	1			T215	1		T156	1		T6	3
auto[536870912:671088639]	auto[1]	55	1			T3	1		T104	1		T134	1
auto[671088640:805306367]	auto[0]	49	1			T214	1		T45	1		T7	1
auto[671088640:805306367]	auto[1]	63	1			T18	1		T90	1		T210	1
auto[805306368:939524095]	auto[0]	40	1			T56	1		T84	1		T72	1
auto[805306368:939524095]	auto[1]	56	1			T17	1		T43	1		T6	1
auto[939524096:1073741823]	auto[0]	45	1			T44	1		T56	1		T67	1
auto[939524096:1073741823]	auto[1]	58	1			T17	1		T18	1		T210	1
auto[1073741824:1207959551]	auto[0]	55	1			T18	1		T6	1		T46	1
auto[1073741824:1207959551]	auto[1]	56	1			T15	1		T55	1		T69	2
auto[1207959552:1342177279]	auto[0]	53	1			T3	1		T51	1		T48	1
auto[1207959552:1342177279]	auto[1]	52	1			T156	1		T157	1		T6	1
auto[1342177280:1476395007]	auto[0]	55	1			T56	2		T6	2		T8	1
auto[1342177280:1476395007]	auto[1]	54	1			T42	1		T35	1		T104	1
auto[1476395008:1610612735]	auto[0]	42	1			T4	1		T104	1		T52	1
auto[1476395008:1610612735]	auto[1]	51	1			T3	1		T209	1		T6	1
auto[1610612736:1744830463]	auto[0]	40	1			T51	1		T55	1		T6	1
auto[1610612736:1744830463]	auto[1]	65	1			T4	1		T90	1		T210	1
auto[1744830464:1879048191]	auto[0]	47	1			T214	1		T69	1		T6	1
auto[1744830464:1879048191]	auto[1]	56	1			T45	1		T213	1		T52	1
auto[1879048192:2013265919]	auto[0]	42	1			T51	1		T52	1		T56	1
auto[1879048192:2013265919]	auto[1]	52	1			T17	1		T52	1		T6	1
auto[2013265920:2147483647]	auto[0]	59	1			T49	1		T52	1		T95	1
auto[2013265920:2147483647]	auto[1]	59	1			T4	1		T18	1		T47	1
auto[2147483648:2281701375]	auto[0]	49	1			T19	1		T201	1		T56	2
auto[2147483648:2281701375]	auto[1]	50	1			T42	1		T43	1		T138	1
auto[2281701376:2415919103]	auto[0]	52	1			T48	1		T6	1		T88	1
auto[2281701376:2415919103]	auto[1]	43	1			T43	1		T44	1		T45	1
auto[2415919104:2550136831]	auto[0]	41	1			T17	1		T138	1		T69	1
auto[2415919104:2550136831]	auto[1]	49	1			T15	1		T201	1		T44	1
auto[2550136832:2684354559]	auto[0]	48	1			T35	1		T55	1		T134	1
auto[2550136832:2684354559]	auto[1]	59	1			T6	1		T59	1		T279	1
auto[2684354560:2818572287]	auto[0]	48	1			T139	1		T49	1		T56	1
auto[2684354560:2818572287]	auto[1]	40	1			T139	1		T69	1		T70	1
auto[2818572288:2952790015]	auto[0]	47	1			T4	2		T19	1		T42	1
auto[2818572288:2952790015]	auto[1]	53	1			T3	1		T121	1		T6	1
auto[2952790016:3087007743]	auto[0]	45	1			T17	1		T55	1		T7	1
auto[2952790016:3087007743]	auto[1]	41	1			T43	1		T55	1		T121	1
auto[3087007744:3221225471]	auto[0]	40	1			T215	1		T45	1		T53	1
auto[3087007744:3221225471]	auto[1]	54	1			T49	1		T209	1		T94	1
auto[3221225472:3355443199]	auto[0]	41	1			T45	1		T69	1		T56	1
auto[3221225472:3355443199]	auto[1]	56	1			T209	1		T53	1		T6	1
auto[3355443200:3489660927]	auto[0]	47	1			T52	1		T6	1		T283	1
auto[3355443200:3489660927]	auto[1]	57	1			T4	1		T15	1		T210	1
auto[3489660928:3623878655]	auto[0]	38	1			T48	2		T6	1		T46	1
auto[3489660928:3623878655]	auto[1]	63	1			T42	1		T55	1		T139	1
auto[3623878656:3758096383]	auto[0]	49	1			T3	1		T69	2		T6	2
auto[3623878656:3758096383]	auto[1]	50	1			T35	1		T6	1		T95	1
auto[3758096384:3892314111]	auto[0]	52	1			T55	1		T139	1		T6	1
auto[3758096384:3892314111]	auto[1]	47	1			T18	1		T55	1		T156	1
auto[3892314112:4026531839]	auto[0]	41	1			T3	1		T6	1		T46	1
auto[3892314112:4026531839]	auto[1]	41	1			T4	1		T18	1		T201	1
auto[4026531840:4160749567]	auto[0]	53	1			T19	1		T43	1		T215	1
auto[4026531840:4160749567]	auto[1]	38	1			T200	1		T95	1		T310	1
auto[4160749568:4294967295]	auto[0]	30	1			T44	1		T45	1		T138	1
auto[4160749568:4294967295]	auto[1]	45	1			T215	1		T218	1		T103	1