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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4264 1 T3 12 T4 10 T15 2
auto[1] 2102 1 T3 2 T4 4 T15 4



Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 220 1 T43 2 T201 2 T215 2
auto[134217728:268435455] 200 1 T210 2 T215 2 T44 2
auto[268435456:402653183] 216 1 T215 2 T52 2 T69 2
auto[402653184:536870911] 198 1 T3 2 T44 2 T55 2
auto[536870912:671088639] 216 1 T3 2 T18 2 T210 2
auto[671088640:805306367] 168 1 T90 2 T55 2 T199 2
auto[805306368:939524095] 210 1 T17 2 T19 2 T121 2
auto[939524096:1073741823] 178 1 T4 2 T18 2 T121 2
auto[1073741824:1207959551] 188 1 T42 2 T210 2 T45 2
auto[1207959552:1342177279] 182 1 T43 2 T47 2 T104 2
auto[1342177280:1476395007] 194 1 T18 2 T210 2 T55 2
auto[1476395008:1610612735] 208 1 T17 2 T42 2 T215 2
auto[1610612736:1744830463] 174 1 T35 2 T156 2 T95 2
auto[1744830464:1879048191] 246 1 T4 4 T15 2 T19 2
auto[1879048192:2013265919] 200 1 T3 2 T210 2 T209 2
auto[2013265920:2147483647] 192 1 T3 2 T17 2 T18 2
auto[2147483648:2281701375] 200 1 T4 2 T35 2 T213 2
auto[2281701376:2415919103] 208 1 T44 2 T55 2 T213 2
auto[2415919104:2550136831] 180 1 T51 2 T55 2 T48 2
auto[2550136832:2684354559] 196 1 T15 2 T18 2 T45 2
auto[2684354560:2818572287] 198 1 T15 2 T51 2 T49 2
auto[2818572288:2952790015] 198 1 T17 2 T139 2 T6 4
auto[2952790016:3087007743] 182 1 T17 2 T18 2 T42 2
auto[3087007744:3221225471] 196 1 T201 2 T55 2 T48 2
auto[3221225472:3355443199] 208 1 T3 2 T43 2 T210 2
auto[3355443200:3489660927] 216 1 T19 2 T43 2 T35 2
auto[3489660928:3623878655] 184 1 T43 2 T20 2 T7 2
auto[3623878656:3758096383] 214 1 T18 2 T42 2 T90 2
auto[3758096384:3892314111] 216 1 T45 2 T121 2 T52 2
auto[3892314112:4026531839] 190 1 T3 2 T19 2 T201 2
auto[4026531840:4160749567] 204 1 T4 2 T19 2 T35 2
auto[4160749568:4294967295] 186 1 T3 2 T4 4 T55 2



Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 156 1 T43 2 T201 2 T215 2
auto[0:134217727] auto[1] 64 1 T55 2 T139 2 T49 2
auto[134217728:268435455] auto[0] 136 1 T210 2 T215 2 T44 2
auto[134217728:268435455] auto[1] 64 1 T138 2 T52 2 T7 2
auto[268435456:402653183] auto[0] 134 1 T215 2 T69 2 T56 2
auto[268435456:402653183] auto[1] 82 1 T52 2 T84 2 T247 2
auto[402653184:536870911] auto[0] 150 1 T3 2 T44 2 T55 2
auto[402653184:536870911] auto[1] 48 1 T143 2 T416 2 T247 2
auto[536870912:671088639] auto[0] 146 1 T3 2 T55 2 T48 2
auto[536870912:671088639] auto[1] 70 1 T18 2 T210 2 T72 2
auto[671088640:805306367] auto[0] 114 1 T90 2 T55 2 T70 2
auto[671088640:805306367] auto[1] 54 1 T199 2 T46 2 T87 2
auto[805306368:939524095] auto[0] 130 1 T17 2 T19 2 T138 2
auto[805306368:939524095] auto[1] 80 1 T121 2 T218 2 T46 2
auto[939524096:1073741823] auto[0] 120 1 T4 2 T121 2 T7 2
auto[939524096:1073741823] auto[1] 58 1 T18 2 T6 2 T74 2
auto[1073741824:1207959551] auto[0] 118 1 T42 2 T210 2 T45 2
auto[1073741824:1207959551] auto[1] 70 1 T46 2 T247 2 T249 2
auto[1207959552:1342177279] auto[0] 120 1 T104 2 T55 2 T69 2
auto[1207959552:1342177279] auto[1] 62 1 T43 2 T47 2 T71 2
auto[1342177280:1476395007] auto[0] 130 1 T18 2 T210 2 T55 2
auto[1342177280:1476395007] auto[1] 64 1 T213 2 T6 2 T60 2
auto[1476395008:1610612735] auto[0] 142 1 T215 2 T55 2 T69 2
auto[1476395008:1610612735] auto[1] 66 1 T17 2 T42 2 T139 2
auto[1610612736:1744830463] auto[0] 128 1 T35 2 T156 2 T72 2
auto[1610612736:1744830463] auto[1] 46 1 T95 2 T46 2 T60 2
auto[1744830464:1879048191] auto[0] 166 1 T19 2 T90 2 T45 2
auto[1744830464:1879048191] auto[1] 80 1 T4 4 T15 2 T52 2
auto[1879048192:2013265919] auto[0] 144 1 T3 2 T210 2 T209 2
auto[1879048192:2013265919] auto[1] 56 1 T88 2 T72 2 T247 2
auto[2013265920:2147483647] auto[0] 132 1 T3 2 T17 2 T18 2
auto[2013265920:2147483647] auto[1] 60 1 T43 2 T104 2 T6 2
auto[2147483648:2281701375] auto[0] 136 1 T4 2 T35 2 T213 2
auto[2147483648:2281701375] auto[1] 64 1 T157 2 T7 2 T8 2
auto[2281701376:2415919103] auto[0] 136 1 T44 2 T213 2 T156 2
auto[2281701376:2415919103] auto[1] 72 1 T55 2 T139 2 T6 2
auto[2415919104:2550136831] auto[0] 118 1 T51 2 T55 2 T48 2
auto[2415919104:2550136831] auto[1] 62 1 T10 2 T71 2 T247 2
auto[2550136832:2684354559] auto[0] 128 1 T18 2 T138 2 T46 4
auto[2550136832:2684354559] auto[1] 68 1 T15 2 T45 2 T53 2
auto[2684354560:2818572287] auto[0] 130 1 T15 2 T49 2 T209 2
auto[2684354560:2818572287] auto[1] 68 1 T51 2 T95 2 T251 2
auto[2818572288:2952790015] auto[0] 118 1 T17 2 T6 4 T250 2
auto[2818572288:2952790015] auto[1] 80 1 T139 2 T7 2 T84 2
auto[2952790016:3087007743] auto[0] 138 1 T17 2 T18 2 T42 2
auto[2952790016:3087007743] auto[1] 44 1 T215 2 T53 2 T20 2
auto[3087007744:3221225471] auto[0] 132 1 T55 2 T56 2 T6 2
auto[3087007744:3221225471] auto[1] 64 1 T201 2 T48 2 T69 2
auto[3221225472:3355443199] auto[0] 130 1 T3 2 T43 2 T51 2
auto[3221225472:3355443199] auto[1] 78 1 T210 2 T139 2 T56 2
auto[3355443200:3489660927] auto[0] 146 1 T19 2 T43 2 T35 2
auto[3355443200:3489660927] auto[1] 70 1 T52 2 T53 2 T200 2
auto[3489660928:3623878655] auto[0] 114 1 T60 2 T414 2 T249 2
auto[3489660928:3623878655] auto[1] 70 1 T43 2 T20 2 T7 2
auto[3623878656:3758096383] auto[0] 140 1 T55 2 T94 2 T60 2
auto[3623878656:3758096383] auto[1] 74 1 T18 2 T42 2 T90 2
auto[3758096384:3892314111] auto[0] 142 1 T45 2 T121 2 T53 2
auto[3758096384:3892314111] auto[1] 74 1 T52 2 T68 2 T72 2
auto[3892314112:4026531839] auto[0] 112 1 T19 2 T55 2 T156 2
auto[3892314112:4026531839] auto[1] 78 1 T3 2 T201 2 T214 2
auto[4026531840:4160749567] auto[0] 138 1 T4 2 T19 2 T55 2
auto[4026531840:4160749567] auto[1] 66 1 T35 2 T60 2 T72 2
auto[4160749568:4294967295] auto[0] 140 1 T3 2 T4 4 T48 2
auto[4160749568:4294967295] auto[1] 46 1 T55 2 T248 2 T222 2

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