Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.80 99.04 97.99 98.94 100.00 99.02 98.41 91.19


Total test records in report: 1079
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T1004 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.438829158 Jul 19 04:31:04 PM PDT 24 Jul 19 04:31:25 PM PDT 24 89132486 ps
T164 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.3922011926 Jul 19 04:31:08 PM PDT 24 Jul 19 04:31:28 PM PDT 24 1184112308 ps
T1005 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3814725344 Jul 19 04:32:20 PM PDT 24 Jul 19 04:32:26 PM PDT 24 28718422 ps
T1006 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.862111726 Jul 19 04:31:24 PM PDT 24 Jul 19 04:31:44 PM PDT 24 96175037 ps
T1007 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.3554059629 Jul 19 04:31:20 PM PDT 24 Jul 19 04:31:38 PM PDT 24 133681653 ps
T1008 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.967549699 Jul 19 04:31:05 PM PDT 24 Jul 19 04:31:23 PM PDT 24 25523740 ps
T1009 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.4228662747 Jul 19 04:31:16 PM PDT 24 Jul 19 04:31:35 PM PDT 24 804897202 ps
T1010 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.4181190906 Jul 19 04:31:30 PM PDT 24 Jul 19 04:31:47 PM PDT 24 259359812 ps
T1011 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1967272599 Jul 19 04:31:06 PM PDT 24 Jul 19 04:31:31 PM PDT 24 2692983175 ps
T1012 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2047005181 Jul 19 04:31:18 PM PDT 24 Jul 19 04:31:38 PM PDT 24 225674759 ps
T1013 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3084540335 Jul 19 04:31:23 PM PDT 24 Jul 19 04:31:40 PM PDT 24 197004315 ps
T1014 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.219904600 Jul 19 04:31:18 PM PDT 24 Jul 19 04:31:35 PM PDT 24 46606545 ps
T1015 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.987428596 Jul 19 04:31:35 PM PDT 24 Jul 19 04:31:48 PM PDT 24 20426729 ps
T1016 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1087878501 Jul 19 04:31:25 PM PDT 24 Jul 19 04:31:43 PM PDT 24 103562643 ps
T1017 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.1690431861 Jul 19 04:31:10 PM PDT 24 Jul 19 04:31:33 PM PDT 24 263675191 ps
T1018 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2394023660 Jul 19 04:31:12 PM PDT 24 Jul 19 04:31:37 PM PDT 24 407616909 ps
T1019 /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2827369738 Jul 19 04:31:20 PM PDT 24 Jul 19 04:31:38 PM PDT 24 96717629 ps
T1020 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.340338116 Jul 19 04:31:18 PM PDT 24 Jul 19 04:31:44 PM PDT 24 784765333 ps
T1021 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.145799409 Jul 19 04:31:30 PM PDT 24 Jul 19 04:31:47 PM PDT 24 56978940 ps
T1022 /workspace/coverage/cover_reg_top/3.keymgr_intr_test.74339543 Jul 19 04:31:17 PM PDT 24 Jul 19 04:31:33 PM PDT 24 24216121 ps
T1023 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1160077317 Jul 19 04:31:25 PM PDT 24 Jul 19 04:31:44 PM PDT 24 335367901 ps
T1024 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2005135691 Jul 19 04:31:08 PM PDT 24 Jul 19 04:31:34 PM PDT 24 260312135 ps
T171 /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.748714615 Jul 19 04:31:13 PM PDT 24 Jul 19 04:31:34 PM PDT 24 412713256 ps
T1025 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2908634530 Jul 19 04:31:17 PM PDT 24 Jul 19 04:31:34 PM PDT 24 37143756 ps
T1026 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3335597117 Jul 19 04:31:00 PM PDT 24 Jul 19 04:31:31 PM PDT 24 260654878 ps
T1027 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2484233751 Jul 19 04:31:13 PM PDT 24 Jul 19 04:31:31 PM PDT 24 172420097 ps
T1028 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1666878575 Jul 19 04:31:26 PM PDT 24 Jul 19 04:31:43 PM PDT 24 139304980 ps
T1029 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1089565592 Jul 19 04:31:16 PM PDT 24 Jul 19 04:31:35 PM PDT 24 168758089 ps
T1030 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.693394190 Jul 19 04:31:04 PM PDT 24 Jul 19 04:31:35 PM PDT 24 1009099829 ps
T1031 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1172297454 Jul 19 04:31:27 PM PDT 24 Jul 19 04:31:45 PM PDT 24 258430599 ps
T1032 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3241387871 Jul 19 04:31:25 PM PDT 24 Jul 19 04:31:42 PM PDT 24 13006571 ps
T1033 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1597563327 Jul 19 04:32:32 PM PDT 24 Jul 19 04:32:40 PM PDT 24 17036564 ps
T1034 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.739224804 Jul 19 04:31:21 PM PDT 24 Jul 19 04:31:40 PM PDT 24 332003446 ps
T1035 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3932032188 Jul 19 04:31:34 PM PDT 24 Jul 19 04:31:49 PM PDT 24 190194196 ps
T1036 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.1810349254 Jul 19 04:31:38 PM PDT 24 Jul 19 04:31:50 PM PDT 24 9952631 ps
T1037 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2900932743 Jul 19 04:31:27 PM PDT 24 Jul 19 04:31:46 PM PDT 24 347884019 ps
T1038 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3039793623 Jul 19 04:31:26 PM PDT 24 Jul 19 04:31:43 PM PDT 24 10147250 ps
T1039 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.1108729338 Jul 19 04:31:05 PM PDT 24 Jul 19 04:31:22 PM PDT 24 25584990 ps
T1040 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.2796655629 Jul 19 04:31:15 PM PDT 24 Jul 19 04:31:34 PM PDT 24 199875113 ps
T1041 /workspace/coverage/cover_reg_top/4.keymgr_intr_test.2341487467 Jul 19 04:31:29 PM PDT 24 Jul 19 04:31:45 PM PDT 24 19641000 ps
T1042 /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.1427304880 Jul 19 04:31:22 PM PDT 24 Jul 19 04:31:39 PM PDT 24 291039860 ps
T1043 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.4227505511 Jul 19 04:31:11 PM PDT 24 Jul 19 04:31:30 PM PDT 24 194640977 ps
T1044 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.327173054 Jul 19 04:31:17 PM PDT 24 Jul 19 04:31:35 PM PDT 24 18389425 ps
T1045 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.4051009124 Jul 19 04:31:15 PM PDT 24 Jul 19 04:31:32 PM PDT 24 22325031 ps
T1046 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.612839915 Jul 19 04:31:36 PM PDT 24 Jul 19 04:31:50 PM PDT 24 112785876 ps
T1047 /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1632534724 Jul 19 04:31:08 PM PDT 24 Jul 19 04:31:27 PM PDT 24 196618429 ps
T1048 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.383165828 Jul 19 04:31:20 PM PDT 24 Jul 19 04:31:38 PM PDT 24 250553084 ps
T1049 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.4024289344 Jul 19 04:31:15 PM PDT 24 Jul 19 04:31:39 PM PDT 24 525360561 ps
T161 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.1136550989 Jul 19 04:31:15 PM PDT 24 Jul 19 04:31:37 PM PDT 24 779604800 ps
T1050 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.562669384 Jul 19 04:31:25 PM PDT 24 Jul 19 04:31:41 PM PDT 24 11171884 ps
T1051 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.51185082 Jul 19 04:31:06 PM PDT 24 Jul 19 04:31:26 PM PDT 24 453998797 ps
T1052 /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.43904713 Jul 19 04:31:25 PM PDT 24 Jul 19 04:31:43 PM PDT 24 97567632 ps
T1053 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.3265666565 Jul 19 04:31:32 PM PDT 24 Jul 19 04:31:47 PM PDT 24 80926606 ps
T1054 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.1964078684 Jul 19 04:32:20 PM PDT 24 Jul 19 04:32:31 PM PDT 24 871751818 ps
T1055 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.2580927734 Jul 19 04:31:11 PM PDT 24 Jul 19 04:31:31 PM PDT 24 181548572 ps
T1056 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.544439796 Jul 19 04:31:18 PM PDT 24 Jul 19 04:31:35 PM PDT 24 37317269 ps
T1057 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1879574162 Jul 19 04:31:30 PM PDT 24 Jul 19 04:31:54 PM PDT 24 458025199 ps
T1058 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.656010123 Jul 19 04:31:23 PM PDT 24 Jul 19 04:31:40 PM PDT 24 17972545 ps
T1059 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2345731525 Jul 19 04:31:19 PM PDT 24 Jul 19 04:31:39 PM PDT 24 555144508 ps
T1060 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.4225468118 Jul 19 04:31:26 PM PDT 24 Jul 19 04:31:43 PM PDT 24 38265721 ps
T1061 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.16823004 Jul 19 04:31:18 PM PDT 24 Jul 19 04:31:36 PM PDT 24 120160510 ps
T1062 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.4276097159 Jul 19 04:31:30 PM PDT 24 Jul 19 04:31:47 PM PDT 24 22387641 ps
T1063 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2563422625 Jul 19 04:31:18 PM PDT 24 Jul 19 04:31:36 PM PDT 24 50447424 ps
T1064 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.3388542533 Jul 19 04:31:15 PM PDT 24 Jul 19 04:31:41 PM PDT 24 820378178 ps
T1065 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3584973779 Jul 19 04:31:04 PM PDT 24 Jul 19 04:31:34 PM PDT 24 398142356 ps
T1066 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1951019642 Jul 19 04:31:05 PM PDT 24 Jul 19 04:31:28 PM PDT 24 866962647 ps
T1067 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.210964944 Jul 19 04:31:28 PM PDT 24 Jul 19 04:31:45 PM PDT 24 28781638 ps
T1068 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1233495320 Jul 19 04:31:27 PM PDT 24 Jul 19 04:31:45 PM PDT 24 12622632 ps
T1069 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2909426593 Jul 19 04:31:28 PM PDT 24 Jul 19 04:31:45 PM PDT 24 12471463 ps
T1070 /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1455267109 Jul 19 04:31:35 PM PDT 24 Jul 19 04:31:49 PM PDT 24 10161729 ps
T1071 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.1541591386 Jul 19 04:31:26 PM PDT 24 Jul 19 04:31:43 PM PDT 24 23883402 ps
T1072 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.27303192 Jul 19 04:31:08 PM PDT 24 Jul 19 04:31:28 PM PDT 24 175386353 ps
T1073 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.4001090481 Jul 19 04:31:02 PM PDT 24 Jul 19 04:31:21 PM PDT 24 70313931 ps
T1074 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.2946915277 Jul 19 04:31:18 PM PDT 24 Jul 19 04:31:39 PM PDT 24 133568481 ps
T1075 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.728898445 Jul 19 04:31:29 PM PDT 24 Jul 19 04:31:45 PM PDT 24 21381024 ps
T1076 /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.1363970730 Jul 19 04:31:21 PM PDT 24 Jul 19 04:31:40 PM PDT 24 81531204 ps
T1077 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2594765627 Jul 19 04:31:33 PM PDT 24 Jul 19 04:31:48 PM PDT 24 12997587 ps
T1078 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2138637885 Jul 19 04:31:26 PM PDT 24 Jul 19 04:31:45 PM PDT 24 38228264 ps
T1079 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2740727064 Jul 19 04:31:09 PM PDT 24 Jul 19 04:31:28 PM PDT 24 113724628 ps

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.108858612
Short name T4
Test name
Test status
Simulation time 508216201 ps
CPU time 15.94 seconds
Started Jul 19 05:30:14 PM PDT 24
Finished Jul 19 05:30:31 PM PDT 24
Peak memory 222324 kb
Host smart-23660870-f26e-471f-9f72-c4506f260c11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108858612 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.108858612
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.285595417
Short name T6
Test name
Test status
Simulation time 2545106746 ps
CPU time 33.15 seconds
Started Jul 19 05:34:36 PM PDT 24
Finished Jul 19 05:35:15 PM PDT 24
Peak memory 222276 kb
Host smart-214f2a6c-7e99-413f-bbe6-70b78220b44f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285595417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.285595417
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.525273466
Short name T60
Test name
Test status
Simulation time 974345513 ps
CPU time 21.08 seconds
Started Jul 19 05:32:12 PM PDT 24
Finished Jul 19 05:32:35 PM PDT 24
Peak memory 214964 kb
Host smart-5bd0f27c-79cc-4a84-aa61-c80c831cb493
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525273466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.525273466
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.289400003
Short name T12
Test name
Test status
Simulation time 269817448 ps
CPU time 5.47 seconds
Started Jul 19 05:28:23 PM PDT 24
Finished Jul 19 05:28:30 PM PDT 24
Peak memory 237204 kb
Host smart-745e29b7-fcf1-4464-8892-3bdd49f6966b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289400003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.289400003
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.4262707663
Short name T46
Test name
Test status
Simulation time 291684360 ps
CPU time 20.6 seconds
Started Jul 19 05:34:15 PM PDT 24
Finished Jul 19 05:34:38 PM PDT 24
Peak memory 222576 kb
Host smart-637ac71f-7bce-4203-b483-e2eee0494ec2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262707663 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.4262707663
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.441703931
Short name T72
Test name
Test status
Simulation time 1322183622 ps
CPU time 17.76 seconds
Started Jul 19 05:32:21 PM PDT 24
Finished Jul 19 05:32:40 PM PDT 24
Peak memory 216080 kb
Host smart-8048e4bc-1131-45d6-b6d9-e16d28852bc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441703931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.441703931
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.2313656745
Short name T156
Test name
Test status
Simulation time 352682534 ps
CPU time 9.06 seconds
Started Jul 19 05:31:19 PM PDT 24
Finished Jul 19 05:31:29 PM PDT 24
Peak memory 222300 kb
Host smart-6d9f77d3-451c-4749-84e6-f32b96fba7a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2313656745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.2313656745
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.1649902234
Short name T11
Test name
Test status
Simulation time 428768049 ps
CPU time 3.5 seconds
Started Jul 19 05:29:02 PM PDT 24
Finished Jul 19 05:29:06 PM PDT 24
Peak memory 222540 kb
Host smart-ee969863-7ae8-4da9-b673-081d4d291c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649902234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.1649902234
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.3468172891
Short name T17
Test name
Test status
Simulation time 2033789552 ps
CPU time 21.28 seconds
Started Jul 19 05:29:11 PM PDT 24
Finished Jul 19 05:29:33 PM PDT 24
Peak memory 208960 kb
Host smart-7eb72ee3-aa69-4155-bbe7-156d406a7ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468172891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.3468172891
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.1254717082
Short name T117
Test name
Test status
Simulation time 257694523 ps
CPU time 8.4 seconds
Started Jul 19 04:31:15 PM PDT 24
Finished Jul 19 04:31:39 PM PDT 24
Peak memory 214576 kb
Host smart-d5f74277-e44a-40dd-9565-9ddbd8332db2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254717082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.1254717082
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.4125065583
Short name T409
Test name
Test status
Simulation time 1318301553 ps
CPU time 65.32 seconds
Started Jul 19 05:34:02 PM PDT 24
Finished Jul 19 05:35:08 PM PDT 24
Peak memory 215220 kb
Host smart-bdea8142-42d6-49d9-a259-a40c6a254e0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4125065583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.4125065583
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.312400080
Short name T247
Test name
Test status
Simulation time 2827207843 ps
CPU time 68.39 seconds
Started Jul 19 05:33:34 PM PDT 24
Finished Jul 19 05:34:44 PM PDT 24
Peak memory 216152 kb
Host smart-64ef5935-644a-45c0-9a2f-9c5a778871dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312400080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.312400080
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.4062481172
Short name T5
Test name
Test status
Simulation time 120014772 ps
CPU time 1.79 seconds
Started Jul 19 05:31:37 PM PDT 24
Finished Jul 19 05:31:41 PM PDT 24
Peak memory 209628 kb
Host smart-6066ba43-5b64-452d-9712-77aaa41ace7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062481172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.4062481172
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1950418224
Short name T26
Test name
Test status
Simulation time 123848511 ps
CPU time 2.64 seconds
Started Jul 19 05:33:34 PM PDT 24
Finished Jul 19 05:33:39 PM PDT 24
Peak memory 214080 kb
Host smart-e1b7226a-7f7f-46ec-8500-1226e717cdd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950418224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1950418224
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.2835932582
Short name T55
Test name
Test status
Simulation time 25447430206 ps
CPU time 154.45 seconds
Started Jul 19 05:31:51 PM PDT 24
Finished Jul 19 05:34:27 PM PDT 24
Peak memory 222400 kb
Host smart-1e516546-7ff6-461d-9716-5c7792905820
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835932582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.2835932582
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.2692928238
Short name T353
Test name
Test status
Simulation time 859360177 ps
CPU time 13.38 seconds
Started Jul 19 05:31:20 PM PDT 24
Finished Jul 19 05:31:35 PM PDT 24
Peak memory 215392 kb
Host smart-5c889c4a-6eb7-4f77-aa1b-c2c767ab69fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2692928238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.2692928238
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.335180874
Short name T148
Test name
Test status
Simulation time 89266656 ps
CPU time 5.16 seconds
Started Jul 19 05:34:17 PM PDT 24
Finished Jul 19 05:34:26 PM PDT 24
Peak memory 222232 kb
Host smart-a4be36e8-4fbf-40be-a79d-da99160cc203
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=335180874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.335180874
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.2998706510
Short name T51
Test name
Test status
Simulation time 167132853 ps
CPU time 2.5 seconds
Started Jul 19 05:32:20 PM PDT 24
Finished Jul 19 05:32:23 PM PDT 24
Peak memory 214000 kb
Host smart-78741dd5-d971-45a8-ba37-6df28163906c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998706510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.2998706510
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.3483477970
Short name T181
Test name
Test status
Simulation time 48288658 ps
CPU time 2.93 seconds
Started Jul 19 05:32:18 PM PDT 24
Finished Jul 19 05:32:22 PM PDT 24
Peak memory 222436 kb
Host smart-e4daa1ce-b567-44eb-9271-1629c1154e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483477970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.3483477970
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.3139642465
Short name T145
Test name
Test status
Simulation time 268415093 ps
CPU time 13.46 seconds
Started Jul 19 05:32:20 PM PDT 24
Finished Jul 19 05:32:35 PM PDT 24
Peak memory 215560 kb
Host smart-62b2b4fd-924f-4243-afad-a35818b0fef9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3139642465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.3139642465
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.1386647765
Short name T122
Test name
Test status
Simulation time 1344131036 ps
CPU time 13.24 seconds
Started Jul 19 04:31:26 PM PDT 24
Finished Jul 19 04:31:55 PM PDT 24
Peak memory 214416 kb
Host smart-bcf6832d-2bc5-43bb-9f9e-222cf4b011e9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386647765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.1386647765
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.3683573805
Short name T7
Test name
Test status
Simulation time 8632647575 ps
CPU time 228.28 seconds
Started Jul 19 05:32:39 PM PDT 24
Finished Jul 19 05:36:30 PM PDT 24
Peak memory 217732 kb
Host smart-fa83af39-115b-41db-aca8-b2882c433fd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683573805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.3683573805
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.664810138
Short name T22
Test name
Test status
Simulation time 612380506 ps
CPU time 6.14 seconds
Started Jul 19 05:31:29 PM PDT 24
Finished Jul 19 05:31:37 PM PDT 24
Peak memory 214348 kb
Host smart-321b2357-09b4-4235-b438-aa46edb555a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664810138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.664810138
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.522971487
Short name T256
Test name
Test status
Simulation time 59113173 ps
CPU time 3.9 seconds
Started Jul 19 05:31:02 PM PDT 24
Finished Jul 19 05:31:08 PM PDT 24
Peak memory 214096 kb
Host smart-17318eeb-5dc1-4211-bd6b-e7eebd583459
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=522971487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.522971487
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.1269732335
Short name T30
Test name
Test status
Simulation time 1705796725 ps
CPU time 16.07 seconds
Started Jul 19 05:31:02 PM PDT 24
Finished Jul 19 05:31:19 PM PDT 24
Peak memory 209492 kb
Host smart-c9fe05a5-1949-43b2-b68c-e841c407c024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269732335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.1269732335
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.3835339482
Short name T37
Test name
Test status
Simulation time 419527715 ps
CPU time 3.9 seconds
Started Jul 19 05:34:07 PM PDT 24
Finished Jul 19 05:34:12 PM PDT 24
Peak memory 210192 kb
Host smart-524968e4-03b6-431b-9dec-9c23b3555d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835339482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3835339482
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.1727972734
Short name T426
Test name
Test status
Simulation time 1599006016 ps
CPU time 42.43 seconds
Started Jul 19 05:33:44 PM PDT 24
Finished Jul 19 05:34:28 PM PDT 24
Peak memory 222220 kb
Host smart-be3a6db7-ab33-4a78-8946-3c139db50163
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1727972734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.1727972734
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.639570092
Short name T237
Test name
Test status
Simulation time 2400553385 ps
CPU time 46.83 seconds
Started Jul 19 05:31:13 PM PDT 24
Finished Jul 19 05:32:01 PM PDT 24
Peak memory 222348 kb
Host smart-ce436774-7dc6-46cf-8f98-0cca473091ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639570092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.639570092
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.2750318101
Short name T102
Test name
Test status
Simulation time 384117581 ps
CPU time 4.6 seconds
Started Jul 19 05:29:28 PM PDT 24
Finished Jul 19 05:29:34 PM PDT 24
Peak memory 214076 kb
Host smart-556de157-b10c-4d61-8934-9b5e7d10a85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750318101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.2750318101
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.1539836543
Short name T75
Test name
Test status
Simulation time 8121104455 ps
CPU time 46.74 seconds
Started Jul 19 05:33:20 PM PDT 24
Finished Jul 19 05:34:08 PM PDT 24
Peak memory 222308 kb
Host smart-62f11c6d-9aca-460c-b041-35f4a77d14e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539836543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.1539836543
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.806587155
Short name T69
Test name
Test status
Simulation time 754019679 ps
CPU time 9.87 seconds
Started Jul 19 05:33:34 PM PDT 24
Finished Jul 19 05:33:46 PM PDT 24
Peak memory 215380 kb
Host smart-3d0f34fc-0fcc-4974-bb37-ae34fc2d3c40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806587155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.806587155
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.2394770397
Short name T344
Test name
Test status
Simulation time 114838544 ps
CPU time 6.64 seconds
Started Jul 19 05:34:22 PM PDT 24
Finished Jul 19 05:34:33 PM PDT 24
Peak memory 214896 kb
Host smart-b3bed84d-d4a6-461d-ac25-9e25c64218d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2394770397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.2394770397
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.2754143716
Short name T53
Test name
Test status
Simulation time 94678747 ps
CPU time 2.19 seconds
Started Jul 19 05:28:14 PM PDT 24
Finished Jul 19 05:28:18 PM PDT 24
Peak memory 214020 kb
Host smart-86446de0-09d4-4e21-a7da-0c54b68266aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754143716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.2754143716
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2313410487
Short name T118
Test name
Test status
Simulation time 2028678731 ps
CPU time 8.7 seconds
Started Jul 19 04:31:23 PM PDT 24
Finished Jul 19 04:31:49 PM PDT 24
Peak memory 214268 kb
Host smart-38c66674-7821-47d8-a827-1b5483abf162
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313410487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.2313410487
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.3423845335
Short name T109
Test name
Test status
Simulation time 68317629 ps
CPU time 0.77 seconds
Started Jul 19 05:30:33 PM PDT 24
Finished Jul 19 05:30:36 PM PDT 24
Peak memory 205836 kb
Host smart-9234ed3f-7586-4c4e-b27d-b65ea5e31ef1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423845335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.3423845335
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.4256122885
Short name T424
Test name
Test status
Simulation time 269548778 ps
CPU time 14 seconds
Started Jul 19 05:28:04 PM PDT 24
Finished Jul 19 05:28:21 PM PDT 24
Peak memory 215228 kb
Host smart-dc29a05d-43cb-42ba-ad3c-457ac9f12825
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4256122885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.4256122885
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.2456115586
Short name T93
Test name
Test status
Simulation time 393980018 ps
CPU time 3.17 seconds
Started Jul 19 05:29:01 PM PDT 24
Finished Jul 19 05:29:05 PM PDT 24
Peak memory 222228 kb
Host smart-321eb4f3-79a9-420d-89d5-aecfa185d410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456115586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.2456115586
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.2047258152
Short name T238
Test name
Test status
Simulation time 3173167381 ps
CPU time 44.41 seconds
Started Jul 19 05:27:54 PM PDT 24
Finished Jul 19 05:28:42 PM PDT 24
Peak memory 216560 kb
Host smart-045dfac1-2479-4eba-8a74-6b943319b5e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047258152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.2047258152
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.907866336
Short name T162
Test name
Test status
Simulation time 552003934 ps
CPU time 5.38 seconds
Started Jul 19 04:31:19 PM PDT 24
Finished Jul 19 04:31:41 PM PDT 24
Peak memory 215464 kb
Host smart-ac90d0f8-cbed-4b1e-98da-7cf9359853fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907866336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.
907866336
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2724583864
Short name T160
Test name
Test status
Simulation time 315162337 ps
CPU time 10.63 seconds
Started Jul 19 04:31:20 PM PDT 24
Finished Jul 19 04:31:47 PM PDT 24
Peak memory 216704 kb
Host smart-da0589dc-154d-494d-a1b4-4c9678ac7888
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724583864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.2724583864
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.4230854946
Short name T20
Test name
Test status
Simulation time 146775225 ps
CPU time 4.6 seconds
Started Jul 19 05:30:38 PM PDT 24
Finished Jul 19 05:30:45 PM PDT 24
Peak memory 222524 kb
Host smart-1a8ffd27-ced0-4de0-aa8f-3aa9cd8fdd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230854946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.4230854946
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.1733370423
Short name T262
Test name
Test status
Simulation time 951721591 ps
CPU time 14.11 seconds
Started Jul 19 05:27:55 PM PDT 24
Finished Jul 19 05:28:12 PM PDT 24
Peak memory 215340 kb
Host smart-1ab944bc-d4d8-4e99-8a5b-66b2c6686060
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1733370423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.1733370423
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_random.1373988498
Short name T210
Test name
Test status
Simulation time 1212948560 ps
CPU time 10.71 seconds
Started Jul 19 05:30:38 PM PDT 24
Finished Jul 19 05:30:50 PM PDT 24
Peak memory 209064 kb
Host smart-36ffcf82-a22d-4185-beb9-f4c7cb9fc126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373988498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.1373988498
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.1104831735
Short name T413
Test name
Test status
Simulation time 1858727909 ps
CPU time 12.54 seconds
Started Jul 19 05:30:39 PM PDT 24
Finished Jul 19 05:30:53 PM PDT 24
Peak memory 214056 kb
Host smart-d0cd0d54-efe6-4812-8b3f-ee6824d66b10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1104831735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.1104831735
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.1384851821
Short name T281
Test name
Test status
Simulation time 103194027 ps
CPU time 4.77 seconds
Started Jul 19 05:32:49 PM PDT 24
Finished Jul 19 05:32:55 PM PDT 24
Peak memory 214112 kb
Host smart-75e7d955-d845-409c-953a-f3e5c435e4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384851821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.1384851821
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.2288966755
Short name T360
Test name
Test status
Simulation time 131539660 ps
CPU time 2.49 seconds
Started Jul 19 05:33:41 PM PDT 24
Finished Jul 19 05:33:45 PM PDT 24
Peak memory 222124 kb
Host smart-23b462d2-ea2b-4dc3-806f-aa80ffbb0d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288966755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.2288966755
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.1077482828
Short name T187
Test name
Test status
Simulation time 75021467 ps
CPU time 3.08 seconds
Started Jul 19 05:29:38 PM PDT 24
Finished Jul 19 05:29:41 PM PDT 24
Peak memory 217712 kb
Host smart-fbdf521b-bf6b-4079-bec8-6a64cdf0161d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077482828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.1077482828
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.1933786075
Short name T179
Test name
Test status
Simulation time 534771227 ps
CPU time 5.28 seconds
Started Jul 19 05:31:10 PM PDT 24
Finished Jul 19 05:31:17 PM PDT 24
Peak memory 210180 kb
Host smart-1ce7ff68-739b-46da-a2aa-4892dfc1a500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933786075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.1933786075
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.3452007191
Short name T184
Test name
Test status
Simulation time 173970763 ps
CPU time 2.15 seconds
Started Jul 19 05:30:51 PM PDT 24
Finished Jul 19 05:30:54 PM PDT 24
Peak memory 222416 kb
Host smart-1de2dd0c-3a62-49cc-afa5-b5f4aaf4a1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452007191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.3452007191
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.1968721995
Short name T510
Test name
Test status
Simulation time 202705077 ps
CPU time 2.99 seconds
Started Jul 19 05:29:56 PM PDT 24
Finished Jul 19 05:30:01 PM PDT 24
Peak memory 208412 kb
Host smart-85959dc4-ad9c-4dec-a866-0b56be155d68
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968721995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.1968721995
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.2116167052
Short name T83
Test name
Test status
Simulation time 595823365 ps
CPU time 30.22 seconds
Started Jul 19 05:29:56 PM PDT 24
Finished Jul 19 05:30:28 PM PDT 24
Peak memory 216168 kb
Host smart-91f39cd4-459b-4c99-aac4-be96a87834fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116167052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.2116167052
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.2941791166
Short name T346
Test name
Test status
Simulation time 2228934423 ps
CPU time 54.2 seconds
Started Jul 19 05:30:44 PM PDT 24
Finished Jul 19 05:31:39 PM PDT 24
Peak memory 214840 kb
Host smart-0e8379ec-f434-4106-9f6f-ee03500cdb0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941791166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.2941791166
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.367106776
Short name T248
Test name
Test status
Simulation time 880874951 ps
CPU time 13.1 seconds
Started Jul 19 05:33:11 PM PDT 24
Finished Jul 19 05:33:26 PM PDT 24
Peak memory 216636 kb
Host smart-ccbb9b31-7caf-4ffc-ab43-09915d4283a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367106776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.367106776
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.734416518
Short name T197
Test name
Test status
Simulation time 10469306653 ps
CPU time 48.77 seconds
Started Jul 19 05:29:22 PM PDT 24
Finished Jul 19 05:30:12 PM PDT 24
Peak memory 222324 kb
Host smart-4e2ef6a7-b624-4662-9fe6-ea329a6b19b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734416518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.734416518
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.1377869407
Short name T186
Test name
Test status
Simulation time 72504474 ps
CPU time 2.51 seconds
Started Jul 19 05:33:06 PM PDT 24
Finished Jul 19 05:33:10 PM PDT 24
Peak memory 215152 kb
Host smart-1bb89637-2ab8-49e3-acca-2f9fb7b7ffee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377869407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1377869407
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.1061137777
Short name T158
Test name
Test status
Simulation time 120219774 ps
CPU time 4.47 seconds
Started Jul 19 04:32:36 PM PDT 24
Finished Jul 19 04:32:48 PM PDT 24
Peak memory 206404 kb
Host smart-8fb2ece4-bcd8-46c7-b900-a7fba93236f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061137777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.1061137777
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.2141807477
Short name T23
Test name
Test status
Simulation time 46260120 ps
CPU time 2.45 seconds
Started Jul 19 05:28:14 PM PDT 24
Finished Jul 19 05:28:18 PM PDT 24
Peak memory 214400 kb
Host smart-7cc66fcf-e146-4352-8c7c-7126b70d466b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141807477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.2141807477
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.3998270905
Short name T188
Test name
Test status
Simulation time 316285861 ps
CPU time 4.81 seconds
Started Jul 19 05:34:15 PM PDT 24
Finished Jul 19 05:34:23 PM PDT 24
Peak memory 222568 kb
Host smart-3d5c10c3-3fa6-4800-a8ed-8f14cf9e1a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998270905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.3998270905
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.586983322
Short name T243
Test name
Test status
Simulation time 921804642 ps
CPU time 7.26 seconds
Started Jul 19 05:27:23 PM PDT 24
Finished Jul 19 05:27:32 PM PDT 24
Peak memory 214040 kb
Host smart-89c8705c-e971-4017-92b8-fab2c517dbda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=586983322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.586983322
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.614337377
Short name T806
Test name
Test status
Simulation time 87879952 ps
CPU time 3.03 seconds
Started Jul 19 05:30:04 PM PDT 24
Finished Jul 19 05:30:08 PM PDT 24
Peak memory 214104 kb
Host smart-9215f32c-46cf-4d56-8a25-da44af45afca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614337377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.614337377
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.1103107110
Short name T364
Test name
Test status
Simulation time 59457494 ps
CPU time 4.21 seconds
Started Jul 19 05:30:52 PM PDT 24
Finished Jul 19 05:30:57 PM PDT 24
Peak memory 215248 kb
Host smart-08a5b4bf-8cfb-4c34-9106-6a0bf27284c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1103107110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.1103107110
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.4193868144
Short name T81
Test name
Test status
Simulation time 1203027514 ps
CPU time 18.48 seconds
Started Jul 19 05:31:03 PM PDT 24
Finished Jul 19 05:31:24 PM PDT 24
Peak memory 215328 kb
Host smart-9c1dec25-703f-4277-8f1e-cc67b80d5714
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193868144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.4193868144
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.872056918
Short name T284
Test name
Test status
Simulation time 299766764 ps
CPU time 4.16 seconds
Started Jul 19 05:31:47 PM PDT 24
Finished Jul 19 05:31:53 PM PDT 24
Peak memory 214072 kb
Host smart-f0fcbc55-2d54-477f-929c-4e095dc48ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872056918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.872056918
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.949889110
Short name T135
Test name
Test status
Simulation time 546437909 ps
CPU time 3.49 seconds
Started Jul 19 05:32:01 PM PDT 24
Finished Jul 19 05:32:06 PM PDT 24
Peak memory 206716 kb
Host smart-50e7fd6a-79d6-4ea8-be18-509998f55ce9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949889110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.949889110
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.870671508
Short name T337
Test name
Test status
Simulation time 42922847 ps
CPU time 2.74 seconds
Started Jul 19 05:33:04 PM PDT 24
Finished Jul 19 05:33:08 PM PDT 24
Peak memory 220488 kb
Host smart-41df7037-f771-45ea-8660-39815a693d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870671508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.870671508
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.564713965
Short name T67
Test name
Test status
Simulation time 637520777 ps
CPU time 21.83 seconds
Started Jul 19 05:33:19 PM PDT 24
Finished Jul 19 05:33:42 PM PDT 24
Peak memory 221056 kb
Host smart-c53a0c2b-7735-41a2-984a-b3ee2e2df641
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564713965 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.564713965
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.204034964
Short name T167
Test name
Test status
Simulation time 567329752 ps
CPU time 7.01 seconds
Started Jul 19 04:32:32 PM PDT 24
Finished Jul 19 04:32:46 PM PDT 24
Peak memory 216820 kb
Host smart-db58e495-221c-41eb-8972-5be24c3df6e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204034964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_err
.204034964
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3253154849
Short name T177
Test name
Test status
Simulation time 418750960 ps
CPU time 5.97 seconds
Started Jul 19 04:31:28 PM PDT 24
Finished Jul 19 04:31:50 PM PDT 24
Peak memory 214252 kb
Host smart-edd58b08-ed48-4383-8e50-d46ba0f871a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253154849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.3253154849
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.3663308272
Short name T383
Test name
Test status
Simulation time 92916234 ps
CPU time 4.23 seconds
Started Jul 19 05:27:55 PM PDT 24
Finished Jul 19 05:28:03 PM PDT 24
Peak memory 222404 kb
Host smart-56b2080a-ea3d-41c1-ad52-d672677905d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663308272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.3663308272
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.3175445678
Short name T185
Test name
Test status
Simulation time 110873727 ps
CPU time 4.9 seconds
Started Jul 19 05:32:33 PM PDT 24
Finished Jul 19 05:32:39 PM PDT 24
Peak memory 217728 kb
Host smart-759663cb-e7eb-485c-8af6-646158529420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175445678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3175445678
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.4008240574
Short name T182
Test name
Test status
Simulation time 186424678 ps
CPU time 2.96 seconds
Started Jul 19 05:34:22 PM PDT 24
Finished Jul 19 05:34:29 PM PDT 24
Peak memory 217336 kb
Host smart-b09f6c33-5798-4bbd-b20f-c549f0740cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008240574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.4008240574
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.126305793
Short name T258
Test name
Test status
Simulation time 135217102 ps
CPU time 4.18 seconds
Started Jul 19 05:27:47 PM PDT 24
Finished Jul 19 05:27:53 PM PDT 24
Peak memory 207760 kb
Host smart-fa103262-1e3e-40de-be94-868efc0aac83
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126305793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.126305793
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.1377201661
Short name T130
Test name
Test status
Simulation time 1027627310 ps
CPU time 21.77 seconds
Started Jul 19 05:31:02 PM PDT 24
Finished Jul 19 05:31:26 PM PDT 24
Peak memory 222272 kb
Host smart-df9e8cac-5358-46dc-8928-b3b0e29c30a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377201661 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.1377201661
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.1439194743
Short name T351
Test name
Test status
Simulation time 59361340 ps
CPU time 4.16 seconds
Started Jul 19 05:31:27 PM PDT 24
Finished Jul 19 05:31:32 PM PDT 24
Peak memory 215036 kb
Host smart-84ccdd0e-1f21-4d16-a828-e9b3a96ce56b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1439194743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.1439194743
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_random.1915784403
Short name T324
Test name
Test status
Simulation time 8129848296 ps
CPU time 48.48 seconds
Started Jul 19 05:31:37 PM PDT 24
Finished Jul 19 05:32:28 PM PDT 24
Peak memory 210404 kb
Host smart-822784b4-5277-426e-9af8-52b6ba1a59ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915784403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.1915784403
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.1460974289
Short name T227
Test name
Test status
Simulation time 8870585335 ps
CPU time 48.74 seconds
Started Jul 19 05:32:21 PM PDT 24
Finished Jul 19 05:33:11 PM PDT 24
Peak memory 214916 kb
Host smart-de198bd0-b4fc-43de-aea3-0f86010da33f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460974289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.1460974289
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.765263018
Short name T52
Test name
Test status
Simulation time 120196058 ps
CPU time 2.66 seconds
Started Jul 19 05:32:39 PM PDT 24
Finished Jul 19 05:32:44 PM PDT 24
Peak memory 214072 kb
Host smart-edab6b84-ecd5-4c6d-a109-565235af3e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765263018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.765263018
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.3086226833
Short name T314
Test name
Test status
Simulation time 5094777283 ps
CPU time 74.32 seconds
Started Jul 19 05:32:39 PM PDT 24
Finished Jul 19 05:33:56 PM PDT 24
Peak memory 215744 kb
Host smart-e4a05ecd-b263-4494-b666-1591eaa3ce44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3086226833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3086226833
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.1672061217
Short name T249
Test name
Test status
Simulation time 1384719697 ps
CPU time 15.06 seconds
Started Jul 19 05:34:30 PM PDT 24
Finished Jul 19 05:34:46 PM PDT 24
Peak memory 220492 kb
Host smart-de224085-b359-4a93-977d-ede3f0274825
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672061217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1672061217
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.3525725206
Short name T174
Test name
Test status
Simulation time 855733661 ps
CPU time 10.02 seconds
Started Jul 19 04:31:14 PM PDT 24
Finished Jul 19 04:31:40 PM PDT 24
Peak memory 206144 kb
Host smart-ae666756-b6ba-4a8a-baf6-8458d26c5de6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525725206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.3525725206
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1419872039
Short name T173
Test name
Test status
Simulation time 54964426 ps
CPU time 2.58 seconds
Started Jul 19 04:31:20 PM PDT 24
Finished Jul 19 04:31:39 PM PDT 24
Peak memory 214352 kb
Host smart-3d9383ab-f4b8-417f-b8ee-e25f429e87cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419872039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.1419872039
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.3953527421
Short name T13
Test name
Test status
Simulation time 269931452 ps
CPU time 8.42 seconds
Started Jul 19 05:27:30 PM PDT 24
Finished Jul 19 05:27:43 PM PDT 24
Peak memory 230324 kb
Host smart-616fdca0-959a-4d54-b559-bad8f91d11be
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953527421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.3953527421
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.1351161777
Short name T41
Test name
Test status
Simulation time 317137386 ps
CPU time 6.89 seconds
Started Jul 19 05:28:42 PM PDT 24
Finished Jul 19 05:28:50 PM PDT 24
Peak memory 237500 kb
Host smart-91d9e1d9-ab02-4431-83bb-1477e1c34919
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351161777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.1351161777
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.1306632476
Short name T175
Test name
Test status
Simulation time 143217565 ps
CPU time 2.05 seconds
Started Jul 19 05:33:19 PM PDT 24
Finished Jul 19 05:33:22 PM PDT 24
Peak memory 209824 kb
Host smart-1a21827d-3435-44e5-aad7-d5c6f3224039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306632476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.1306632476
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.3018092015
Short name T170
Test name
Test status
Simulation time 106699806 ps
CPU time 2.84 seconds
Started Jul 19 05:34:14 PM PDT 24
Finished Jul 19 05:34:20 PM PDT 24
Peak memory 210452 kb
Host smart-4e121635-20ff-4636-b8c1-8415205a361a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018092015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.3018092015
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.1941305810
Short name T183
Test name
Test status
Simulation time 218562156 ps
CPU time 3.24 seconds
Started Jul 19 05:30:33 PM PDT 24
Finished Jul 19 05:30:39 PM PDT 24
Peak memory 222360 kb
Host smart-03b7e037-0b11-46dc-9ee3-31e0e55b6275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941305810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.1941305810
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.3271738940
Short name T392
Test name
Test status
Simulation time 65461207 ps
CPU time 2.74 seconds
Started Jul 19 05:27:55 PM PDT 24
Finished Jul 19 05:28:02 PM PDT 24
Peak memory 209916 kb
Host smart-4f43d47b-d07f-4d77-9501-60c659b674a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271738940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.3271738940
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.194016641
Short name T370
Test name
Test status
Simulation time 1273582484 ps
CPU time 16.65 seconds
Started Jul 19 05:30:22 PM PDT 24
Finished Jul 19 05:30:39 PM PDT 24
Peak memory 215144 kb
Host smart-9985b4c6-c83c-4314-8d57-bc0f0f20e9bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194016641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.194016641
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.1459952166
Short name T239
Test name
Test status
Simulation time 2466896705 ps
CPU time 32.4 seconds
Started Jul 19 05:30:31 PM PDT 24
Finished Jul 19 05:31:05 PM PDT 24
Peak memory 216372 kb
Host smart-aa94f060-707e-4bd5-97e2-8da1f6f27f78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459952166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.1459952166
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.924869540
Short name T223
Test name
Test status
Simulation time 6627113527 ps
CPU time 20.49 seconds
Started Jul 19 05:30:33 PM PDT 24
Finished Jul 19 05:30:56 PM PDT 24
Peak memory 222392 kb
Host smart-f79ff45b-ab33-478b-ac8b-437d715e9112
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924869540 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.924869540
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.1715598627
Short name T79
Test name
Test status
Simulation time 804602729 ps
CPU time 34.59 seconds
Started Jul 19 05:30:36 PM PDT 24
Finished Jul 19 05:31:11 PM PDT 24
Peak memory 220672 kb
Host smart-7715014c-c1d8-4691-ae41-0f2cf25d0bca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715598627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.1715598627
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.1966876598
Short name T235
Test name
Test status
Simulation time 2885977603 ps
CPU time 17.62 seconds
Started Jul 19 05:30:46 PM PDT 24
Finished Jul 19 05:31:04 PM PDT 24
Peak memory 222416 kb
Host smart-d366b2c1-42b8-46b4-9aa2-4dc12fbfe4cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966876598 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.1966876598
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.2240204651
Short name T319
Test name
Test status
Simulation time 928437868 ps
CPU time 3.55 seconds
Started Jul 19 05:31:07 PM PDT 24
Finished Jul 19 05:31:13 PM PDT 24
Peak memory 220384 kb
Host smart-0fcac44c-5c00-4bd3-8547-ac7f36266ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240204651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2240204651
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.423242128
Short name T231
Test name
Test status
Simulation time 102097421 ps
CPU time 3.11 seconds
Started Jul 19 05:31:10 PM PDT 24
Finished Jul 19 05:31:14 PM PDT 24
Peak memory 217784 kb
Host smart-b51ba426-3b9b-4309-926d-50f802cc4e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423242128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.423242128
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_sideload.1130095364
Short name T207
Test name
Test status
Simulation time 57636828 ps
CPU time 3.13 seconds
Started Jul 19 05:31:01 PM PDT 24
Finished Jul 19 05:31:05 PM PDT 24
Peak memory 208220 kb
Host smart-57412cf0-51df-47fa-b3da-003aabf6d3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130095364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.1130095364
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.245858386
Short name T391
Test name
Test status
Simulation time 669601771 ps
CPU time 7.12 seconds
Started Jul 19 05:31:29 PM PDT 24
Finished Jul 19 05:31:38 PM PDT 24
Peak memory 209308 kb
Host smart-e5eb6887-f5c4-4b56-80c7-f43a492aa3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245858386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.245858386
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.2485008122
Short name T579
Test name
Test status
Simulation time 93681620 ps
CPU time 4.23 seconds
Started Jul 19 05:31:38 PM PDT 24
Finished Jul 19 05:31:44 PM PDT 24
Peak memory 214088 kb
Host smart-0bb5b541-31bf-41c4-b687-e325cf0a52d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485008122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2485008122
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.3217102148
Short name T245
Test name
Test status
Simulation time 279462516 ps
CPU time 7.23 seconds
Started Jul 19 05:31:46 PM PDT 24
Finished Jul 19 05:31:54 PM PDT 24
Peak memory 214064 kb
Host smart-e44ae7fe-08d0-46a2-afc6-30d9b4d65b36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3217102148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.3217102148
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.1988292838
Short name T338
Test name
Test status
Simulation time 254425939 ps
CPU time 5.53 seconds
Started Jul 19 05:31:58 PM PDT 24
Finished Jul 19 05:32:05 PM PDT 24
Peak memory 222148 kb
Host smart-de957aa3-e3ab-4026-9239-acb0fd1b7446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988292838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.1988292838
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.1341985237
Short name T101
Test name
Test status
Simulation time 205484591 ps
CPU time 2.94 seconds
Started Jul 19 05:33:11 PM PDT 24
Finished Jul 19 05:33:15 PM PDT 24
Peak memory 208792 kb
Host smart-6745c7fc-0190-42a2-9432-4808d8987838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341985237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.1341985237
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_random.3061928892
Short name T369
Test name
Test status
Simulation time 34642874 ps
CPU time 2.51 seconds
Started Jul 19 05:33:20 PM PDT 24
Finished Jul 19 05:33:24 PM PDT 24
Peak memory 208160 kb
Host smart-e60fa927-0b66-4283-88e4-21995cfb0b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061928892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.3061928892
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.3216343838
Short name T100
Test name
Test status
Simulation time 105187815 ps
CPU time 2.21 seconds
Started Jul 19 05:34:09 PM PDT 24
Finished Jul 19 05:34:13 PM PDT 24
Peak memory 209320 kb
Host smart-8a46a215-2364-4432-a123-2c5da37491c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216343838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.3216343838
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.1999765420
Short name T382
Test name
Test status
Simulation time 471338966 ps
CPU time 4.83 seconds
Started Jul 19 05:29:49 PM PDT 24
Finished Jul 19 05:29:54 PM PDT 24
Peak memory 214084 kb
Host smart-572d00b7-972e-4117-a755-7fe012c294e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1999765420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.1999765420
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.4130232419
Short name T157
Test name
Test status
Simulation time 210857110 ps
CPU time 2.71 seconds
Started Jul 19 05:31:28 PM PDT 24
Finished Jul 19 05:31:31 PM PDT 24
Peak memory 217632 kb
Host smart-c9f7ead4-eaf8-4499-bf14-04ea0700e39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130232419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.4130232419
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1951019642
Short name T1066
Test name
Test status
Simulation time 866962647 ps
CPU time 5.14 seconds
Started Jul 19 04:31:05 PM PDT 24
Finished Jul 19 04:31:28 PM PDT 24
Peak memory 206060 kb
Host smart-2cbaf985-011b-431e-b65f-5d8a26fbea4e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951019642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1
951019642
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1097817517
Short name T938
Test name
Test status
Simulation time 455815229 ps
CPU time 7.56 seconds
Started Jul 19 04:31:04 PM PDT 24
Finished Jul 19 04:31:28 PM PDT 24
Peak memory 205992 kb
Host smart-6b679359-d68e-473d-91f0-18599b85be8e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097817517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.1
097817517
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3906662698
Short name T950
Test name
Test status
Simulation time 94891666 ps
CPU time 0.89 seconds
Started Jul 19 04:31:14 PM PDT 24
Finished Jul 19 04:31:31 PM PDT 24
Peak memory 205940 kb
Host smart-1f967beb-eedc-42e0-85ba-596554c9c534
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906662698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.3
906662698
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3091169726
Short name T166
Test name
Test status
Simulation time 235887970 ps
CPU time 1.64 seconds
Started Jul 19 04:31:19 PM PDT 24
Finished Jul 19 04:31:37 PM PDT 24
Peak memory 214308 kb
Host smart-843f3d5d-dadd-45e1-a48e-84e135b1b9ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091169726 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.3091169726
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.4225468118
Short name T1060
Test name
Test status
Simulation time 38265721 ps
CPU time 0.98 seconds
Started Jul 19 04:31:26 PM PDT 24
Finished Jul 19 04:31:43 PM PDT 24
Peak memory 206028 kb
Host smart-5f320e1a-08d7-4c09-9a4b-62d5f424d036
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225468118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.4225468118
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.1108729338
Short name T1039
Test name
Test status
Simulation time 25584990 ps
CPU time 0.81 seconds
Started Jul 19 04:31:05 PM PDT 24
Finished Jul 19 04:31:22 PM PDT 24
Peak memory 205868 kb
Host smart-cdbb68d2-e963-4626-a1eb-286a69dd90b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108729338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.1108729338
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.2580927734
Short name T1055
Test name
Test status
Simulation time 181548572 ps
CPU time 3.38 seconds
Started Jul 19 04:31:11 PM PDT 24
Finished Jul 19 04:31:31 PM PDT 24
Peak memory 206008 kb
Host smart-a0faecdc-4f97-495a-8cd7-2208ab31d951
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580927734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.2580927734
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1230458243
Short name T1003
Test name
Test status
Simulation time 140047257 ps
CPU time 4.19 seconds
Started Jul 19 04:31:05 PM PDT 24
Finished Jul 19 04:31:26 PM PDT 24
Peak memory 214424 kb
Host smart-7432cc82-3027-41e2-9583-f7d7e4cd6c62
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230458243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.1230458243
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1295905834
Short name T991
Test name
Test status
Simulation time 1572899907 ps
CPU time 5.52 seconds
Started Jul 19 04:31:10 PM PDT 24
Finished Jul 19 04:31:32 PM PDT 24
Peak memory 214560 kb
Host smart-7ff6fe1b-3cac-42d3-aa4d-e81bdaf7471b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295905834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.1295905834
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1830041429
Short name T974
Test name
Test status
Simulation time 215257277 ps
CPU time 3.81 seconds
Started Jul 19 04:31:05 PM PDT 24
Finished Jul 19 04:31:25 PM PDT 24
Peak memory 214180 kb
Host smart-4b4e886b-4c72-4f81-8198-ca4a901f8b95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830041429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1830041429
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.1908078345
Short name T178
Test name
Test status
Simulation time 126254150 ps
CPU time 4.06 seconds
Started Jul 19 04:31:18 PM PDT 24
Finished Jul 19 04:31:39 PM PDT 24
Peak memory 214232 kb
Host smart-a5f6a302-f914-458c-b286-d6669a89a82b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908078345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.1908078345
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3584973779
Short name T1065
Test name
Test status
Simulation time 398142356 ps
CPU time 12.94 seconds
Started Jul 19 04:31:04 PM PDT 24
Finished Jul 19 04:31:34 PM PDT 24
Peak memory 206104 kb
Host smart-0f9cdf49-5895-4e9d-b05e-c1d4bf6338f3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584973779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.3
584973779
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3335597117
Short name T1026
Test name
Test status
Simulation time 260654878 ps
CPU time 14.23 seconds
Started Jul 19 04:31:00 PM PDT 24
Finished Jul 19 04:31:31 PM PDT 24
Peak memory 206256 kb
Host smart-231a3f67-7157-44f8-a001-59833dbc7a79
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335597117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.3
335597117
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.982192789
Short name T981
Test name
Test status
Simulation time 37057150 ps
CPU time 0.9 seconds
Started Jul 19 04:31:07 PM PDT 24
Finished Jul 19 04:31:24 PM PDT 24
Peak memory 205916 kb
Host smart-d7a3c77a-c79d-465f-8c03-d78cd5768bde
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982192789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.982192789
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.274824339
Short name T993
Test name
Test status
Simulation time 140017814 ps
CPU time 1.4 seconds
Started Jul 19 04:31:03 PM PDT 24
Finished Jul 19 04:31:21 PM PDT 24
Peak memory 214348 kb
Host smart-62ea68ae-2cfd-4f1f-b5f2-bbb2b7361e39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274824339 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.274824339
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.967549699
Short name T1008
Test name
Test status
Simulation time 25523740 ps
CPU time 1.11 seconds
Started Jul 19 04:31:05 PM PDT 24
Finished Jul 19 04:31:23 PM PDT 24
Peak memory 206044 kb
Host smart-5ada4148-2443-4e74-9e23-c19954604d53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967549699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.967549699
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.185213136
Short name T918
Test name
Test status
Simulation time 9130392 ps
CPU time 0.89 seconds
Started Jul 19 04:31:00 PM PDT 24
Finished Jul 19 04:31:18 PM PDT 24
Peak memory 205840 kb
Host smart-5d857b57-3099-4c09-8db9-88d5e94c1f18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185213136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.185213136
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.438829158
Short name T1004
Test name
Test status
Simulation time 89132486 ps
CPU time 3.4 seconds
Started Jul 19 04:31:04 PM PDT 24
Finished Jul 19 04:31:25 PM PDT 24
Peak memory 205980 kb
Host smart-9aa59176-65f3-40c5-8756-f97d73aadef2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438829158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sam
e_csr_outstanding.438829158
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2488132879
Short name T970
Test name
Test status
Simulation time 81403277 ps
CPU time 1.62 seconds
Started Jul 19 04:31:02 PM PDT 24
Finished Jul 19 04:31:20 PM PDT 24
Peak memory 214504 kb
Host smart-46c0d2d3-bd73-4706-8682-f4ade83634fb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488132879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.2488132879
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.735861243
Short name T992
Test name
Test status
Simulation time 84589204 ps
CPU time 4.36 seconds
Started Jul 19 04:31:12 PM PDT 24
Finished Jul 19 04:31:32 PM PDT 24
Peak memory 214404 kb
Host smart-276f6c43-5212-4120-8b1c-4d71e4ff9e3f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735861243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_shadow_reg_errors_with_csr_rw.735861243
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1426124962
Short name T910
Test name
Test status
Simulation time 76105255 ps
CPU time 2.8 seconds
Started Jul 19 04:31:06 PM PDT 24
Finished Jul 19 04:31:26 PM PDT 24
Peak memory 214292 kb
Host smart-f5607a08-bf97-496f-92e1-78ea68e8de03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426124962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1426124962
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.14221443
Short name T986
Test name
Test status
Simulation time 120703662 ps
CPU time 3.54 seconds
Started Jul 19 04:31:00 PM PDT 24
Finished Jul 19 04:31:21 PM PDT 24
Peak memory 214372 kb
Host smart-ef7210b8-b1d6-494e-8d9e-780eff451b6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14221443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.14221443
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2563422625
Short name T1063
Test name
Test status
Simulation time 50447424 ps
CPU time 1.89 seconds
Started Jul 19 04:31:18 PM PDT 24
Finished Jul 19 04:31:36 PM PDT 24
Peak memory 222480 kb
Host smart-681ee6a5-8360-4170-9e04-10b496e76b71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563422625 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.2563422625
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.4276097159
Short name T1062
Test name
Test status
Simulation time 22387641 ps
CPU time 1.11 seconds
Started Jul 19 04:31:30 PM PDT 24
Finished Jul 19 04:31:47 PM PDT 24
Peak memory 205832 kb
Host smart-6be8febb-ea48-4e76-87ec-5264f354f71a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276097159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.4276097159
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2947591608
Short name T996
Test name
Test status
Simulation time 14783158 ps
CPU time 0.76 seconds
Started Jul 19 04:31:30 PM PDT 24
Finished Jul 19 04:31:47 PM PDT 24
Peak memory 205772 kb
Host smart-bf5e927b-40b1-4dff-b9e4-e8f53171ba76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947591608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.2947591608
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.3174320104
Short name T939
Test name
Test status
Simulation time 188826782 ps
CPU time 3.4 seconds
Started Jul 19 04:31:25 PM PDT 24
Finished Jul 19 04:31:44 PM PDT 24
Peak memory 206068 kb
Host smart-f089c958-3d9f-491c-beff-1f3dc22d2541
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174320104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.3174320104
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.2796655629
Short name T1040
Test name
Test status
Simulation time 199875113 ps
CPU time 3.11 seconds
Started Jul 19 04:31:15 PM PDT 24
Finished Jul 19 04:31:34 PM PDT 24
Peak memory 214500 kb
Host smart-cdb91414-c9af-41fd-83b5-bd094a613c5c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796655629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.2796655629
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1879574162
Short name T1057
Test name
Test status
Simulation time 458025199 ps
CPU time 8.45 seconds
Started Jul 19 04:31:30 PM PDT 24
Finished Jul 19 04:31:54 PM PDT 24
Peak memory 214392 kb
Host smart-b925ec13-6035-4230-8d87-30a9e2983f8a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879574162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.1879574162
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2383105403
Short name T914
Test name
Test status
Simulation time 175962372 ps
CPU time 2.95 seconds
Started Jul 19 04:31:24 PM PDT 24
Finished Jul 19 04:31:43 PM PDT 24
Peak memory 214172 kb
Host smart-1bfdb20e-fe81-43f8-8892-ad795817fe32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383105403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2383105403
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.1136550989
Short name T161
Test name
Test status
Simulation time 779604800 ps
CPU time 6.1 seconds
Started Jul 19 04:31:15 PM PDT 24
Finished Jul 19 04:31:37 PM PDT 24
Peak memory 214204 kb
Host smart-f03c2032-d954-4ca6-bbc6-254e8dfd93e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136550989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.1136550989
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.4171259598
Short name T943
Test name
Test status
Simulation time 97116215 ps
CPU time 1.48 seconds
Started Jul 19 04:32:36 PM PDT 24
Finished Jul 19 04:32:45 PM PDT 24
Peak memory 214208 kb
Host smart-3a0bf8c7-d5a4-422c-8de7-09e38eae4a7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171259598 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.4171259598
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2175793722
Short name T967
Test name
Test status
Simulation time 45958877 ps
CPU time 1.08 seconds
Started Jul 19 04:31:17 PM PDT 24
Finished Jul 19 04:31:34 PM PDT 24
Peak memory 206044 kb
Host smart-e08ef2c0-8799-4d85-b690-7157d8ac14dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175793722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.2175793722
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.4051009124
Short name T1045
Test name
Test status
Simulation time 22325031 ps
CPU time 0.73 seconds
Started Jul 19 04:31:15 PM PDT 24
Finished Jul 19 04:31:32 PM PDT 24
Peak memory 205864 kb
Host smart-9139f86a-b7a6-4451-a425-02ffea234f56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051009124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.4051009124
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.4132392136
Short name T973
Test name
Test status
Simulation time 335441234 ps
CPU time 3.28 seconds
Started Jul 19 04:31:30 PM PDT 24
Finished Jul 19 04:31:49 PM PDT 24
Peak memory 205844 kb
Host smart-737286e2-f94b-44bf-81d8-101a48f41761
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132392136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.4132392136
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.746319222
Short name T120
Test name
Test status
Simulation time 73567811 ps
CPU time 1.6 seconds
Started Jul 19 04:31:26 PM PDT 24
Finished Jul 19 04:31:43 PM PDT 24
Peak memory 214536 kb
Host smart-b36d7a0d-62ce-4274-a4c6-5da5966a57a3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746319222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shado
w_reg_errors.746319222
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2394023660
Short name T1018
Test name
Test status
Simulation time 407616909 ps
CPU time 9.51 seconds
Started Jul 19 04:31:12 PM PDT 24
Finished Jul 19 04:31:37 PM PDT 24
Peak memory 214544 kb
Host smart-f546c151-556b-4339-8ccd-7620cc04092d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394023660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.2394023660
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1089565592
Short name T1029
Test name
Test status
Simulation time 168758089 ps
CPU time 2.96 seconds
Started Jul 19 04:31:16 PM PDT 24
Finished Jul 19 04:31:35 PM PDT 24
Peak memory 214232 kb
Host smart-0032404c-e46c-4e8a-b3cd-00f7f54b840f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089565592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1089565592
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.3922011926
Short name T164
Test name
Test status
Simulation time 1184112308 ps
CPU time 3.43 seconds
Started Jul 19 04:31:08 PM PDT 24
Finished Jul 19 04:31:28 PM PDT 24
Peak memory 215516 kb
Host smart-4ffbf848-1965-4c31-82b3-7397f151c0b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922011926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.3922011926
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1562758667
Short name T935
Test name
Test status
Simulation time 27880591 ps
CPU time 1.39 seconds
Started Jul 19 04:31:30 PM PDT 24
Finished Jul 19 04:31:47 PM PDT 24
Peak memory 214308 kb
Host smart-0ce49ffa-6181-4844-9584-61baf85a7edc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562758667 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.1562758667
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1089394310
Short name T1000
Test name
Test status
Simulation time 38089369 ps
CPU time 0.96 seconds
Started Jul 19 04:32:36 PM PDT 24
Finished Jul 19 04:32:44 PM PDT 24
Peak memory 206000 kb
Host smart-da9b7750-ca8c-4e8e-a32b-db5cb45e3bf6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089394310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1089394310
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1660881217
Short name T987
Test name
Test status
Simulation time 15612376 ps
CPU time 0.8 seconds
Started Jul 19 04:31:12 PM PDT 24
Finished Jul 19 04:31:28 PM PDT 24
Peak memory 205748 kb
Host smart-47d29c83-2547-4e2a-b064-0b4072707aea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660881217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.1660881217
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.101350000
Short name T152
Test name
Test status
Simulation time 565758082 ps
CPU time 2.46 seconds
Started Jul 19 04:31:20 PM PDT 24
Finished Jul 19 04:31:39 PM PDT 24
Peak memory 206084 kb
Host smart-4420218e-a3c3-408b-b20e-b9ab4c095725
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101350000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_sa
me_csr_outstanding.101350000
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1865993767
Short name T127
Test name
Test status
Simulation time 83236290 ps
CPU time 1.99 seconds
Started Jul 19 04:31:19 PM PDT 24
Finished Jul 19 04:31:38 PM PDT 24
Peak memory 218568 kb
Host smart-af683e06-25e2-4f2c-94a8-10b0dcdaf313
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865993767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.1865993767
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.3388542533
Short name T1064
Test name
Test status
Simulation time 820378178 ps
CPU time 9.9 seconds
Started Jul 19 04:31:15 PM PDT 24
Finished Jul 19 04:31:41 PM PDT 24
Peak memory 214460 kb
Host smart-1b748ef7-19af-4c52-8cd0-4e9afc00461f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388542533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.3388542533
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.950293351
Short name T937
Test name
Test status
Simulation time 62399756 ps
CPU time 2.22 seconds
Started Jul 19 04:31:30 PM PDT 24
Finished Jul 19 04:31:48 PM PDT 24
Peak memory 214244 kb
Host smart-ce3014f4-8f51-4753-89e2-4276c6ed10e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950293351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.950293351
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.3232289248
Short name T975
Test name
Test status
Simulation time 131858309 ps
CPU time 2.35 seconds
Started Jul 19 04:32:34 PM PDT 24
Finished Jul 19 04:32:44 PM PDT 24
Peak memory 214256 kb
Host smart-1a45f176-ba49-4ded-8f39-3947634310c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232289248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.3232289248
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.4181190906
Short name T1010
Test name
Test status
Simulation time 259359812 ps
CPU time 1.59 seconds
Started Jul 19 04:31:30 PM PDT 24
Finished Jul 19 04:31:47 PM PDT 24
Peak memory 214312 kb
Host smart-308bdd49-94f3-44c6-975a-323e27a7b0b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181190906 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.4181190906
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1008666181
Short name T940
Test name
Test status
Simulation time 278900977 ps
CPU time 1.07 seconds
Started Jul 19 04:31:30 PM PDT 24
Finished Jul 19 04:31:47 PM PDT 24
Peak memory 205968 kb
Host smart-f4767be0-49ad-4579-9744-450592a1cacc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008666181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.1008666181
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3307414900
Short name T936
Test name
Test status
Simulation time 11137835 ps
CPU time 0.83 seconds
Started Jul 19 04:31:08 PM PDT 24
Finished Jul 19 04:31:25 PM PDT 24
Peak memory 206124 kb
Host smart-a87421f8-18f1-47d9-a9c3-96abfba188a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307414900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3307414900
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1870986614
Short name T949
Test name
Test status
Simulation time 37579994 ps
CPU time 2.03 seconds
Started Jul 19 04:31:16 PM PDT 24
Finished Jul 19 04:31:33 PM PDT 24
Peak memory 206108 kb
Host smart-a477b91d-cdf3-47a3-bfa1-25b77c15cb16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870986614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.1870986614
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.4223583633
Short name T126
Test name
Test status
Simulation time 76584301 ps
CPU time 1.83 seconds
Started Jul 19 04:32:36 PM PDT 24
Finished Jul 19 04:32:45 PM PDT 24
Peak memory 214372 kb
Host smart-fbeacbde-4d9f-4f25-89b2-eb8e97db4f6f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223583633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.4223583633
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3289513730
Short name T984
Test name
Test status
Simulation time 413242953 ps
CPU time 14.6 seconds
Started Jul 19 04:31:06 PM PDT 24
Finished Jul 19 04:31:38 PM PDT 24
Peak memory 214476 kb
Host smart-f7690a4f-a8df-481d-a58f-ac728be84bc9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289513730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3289513730
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.919045194
Short name T920
Test name
Test status
Simulation time 890729209 ps
CPU time 3.98 seconds
Started Jul 19 04:31:18 PM PDT 24
Finished Jul 19 04:31:38 PM PDT 24
Peak memory 214272 kb
Host smart-555156fd-622c-4f18-a035-44122fdb25de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919045194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.919045194
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1333342218
Short name T941
Test name
Test status
Simulation time 24244741 ps
CPU time 1.58 seconds
Started Jul 19 04:31:16 PM PDT 24
Finished Jul 19 04:31:33 PM PDT 24
Peak memory 214392 kb
Host smart-288dedd7-d7da-4999-a332-cb3218b6b50d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333342218 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.1333342218
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.210964944
Short name T1067
Test name
Test status
Simulation time 28781638 ps
CPU time 1.48 seconds
Started Jul 19 04:31:28 PM PDT 24
Finished Jul 19 04:31:45 PM PDT 24
Peak memory 206116 kb
Host smart-9056ec9e-99ac-49b7-a5b0-6e4720558604
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210964944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.210964944
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.183696804
Short name T911
Test name
Test status
Simulation time 14670433 ps
CPU time 0.94 seconds
Started Jul 19 04:31:25 PM PDT 24
Finished Jul 19 04:31:43 PM PDT 24
Peak memory 206216 kb
Host smart-a34d61c0-4b53-42c7-abfb-b4ce2f42d0e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183696804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.183696804
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.612839915
Short name T1046
Test name
Test status
Simulation time 112785876 ps
CPU time 2.33 seconds
Started Jul 19 04:31:36 PM PDT 24
Finished Jul 19 04:31:50 PM PDT 24
Peak memory 206068 kb
Host smart-24ffe6b4-7dbc-4240-bfb4-ba25606b8edc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612839915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_sa
me_csr_outstanding.612839915
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.16823004
Short name T1061
Test name
Test status
Simulation time 120160510 ps
CPU time 2.44 seconds
Started Jul 19 04:31:18 PM PDT 24
Finished Jul 19 04:31:36 PM PDT 24
Peak memory 214552 kb
Host smart-f4d8e153-3754-4462-9857-41a6ca0740af
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16823004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shadow
_reg_errors.16823004
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.822561913
Short name T966
Test name
Test status
Simulation time 834890325 ps
CPU time 14.54 seconds
Started Jul 19 04:31:12 PM PDT 24
Finished Jul 19 04:31:43 PM PDT 24
Peak memory 214484 kb
Host smart-90924113-c1fe-45cf-a662-cf949f5ffd27
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822561913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
keymgr_shadow_reg_errors_with_csr_rw.822561913
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.3984958321
Short name T969
Test name
Test status
Simulation time 52156670 ps
CPU time 3.57 seconds
Started Jul 19 04:31:24 PM PDT 24
Finished Jul 19 04:31:44 PM PDT 24
Peak memory 214248 kb
Host smart-baf0c6e2-256d-434a-b4d9-0611ecc31e5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984958321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.3984958321
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1172297454
Short name T1031
Test name
Test status
Simulation time 258430599 ps
CPU time 1.37 seconds
Started Jul 19 04:31:27 PM PDT 24
Finished Jul 19 04:31:45 PM PDT 24
Peak memory 206092 kb
Host smart-699566a2-bff2-46d5-8a9c-9752c040d5dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172297454 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.1172297454
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.3366548841
Short name T959
Test name
Test status
Simulation time 16811532 ps
CPU time 0.84 seconds
Started Jul 19 04:31:22 PM PDT 24
Finished Jul 19 04:31:39 PM PDT 24
Peak memory 205860 kb
Host smart-46068212-8e79-4315-894c-c6373f3ccf4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366548841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.3366548841
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.1647314470
Short name T930
Test name
Test status
Simulation time 8353055 ps
CPU time 0.71 seconds
Started Jul 19 04:31:22 PM PDT 24
Finished Jul 19 04:31:38 PM PDT 24
Peak memory 205848 kb
Host smart-cdcc2d34-fc3b-4710-a278-b572c0050130
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647314470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.1647314470
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1713984593
Short name T153
Test name
Test status
Simulation time 344840050 ps
CPU time 4.61 seconds
Started Jul 19 04:31:23 PM PDT 24
Finished Jul 19 04:31:43 PM PDT 24
Peak memory 206048 kb
Host smart-cdf9430f-fc12-4908-8c0a-5a8fede09ba1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713984593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.1713984593
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.971738754
Short name T124
Test name
Test status
Simulation time 51672416 ps
CPU time 2.13 seconds
Started Jul 19 04:31:29 PM PDT 24
Finished Jul 19 04:31:47 PM PDT 24
Peak memory 214436 kb
Host smart-3fb4da5d-a3d5-4c3c-aee2-b6f86689060a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971738754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shado
w_reg_errors.971738754
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.1427304880
Short name T1042
Test name
Test status
Simulation time 291039860 ps
CPU time 1.82 seconds
Started Jul 19 04:31:22 PM PDT 24
Finished Jul 19 04:31:39 PM PDT 24
Peak memory 222368 kb
Host smart-c7e7be6a-b0d4-4c87-a4b3-2872c7097dd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427304880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.1427304880
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.705600316
Short name T163
Test name
Test status
Simulation time 132616775 ps
CPU time 3.41 seconds
Started Jul 19 04:31:19 PM PDT 24
Finished Jul 19 04:31:39 PM PDT 24
Peak memory 214248 kb
Host smart-572df772-f7c8-4bf4-8311-591a058feb76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705600316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err
.705600316
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3675454001
Short name T956
Test name
Test status
Simulation time 23147873 ps
CPU time 1.08 seconds
Started Jul 19 04:32:32 PM PDT 24
Finished Jul 19 04:32:40 PM PDT 24
Peak memory 205976 kb
Host smart-d557e2fc-3658-4b4a-9c17-fbdd1ebdcd2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675454001 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.3675454001
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.2490513360
Short name T1001
Test name
Test status
Simulation time 65077541 ps
CPU time 1.13 seconds
Started Jul 19 04:31:22 PM PDT 24
Finished Jul 19 04:31:39 PM PDT 24
Peak memory 206020 kb
Host smart-2465521e-b750-4ffe-a3df-61805331f5eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490513360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.2490513360
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1597563327
Short name T1033
Test name
Test status
Simulation time 17036564 ps
CPU time 0.74 seconds
Started Jul 19 04:32:32 PM PDT 24
Finished Jul 19 04:32:40 PM PDT 24
Peak memory 205716 kb
Host smart-7b3646ff-64f6-40dd-9d95-c20c3e80fbeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597563327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1597563327
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.4119300917
Short name T150
Test name
Test status
Simulation time 91602792 ps
CPU time 1.43 seconds
Started Jul 19 04:31:24 PM PDT 24
Finished Jul 19 04:31:42 PM PDT 24
Peak memory 206060 kb
Host smart-c14cb54d-ae88-4bc8-92ff-b9b9e4651e14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119300917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.4119300917
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2047005181
Short name T1012
Test name
Test status
Simulation time 225674759 ps
CPU time 3.34 seconds
Started Jul 19 04:31:18 PM PDT 24
Finished Jul 19 04:31:38 PM PDT 24
Peak memory 214504 kb
Host smart-2a4077ad-6f54-4a46-b0ce-b2393fa834f6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047005181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.2047005181
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1408564979
Short name T123
Test name
Test status
Simulation time 85974602 ps
CPU time 3.59 seconds
Started Jul 19 04:31:22 PM PDT 24
Finished Jul 19 04:31:42 PM PDT 24
Peak memory 214524 kb
Host smart-3a963f1c-fe02-4619-89f4-232e1cbfc046
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408564979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.1408564979
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1859206492
Short name T955
Test name
Test status
Simulation time 194353200 ps
CPU time 1.63 seconds
Started Jul 19 04:31:17 PM PDT 24
Finished Jul 19 04:31:35 PM PDT 24
Peak memory 215656 kb
Host smart-07be270e-654a-4aca-a0ab-7ab40de42634
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859206492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1859206492
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.43904713
Short name T1052
Test name
Test status
Simulation time 97567632 ps
CPU time 2.44 seconds
Started Jul 19 04:31:25 PM PDT 24
Finished Jul 19 04:31:43 PM PDT 24
Peak memory 215236 kb
Host smart-48f1df5f-dde0-447a-852d-17ee1308e667
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43904713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_err.43904713
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3117275469
Short name T960
Test name
Test status
Simulation time 56726319 ps
CPU time 2.02 seconds
Started Jul 19 04:31:17 PM PDT 24
Finished Jul 19 04:31:35 PM PDT 24
Peak memory 214184 kb
Host smart-3bc055ec-bf99-4ed6-9da4-2c25d9a70b69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117275469 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.3117275469
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.3219010865
Short name T946
Test name
Test status
Simulation time 36717917 ps
CPU time 1.01 seconds
Started Jul 19 04:31:21 PM PDT 24
Finished Jul 19 04:31:38 PM PDT 24
Peak memory 205944 kb
Host smart-dcbe2de7-af3e-4331-a259-aec704559919
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219010865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.3219010865
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.888276139
Short name T957
Test name
Test status
Simulation time 9159154 ps
CPU time 0.7 seconds
Started Jul 19 04:31:22 PM PDT 24
Finished Jul 19 04:31:38 PM PDT 24
Peak memory 205852 kb
Host smart-c4641614-fcda-4a06-9853-3aa839fb2e8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888276139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.888276139
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.572573215
Short name T947
Test name
Test status
Simulation time 130025560 ps
CPU time 2.03 seconds
Started Jul 19 04:31:38 PM PDT 24
Finished Jul 19 04:31:51 PM PDT 24
Peak memory 206028 kb
Host smart-f43ec076-f28c-4a6c-9d71-ad72d099dcbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572573215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_sa
me_csr_outstanding.572573215
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2900932743
Short name T1037
Test name
Test status
Simulation time 347884019 ps
CPU time 2.76 seconds
Started Jul 19 04:31:27 PM PDT 24
Finished Jul 19 04:31:46 PM PDT 24
Peak memory 214536 kb
Host smart-6bb7b78e-33c8-4b46-a49c-85ed1c0c7808
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900932743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.2900932743
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.1808096964
Short name T925
Test name
Test status
Simulation time 48806804 ps
CPU time 1.45 seconds
Started Jul 19 04:31:21 PM PDT 24
Finished Jul 19 04:31:39 PM PDT 24
Peak memory 214272 kb
Host smart-9f8b8f9c-1fe5-4c07-82bc-b2296ab07d09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808096964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.1808096964
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.3668509461
Short name T169
Test name
Test status
Simulation time 273269835 ps
CPU time 9.12 seconds
Started Jul 19 04:31:19 PM PDT 24
Finished Jul 19 04:31:45 PM PDT 24
Peak memory 214276 kb
Host smart-a5f6e4bb-1d17-4baf-994b-7463fc37cf13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668509461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.3668509461
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1571596311
Short name T998
Test name
Test status
Simulation time 185607081 ps
CPU time 1.51 seconds
Started Jul 19 04:31:33 PM PDT 24
Finished Jul 19 04:31:48 PM PDT 24
Peak memory 206120 kb
Host smart-e311ab47-4f15-4711-82ee-146d7f0b3e5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571596311 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.1571596311
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.1541591386
Short name T1071
Test name
Test status
Simulation time 23883402 ps
CPU time 0.93 seconds
Started Jul 19 04:31:26 PM PDT 24
Finished Jul 19 04:31:43 PM PDT 24
Peak memory 205924 kb
Host smart-cf556d13-f686-4c51-841f-4a0a8e8bdeaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541591386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.1541591386
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.1111302921
Short name T972
Test name
Test status
Simulation time 44571528 ps
CPU time 0.83 seconds
Started Jul 19 04:31:23 PM PDT 24
Finished Jul 19 04:31:41 PM PDT 24
Peak memory 205736 kb
Host smart-1d771d64-1d48-4b0f-9cdd-c819a424fe80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111302921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.1111302921
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.67067972
Short name T151
Test name
Test status
Simulation time 47905541 ps
CPU time 1.55 seconds
Started Jul 19 04:31:23 PM PDT 24
Finished Jul 19 04:31:41 PM PDT 24
Peak memory 205932 kb
Host smart-e2031000-8e02-4b67-a4a1-fb1acc633587
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67067972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_sam
e_csr_outstanding.67067972
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1160077317
Short name T1023
Test name
Test status
Simulation time 335367901 ps
CPU time 3.28 seconds
Started Jul 19 04:31:25 PM PDT 24
Finished Jul 19 04:31:44 PM PDT 24
Peak memory 214508 kb
Host smart-e5682b36-a8f5-4aca-8e0d-ea4911f3591d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160077317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.1160077317
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.1964078684
Short name T1054
Test name
Test status
Simulation time 871751818 ps
CPU time 6.08 seconds
Started Jul 19 04:32:20 PM PDT 24
Finished Jul 19 04:32:31 PM PDT 24
Peak memory 220084 kb
Host smart-c579904f-b79e-4685-8541-c1e765d5c449
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964078684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.1964078684
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1087878501
Short name T1016
Test name
Test status
Simulation time 103562643 ps
CPU time 1.64 seconds
Started Jul 19 04:31:25 PM PDT 24
Finished Jul 19 04:31:43 PM PDT 24
Peak memory 214276 kb
Host smart-13d0a33d-ff32-4a30-8a43-6e4d01c8bac1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087878501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.1087878501
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3672057019
Short name T172
Test name
Test status
Simulation time 133842824 ps
CPU time 3.89 seconds
Started Jul 19 04:31:30 PM PDT 24
Finished Jul 19 04:31:49 PM PDT 24
Peak memory 214440 kb
Host smart-b6f8355b-e690-46df-b78f-5e2fabdcdc42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672057019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.3672057019
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3932032188
Short name T1035
Test name
Test status
Simulation time 190194196 ps
CPU time 2.15 seconds
Started Jul 19 04:31:34 PM PDT 24
Finished Jul 19 04:31:49 PM PDT 24
Peak memory 214252 kb
Host smart-7667324f-b6d4-4b70-adb1-cad02141c829
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932032188 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3932032188
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.2150791528
Short name T165
Test name
Test status
Simulation time 16296768 ps
CPU time 1.1 seconds
Started Jul 19 04:31:25 PM PDT 24
Finished Jul 19 04:31:42 PM PDT 24
Peak memory 205984 kb
Host smart-0a889430-7c93-4dc6-991d-e5b00c20bb6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150791528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.2150791528
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.1930640094
Short name T922
Test name
Test status
Simulation time 10091625 ps
CPU time 0.68 seconds
Started Jul 19 04:31:16 PM PDT 24
Finished Jul 19 04:31:33 PM PDT 24
Peak memory 205784 kb
Host smart-23977e49-ffeb-4b3d-b6df-53dc96b9e7d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930640094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.1930640094
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2138637885
Short name T1078
Test name
Test status
Simulation time 38228264 ps
CPU time 2.25 seconds
Started Jul 19 04:31:26 PM PDT 24
Finished Jul 19 04:31:45 PM PDT 24
Peak memory 205704 kb
Host smart-18794192-b097-495f-9951-194a86671459
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138637885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.2138637885
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3084540335
Short name T1013
Test name
Test status
Simulation time 197004315 ps
CPU time 1.52 seconds
Started Jul 19 04:31:23 PM PDT 24
Finished Jul 19 04:31:40 PM PDT 24
Peak memory 214532 kb
Host smart-f3d033ea-4d30-429e-b995-3f7a41d56061
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084540335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3084540335
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1518149241
Short name T979
Test name
Test status
Simulation time 986355828 ps
CPU time 6.32 seconds
Started Jul 19 04:31:25 PM PDT 24
Finished Jul 19 04:31:47 PM PDT 24
Peak memory 214392 kb
Host smart-3f737030-5d87-4337-80c8-b1190b7532af
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518149241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.1518149241
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.1363970730
Short name T1076
Test name
Test status
Simulation time 81531204 ps
CPU time 2.56 seconds
Started Jul 19 04:31:21 PM PDT 24
Finished Jul 19 04:31:40 PM PDT 24
Peak memory 214196 kb
Host smart-d27dcb19-58e9-4915-89db-20e40671baf3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363970730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.1363970730
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3946330841
Short name T929
Test name
Test status
Simulation time 721981385 ps
CPU time 11.55 seconds
Started Jul 19 04:31:06 PM PDT 24
Finished Jul 19 04:31:35 PM PDT 24
Peak memory 206072 kb
Host smart-1819c2a1-2b08-420d-88b8-3740d5b19cb8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946330841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3
946330841
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.968084134
Short name T962
Test name
Test status
Simulation time 891731603 ps
CPU time 15.92 seconds
Started Jul 19 04:31:04 PM PDT 24
Finished Jul 19 04:31:36 PM PDT 24
Peak memory 206116 kb
Host smart-8d07d034-5460-448f-b5d8-799ae1caf18f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968084134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.968084134
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3466662718
Short name T983
Test name
Test status
Simulation time 33315806 ps
CPU time 1.45 seconds
Started Jul 19 04:31:08 PM PDT 24
Finished Jul 19 04:31:26 PM PDT 24
Peak memory 206080 kb
Host smart-f04346b9-e7c6-48f7-aeac-47140a0443ed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466662718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.3
466662718
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1632534724
Short name T1047
Test name
Test status
Simulation time 196618429 ps
CPU time 1.67 seconds
Started Jul 19 04:31:08 PM PDT 24
Finished Jul 19 04:31:27 PM PDT 24
Peak memory 214332 kb
Host smart-9e6dd739-07b5-4c6e-861e-be541493c401
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632534724 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.1632534724
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3451476847
Short name T934
Test name
Test status
Simulation time 49478297 ps
CPU time 1.21 seconds
Started Jul 19 04:31:19 PM PDT 24
Finished Jul 19 04:31:37 PM PDT 24
Peak memory 206116 kb
Host smart-807a3fc1-01aa-4168-8940-8633c13ffa8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451476847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.3451476847
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.1543738917
Short name T977
Test name
Test status
Simulation time 8896432 ps
CPU time 0.78 seconds
Started Jul 19 04:31:14 PM PDT 24
Finished Jul 19 04:31:31 PM PDT 24
Peak memory 205868 kb
Host smart-6d207f2c-c0f3-487c-9c89-f0cd3aae2174
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543738917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.1543738917
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.51185082
Short name T1051
Test name
Test status
Simulation time 453998797 ps
CPU time 2.87 seconds
Started Jul 19 04:31:06 PM PDT 24
Finished Jul 19 04:31:26 PM PDT 24
Peak memory 205996 kb
Host smart-cd671ea3-ac47-45f9-952a-428da3e104a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51185082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_same
_csr_outstanding.51185082
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2412937905
Short name T953
Test name
Test status
Simulation time 240107306 ps
CPU time 2.95 seconds
Started Jul 19 04:31:07 PM PDT 24
Finished Jul 19 04:31:30 PM PDT 24
Peak memory 214472 kb
Host smart-f325f9eb-92ab-426a-8d2f-87ab346edece
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412937905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.2412937905
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3355397124
Short name T119
Test name
Test status
Simulation time 1646826905 ps
CPU time 13.76 seconds
Started Jul 19 04:31:06 PM PDT 24
Finished Jul 19 04:31:37 PM PDT 24
Peak memory 214492 kb
Host smart-701e760f-5d04-4d2c-b5a9-51e97e006e75
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355397124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.3355397124
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3077239368
Short name T982
Test name
Test status
Simulation time 143597237 ps
CPU time 5.1 seconds
Started Jul 19 04:31:04 PM PDT 24
Finished Jul 19 04:31:26 PM PDT 24
Peak memory 214256 kb
Host smart-444c2631-a858-47b6-a3f1-2ddc8601ab1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077239368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.3077239368
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.987428596
Short name T1015
Test name
Test status
Simulation time 20426729 ps
CPU time 0.72 seconds
Started Jul 19 04:31:35 PM PDT 24
Finished Jul 19 04:31:48 PM PDT 24
Peak memory 205752 kb
Host smart-5c596dff-3c99-464b-9473-e8d0aee4ed8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987428596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.987428596
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3667702181
Short name T921
Test name
Test status
Simulation time 11205345 ps
CPU time 0.74 seconds
Started Jul 19 04:31:35 PM PDT 24
Finished Jul 19 04:31:49 PM PDT 24
Peak memory 205852 kb
Host smart-f7c98970-4423-43fa-8e4a-34f952e9ce1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667702181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.3667702181
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1201142917
Short name T995
Test name
Test status
Simulation time 18876846 ps
CPU time 0.7 seconds
Started Jul 19 04:31:32 PM PDT 24
Finished Jul 19 04:31:47 PM PDT 24
Peak memory 205840 kb
Host smart-8122a2e5-83ed-48ec-ba06-28c12ea1b24a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201142917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.1201142917
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.676958143
Short name T912
Test name
Test status
Simulation time 8915871 ps
CPU time 0.71 seconds
Started Jul 19 04:31:27 PM PDT 24
Finished Jul 19 04:31:44 PM PDT 24
Peak memory 205868 kb
Host smart-679c62ef-cf69-4aae-8693-79efa0a11e28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676958143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.676958143
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.4216686188
Short name T913
Test name
Test status
Simulation time 14787131 ps
CPU time 0.73 seconds
Started Jul 19 04:31:29 PM PDT 24
Finished Jul 19 04:31:46 PM PDT 24
Peak memory 205868 kb
Host smart-3eb3452e-e6bf-487c-a757-0dad72feb044
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216686188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.4216686188
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.1810349254
Short name T1036
Test name
Test status
Simulation time 9952631 ps
CPU time 0.71 seconds
Started Jul 19 04:31:38 PM PDT 24
Finished Jul 19 04:31:50 PM PDT 24
Peak memory 205792 kb
Host smart-5b40040b-6e49-41e9-aa0e-076eb0ee7b44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810349254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.1810349254
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2909426593
Short name T1069
Test name
Test status
Simulation time 12471463 ps
CPU time 0.84 seconds
Started Jul 19 04:31:28 PM PDT 24
Finished Jul 19 04:31:45 PM PDT 24
Peak memory 205868 kb
Host smart-50724fc5-0a7f-44c8-9540-f6b395c3a648
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909426593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2909426593
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.1489393084
Short name T919
Test name
Test status
Simulation time 33113108 ps
CPU time 0.78 seconds
Started Jul 19 04:31:37 PM PDT 24
Finished Jul 19 04:31:49 PM PDT 24
Peak memory 205868 kb
Host smart-21a7b9f9-98b7-4e26-8814-fe3575bdad4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489393084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.1489393084
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2033627248
Short name T924
Test name
Test status
Simulation time 12146378 ps
CPU time 0.7 seconds
Started Jul 19 04:31:29 PM PDT 24
Finished Jul 19 04:31:45 PM PDT 24
Peak memory 205752 kb
Host smart-fc5e9792-bebc-4309-90b2-2aa7822954b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033627248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2033627248
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.3340198326
Short name T961
Test name
Test status
Simulation time 9046753 ps
CPU time 0.85 seconds
Started Jul 19 04:31:30 PM PDT 24
Finished Jul 19 04:31:46 PM PDT 24
Peak memory 205868 kb
Host smart-cbbc920c-3ba5-44ee-9b63-cbd59294413b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340198326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.3340198326
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2005135691
Short name T1024
Test name
Test status
Simulation time 260312135 ps
CPU time 8.77 seconds
Started Jul 19 04:31:08 PM PDT 24
Finished Jul 19 04:31:34 PM PDT 24
Peak memory 206040 kb
Host smart-b4941c7b-6c27-49d8-9249-126291f2d5f8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005135691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.2
005135691
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.693394190
Short name T1030
Test name
Test status
Simulation time 1009099829 ps
CPU time 13.91 seconds
Started Jul 19 04:31:04 PM PDT 24
Finished Jul 19 04:31:35 PM PDT 24
Peak memory 206088 kb
Host smart-f5c1a5e9-b76a-4cb8-b551-19a9dd6d4faf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693394190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.693394190
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.1150755577
Short name T965
Test name
Test status
Simulation time 40723290 ps
CPU time 1.34 seconds
Started Jul 19 04:31:04 PM PDT 24
Finished Jul 19 04:31:22 PM PDT 24
Peak memory 206128 kb
Host smart-9ea4d4d2-f85f-4905-b474-0e05245c59ba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150755577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.1
150755577
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3776411782
Short name T928
Test name
Test status
Simulation time 54779687 ps
CPU time 1.22 seconds
Started Jul 19 04:31:03 PM PDT 24
Finished Jul 19 04:31:21 PM PDT 24
Peak memory 214360 kb
Host smart-55dfd392-675b-45d6-a8a4-aeaa574617dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776411782 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.3776411782
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.327173054
Short name T1044
Test name
Test status
Simulation time 18389425 ps
CPU time 1.1 seconds
Started Jul 19 04:31:17 PM PDT 24
Finished Jul 19 04:31:35 PM PDT 24
Peak memory 206004 kb
Host smart-a1629873-b051-4437-834c-3f3420437df0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327173054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.327173054
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.74339543
Short name T1022
Test name
Test status
Simulation time 24216121 ps
CPU time 0.77 seconds
Started Jul 19 04:31:17 PM PDT 24
Finished Jul 19 04:31:33 PM PDT 24
Peak memory 205916 kb
Host smart-f425ac97-eb8e-4d6c-b887-cb586f3fbbae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74339543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.74339543
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.4001090481
Short name T1073
Test name
Test status
Simulation time 70313931 ps
CPU time 2.49 seconds
Started Jul 19 04:31:02 PM PDT 24
Finished Jul 19 04:31:21 PM PDT 24
Peak memory 206068 kb
Host smart-1a927284-8d5f-4327-bb09-ce23d0583306
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001090481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.4001090481
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2484233751
Short name T1027
Test name
Test status
Simulation time 172420097 ps
CPU time 2.27 seconds
Started Jul 19 04:31:13 PM PDT 24
Finished Jul 19 04:31:31 PM PDT 24
Peak memory 214568 kb
Host smart-6e034da5-a15b-43f4-abdc-1f24ec918b1b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484233751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.2484233751
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.340338116
Short name T1020
Test name
Test status
Simulation time 784765333 ps
CPU time 9.55 seconds
Started Jul 19 04:31:18 PM PDT 24
Finished Jul 19 04:31:44 PM PDT 24
Peak memory 220392 kb
Host smart-5ff6f39a-da61-44e4-b55c-2d770da8bd78
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340338116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_shadow_reg_errors_with_csr_rw.340338116
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.1045201604
Short name T1002
Test name
Test status
Simulation time 127561004 ps
CPU time 2.01 seconds
Started Jul 19 04:31:18 PM PDT 24
Finished Jul 19 04:31:36 PM PDT 24
Peak memory 214252 kb
Host smart-5b07acee-1634-494e-8a76-f1c621cdae6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045201604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.1045201604
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.656010123
Short name T1058
Test name
Test status
Simulation time 17972545 ps
CPU time 0.76 seconds
Started Jul 19 04:31:23 PM PDT 24
Finished Jul 19 04:31:40 PM PDT 24
Peak memory 205828 kb
Host smart-77d4050c-0915-47ff-bc2f-3d28a07e2ad2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656010123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.656010123
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.860058197
Short name T942
Test name
Test status
Simulation time 9256974 ps
CPU time 0.7 seconds
Started Jul 19 04:31:28 PM PDT 24
Finished Jul 19 04:31:45 PM PDT 24
Peak memory 205852 kb
Host smart-dc1787e0-fa34-420e-b245-7091285f8b0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860058197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.860058197
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.145799409
Short name T1021
Test name
Test status
Simulation time 56978940 ps
CPU time 0.69 seconds
Started Jul 19 04:31:30 PM PDT 24
Finished Jul 19 04:31:47 PM PDT 24
Peak memory 205756 kb
Host smart-670b5deb-1227-4927-bc22-65d34417e560
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145799409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.145799409
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.4051291205
Short name T980
Test name
Test status
Simulation time 28893023 ps
CPU time 0.71 seconds
Started Jul 19 04:31:25 PM PDT 24
Finished Jul 19 04:31:42 PM PDT 24
Peak memory 205840 kb
Host smart-595ac261-4d08-418b-b35c-6537314e1c0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051291205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.4051291205
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1666878575
Short name T1028
Test name
Test status
Simulation time 139304980 ps
CPU time 0.88 seconds
Started Jul 19 04:31:26 PM PDT 24
Finished Jul 19 04:31:43 PM PDT 24
Peak memory 205796 kb
Host smart-7754fb0e-0bf2-4ab3-98e2-72382c72c01c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666878575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1666878575
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.4098487419
Short name T944
Test name
Test status
Simulation time 10490861 ps
CPU time 0.79 seconds
Started Jul 19 04:31:26 PM PDT 24
Finished Jul 19 04:31:42 PM PDT 24
Peak memory 205796 kb
Host smart-2098e326-75ed-4f98-aabe-b415c184720c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098487419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.4098487419
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1233495320
Short name T1068
Test name
Test status
Simulation time 12622632 ps
CPU time 0.87 seconds
Started Jul 19 04:31:27 PM PDT 24
Finished Jul 19 04:31:45 PM PDT 24
Peak memory 205836 kb
Host smart-3496f772-9170-4dc2-93c7-7a10f8d97c36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233495320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.1233495320
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.3825513256
Short name T988
Test name
Test status
Simulation time 12037597 ps
CPU time 0.68 seconds
Started Jul 19 04:31:34 PM PDT 24
Finished Jul 19 04:31:48 PM PDT 24
Peak memory 205740 kb
Host smart-9bbd127c-088e-4536-a88e-5e20c14e3b0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825513256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.3825513256
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.1966288737
Short name T999
Test name
Test status
Simulation time 75371902 ps
CPU time 0.88 seconds
Started Jul 19 04:31:26 PM PDT 24
Finished Jul 19 04:31:43 PM PDT 24
Peak memory 205540 kb
Host smart-0b614118-5e8b-432a-839d-1e224751a0fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966288737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.1966288737
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.728898445
Short name T1075
Test name
Test status
Simulation time 21381024 ps
CPU time 0.72 seconds
Started Jul 19 04:31:29 PM PDT 24
Finished Jul 19 04:31:45 PM PDT 24
Peak memory 205876 kb
Host smart-966c4b1e-8a31-4f50-86e6-b0d2eb5f7694
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728898445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.728898445
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.4273011453
Short name T931
Test name
Test status
Simulation time 516850575 ps
CPU time 10.19 seconds
Started Jul 19 04:31:29 PM PDT 24
Finished Jul 19 04:31:55 PM PDT 24
Peak memory 205900 kb
Host smart-0ce228fd-5776-439d-a5c6-d8f13c314318
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273011453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.4
273011453
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1967272599
Short name T1011
Test name
Test status
Simulation time 2692983175 ps
CPU time 8.15 seconds
Started Jul 19 04:31:06 PM PDT 24
Finished Jul 19 04:31:31 PM PDT 24
Peak memory 206156 kb
Host smart-942a1c2d-f745-4d68-9f6a-9d02005ddbcd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967272599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.1
967272599
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1852626993
Short name T917
Test name
Test status
Simulation time 31776482 ps
CPU time 0.93 seconds
Started Jul 19 04:31:18 PM PDT 24
Finished Jul 19 04:31:35 PM PDT 24
Peak memory 205884 kb
Host smart-77425e0d-b6ee-4b9d-b715-890cb337f5c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852626993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.1
852626993
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.733747097
Short name T916
Test name
Test status
Simulation time 55291957 ps
CPU time 1.28 seconds
Started Jul 19 04:31:09 PM PDT 24
Finished Jul 19 04:31:27 PM PDT 24
Peak memory 214324 kb
Host smart-8a780d30-952a-4b7c-9144-18b29697dd4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733747097 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.733747097
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.3553697809
Short name T149
Test name
Test status
Simulation time 19067250 ps
CPU time 0.86 seconds
Started Jul 19 04:31:07 PM PDT 24
Finished Jul 19 04:31:24 PM PDT 24
Peak memory 205924 kb
Host smart-5c2539c0-411d-49cc-a1e8-f6ca81f8aece
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553697809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.3553697809
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.2341487467
Short name T1041
Test name
Test status
Simulation time 19641000 ps
CPU time 0.72 seconds
Started Jul 19 04:31:29 PM PDT 24
Finished Jul 19 04:31:45 PM PDT 24
Peak memory 205752 kb
Host smart-646632e2-3c9e-4e79-95c1-ef1032f10df7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341487467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.2341487467
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.882760768
Short name T978
Test name
Test status
Simulation time 192541173 ps
CPU time 2.15 seconds
Started Jul 19 04:31:11 PM PDT 24
Finished Jul 19 04:31:29 PM PDT 24
Peak memory 214312 kb
Host smart-1d7de028-c6ed-441d-ac85-b310ef5929e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882760768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sam
e_csr_outstanding.882760768
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.739224804
Short name T1034
Test name
Test status
Simulation time 332003446 ps
CPU time 2.23 seconds
Started Jul 19 04:31:21 PM PDT 24
Finished Jul 19 04:31:40 PM PDT 24
Peak memory 214448 kb
Host smart-d7218fa8-e9a5-416b-9ca0-0732a2cef3f3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739224804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow
_reg_errors.739224804
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.1642101848
Short name T952
Test name
Test status
Simulation time 272736676 ps
CPU time 4.85 seconds
Started Jul 19 04:31:09 PM PDT 24
Finished Jul 19 04:31:30 PM PDT 24
Peak memory 214604 kb
Host smart-abd8f2ad-e743-434c-bcc5-87c4e7493528
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642101848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.1642101848
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.176043682
Short name T951
Test name
Test status
Simulation time 25440889 ps
CPU time 1.58 seconds
Started Jul 19 04:31:24 PM PDT 24
Finished Jul 19 04:31:42 PM PDT 24
Peak memory 206076 kb
Host smart-22c75777-1972-425a-81ce-09695f2e9fe4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176043682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.176043682
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.1690431861
Short name T1017
Test name
Test status
Simulation time 263675191 ps
CPU time 5.89 seconds
Started Jul 19 04:31:10 PM PDT 24
Finished Jul 19 04:31:33 PM PDT 24
Peak memory 206076 kb
Host smart-fc7b31b1-ca51-4321-95f2-5568731473a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690431861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.1690431861
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3039793623
Short name T1038
Test name
Test status
Simulation time 10147250 ps
CPU time 0.83 seconds
Started Jul 19 04:31:26 PM PDT 24
Finished Jul 19 04:31:43 PM PDT 24
Peak memory 205788 kb
Host smart-9c0ba8d5-861f-4277-a627-9e7c1b3542f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039793623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.3039793623
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.1921047534
Short name T994
Test name
Test status
Simulation time 42747158 ps
CPU time 0.77 seconds
Started Jul 19 04:31:28 PM PDT 24
Finished Jul 19 04:31:45 PM PDT 24
Peak memory 205864 kb
Host smart-1eb5d1c7-aeef-4b43-b484-06f3ea825565
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921047534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.1921047534
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.4197960110
Short name T932
Test name
Test status
Simulation time 20303102 ps
CPU time 0.71 seconds
Started Jul 19 04:31:38 PM PDT 24
Finished Jul 19 04:31:50 PM PDT 24
Peak memory 205856 kb
Host smart-da331aec-7e40-4bd9-a04b-69e5696f8a7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197960110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.4197960110
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1455267109
Short name T1070
Test name
Test status
Simulation time 10161729 ps
CPU time 0.81 seconds
Started Jul 19 04:31:35 PM PDT 24
Finished Jul 19 04:31:49 PM PDT 24
Peak memory 206148 kb
Host smart-b3f0a283-4fd2-44f1-8a19-8a02335fd409
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455267109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1455267109
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1898315495
Short name T927
Test name
Test status
Simulation time 44341598 ps
CPU time 0.69 seconds
Started Jul 19 04:31:38 PM PDT 24
Finished Jul 19 04:31:50 PM PDT 24
Peak memory 205784 kb
Host smart-8ecc3340-db33-4af8-932f-e3155007ddcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898315495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.1898315495
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.57426953
Short name T923
Test name
Test status
Simulation time 23800161 ps
CPU time 0.77 seconds
Started Jul 19 04:31:34 PM PDT 24
Finished Jul 19 04:31:48 PM PDT 24
Peak memory 205812 kb
Host smart-c67987ca-4c68-4b72-a9af-c9a97c62f5e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57426953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.57426953
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.562669384
Short name T1050
Test name
Test status
Simulation time 11171884 ps
CPU time 0.7 seconds
Started Jul 19 04:31:25 PM PDT 24
Finished Jul 19 04:31:41 PM PDT 24
Peak memory 205860 kb
Host smart-f1db909a-047e-4892-98bf-30669764e175
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562669384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.562669384
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.4090549005
Short name T945
Test name
Test status
Simulation time 8139503 ps
CPU time 0.74 seconds
Started Jul 19 04:31:32 PM PDT 24
Finished Jul 19 04:31:47 PM PDT 24
Peak memory 206064 kb
Host smart-684717b4-6ada-46a7-a10c-71e9e20d78b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090549005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.4090549005
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2594765627
Short name T1077
Test name
Test status
Simulation time 12997587 ps
CPU time 0.79 seconds
Started Jul 19 04:31:33 PM PDT 24
Finished Jul 19 04:31:48 PM PDT 24
Peak memory 205864 kb
Host smart-3fdb5414-1124-4b63-9387-bd49a426c2b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594765627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.2594765627
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.3265666565
Short name T1053
Test name
Test status
Simulation time 80926606 ps
CPU time 0.72 seconds
Started Jul 19 04:31:32 PM PDT 24
Finished Jul 19 04:31:47 PM PDT 24
Peak memory 205860 kb
Host smart-cbb80436-bcf0-4b77-a648-c45fe5d9dd88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265666565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.3265666565
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3733991486
Short name T985
Test name
Test status
Simulation time 87617839 ps
CPU time 1.35 seconds
Started Jul 19 04:31:21 PM PDT 24
Finished Jul 19 04:31:38 PM PDT 24
Peak memory 206140 kb
Host smart-40b26126-3a43-47c1-a93f-f0217a6408c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733991486 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3733991486
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3241387871
Short name T1032
Test name
Test status
Simulation time 13006571 ps
CPU time 0.98 seconds
Started Jul 19 04:31:25 PM PDT 24
Finished Jul 19 04:31:42 PM PDT 24
Peak memory 206020 kb
Host smart-28c2f150-b4c2-4f28-b264-5f55d93c4620
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241387871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.3241387871
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.1022809469
Short name T933
Test name
Test status
Simulation time 33762322 ps
CPU time 0.66 seconds
Started Jul 19 04:31:13 PM PDT 24
Finished Jul 19 04:31:29 PM PDT 24
Peak memory 205784 kb
Host smart-b9426fb8-e622-4269-a38a-5f6c7c77629a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022809469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.1022809469
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.4227505511
Short name T1043
Test name
Test status
Simulation time 194640977 ps
CPU time 2.53 seconds
Started Jul 19 04:31:11 PM PDT 24
Finished Jul 19 04:31:30 PM PDT 24
Peak memory 206060 kb
Host smart-88e7bfb8-41ee-464c-bc7c-8b7314804625
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227505511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.4227505511
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.27303192
Short name T1072
Test name
Test status
Simulation time 175386353 ps
CPU time 3.05 seconds
Started Jul 19 04:31:08 PM PDT 24
Finished Jul 19 04:31:28 PM PDT 24
Peak memory 214556 kb
Host smart-e8b21bb0-9f38-4f51-be71-84b2835759a1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27303192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow_
reg_errors.27303192
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.584914602
Short name T964
Test name
Test status
Simulation time 339592425 ps
CPU time 10.56 seconds
Started Jul 19 04:31:20 PM PDT 24
Finished Jul 19 04:31:47 PM PDT 24
Peak memory 221260 kb
Host smart-9e8b332a-f37a-41fb-a8a3-e0b0b9e8e0ff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584914602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_shadow_reg_errors_with_csr_rw.584914602
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.1063384112
Short name T963
Test name
Test status
Simulation time 619279211 ps
CPU time 3.51 seconds
Started Jul 19 04:31:24 PM PDT 24
Finished Jul 19 04:31:44 PM PDT 24
Peak memory 214248 kb
Host smart-a3811641-46dd-4f84-b411-d526dc3f22fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063384112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.1063384112
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.748714615
Short name T171
Test name
Test status
Simulation time 412713256 ps
CPU time 4.37 seconds
Started Jul 19 04:31:13 PM PDT 24
Finished Jul 19 04:31:34 PM PDT 24
Peak memory 206024 kb
Host smart-f805f31d-614b-4717-81bc-facab4a64b48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748714615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.
748714615
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3936495789
Short name T989
Test name
Test status
Simulation time 25413013 ps
CPU time 1.47 seconds
Started Jul 19 04:31:20 PM PDT 24
Finished Jul 19 04:31:38 PM PDT 24
Peak memory 214260 kb
Host smart-f3c1ab97-8f63-4e1e-9203-11e70f838a22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936495789 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.3936495789
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1501839924
Short name T154
Test name
Test status
Simulation time 341779169 ps
CPU time 1.02 seconds
Started Jul 19 04:31:24 PM PDT 24
Finished Jul 19 04:31:42 PM PDT 24
Peak memory 205956 kb
Host smart-8c47282f-7ed0-4329-b65d-660492a9fd84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501839924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1501839924
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2908634530
Short name T1025
Test name
Test status
Simulation time 37143756 ps
CPU time 0.8 seconds
Started Jul 19 04:31:17 PM PDT 24
Finished Jul 19 04:31:34 PM PDT 24
Peak memory 205860 kb
Host smart-0418e1c1-12b8-4e42-b8c3-ae45340fcd19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908634530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.2908634530
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.2821662226
Short name T976
Test name
Test status
Simulation time 136214474 ps
CPU time 2.45 seconds
Started Jul 19 04:31:18 PM PDT 24
Finished Jul 19 04:31:37 PM PDT 24
Peak memory 206048 kb
Host smart-f9e52e0c-1761-424e-b6d1-bcb4c0f3cae3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821662226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.2821662226
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2345731525
Short name T1059
Test name
Test status
Simulation time 555144508 ps
CPU time 2.89 seconds
Started Jul 19 04:31:19 PM PDT 24
Finished Jul 19 04:31:39 PM PDT 24
Peak memory 214616 kb
Host smart-9f313b0a-7f3c-4362-a9bf-144608b9e45d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345731525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.2345731525
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.4037428934
Short name T958
Test name
Test status
Simulation time 490343960 ps
CPU time 3.2 seconds
Started Jul 19 04:31:23 PM PDT 24
Finished Jul 19 04:31:44 PM PDT 24
Peak memory 216664 kb
Host smart-581da481-a859-4295-9b3b-d144f96438d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037428934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.4037428934
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3814725344
Short name T1005
Test name
Test status
Simulation time 28718422 ps
CPU time 1.62 seconds
Started Jul 19 04:32:20 PM PDT 24
Finished Jul 19 04:32:26 PM PDT 24
Peak memory 213132 kb
Host smart-4294f016-a21a-4b06-9d9f-41b35ba42a0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814725344 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.3814725344
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1041513758
Short name T926
Test name
Test status
Simulation time 138823960 ps
CPU time 1.01 seconds
Started Jul 19 04:31:26 PM PDT 24
Finished Jul 19 04:31:43 PM PDT 24
Peak memory 206012 kb
Host smart-69b296a6-b715-4365-84c8-ae6dd3641a16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041513758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.1041513758
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.1281684361
Short name T997
Test name
Test status
Simulation time 46439976 ps
CPU time 0.84 seconds
Started Jul 19 04:31:12 PM PDT 24
Finished Jul 19 04:31:29 PM PDT 24
Peak memory 205748 kb
Host smart-fa5eb115-690c-433f-9c65-996b4acfb02a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281684361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.1281684361
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2740727064
Short name T1079
Test name
Test status
Simulation time 113724628 ps
CPU time 2.38 seconds
Started Jul 19 04:31:09 PM PDT 24
Finished Jul 19 04:31:28 PM PDT 24
Peak memory 206100 kb
Host smart-8699c176-adf0-46d1-8931-3c3ffb5b46bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740727064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.2740727064
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3730671317
Short name T971
Test name
Test status
Simulation time 494462623 ps
CPU time 3.95 seconds
Started Jul 19 04:31:19 PM PDT 24
Finished Jul 19 04:31:40 PM PDT 24
Peak memory 214732 kb
Host smart-b4a207aa-41f5-4bb3-87d4-4cc9f3e20d3b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730671317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.3730671317
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2359084576
Short name T990
Test name
Test status
Simulation time 1611076043 ps
CPU time 9.44 seconds
Started Jul 19 04:31:26 PM PDT 24
Finished Jul 19 04:31:52 PM PDT 24
Peak memory 214476 kb
Host smart-b452a0a6-ec54-46bb-a26a-0f847d5de3f4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359084576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.2359084576
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.2616068685
Short name T915
Test name
Test status
Simulation time 440739345 ps
CPU time 2.77 seconds
Started Jul 19 04:31:15 PM PDT 24
Finished Jul 19 04:31:34 PM PDT 24
Peak memory 214616 kb
Host smart-7935363a-10d4-42da-8ffe-fa6d68f64737
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616068685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.2616068685
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2941243948
Short name T948
Test name
Test status
Simulation time 43869246 ps
CPU time 1.72 seconds
Started Jul 19 04:31:21 PM PDT 24
Finished Jul 19 04:31:39 PM PDT 24
Peak memory 214268 kb
Host smart-faff6cd8-ba84-4aa6-bd6b-3afa1da587be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941243948 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.2941243948
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2827369738
Short name T1019
Test name
Test status
Simulation time 96717629 ps
CPU time 1.49 seconds
Started Jul 19 04:31:20 PM PDT 24
Finished Jul 19 04:31:38 PM PDT 24
Peak memory 206088 kb
Host smart-d40f7e72-3348-4732-bcbc-7f168dd438bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827369738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.2827369738
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.219904600
Short name T1014
Test name
Test status
Simulation time 46606545 ps
CPU time 0.82 seconds
Started Jul 19 04:31:18 PM PDT 24
Finished Jul 19 04:31:35 PM PDT 24
Peak memory 205864 kb
Host smart-6be29e1d-4e2b-4e4a-9348-ff2b105decc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219904600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.219904600
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.383165828
Short name T1048
Test name
Test status
Simulation time 250553084 ps
CPU time 1.75 seconds
Started Jul 19 04:31:20 PM PDT 24
Finished Jul 19 04:31:38 PM PDT 24
Peak memory 205984 kb
Host smart-49c819d5-9916-4fcd-bb74-6cfe3f697039
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383165828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sam
e_csr_outstanding.383165828
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.4228662747
Short name T1009
Test name
Test status
Simulation time 804897202 ps
CPU time 3.37 seconds
Started Jul 19 04:31:16 PM PDT 24
Finished Jul 19 04:31:35 PM PDT 24
Peak memory 214464 kb
Host smart-34ccff63-31bf-49a3-a1cc-7bb13c20e1f5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228662747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.4228662747
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.4024289344
Short name T1049
Test name
Test status
Simulation time 525360561 ps
CPU time 8.18 seconds
Started Jul 19 04:31:15 PM PDT 24
Finished Jul 19 04:31:39 PM PDT 24
Peak memory 214512 kb
Host smart-3df9483b-7b63-4e08-aafc-e4a25e92332b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024289344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.4024289344
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.2946915277
Short name T1074
Test name
Test status
Simulation time 133568481 ps
CPU time 4.46 seconds
Started Jul 19 04:31:18 PM PDT 24
Finished Jul 19 04:31:39 PM PDT 24
Peak memory 214232 kb
Host smart-764262eb-74c2-4bb7-a369-0cee056f7526
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946915277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.2946915277
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.3530623257
Short name T954
Test name
Test status
Simulation time 77400128 ps
CPU time 3.4 seconds
Started Jul 19 04:31:30 PM PDT 24
Finished Jul 19 04:31:49 PM PDT 24
Peak memory 214096 kb
Host smart-8281af26-d17e-4f99-a201-1ec6b2049c63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530623257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.3530623257
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.615073443
Short name T968
Test name
Test status
Simulation time 26511005 ps
CPU time 1.12 seconds
Started Jul 19 04:31:06 PM PDT 24
Finished Jul 19 04:31:24 PM PDT 24
Peak memory 206192 kb
Host smart-e7fda2cd-b874-4a83-aaf8-bdf684fddf61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615073443 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.615073443
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1589538276
Short name T396
Test name
Test status
Simulation time 106982118 ps
CPU time 1.12 seconds
Started Jul 19 04:31:25 PM PDT 24
Finished Jul 19 04:31:42 PM PDT 24
Peak memory 205952 kb
Host smart-4e90abc3-4757-4def-991e-a363a1b52291
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589538276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.1589538276
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.544439796
Short name T1056
Test name
Test status
Simulation time 37317269 ps
CPU time 0.71 seconds
Started Jul 19 04:31:18 PM PDT 24
Finished Jul 19 04:31:35 PM PDT 24
Peak memory 205788 kb
Host smart-8be9713d-e1bf-4459-85e5-e4202222311f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544439796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.544439796
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.3554059629
Short name T1007
Test name
Test status
Simulation time 133681653 ps
CPU time 1.55 seconds
Started Jul 19 04:31:20 PM PDT 24
Finished Jul 19 04:31:38 PM PDT 24
Peak memory 206028 kb
Host smart-4d3b8317-3070-4f57-824c-9717f172b719
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554059629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.3554059629
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1099197605
Short name T125
Test name
Test status
Simulation time 92726496 ps
CPU time 2.14 seconds
Started Jul 19 04:31:15 PM PDT 24
Finished Jul 19 04:31:33 PM PDT 24
Peak memory 214596 kb
Host smart-92a4d419-e991-4992-bd02-f5cfda8269c9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099197605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.1099197605
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.862111726
Short name T1006
Test name
Test status
Simulation time 96175037 ps
CPU time 3.22 seconds
Started Jul 19 04:31:24 PM PDT 24
Finished Jul 19 04:31:44 PM PDT 24
Peak memory 214448 kb
Host smart-8dc8c8c8-3a01-4544-b87d-4bc1f8c15db8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862111726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.k
eymgr_shadow_reg_errors_with_csr_rw.862111726
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.1506959621
Short name T194
Test name
Test status
Simulation time 151823937 ps
CPU time 3.51 seconds
Started Jul 19 04:31:20 PM PDT 24
Finished Jul 19 04:31:40 PM PDT 24
Peak memory 217248 kb
Host smart-419fc948-c406-44f8-a96c-f4d7ab0e5108
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506959621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.1506959621
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2354923981
Short name T168
Test name
Test status
Simulation time 189122536 ps
CPU time 2.76 seconds
Started Jul 19 04:32:35 PM PDT 24
Finished Jul 19 04:32:46 PM PDT 24
Peak memory 214200 kb
Host smart-4c1d9564-5a0b-4c67-ac6a-ddbff97318f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354923981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.2354923981
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.955568801
Short name T636
Test name
Test status
Simulation time 47208821 ps
CPU time 0.85 seconds
Started Jul 19 05:27:37 PM PDT 24
Finished Jul 19 05:27:40 PM PDT 24
Peak memory 205856 kb
Host smart-562faa25-5164-4dda-979c-5888a98ea7ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955568801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.955568801
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.3574524416
Short name T874
Test name
Test status
Simulation time 293995145 ps
CPU time 4.16 seconds
Started Jul 19 05:27:30 PM PDT 24
Finished Jul 19 05:27:39 PM PDT 24
Peak memory 208676 kb
Host smart-6405f74a-1d7f-47be-81f7-32a84512dad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574524416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.3574524416
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.642005575
Short name T583
Test name
Test status
Simulation time 82028456 ps
CPU time 1.86 seconds
Started Jul 19 05:27:29 PM PDT 24
Finished Jul 19 05:27:33 PM PDT 24
Peak memory 208956 kb
Host smart-de1e9c0f-6244-451c-b32b-0a6ed0b0114c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642005575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.642005575
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.922653115
Short name T845
Test name
Test status
Simulation time 159768836 ps
CPU time 1.85 seconds
Started Jul 19 05:27:29 PM PDT 24
Finished Jul 19 05:27:33 PM PDT 24
Peak memory 214964 kb
Host smart-94be0bbe-e061-46b6-83ca-03cca5f666c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922653115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.922653115
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.3096208124
Short name T720
Test name
Test status
Simulation time 119860658 ps
CPU time 4.93 seconds
Started Jul 19 05:27:30 PM PDT 24
Finished Jul 19 05:27:38 PM PDT 24
Peak memory 213996 kb
Host smart-61440ff5-3070-4a82-b434-a0976c751619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096208124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3096208124
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.1841319304
Short name T808
Test name
Test status
Simulation time 139790367 ps
CPU time 3.53 seconds
Started Jul 19 05:27:31 PM PDT 24
Finished Jul 19 05:27:40 PM PDT 24
Peak memory 207364 kb
Host smart-3bb7707b-503e-4c52-8424-2f20fd4dc1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841319304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.1841319304
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.1825104198
Short name T676
Test name
Test status
Simulation time 143291647 ps
CPU time 2.46 seconds
Started Jul 19 05:27:21 PM PDT 24
Finished Jul 19 05:27:27 PM PDT 24
Peak memory 206928 kb
Host smart-ffc506da-ac58-4499-9cf3-aad8166ed5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825104198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.1825104198
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.2423759195
Short name T627
Test name
Test status
Simulation time 49985991 ps
CPU time 2.93 seconds
Started Jul 19 05:27:31 PM PDT 24
Finished Jul 19 05:27:39 PM PDT 24
Peak memory 206688 kb
Host smart-9c585081-2a30-492f-ba2a-1e23d8ecc284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423759195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.2423759195
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.1865537427
Short name T136
Test name
Test status
Simulation time 79615604 ps
CPU time 2.43 seconds
Started Jul 19 05:27:13 PM PDT 24
Finished Jul 19 05:27:24 PM PDT 24
Peak memory 206544 kb
Host smart-f458213f-f140-4b89-b6d5-6f8ff3380ca5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865537427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.1865537427
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.2302521656
Short name T89
Test name
Test status
Simulation time 344814974 ps
CPU time 5.42 seconds
Started Jul 19 05:27:13 PM PDT 24
Finished Jul 19 05:27:26 PM PDT 24
Peak memory 208044 kb
Host smart-b017674e-a6a0-49b1-942d-07fab5213e15
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302521656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.2302521656
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.2976255861
Short name T348
Test name
Test status
Simulation time 192976020 ps
CPU time 3.26 seconds
Started Jul 19 05:27:20 PM PDT 24
Finished Jul 19 05:27:27 PM PDT 24
Peak memory 208180 kb
Host smart-0de8ba02-2d6c-4054-b960-5a094f6ccbf5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976255861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.2976255861
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.893042254
Short name T214
Test name
Test status
Simulation time 259538307 ps
CPU time 2.84 seconds
Started Jul 19 05:27:28 PM PDT 24
Finished Jul 19 05:27:32 PM PDT 24
Peak memory 209064 kb
Host smart-458e7c46-c663-4360-830d-4265b1d13968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893042254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.893042254
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.725461545
Short name T825
Test name
Test status
Simulation time 780907975 ps
CPU time 5.33 seconds
Started Jul 19 05:27:05 PM PDT 24
Finished Jul 19 05:27:16 PM PDT 24
Peak memory 208360 kb
Host smart-8625510e-11cf-4456-9635-f81de1c5ea97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725461545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.725461545
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.850734183
Short name T802
Test name
Test status
Simulation time 5813882620 ps
CPU time 38.02 seconds
Started Jul 19 05:27:28 PM PDT 24
Finished Jul 19 05:28:07 PM PDT 24
Peak memory 222288 kb
Host smart-1116305f-2ab4-4d8a-b87b-7407d4ae12ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850734183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.850734183
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.1114952057
Short name T190
Test name
Test status
Simulation time 296800840 ps
CPU time 10.48 seconds
Started Jul 19 05:27:28 PM PDT 24
Finished Jul 19 05:27:41 PM PDT 24
Peak memory 219004 kb
Host smart-b8ef73cf-e783-46e0-bdca-9d3f6b7c21c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114952057 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.1114952057
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.11882639
Short name T342
Test name
Test status
Simulation time 681422515 ps
CPU time 7.88 seconds
Started Jul 19 05:27:31 PM PDT 24
Finished Jul 19 05:27:44 PM PDT 24
Peak memory 214160 kb
Host smart-d4d0a7c1-4533-44d4-9b0b-6778cb1ae44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11882639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.11882639
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.1128561220
Short name T743
Test name
Test status
Simulation time 127823080 ps
CPU time 3.6 seconds
Started Jul 19 05:27:29 PM PDT 24
Finished Jul 19 05:27:35 PM PDT 24
Peak memory 210848 kb
Host smart-62384d34-dfd9-49f7-bbfa-87bfc15a2cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128561220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.1128561220
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.983410950
Short name T457
Test name
Test status
Simulation time 40811677 ps
CPU time 0.9 seconds
Started Jul 19 05:28:03 PM PDT 24
Finished Jul 19 05:28:07 PM PDT 24
Peak memory 205836 kb
Host smart-a7bf8868-0c63-4f0b-abb0-c808c3385256
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983410950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.983410950
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.2665237393
Short name T596
Test name
Test status
Simulation time 303085889 ps
CPU time 3.79 seconds
Started Jul 19 05:27:46 PM PDT 24
Finished Jul 19 05:27:52 PM PDT 24
Peak memory 214052 kb
Host smart-96898c32-74b8-4796-8de7-c78d3bb8b032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665237393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.2665237393
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.741167202
Short name T339
Test name
Test status
Simulation time 119278637 ps
CPU time 3.11 seconds
Started Jul 19 05:27:55 PM PDT 24
Finished Jul 19 05:28:02 PM PDT 24
Peak memory 214108 kb
Host smart-4b227295-fb79-447c-b7b0-7df2a416a19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741167202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.741167202
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.2019551414
Short name T389
Test name
Test status
Simulation time 169703151 ps
CPU time 4.41 seconds
Started Jul 19 05:27:48 PM PDT 24
Finished Jul 19 05:27:55 PM PDT 24
Peak memory 222124 kb
Host smart-28d53803-629c-45c4-9d19-3bbb8b32d97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019551414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.2019551414
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.2653640494
Short name T642
Test name
Test status
Simulation time 489785799 ps
CPU time 1.86 seconds
Started Jul 19 05:27:46 PM PDT 24
Finished Jul 19 05:27:51 PM PDT 24
Peak memory 206416 kb
Host smart-5484f8c7-aaf3-46b1-a231-f6f960d76ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653640494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.2653640494
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.558229563
Short name T885
Test name
Test status
Simulation time 54946502 ps
CPU time 3.61 seconds
Started Jul 19 05:27:46 PM PDT 24
Finished Jul 19 05:27:52 PM PDT 24
Peak memory 207640 kb
Host smart-f61e3f75-edd7-4b09-b40f-920d0b45a5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558229563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.558229563
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.931267053
Short name T108
Test name
Test status
Simulation time 562654905 ps
CPU time 13.89 seconds
Started Jul 19 05:27:56 PM PDT 24
Finished Jul 19 05:28:13 PM PDT 24
Peak memory 234392 kb
Host smart-509daf05-0d32-4eb6-91fc-2af6de1cffff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931267053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.931267053
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.2415384686
Short name T312
Test name
Test status
Simulation time 49464930 ps
CPU time 2.62 seconds
Started Jul 19 05:27:39 PM PDT 24
Finished Jul 19 05:27:44 PM PDT 24
Peak memory 206568 kb
Host smart-cb47a7eb-97b4-47ae-9b5a-6388d16592b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415384686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.2415384686
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.1103389276
Short name T657
Test name
Test status
Simulation time 648361294 ps
CPU time 3.91 seconds
Started Jul 19 05:27:54 PM PDT 24
Finished Jul 19 05:28:01 PM PDT 24
Peak memory 208520 kb
Host smart-763e197f-84ca-4b51-9a3c-38957b924df4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103389276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.1103389276
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.3569546799
Short name T461
Test name
Test status
Simulation time 127587988 ps
CPU time 3.2 seconds
Started Jul 19 05:27:48 PM PDT 24
Finished Jul 19 05:27:53 PM PDT 24
Peak memory 206752 kb
Host smart-96ddfeb2-66a3-4095-860d-540811c8595c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569546799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.3569546799
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.3825944177
Short name T498
Test name
Test status
Simulation time 380248787 ps
CPU time 4.76 seconds
Started Jul 19 05:27:53 PM PDT 24
Finished Jul 19 05:28:01 PM PDT 24
Peak memory 218144 kb
Host smart-a83fc69c-3877-4439-b0be-be8b966afe98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825944177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.3825944177
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.716161102
Short name T520
Test name
Test status
Simulation time 279306043 ps
CPU time 2.52 seconds
Started Jul 19 05:27:39 PM PDT 24
Finished Jul 19 05:27:44 PM PDT 24
Peak memory 206624 kb
Host smart-2a0dd5b2-d99c-4e13-9f63-6abc88b0881a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716161102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.716161102
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.1611958485
Short name T363
Test name
Test status
Simulation time 650135492 ps
CPU time 7.17 seconds
Started Jul 19 05:27:54 PM PDT 24
Finished Jul 19 05:28:05 PM PDT 24
Peak memory 214100 kb
Host smart-5312ad27-1d49-465a-832d-a2d374c85635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611958485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.1611958485
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.2014297894
Short name T455
Test name
Test status
Simulation time 117974424 ps
CPU time 0.84 seconds
Started Jul 19 05:30:04 PM PDT 24
Finished Jul 19 05:30:06 PM PDT 24
Peak memory 205788 kb
Host smart-a662745f-13fa-40c7-a703-37fe9fb61861
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014297894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.2014297894
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.1361144054
Short name T419
Test name
Test status
Simulation time 83077561 ps
CPU time 3.42 seconds
Started Jul 19 05:29:58 PM PDT 24
Finished Jul 19 05:30:02 PM PDT 24
Peak memory 214996 kb
Host smart-3e1efd4d-63e9-455f-bd58-28fa0866e051
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1361144054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.1361144054
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.2368050307
Short name T29
Test name
Test status
Simulation time 83588658 ps
CPU time 3.45 seconds
Started Jul 19 05:29:54 PM PDT 24
Finished Jul 19 05:29:59 PM PDT 24
Peak memory 217900 kb
Host smart-83ed87ae-337e-46b9-8c8e-f378e7c53c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368050307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.2368050307
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.954738640
Short name T769
Test name
Test status
Simulation time 48595785 ps
CPU time 2 seconds
Started Jul 19 05:29:56 PM PDT 24
Finished Jul 19 05:30:00 PM PDT 24
Peak memory 214040 kb
Host smart-7980f219-24d4-4a12-9218-4b013ee71fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954738640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.954738640
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.804688773
Short name T95
Test name
Test status
Simulation time 388921408 ps
CPU time 3.77 seconds
Started Jul 19 05:29:56 PM PDT 24
Finished Jul 19 05:30:01 PM PDT 24
Peak memory 214044 kb
Host smart-313d2ace-50f3-47b3-a13d-c85616a47194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804688773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.804688773
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.3870375703
Short name T261
Test name
Test status
Simulation time 45855975 ps
CPU time 1.76 seconds
Started Jul 19 05:29:53 PM PDT 24
Finished Jul 19 05:29:56 PM PDT 24
Peak memory 214004 kb
Host smart-f99b396b-0eb9-4e41-b1f1-13f6c2fce43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870375703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.3870375703
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.3421929713
Short name T68
Test name
Test status
Simulation time 91729543 ps
CPU time 3.38 seconds
Started Jul 19 05:29:54 PM PDT 24
Finished Jul 19 05:29:58 PM PDT 24
Peak memory 214088 kb
Host smart-7a6c2f6f-4edf-45e6-b4f7-4de8fcdb37ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421929713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.3421929713
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.4192784922
Short name T252
Test name
Test status
Simulation time 84608072 ps
CPU time 4.16 seconds
Started Jul 19 05:29:56 PM PDT 24
Finished Jul 19 05:30:01 PM PDT 24
Peak memory 207252 kb
Host smart-68d55864-44b3-4683-af79-caf5b30a90f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192784922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.4192784922
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.2527899297
Short name T203
Test name
Test status
Simulation time 275802832 ps
CPU time 2.78 seconds
Started Jul 19 05:29:55 PM PDT 24
Finished Jul 19 05:29:59 PM PDT 24
Peak memory 206456 kb
Host smart-b0efa2b9-a056-466e-a67a-a9f5293680e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527899297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.2527899297
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.418547525
Short name T533
Test name
Test status
Simulation time 192055856 ps
CPU time 2.83 seconds
Started Jul 19 05:29:54 PM PDT 24
Finished Jul 19 05:29:58 PM PDT 24
Peak memory 206656 kb
Host smart-41398d97-8c91-46b8-888a-cc47facae96f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418547525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.418547525
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.3681691104
Short name T483
Test name
Test status
Simulation time 427926571 ps
CPU time 7.28 seconds
Started Jul 19 05:29:55 PM PDT 24
Finished Jul 19 05:30:04 PM PDT 24
Peak memory 207796 kb
Host smart-2eb9543e-2e5a-4bb0-afde-5b035d29c024
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681691104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.3681691104
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.2842786937
Short name T199
Test name
Test status
Simulation time 1005563723 ps
CPU time 11.42 seconds
Started Jul 19 05:29:54 PM PDT 24
Finished Jul 19 05:30:07 PM PDT 24
Peak memory 208148 kb
Host smart-8a72f1c3-f43e-40b6-b159-4e168ff4e663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842786937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.2842786937
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.3492611406
Short name T580
Test name
Test status
Simulation time 27411713 ps
CPU time 2.09 seconds
Started Jul 19 05:29:56 PM PDT 24
Finished Jul 19 05:29:59 PM PDT 24
Peak memory 208460 kb
Host smart-a7e8dd24-e60c-4ca9-83d0-92ddb6fd0bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492611406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3492611406
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.2463083961
Short name T899
Test name
Test status
Simulation time 413830734 ps
CPU time 4.17 seconds
Started Jul 19 05:29:56 PM PDT 24
Finished Jul 19 05:30:01 PM PDT 24
Peak memory 206672 kb
Host smart-cfbd2195-a1f6-43a0-8097-a6ecb7bc14ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463083961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.2463083961
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.3994348540
Short name T195
Test name
Test status
Simulation time 259136575 ps
CPU time 2.88 seconds
Started Jul 19 05:29:54 PM PDT 24
Finished Jul 19 05:29:58 PM PDT 24
Peak memory 209896 kb
Host smart-cab8fc00-c70b-428d-95fe-65cb1cf98588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994348540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.3994348540
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.2061435799
Short name T531
Test name
Test status
Simulation time 33163170 ps
CPU time 0.7 seconds
Started Jul 19 05:30:10 PM PDT 24
Finished Jul 19 05:30:11 PM PDT 24
Peak memory 205784 kb
Host smart-2543c2be-18fc-4c1f-8a54-39b15b537b76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061435799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.2061435799
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.3108658945
Short name T333
Test name
Test status
Simulation time 227401247 ps
CPU time 4.61 seconds
Started Jul 19 05:30:12 PM PDT 24
Finished Jul 19 05:30:18 PM PDT 24
Peak memory 214876 kb
Host smart-83e0bf15-1f9f-4e70-8793-aecdf923699c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3108658945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.3108658945
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.2703900354
Short name T10
Test name
Test status
Simulation time 132689798 ps
CPU time 1.79 seconds
Started Jul 19 05:30:10 PM PDT 24
Finished Jul 19 05:30:13 PM PDT 24
Peak memory 216568 kb
Host smart-3eb19dfc-46e4-4524-bb6b-027e04d38c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703900354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.2703900354
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.3691914275
Short name T724
Test name
Test status
Simulation time 13171201 ps
CPU time 1.33 seconds
Started Jul 19 05:30:02 PM PDT 24
Finished Jul 19 05:30:04 PM PDT 24
Peak memory 206884 kb
Host smart-9a6d5a17-1c8d-4b01-a2b3-873d97a8fc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691914275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3691914275
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.2822128702
Short name T92
Test name
Test status
Simulation time 166570056 ps
CPU time 4.21 seconds
Started Jul 19 05:30:06 PM PDT 24
Finished Jul 19 05:30:11 PM PDT 24
Peak memory 214124 kb
Host smart-b00c97de-e904-4c14-91af-b21a6581896d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822128702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.2822128702
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.62850365
Short name T230
Test name
Test status
Simulation time 221499128 ps
CPU time 3.08 seconds
Started Jul 19 05:30:13 PM PDT 24
Finished Jul 19 05:30:17 PM PDT 24
Peak memory 222120 kb
Host smart-848fc85d-5c6a-45a8-8ee2-7e7d49b6cf9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62850365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.62850365
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.1697340076
Short name T903
Test name
Test status
Simulation time 213068539 ps
CPU time 6.51 seconds
Started Jul 19 05:30:12 PM PDT 24
Finished Jul 19 05:30:21 PM PDT 24
Peak memory 209400 kb
Host smart-95de1872-4fc0-466b-89c0-86a1fdf93eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697340076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.1697340076
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.634859873
Short name T345
Test name
Test status
Simulation time 395195748 ps
CPU time 3.41 seconds
Started Jul 19 05:30:13 PM PDT 24
Finished Jul 19 05:30:18 PM PDT 24
Peak memory 208456 kb
Host smart-3313cc3b-e696-42a5-9b99-356b38f2f245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634859873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.634859873
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.684171703
Short name T776
Test name
Test status
Simulation time 61260826 ps
CPU time 3.14 seconds
Started Jul 19 05:30:05 PM PDT 24
Finished Jul 19 05:30:09 PM PDT 24
Peak memory 206756 kb
Host smart-ce3afab7-93e6-4b62-8d83-db2f8aa3bf11
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684171703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.684171703
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.1729328348
Short name T436
Test name
Test status
Simulation time 69316629 ps
CPU time 2.33 seconds
Started Jul 19 05:30:12 PM PDT 24
Finished Jul 19 05:30:16 PM PDT 24
Peak memory 206680 kb
Host smart-fc5ac101-05e0-43af-b024-ca17e26e74da
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729328348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.1729328348
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.253767962
Short name T709
Test name
Test status
Simulation time 191217666 ps
CPU time 6.24 seconds
Started Jul 19 05:30:05 PM PDT 24
Finished Jul 19 05:30:12 PM PDT 24
Peak memory 208312 kb
Host smart-48dac893-73d3-42e7-bdb7-fd06439afcbc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253767962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.253767962
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.4042280593
Short name T909
Test name
Test status
Simulation time 246361545 ps
CPU time 1.99 seconds
Started Jul 19 05:30:15 PM PDT 24
Finished Jul 19 05:30:19 PM PDT 24
Peak memory 208876 kb
Host smart-7c9d790a-e3e1-4cbf-8f07-afddb96305a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042280593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.4042280593
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.2119146375
Short name T208
Test name
Test status
Simulation time 213027698 ps
CPU time 3.71 seconds
Started Jul 19 05:30:03 PM PDT 24
Finished Jul 19 05:30:07 PM PDT 24
Peak memory 206824 kb
Host smart-d546bf16-a337-4eff-891d-f22344db13f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119146375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.2119146375
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.386874442
Short name T2
Test name
Test status
Simulation time 110583817 ps
CPU time 2.6 seconds
Started Jul 19 05:30:12 PM PDT 24
Finished Jul 19 05:30:17 PM PDT 24
Peak memory 208384 kb
Host smart-c7271ed2-66ca-428e-8817-bf84f147acd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386874442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.386874442
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.2623372563
Short name T128
Test name
Test status
Simulation time 1590116207 ps
CPU time 7.24 seconds
Started Jul 19 05:30:11 PM PDT 24
Finished Jul 19 05:30:20 PM PDT 24
Peak memory 219472 kb
Host smart-0c64e787-019a-4cf2-8b86-75fdede92229
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623372563 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.2623372563
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.22316512
Short name T692
Test name
Test status
Simulation time 203838784 ps
CPU time 4.85 seconds
Started Jul 19 05:30:03 PM PDT 24
Finished Jul 19 05:30:08 PM PDT 24
Peak memory 207292 kb
Host smart-64df01c4-9e5b-4602-a03c-f6d7bc4fe596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22316512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.22316512
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.356024163
Short name T394
Test name
Test status
Simulation time 114999893 ps
CPU time 2.65 seconds
Started Jul 19 05:30:09 PM PDT 24
Finished Jul 19 05:30:13 PM PDT 24
Peak memory 209840 kb
Host smart-bdf47674-a708-47ad-8084-47b46690d8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356024163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.356024163
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.4241776503
Short name T480
Test name
Test status
Simulation time 14517674 ps
CPU time 0.87 seconds
Started Jul 19 05:30:20 PM PDT 24
Finished Jul 19 05:30:22 PM PDT 24
Peak memory 205828 kb
Host smart-4e11e5f0-8b67-4247-9695-e01a406c015b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241776503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.4241776503
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.1864296305
Short name T121
Test name
Test status
Simulation time 3972435203 ps
CPU time 56.41 seconds
Started Jul 19 05:30:11 PM PDT 24
Finished Jul 19 05:31:08 PM PDT 24
Peak memory 215576 kb
Host smart-cf19ca19-2473-4c62-8661-7306684a5804
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1864296305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.1864296305
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.209646413
Short name T639
Test name
Test status
Simulation time 716657688 ps
CPU time 4.67 seconds
Started Jul 19 05:30:19 PM PDT 24
Finished Jul 19 05:30:25 PM PDT 24
Peak memory 209008 kb
Host smart-8e1a79c7-86b3-4e03-aa37-9f1a283fa1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209646413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.209646413
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.417694335
Short name T415
Test name
Test status
Simulation time 250950945 ps
CPU time 2.67 seconds
Started Jul 19 05:30:10 PM PDT 24
Finished Jul 19 05:30:14 PM PDT 24
Peak memory 208892 kb
Host smart-91f6f79d-aaf3-4cca-a835-83abc4635f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417694335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.417694335
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.4107849046
Short name T97
Test name
Test status
Simulation time 367318734 ps
CPU time 4.8 seconds
Started Jul 19 05:30:19 PM PDT 24
Finished Jul 19 05:30:25 PM PDT 24
Peak memory 214068 kb
Host smart-d64eac57-bfc3-4d57-8039-42f1bfefb0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107849046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.4107849046
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.2863742895
Short name T442
Test name
Test status
Simulation time 78075316 ps
CPU time 3.49 seconds
Started Jul 19 05:30:13 PM PDT 24
Finished Jul 19 05:30:19 PM PDT 24
Peak memory 208620 kb
Host smart-e9671f8c-e46f-4b0f-90bd-7fd13d068c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863742895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.2863742895
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.1842912530
Short name T696
Test name
Test status
Simulation time 444992614 ps
CPU time 9.29 seconds
Started Jul 19 05:30:10 PM PDT 24
Finished Jul 19 05:30:21 PM PDT 24
Peak memory 208576 kb
Host smart-a60bc09e-67fd-4ec1-bf64-dc55d4f48e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842912530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.1842912530
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.3087005346
Short name T484
Test name
Test status
Simulation time 53746568 ps
CPU time 2.71 seconds
Started Jul 19 05:30:09 PM PDT 24
Finished Jul 19 05:30:13 PM PDT 24
Peak memory 208656 kb
Host smart-9429bde0-3055-4207-8c4b-4e0fb8da940b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087005346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3087005346
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.3673110488
Short name T771
Test name
Test status
Simulation time 450310897 ps
CPU time 3.74 seconds
Started Jul 19 05:30:11 PM PDT 24
Finished Jul 19 05:30:16 PM PDT 24
Peak memory 208220 kb
Host smart-448284c9-f71c-4a90-8370-7433dbb7be04
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673110488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.3673110488
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.3002191257
Short name T861
Test name
Test status
Simulation time 443326367 ps
CPU time 9.1 seconds
Started Jul 19 05:30:11 PM PDT 24
Finished Jul 19 05:30:22 PM PDT 24
Peak memory 208728 kb
Host smart-a3f1ded4-2ec2-491e-87d3-5685fd13a62b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002191257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.3002191257
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.2967182962
Short name T702
Test name
Test status
Simulation time 1464265948 ps
CPU time 13.73 seconds
Started Jul 19 05:30:11 PM PDT 24
Finished Jul 19 05:30:27 PM PDT 24
Peak memory 207732 kb
Host smart-334fb952-3751-4c9f-b136-4fc9f3f38dd8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967182962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.2967182962
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.1613341325
Short name T827
Test name
Test status
Simulation time 81035259 ps
CPU time 3.19 seconds
Started Jul 19 05:30:22 PM PDT 24
Finished Jul 19 05:30:26 PM PDT 24
Peak memory 207952 kb
Host smart-c4b9abb4-6f70-4998-ac78-16a92e3b2f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613341325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.1613341325
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.4205925069
Short name T433
Test name
Test status
Simulation time 165440481 ps
CPU time 3.95 seconds
Started Jul 19 05:30:14 PM PDT 24
Finished Jul 19 05:30:19 PM PDT 24
Peak memory 208204 kb
Host smart-46ce193a-20e2-467d-bf06-53c62f1c26ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205925069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.4205925069
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.885379911
Short name T269
Test name
Test status
Simulation time 233809862 ps
CPU time 4.97 seconds
Started Jul 19 05:30:19 PM PDT 24
Finished Jul 19 05:30:25 PM PDT 24
Peak memory 218496 kb
Host smart-0946a056-d987-4306-a98f-4961aa846d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885379911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.885379911
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.4053328681
Short name T881
Test name
Test status
Simulation time 352378529 ps
CPU time 3.24 seconds
Started Jul 19 05:30:20 PM PDT 24
Finished Jul 19 05:30:24 PM PDT 24
Peak memory 209772 kb
Host smart-15df5220-df36-45aa-b07f-cf101908410f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053328681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.4053328681
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.2554488049
Short name T417
Test name
Test status
Simulation time 155184381 ps
CPU time 3.19 seconds
Started Jul 19 05:30:30 PM PDT 24
Finished Jul 19 05:30:34 PM PDT 24
Peak memory 215176 kb
Host smart-2314d78c-38f0-4753-b17e-f8d22173fbea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2554488049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.2554488049
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.953706365
Short name T71
Test name
Test status
Simulation time 41232466 ps
CPU time 1.76 seconds
Started Jul 19 05:30:30 PM PDT 24
Finished Jul 19 05:30:33 PM PDT 24
Peak memory 208104 kb
Host smart-33450284-a367-4485-a91c-7be2e1b9762f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953706365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.953706365
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.3800599533
Short name T571
Test name
Test status
Simulation time 138470423 ps
CPU time 1.96 seconds
Started Jul 19 05:30:33 PM PDT 24
Finished Jul 19 05:30:37 PM PDT 24
Peak memory 214052 kb
Host smart-d39468ec-f8b2-4109-8a2c-362c33cddf61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800599533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3800599533
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.2819426968
Short name T552
Test name
Test status
Simulation time 2703469454 ps
CPU time 15.68 seconds
Started Jul 19 05:30:33 PM PDT 24
Finished Jul 19 05:30:51 PM PDT 24
Peak memory 214568 kb
Host smart-dd54640e-6054-45f9-b633-ce4a2ef0e310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819426968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.2819426968
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.264340694
Short name T703
Test name
Test status
Simulation time 66516977 ps
CPU time 2.98 seconds
Started Jul 19 05:30:32 PM PDT 24
Finished Jul 19 05:30:37 PM PDT 24
Peak memory 219232 kb
Host smart-072bc3b7-e659-41c3-8210-507942700e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264340694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.264340694
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.753103476
Short name T215
Test name
Test status
Simulation time 176781998 ps
CPU time 5.31 seconds
Started Jul 19 05:30:32 PM PDT 24
Finished Jul 19 05:30:38 PM PDT 24
Peak memory 208920 kb
Host smart-ed9bd664-62cb-461c-ac99-97ecbf0f9a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753103476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.753103476
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.2923520918
Short name T878
Test name
Test status
Simulation time 126932167 ps
CPU time 4.99 seconds
Started Jul 19 05:30:18 PM PDT 24
Finished Jul 19 05:30:24 PM PDT 24
Peak memory 207740 kb
Host smart-21c8c465-8647-49cb-9655-9a41e59e4681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923520918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.2923520918
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.1897009471
Short name T400
Test name
Test status
Simulation time 2566431592 ps
CPU time 14.78 seconds
Started Jul 19 05:30:18 PM PDT 24
Finished Jul 19 05:30:34 PM PDT 24
Peak memory 208548 kb
Host smart-f0be6b12-f43f-455e-92d7-0e357b9bedf3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897009471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.1897009471
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.1208812508
Short name T116
Test name
Test status
Simulation time 2698479995 ps
CPU time 9.72 seconds
Started Jul 19 05:30:22 PM PDT 24
Finished Jul 19 05:30:32 PM PDT 24
Peak memory 208940 kb
Host smart-e665924b-ce56-4010-ad7a-de806516d0f9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208812508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.1208812508
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.2511016901
Short name T819
Test name
Test status
Simulation time 625851649 ps
CPU time 15.41 seconds
Started Jul 19 05:30:32 PM PDT 24
Finished Jul 19 05:30:48 PM PDT 24
Peak memory 208008 kb
Host smart-482a98d9-622a-4266-bb0a-5405327144d2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511016901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.2511016901
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.1162167691
Short name T666
Test name
Test status
Simulation time 99469750 ps
CPU time 2.14 seconds
Started Jul 19 05:30:33 PM PDT 24
Finished Jul 19 05:30:38 PM PDT 24
Peak memory 207872 kb
Host smart-5b51da9b-c665-48ec-abc7-96d6fd0a3e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162167691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.1162167691
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.331601012
Short name T607
Test name
Test status
Simulation time 69998994 ps
CPU time 2.51 seconds
Started Jul 19 05:30:18 PM PDT 24
Finished Jul 19 05:30:22 PM PDT 24
Peak memory 208032 kb
Host smart-258af0ea-19bf-49ae-9437-2d9476a6bb93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331601012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.331601012
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.2133562707
Short name T574
Test name
Test status
Simulation time 457385090 ps
CPU time 3.51 seconds
Started Jul 19 05:30:35 PM PDT 24
Finished Jul 19 05:30:40 PM PDT 24
Peak memory 214124 kb
Host smart-036e8aae-2e88-449d-977f-0524be9cd24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133562707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2133562707
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.172915263
Short name T57
Test name
Test status
Simulation time 73391152 ps
CPU time 1.75 seconds
Started Jul 19 05:30:32 PM PDT 24
Finished Jul 19 05:30:35 PM PDT 24
Peak memory 209520 kb
Host smart-a4bf52d6-d861-4fe7-841f-ed154e5d8863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172915263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.172915263
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.1762182182
Short name T626
Test name
Test status
Simulation time 43984815 ps
CPU time 0.74 seconds
Started Jul 19 05:30:39 PM PDT 24
Finished Jul 19 05:30:41 PM PDT 24
Peak memory 204608 kb
Host smart-3939c73f-e566-4a54-ba80-5c9e3c846649
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762182182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1762182182
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.854420274
Short name T817
Test name
Test status
Simulation time 28119252 ps
CPU time 2.43 seconds
Started Jul 19 05:30:38 PM PDT 24
Finished Jul 19 05:30:42 PM PDT 24
Peak memory 214184 kb
Host smart-b9c69ed4-0d17-4849-883c-a0606d3a83bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=854420274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.854420274
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.718845998
Short name T304
Test name
Test status
Simulation time 71064273 ps
CPU time 1.67 seconds
Started Jul 19 05:30:40 PM PDT 24
Finished Jul 19 05:30:43 PM PDT 24
Peak memory 207176 kb
Host smart-b92db17f-013b-48a7-9bfc-a91273cd9446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718845998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.718845998
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.287001597
Short name T714
Test name
Test status
Simulation time 163680741 ps
CPU time 3.57 seconds
Started Jul 19 05:30:39 PM PDT 24
Finished Jul 19 05:30:45 PM PDT 24
Peak memory 214100 kb
Host smart-7e8b168c-bbc0-4e3a-8e48-fc19656c323d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287001597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.287001597
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.2672494866
Short name T84
Test name
Test status
Simulation time 88384739 ps
CPU time 3.44 seconds
Started Jul 19 05:30:39 PM PDT 24
Finished Jul 19 05:30:44 PM PDT 24
Peak memory 218884 kb
Host smart-ec6e03a7-bf0c-4975-ad5a-61220338bb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672494866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.2672494866
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.4276779217
Short name T253
Test name
Test status
Simulation time 249404611 ps
CPU time 3.59 seconds
Started Jul 19 05:30:39 PM PDT 24
Finished Jul 19 05:30:45 PM PDT 24
Peak memory 220084 kb
Host smart-d380bc35-fb97-46eb-924b-5334b7364f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276779217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.4276779217
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.2809253432
Short name T272
Test name
Test status
Simulation time 318844307 ps
CPU time 3.79 seconds
Started Jul 19 05:30:38 PM PDT 24
Finished Jul 19 05:30:44 PM PDT 24
Peak memory 209072 kb
Host smart-6f085540-5484-4857-9d38-24f7de9bbf4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809253432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.2809253432
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.2005474902
Short name T689
Test name
Test status
Simulation time 61717493 ps
CPU time 2.98 seconds
Started Jul 19 05:30:31 PM PDT 24
Finished Jul 19 05:30:35 PM PDT 24
Peak memory 208216 kb
Host smart-b13062f8-a1f5-4a57-a0ca-704b9387905a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005474902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.2005474902
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.1674441282
Short name T349
Test name
Test status
Simulation time 21823328 ps
CPU time 1.92 seconds
Started Jul 19 05:30:32 PM PDT 24
Finished Jul 19 05:30:37 PM PDT 24
Peak memory 208520 kb
Host smart-c5a2872f-d2d9-4ed2-8b7d-a0f10957a72d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674441282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.1674441282
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.3366257307
Short name T781
Test name
Test status
Simulation time 100180763 ps
CPU time 3.02 seconds
Started Jul 19 05:30:32 PM PDT 24
Finished Jul 19 05:30:38 PM PDT 24
Peak memory 206676 kb
Host smart-00e8cbb2-4254-4969-9819-ae21286db3bb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366257307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.3366257307
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.4292786489
Short name T835
Test name
Test status
Simulation time 7592028456 ps
CPU time 25.72 seconds
Started Jul 19 05:30:40 PM PDT 24
Finished Jul 19 05:31:07 PM PDT 24
Peak memory 208240 kb
Host smart-3f784908-7139-48d9-8ffa-8006e2f3631d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292786489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.4292786489
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.3857216799
Short name T570
Test name
Test status
Simulation time 238215862 ps
CPU time 2.47 seconds
Started Jul 19 05:30:37 PM PDT 24
Finished Jul 19 05:30:40 PM PDT 24
Peak memory 207148 kb
Host smart-f3938f5c-15d5-47ef-980b-6238790004ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857216799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.3857216799
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.1727504350
Short name T563
Test name
Test status
Simulation time 205849352 ps
CPU time 2.83 seconds
Started Jul 19 05:30:32 PM PDT 24
Finished Jul 19 05:30:37 PM PDT 24
Peak memory 208408 kb
Host smart-08fbebd4-4d9f-4247-acea-95b992e43f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727504350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.1727504350
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.2266850203
Short name T193
Test name
Test status
Simulation time 228495342 ps
CPU time 7.8 seconds
Started Jul 19 05:30:37 PM PDT 24
Finished Jul 19 05:30:46 PM PDT 24
Peak memory 222356 kb
Host smart-5efbbc77-5f3d-4c8a-b853-b550a62bea5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266850203 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.2266850203
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.52618981
Short name T313
Test name
Test status
Simulation time 424355483 ps
CPU time 5.99 seconds
Started Jul 19 05:30:38 PM PDT 24
Finished Jul 19 05:30:46 PM PDT 24
Peak memory 207416 kb
Host smart-93f3bc88-456a-48f5-9739-f508923b9bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52618981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.52618981
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.1759848630
Short name T393
Test name
Test status
Simulation time 147673953 ps
CPU time 3.1 seconds
Started Jul 19 05:30:38 PM PDT 24
Finished Jul 19 05:30:43 PM PDT 24
Peak memory 210160 kb
Host smart-01c17171-4f20-42bd-8ad7-d299b3329d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759848630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1759848630
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.2676725975
Short name T620
Test name
Test status
Simulation time 44961710 ps
CPU time 0.75 seconds
Started Jul 19 05:30:46 PM PDT 24
Finished Jul 19 05:30:48 PM PDT 24
Peak memory 205868 kb
Host smart-c50ed5ff-b95b-4af9-b49f-fdd49e52deff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676725975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.2676725975
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.1051577944
Short name T70
Test name
Test status
Simulation time 1647979362 ps
CPU time 17.8 seconds
Started Jul 19 05:30:44 PM PDT 24
Finished Jul 19 05:31:03 PM PDT 24
Peak memory 208960 kb
Host smart-5502376f-dd06-4634-9bdc-4e9d9c89305e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051577944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.1051577944
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.1706570740
Short name T251
Test name
Test status
Simulation time 515153887 ps
CPU time 3.44 seconds
Started Jul 19 05:30:45 PM PDT 24
Finished Jul 19 05:30:49 PM PDT 24
Peak memory 208460 kb
Host smart-9930fc03-9157-41e3-b0b3-303205f01fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706570740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.1706570740
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.1116821191
Short name T361
Test name
Test status
Simulation time 866985548 ps
CPU time 3.52 seconds
Started Jul 19 05:30:47 PM PDT 24
Finished Jul 19 05:30:52 PM PDT 24
Peak memory 213984 kb
Host smart-50b2cc49-2038-4d88-a68c-faa291de3023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116821191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.1116821191
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.847537193
Short name T564
Test name
Test status
Simulation time 45710559 ps
CPU time 2.71 seconds
Started Jul 19 05:30:46 PM PDT 24
Finished Jul 19 05:30:50 PM PDT 24
Peak memory 208144 kb
Host smart-599bfbbb-90ef-4b8b-bf40-5d07b1f932b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847537193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.847537193
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_sideload.4252743257
Short name T301
Test name
Test status
Simulation time 212374635 ps
CPU time 4.8 seconds
Started Jul 19 05:30:38 PM PDT 24
Finished Jul 19 05:30:44 PM PDT 24
Peak memory 208284 kb
Host smart-6ab1db66-1404-4385-a276-e062afccad8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252743257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.4252743257
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.994896638
Short name T506
Test name
Test status
Simulation time 1902605831 ps
CPU time 21.31 seconds
Started Jul 19 05:30:38 PM PDT 24
Finished Jul 19 05:31:01 PM PDT 24
Peak memory 208136 kb
Host smart-85aec662-905a-482a-bc10-316e73204f8f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994896638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.994896638
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.3803285058
Short name T327
Test name
Test status
Simulation time 43231099 ps
CPU time 1.9 seconds
Started Jul 19 05:30:40 PM PDT 24
Finished Jul 19 05:30:44 PM PDT 24
Peak memory 206632 kb
Host smart-54b138e4-4160-494b-8f80-39cf5ac9b0ae
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803285058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.3803285058
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.916487977
Short name T606
Test name
Test status
Simulation time 664691089 ps
CPU time 7.08 seconds
Started Jul 19 05:30:37 PM PDT 24
Finished Jul 19 05:30:45 PM PDT 24
Peak memory 206672 kb
Host smart-00bc1603-cfda-4750-a447-a3df777b50d8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916487977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.916487977
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.1759010206
Short name T558
Test name
Test status
Simulation time 38496326 ps
CPU time 2.02 seconds
Started Jul 19 05:30:46 PM PDT 24
Finished Jul 19 05:30:49 PM PDT 24
Peak memory 207316 kb
Host smart-558f9b5c-cf7f-462a-809f-7891ec2c6cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759010206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.1759010206
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.2036470112
Short name T752
Test name
Test status
Simulation time 122787381 ps
CPU time 3.05 seconds
Started Jul 19 05:30:38 PM PDT 24
Finished Jul 19 05:30:43 PM PDT 24
Peak memory 208472 kb
Host smart-e2acf38e-da89-4036-9c68-ced2b62f5ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036470112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2036470112
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.2027753738
Short name T767
Test name
Test status
Simulation time 632507725 ps
CPU time 4.88 seconds
Started Jul 19 05:30:47 PM PDT 24
Finished Jul 19 05:30:53 PM PDT 24
Peak memory 208564 kb
Host smart-34d28aa2-c934-49f5-8c5d-56f208c54742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027753738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.2027753738
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.746329174
Short name T39
Test name
Test status
Simulation time 32968639 ps
CPU time 2.12 seconds
Started Jul 19 05:30:46 PM PDT 24
Finished Jul 19 05:30:50 PM PDT 24
Peak memory 209716 kb
Host smart-2a395415-e656-46bd-aecc-edfa1c9b6f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746329174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.746329174
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.4058932437
Short name T464
Test name
Test status
Simulation time 14991342 ps
CPU time 0.78 seconds
Started Jul 19 05:30:54 PM PDT 24
Finished Jul 19 05:30:55 PM PDT 24
Peak memory 205792 kb
Host smart-cf3a87ba-3df9-44f8-8180-f14f64439b93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058932437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.4058932437
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.755701766
Short name T796
Test name
Test status
Simulation time 119168294 ps
CPU time 1.84 seconds
Started Jul 19 05:30:53 PM PDT 24
Finished Jul 19 05:30:56 PM PDT 24
Peak memory 208820 kb
Host smart-7b13d460-f2dd-4d7d-a2d4-9460e9a76ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755701766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.755701766
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.909061953
Short name T798
Test name
Test status
Simulation time 384236563 ps
CPU time 4.7 seconds
Started Jul 19 05:30:53 PM PDT 24
Finished Jul 19 05:30:58 PM PDT 24
Peak memory 207876 kb
Host smart-09fa35fe-3e1b-4d68-b6a8-321171f5b042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909061953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.909061953
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.1600150187
Short name T791
Test name
Test status
Simulation time 7111900408 ps
CPU time 89.5 seconds
Started Jul 19 05:30:54 PM PDT 24
Finished Jul 19 05:32:24 PM PDT 24
Peak memory 222280 kb
Host smart-8776e9c5-b9e6-4235-8cfc-f7389628506c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600150187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.1600150187
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.355444611
Short name T628
Test name
Test status
Simulation time 50195799 ps
CPU time 3.3 seconds
Started Jul 19 05:30:52 PM PDT 24
Finished Jul 19 05:30:57 PM PDT 24
Peak memory 221044 kb
Host smart-be695efe-7b61-4fbf-a2d6-70dac738b5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355444611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.355444611
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.3744643679
Short name T602
Test name
Test status
Simulation time 92207540 ps
CPU time 3.49 seconds
Started Jul 19 05:30:55 PM PDT 24
Finished Jul 19 05:31:00 PM PDT 24
Peak memory 209916 kb
Host smart-2db88317-4322-45a8-ab7a-174c64a3e055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744643679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.3744643679
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.3574328683
Short name T734
Test name
Test status
Simulation time 813847027 ps
CPU time 6.67 seconds
Started Jul 19 05:30:54 PM PDT 24
Finished Jul 19 05:31:01 PM PDT 24
Peak memory 218400 kb
Host smart-3fb11fcf-2948-4f5e-8769-a6d5a48cb50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574328683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3574328683
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.3957966710
Short name T404
Test name
Test status
Simulation time 1718378021 ps
CPU time 23.25 seconds
Started Jul 19 05:30:46 PM PDT 24
Finished Jul 19 05:31:10 PM PDT 24
Peak memory 208232 kb
Host smart-059e2424-e610-4b07-b1c3-6c8f56d155ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957966710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.3957966710
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.2822277624
Short name T783
Test name
Test status
Simulation time 3257138953 ps
CPU time 36.06 seconds
Started Jul 19 05:31:06 PM PDT 24
Finished Jul 19 05:31:44 PM PDT 24
Peak memory 209036 kb
Host smart-9608c102-7822-42de-9269-b383e6240533
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822277624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.2822277624
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.4147303619
Short name T660
Test name
Test status
Simulation time 181205605 ps
CPU time 5.16 seconds
Started Jul 19 05:30:46 PM PDT 24
Finished Jul 19 05:30:53 PM PDT 24
Peak memory 207660 kb
Host smart-f42d7779-29d6-4660-845a-2ef6aab37cae
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147303619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.4147303619
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.335803107
Short name T609
Test name
Test status
Simulation time 207678013 ps
CPU time 7.8 seconds
Started Jul 19 05:30:46 PM PDT 24
Finished Jul 19 05:30:55 PM PDT 24
Peak memory 206828 kb
Host smart-a4d79b49-1278-4386-a92c-422f42b31074
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335803107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.335803107
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.1434841676
Short name T879
Test name
Test status
Simulation time 330493687 ps
CPU time 3.91 seconds
Started Jul 19 05:30:52 PM PDT 24
Finished Jul 19 05:30:56 PM PDT 24
Peak memory 208416 kb
Host smart-bb754fc4-bb73-40c8-8907-722c880012f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434841676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.1434841676
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.1719397753
Short name T665
Test name
Test status
Simulation time 570478196 ps
CPU time 5.17 seconds
Started Jul 19 05:30:44 PM PDT 24
Finished Jul 19 05:30:50 PM PDT 24
Peak memory 208356 kb
Host smart-5a69a585-ddc2-40e4-9660-33416e1bd852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719397753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.1719397753
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.1158338190
Short name T255
Test name
Test status
Simulation time 563264326 ps
CPU time 14.61 seconds
Started Jul 19 05:30:53 PM PDT 24
Finished Jul 19 05:31:08 PM PDT 24
Peak memory 208804 kb
Host smart-749cc902-475f-4aa2-bdb6-684b3a7258c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158338190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.1158338190
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.3220363335
Short name T54
Test name
Test status
Simulation time 714614379 ps
CPU time 26.4 seconds
Started Jul 19 05:30:51 PM PDT 24
Finished Jul 19 05:31:19 PM PDT 24
Peak memory 222372 kb
Host smart-c625f3a7-c2a3-4de6-aa64-716d399070d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220363335 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.3220363335
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.1759990995
Short name T832
Test name
Test status
Simulation time 143455626 ps
CPU time 3.75 seconds
Started Jul 19 05:30:54 PM PDT 24
Finished Jul 19 05:30:59 PM PDT 24
Peak memory 207196 kb
Host smart-b2896190-6779-4f53-8055-bf130ed754a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759990995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1759990995
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.4271740323
Short name T723
Test name
Test status
Simulation time 270302051 ps
CPU time 4.9 seconds
Started Jul 19 05:30:56 PM PDT 24
Finished Jul 19 05:31:02 PM PDT 24
Peak memory 210520 kb
Host smart-c50986fe-a803-452c-9806-8e1de188e226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271740323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.4271740323
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.3005839790
Short name T875
Test name
Test status
Simulation time 8747152 ps
CPU time 0.71 seconds
Started Jul 19 05:31:03 PM PDT 24
Finished Jul 19 05:31:06 PM PDT 24
Peak memory 205852 kb
Host smart-c0498953-4f10-4174-901f-6c0472eca421
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005839790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.3005839790
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.2636912844
Short name T519
Test name
Test status
Simulation time 1564542977 ps
CPU time 14.46 seconds
Started Jul 19 05:31:04 PM PDT 24
Finished Jul 19 05:31:21 PM PDT 24
Peak memory 208064 kb
Host smart-f21d1145-9b36-4a6c-9141-0b3f29de7b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636912844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.2636912844
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.1546941930
Short name T857
Test name
Test status
Simulation time 48358111 ps
CPU time 3.32 seconds
Started Jul 19 05:31:06 PM PDT 24
Finished Jul 19 05:31:10 PM PDT 24
Peak memory 214116 kb
Host smart-5d91ab21-8998-4139-9de9-5bd6e4f0cc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546941930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.1546941930
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.1281708863
Short name T56
Test name
Test status
Simulation time 93536966 ps
CPU time 1.62 seconds
Started Jul 19 05:31:07 PM PDT 24
Finished Jul 19 05:31:10 PM PDT 24
Peak memory 214060 kb
Host smart-8f8825e1-7e76-4da3-a7ba-8274e1a75ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281708863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.1281708863
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.2035581924
Short name T841
Test name
Test status
Simulation time 199129198 ps
CPU time 5.49 seconds
Started Jul 19 05:31:07 PM PDT 24
Finished Jul 19 05:31:15 PM PDT 24
Peak memory 214048 kb
Host smart-06ce15fd-750c-4ed1-966e-9b8eb821096c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035581924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.2035581924
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.3564100668
Short name T496
Test name
Test status
Simulation time 177920090 ps
CPU time 4.12 seconds
Started Jul 19 05:30:56 PM PDT 24
Finished Jul 19 05:31:01 PM PDT 24
Peak memory 208284 kb
Host smart-e61539bc-1bdd-45ef-8f34-c35e998f4fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564100668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3564100668
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.460511850
Short name T141
Test name
Test status
Simulation time 303050916 ps
CPU time 7.67 seconds
Started Jul 19 05:30:52 PM PDT 24
Finished Jul 19 05:31:01 PM PDT 24
Peak memory 207768 kb
Host smart-3147506e-9804-462d-b6c9-4395eebec26d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460511850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.460511850
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.657961904
Short name T717
Test name
Test status
Simulation time 71270296 ps
CPU time 3.28 seconds
Started Jul 19 05:30:56 PM PDT 24
Finished Jul 19 05:31:01 PM PDT 24
Peak memory 207800 kb
Host smart-46825dd9-4aa3-4450-80e8-7ac43380ec05
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657961904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.657961904
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.2171189281
Short name T695
Test name
Test status
Simulation time 638531197 ps
CPU time 2.77 seconds
Started Jul 19 05:31:02 PM PDT 24
Finished Jul 19 05:31:08 PM PDT 24
Peak memory 206716 kb
Host smart-808f1af2-dc3e-463c-b2b0-0d208f1ef067
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171189281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2171189281
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.1432031353
Short name T831
Test name
Test status
Simulation time 57189816 ps
CPU time 2.55 seconds
Started Jul 19 05:31:03 PM PDT 24
Finished Jul 19 05:31:08 PM PDT 24
Peak memory 208852 kb
Host smart-a2339801-b1c7-432d-9c59-ade3a26a9c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432031353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.1432031353
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2208822204
Short name T710
Test name
Test status
Simulation time 1981260286 ps
CPU time 3.93 seconds
Started Jul 19 05:30:54 PM PDT 24
Finished Jul 19 05:30:59 PM PDT 24
Peak memory 208228 kb
Host smart-7bbf77c9-c930-4cea-8ae0-96ba9924c349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208822204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2208822204
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.3609971743
Short name T619
Test name
Test status
Simulation time 243880823 ps
CPU time 3.58 seconds
Started Jul 19 05:31:03 PM PDT 24
Finished Jul 19 05:31:09 PM PDT 24
Peak memory 209136 kb
Host smart-b144349c-b972-4ab2-a473-87cc3e907fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609971743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.3609971743
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.2419723784
Short name T133
Test name
Test status
Simulation time 806455117 ps
CPU time 2.82 seconds
Started Jul 19 05:31:02 PM PDT 24
Finished Jul 19 05:31:07 PM PDT 24
Peak memory 210212 kb
Host smart-a4f07b1b-8e49-4110-83ed-1a29648636dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419723784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.2419723784
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.930528099
Short name T901
Test name
Test status
Simulation time 9572814 ps
CPU time 0.74 seconds
Started Jul 19 05:31:11 PM PDT 24
Finished Jul 19 05:31:13 PM PDT 24
Peak memory 205844 kb
Host smart-d0b50df5-65dd-4264-8a8a-ba83dc9b8a28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930528099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.930528099
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.1326650237
Short name T420
Test name
Test status
Simulation time 94728970 ps
CPU time 5.97 seconds
Started Jul 19 05:31:02 PM PDT 24
Finished Jul 19 05:31:11 PM PDT 24
Peak memory 214096 kb
Host smart-4609ba3c-1d8d-4b9b-bf38-970670b558bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1326650237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.1326650237
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.741281052
Short name T78
Test name
Test status
Simulation time 104770417 ps
CPU time 2.17 seconds
Started Jul 19 05:31:02 PM PDT 24
Finished Jul 19 05:31:06 PM PDT 24
Peak memory 208448 kb
Host smart-70552034-1d27-4257-91b2-99e2ffed5a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741281052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.741281052
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.3350716684
Short name T765
Test name
Test status
Simulation time 469397275 ps
CPU time 5.15 seconds
Started Jul 19 05:31:14 PM PDT 24
Finished Jul 19 05:31:20 PM PDT 24
Peak memory 222056 kb
Host smart-edf68db1-503c-4f47-be24-555b52a94430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350716684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.3350716684
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.3581620045
Short name T96
Test name
Test status
Simulation time 112518276 ps
CPU time 3.33 seconds
Started Jul 19 05:31:11 PM PDT 24
Finished Jul 19 05:31:15 PM PDT 24
Peak memory 222220 kb
Host smart-0cb290b1-fc0d-406b-bb3d-798760e3a405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581620045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.3581620045
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.2245488169
Short name T224
Test name
Test status
Simulation time 78481872 ps
CPU time 2.63 seconds
Started Jul 19 05:31:05 PM PDT 24
Finished Jul 19 05:31:09 PM PDT 24
Peak memory 222364 kb
Host smart-c78088de-b809-4db4-a47a-1cc980b1179b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245488169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.2245488169
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.3802262105
Short name T591
Test name
Test status
Simulation time 683112140 ps
CPU time 5.81 seconds
Started Jul 19 05:31:03 PM PDT 24
Finished Jul 19 05:31:11 PM PDT 24
Peak memory 208712 kb
Host smart-0013d71d-51cc-48ce-ba5e-c8369a0de0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802262105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.3802262105
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.401395567
Short name T354
Test name
Test status
Simulation time 201076487 ps
CPU time 7.23 seconds
Started Jul 19 05:31:03 PM PDT 24
Finished Jul 19 05:31:13 PM PDT 24
Peak memory 207788 kb
Host smart-8c214851-2815-4348-850f-9ee0b30b6934
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401395567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.401395567
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.2228180575
Short name T529
Test name
Test status
Simulation time 24827499 ps
CPU time 2.1 seconds
Started Jul 19 05:31:03 PM PDT 24
Finished Jul 19 05:31:07 PM PDT 24
Peak memory 206700 kb
Host smart-68b3e807-146f-4162-ab95-d2f3f4464c15
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228180575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.2228180575
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.163213441
Short name T725
Test name
Test status
Simulation time 192804671 ps
CPU time 3.48 seconds
Started Jul 19 05:31:04 PM PDT 24
Finished Jul 19 05:31:09 PM PDT 24
Peak memory 208700 kb
Host smart-53260fac-e662-404e-8209-2d221416e0b5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163213441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.163213441
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.1950658013
Short name T368
Test name
Test status
Simulation time 237005609 ps
CPU time 3.28 seconds
Started Jul 19 05:31:12 PM PDT 24
Finished Jul 19 05:31:16 PM PDT 24
Peak memory 214132 kb
Host smart-7bea1b7c-a967-4bc7-b7be-6220a966eba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950658013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.1950658013
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.1123148231
Short name T905
Test name
Test status
Simulation time 33925467 ps
CPU time 2.01 seconds
Started Jul 19 05:31:06 PM PDT 24
Finished Jul 19 05:31:10 PM PDT 24
Peak memory 206440 kb
Host smart-c3b4dec9-68c1-400e-a4a6-c8248b0d8aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123148231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.1123148231
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.2127277766
Short name T271
Test name
Test status
Simulation time 459607157 ps
CPU time 12.72 seconds
Started Jul 19 05:31:09 PM PDT 24
Finished Jul 19 05:31:23 PM PDT 24
Peak memory 208768 kb
Host smart-db284860-24db-4d0f-b065-5ade278b42c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127277766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.2127277766
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.1671315267
Short name T432
Test name
Test status
Simulation time 32924191 ps
CPU time 0.82 seconds
Started Jul 19 05:31:20 PM PDT 24
Finished Jul 19 05:31:22 PM PDT 24
Peak memory 205884 kb
Host smart-e3836523-5719-4ff0-9589-26dafecd612c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671315267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.1671315267
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.3420859076
Short name T560
Test name
Test status
Simulation time 155097471 ps
CPU time 2.39 seconds
Started Jul 19 05:31:20 PM PDT 24
Finished Jul 19 05:31:24 PM PDT 24
Peak memory 208644 kb
Host smart-3d2263c6-e0e8-44b3-8e26-4b5ef1d657fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420859076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.3420859076
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.4283095235
Short name T373
Test name
Test status
Simulation time 275915536 ps
CPU time 2.99 seconds
Started Jul 19 05:31:18 PM PDT 24
Finished Jul 19 05:31:22 PM PDT 24
Peak memory 209288 kb
Host smart-1d2bdd72-d8c6-4835-86de-8d0eec99b58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283095235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.4283095235
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.1077764826
Short name T522
Test name
Test status
Simulation time 183824792 ps
CPU time 3.58 seconds
Started Jul 19 05:31:20 PM PDT 24
Finished Jul 19 05:31:25 PM PDT 24
Peak memory 222172 kb
Host smart-1e41abab-2802-4b38-bbd9-ba42afed987e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077764826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.1077764826
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.3710019563
Short name T267
Test name
Test status
Simulation time 137387148 ps
CPU time 3.3 seconds
Started Jul 19 05:31:19 PM PDT 24
Finished Jul 19 05:31:23 PM PDT 24
Peak memory 222048 kb
Host smart-7c8b77b6-30d7-4193-a924-42a90ef58f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710019563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.3710019563
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.2623289561
Short name T849
Test name
Test status
Simulation time 99910232 ps
CPU time 3.28 seconds
Started Jul 19 05:31:20 PM PDT 24
Finished Jul 19 05:31:25 PM PDT 24
Peak memory 214052 kb
Host smart-0bb3c748-243a-4cb2-9bca-20a58785cd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623289561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.2623289561
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.1542285779
Short name T416
Test name
Test status
Simulation time 116492039 ps
CPU time 4.83 seconds
Started Jul 19 05:31:18 PM PDT 24
Finished Jul 19 05:31:24 PM PDT 24
Peak memory 217992 kb
Host smart-417fa06e-82dd-4a2e-b37d-5a982c9c3e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542285779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.1542285779
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.3223388731
Short name T379
Test name
Test status
Simulation time 100150583 ps
CPU time 3.47 seconds
Started Jul 19 05:31:13 PM PDT 24
Finished Jul 19 05:31:17 PM PDT 24
Peak memory 208164 kb
Host smart-9638332b-b701-4ac3-a526-479431dd03f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223388731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.3223388731
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.2892065762
Short name T634
Test name
Test status
Simulation time 288592047 ps
CPU time 5.34 seconds
Started Jul 19 05:31:09 PM PDT 24
Finished Jul 19 05:31:15 PM PDT 24
Peak memory 208452 kb
Host smart-50d165b0-8b98-4c1b-8f1a-96ba61f8532f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892065762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2892065762
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.3412516615
Short name T756
Test name
Test status
Simulation time 399735992 ps
CPU time 6.42 seconds
Started Jul 19 05:31:13 PM PDT 24
Finished Jul 19 05:31:20 PM PDT 24
Peak memory 208708 kb
Host smart-0417100d-5c6a-40ee-bca1-9aea0e295c91
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412516615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.3412516615
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.3349849677
Short name T453
Test name
Test status
Simulation time 160509521 ps
CPU time 4.49 seconds
Started Jul 19 05:31:14 PM PDT 24
Finished Jul 19 05:31:20 PM PDT 24
Peak memory 207908 kb
Host smart-b83abc50-0eb1-4a30-9a56-d1d3bff8a7ca
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349849677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3349849677
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.4158048310
Short name T212
Test name
Test status
Simulation time 129071555 ps
CPU time 3.83 seconds
Started Jul 19 05:31:19 PM PDT 24
Finished Jul 19 05:31:25 PM PDT 24
Peak memory 207212 kb
Host smart-d9a0155b-5a6a-484b-b791-2518e44e02cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158048310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.4158048310
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.1946775464
Short name T34
Test name
Test status
Simulation time 560870626 ps
CPU time 15.57 seconds
Started Jul 19 05:31:13 PM PDT 24
Finished Jul 19 05:31:29 PM PDT 24
Peak memory 207640 kb
Host smart-cc2c25c3-e265-44a2-a6f6-e7157496af08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946775464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1946775464
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.1679747618
Short name T638
Test name
Test status
Simulation time 216213083 ps
CPU time 7.41 seconds
Started Jul 19 05:31:21 PM PDT 24
Finished Jul 19 05:31:30 PM PDT 24
Peak memory 219216 kb
Host smart-3b5390db-963d-497a-a808-e2a7be5cd021
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679747618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.1679747618
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.3281448388
Short name T320
Test name
Test status
Simulation time 199347263 ps
CPU time 6.12 seconds
Started Jul 19 05:31:19 PM PDT 24
Finished Jul 19 05:31:26 PM PDT 24
Peak memory 219436 kb
Host smart-4d037e5a-93c4-40cf-9c84-3abee91ce5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281448388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3281448388
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.1594693302
Short name T402
Test name
Test status
Simulation time 1046189416 ps
CPU time 13.66 seconds
Started Jul 19 05:31:20 PM PDT 24
Finished Jul 19 05:31:35 PM PDT 24
Peak memory 210388 kb
Host smart-efba2666-9eb9-430d-85a5-847043609069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594693302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.1594693302
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.2627992770
Short name T437
Test name
Test status
Simulation time 72852168 ps
CPU time 0.83 seconds
Started Jul 19 05:28:24 PM PDT 24
Finished Jul 19 05:28:26 PM PDT 24
Peak memory 205864 kb
Host smart-f15b8f0b-08d0-4450-8752-e09da8374baf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627992770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.2627992770
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.2587775959
Short name T315
Test name
Test status
Simulation time 70095265 ps
CPU time 3.12 seconds
Started Jul 19 05:28:04 PM PDT 24
Finished Jul 19 05:28:10 PM PDT 24
Peak memory 209484 kb
Host smart-b7b3e22f-3358-4a82-8783-c7fbb7dee1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587775959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.2587775959
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.1752029102
Short name T94
Test name
Test status
Simulation time 70543913 ps
CPU time 2.47 seconds
Started Jul 19 05:28:14 PM PDT 24
Finished Jul 19 05:28:17 PM PDT 24
Peak memory 214160 kb
Host smart-71b2702e-2ad4-4ffe-8d52-5e5133872245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752029102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.1752029102
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.1967334243
Short name T654
Test name
Test status
Simulation time 2156281600 ps
CPU time 3.08 seconds
Started Jul 19 05:28:17 PM PDT 24
Finished Jul 19 05:28:21 PM PDT 24
Peak memory 219840 kb
Host smart-9fd6e4dc-5c27-4b7a-9f04-7e91f7a6d36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967334243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.1967334243
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.2903890152
Short name T629
Test name
Test status
Simulation time 90423323 ps
CPU time 4.6 seconds
Started Jul 19 05:28:02 PM PDT 24
Finished Jul 19 05:28:10 PM PDT 24
Peak memory 214160 kb
Host smart-cf552818-8bb3-4ae5-b44b-92ef12700c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903890152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.2903890152
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sideload.2085770428
Short name T486
Test name
Test status
Simulation time 206784938 ps
CPU time 7.16 seconds
Started Jul 19 05:28:03 PM PDT 24
Finished Jul 19 05:28:14 PM PDT 24
Peak memory 208268 kb
Host smart-2b25b29b-b503-4804-963a-b65e2cf0ea22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085770428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.2085770428
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.3964257423
Short name T578
Test name
Test status
Simulation time 728946223 ps
CPU time 23.4 seconds
Started Jul 19 05:28:07 PM PDT 24
Finished Jul 19 05:28:33 PM PDT 24
Peak memory 208052 kb
Host smart-2579d396-a1d2-4ce0-a7d3-97231fa204cb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964257423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.3964257423
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.1454383979
Short name T551
Test name
Test status
Simulation time 980222921 ps
CPU time 10 seconds
Started Jul 19 05:28:01 PM PDT 24
Finished Jul 19 05:28:14 PM PDT 24
Peak memory 208776 kb
Host smart-cc72ed3b-d709-46e4-8439-ddaa2f6692f7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454383979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.1454383979
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.2313824838
Short name T545
Test name
Test status
Simulation time 149019209 ps
CPU time 2.54 seconds
Started Jul 19 05:28:03 PM PDT 24
Finished Jul 19 05:28:08 PM PDT 24
Peak memory 206852 kb
Host smart-bedac36a-780b-420a-a243-cf1b1d07a646
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313824838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.2313824838
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.2307458771
Short name T462
Test name
Test status
Simulation time 93463228 ps
CPU time 2.23 seconds
Started Jul 19 05:28:13 PM PDT 24
Finished Jul 19 05:28:17 PM PDT 24
Peak memory 215144 kb
Host smart-e547e88f-9d2a-458e-b4ac-26532be8dd52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307458771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.2307458771
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.90639404
Short name T549
Test name
Test status
Simulation time 87155053 ps
CPU time 3.31 seconds
Started Jul 19 05:28:03 PM PDT 24
Finished Jul 19 05:28:10 PM PDT 24
Peak memory 208052 kb
Host smart-a9f6dfb9-2f94-4ba9-b85a-bf31c42e45fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90639404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.90639404
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.324794480
Short name T729
Test name
Test status
Simulation time 4357828164 ps
CPU time 44.04 seconds
Started Jul 19 05:28:29 PM PDT 24
Finished Jul 19 05:29:14 PM PDT 24
Peak memory 217096 kb
Host smart-2b822b2f-db52-4b67-b638-34d9623c94c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324794480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.324794480
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.4104675496
Short name T598
Test name
Test status
Simulation time 705298197 ps
CPU time 8.01 seconds
Started Jul 19 05:28:24 PM PDT 24
Finished Jul 19 05:28:33 PM PDT 24
Peak memory 222284 kb
Host smart-6ff34bf5-725a-4221-8af0-73c8d325ebf3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104675496 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.4104675496
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.1530568036
Short name T468
Test name
Test status
Simulation time 75696398 ps
CPU time 4.05 seconds
Started Jul 19 05:28:14 PM PDT 24
Finished Jul 19 05:28:19 PM PDT 24
Peak memory 219784 kb
Host smart-70337f1c-6950-4132-a57d-079a830728c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530568036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.1530568036
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.1913194783
Short name T159
Test name
Test status
Simulation time 54537566 ps
CPU time 1.8 seconds
Started Jul 19 05:28:22 PM PDT 24
Finished Jul 19 05:28:25 PM PDT 24
Peak memory 209856 kb
Host smart-27681f62-ea41-41a4-b051-f555602eec8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913194783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.1913194783
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.769452146
Short name T851
Test name
Test status
Simulation time 46362885 ps
CPU time 0.78 seconds
Started Jul 19 05:31:29 PM PDT 24
Finished Jul 19 05:31:30 PM PDT 24
Peak memory 205876 kb
Host smart-d969e229-5cef-4e7d-98de-4b5a7c4c7273
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769452146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.769452146
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.3485220380
Short name T561
Test name
Test status
Simulation time 86956115 ps
CPU time 3.01 seconds
Started Jul 19 05:31:36 PM PDT 24
Finished Jul 19 05:31:41 PM PDT 24
Peak memory 214092 kb
Host smart-7156ab6b-6da5-426a-ba86-cbd10b3533cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485220380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3485220380
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.1265361476
Short name T624
Test name
Test status
Simulation time 94999751 ps
CPU time 4.57 seconds
Started Jul 19 05:31:28 PM PDT 24
Finished Jul 19 05:31:33 PM PDT 24
Peak memory 221632 kb
Host smart-6503e4d0-81ce-4c9c-bc03-4c6ea2d4f85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265361476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.1265361476
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.1169081952
Short name T264
Test name
Test status
Simulation time 187768178 ps
CPU time 3.05 seconds
Started Jul 19 05:31:36 PM PDT 24
Finished Jul 19 05:31:41 PM PDT 24
Peak memory 222092 kb
Host smart-75647365-9a09-4328-9081-1e3bc7bf9dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169081952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.1169081952
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.366954821
Short name T240
Test name
Test status
Simulation time 342772019 ps
CPU time 5.61 seconds
Started Jul 19 05:31:36 PM PDT 24
Finished Jul 19 05:31:43 PM PDT 24
Peak memory 218416 kb
Host smart-58d417ec-af8d-4dad-b908-c26f37dfa954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366954821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.366954821
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.1392559222
Short name T505
Test name
Test status
Simulation time 599156968 ps
CPU time 7.7 seconds
Started Jul 19 05:31:18 PM PDT 24
Finished Jul 19 05:31:27 PM PDT 24
Peak memory 207912 kb
Host smart-abe81888-2b65-43ba-8da2-cc2eb16fd3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392559222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1392559222
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.783975292
Short name T753
Test name
Test status
Simulation time 307602008 ps
CPU time 5.11 seconds
Started Jul 19 05:31:19 PM PDT 24
Finished Jul 19 05:31:25 PM PDT 24
Peak memory 208220 kb
Host smart-dea5f1e2-c826-4959-99fb-d87b0781a0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783975292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.783975292
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.3130563982
Short name T489
Test name
Test status
Simulation time 70572846 ps
CPU time 3.33 seconds
Started Jul 19 05:31:22 PM PDT 24
Finished Jul 19 05:31:27 PM PDT 24
Peak memory 208388 kb
Host smart-d2be5c1c-4e99-4920-8fb6-7cfe2aa22acb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130563982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.3130563982
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.997358580
Short name T615
Test name
Test status
Simulation time 54622330 ps
CPU time 2.28 seconds
Started Jul 19 05:31:20 PM PDT 24
Finished Jul 19 05:31:24 PM PDT 24
Peak memory 208352 kb
Host smart-02cce867-534a-4d0d-953d-c221d1e156ec
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997358580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.997358580
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.3941897411
Short name T860
Test name
Test status
Simulation time 473432780 ps
CPU time 16.33 seconds
Started Jul 19 05:31:19 PM PDT 24
Finished Jul 19 05:31:37 PM PDT 24
Peak memory 207900 kb
Host smart-50d17860-6874-4cc5-8084-9d37a4c413f2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941897411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.3941897411
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.2552739524
Short name T218
Test name
Test status
Simulation time 137960504 ps
CPU time 3.55 seconds
Started Jul 19 05:31:29 PM PDT 24
Finished Jul 19 05:31:34 PM PDT 24
Peak memory 214040 kb
Host smart-9e952d02-6719-46f3-9299-527aa975119e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552739524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.2552739524
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.61935630
Short name T439
Test name
Test status
Simulation time 380495393 ps
CPU time 3.14 seconds
Started Jul 19 05:31:19 PM PDT 24
Finished Jul 19 05:31:23 PM PDT 24
Peak memory 208232 kb
Host smart-cc57882d-c3ef-4a41-998b-e37b518d0e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61935630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.61935630
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.711488411
Short name T747
Test name
Test status
Simulation time 6739381202 ps
CPU time 29.02 seconds
Started Jul 19 05:31:28 PM PDT 24
Finished Jul 19 05:31:58 PM PDT 24
Peak memory 221744 kb
Host smart-c36ffe28-7dc9-466c-a924-0e4ccb908de4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711488411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.711488411
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.1556392106
Short name T189
Test name
Test status
Simulation time 2142408038 ps
CPU time 21.13 seconds
Started Jul 19 05:31:29 PM PDT 24
Finished Jul 19 05:31:52 PM PDT 24
Peak memory 219792 kb
Host smart-0fc562c8-aad3-4a4f-8926-3b04624db34a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556392106 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.1556392106
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.3380231058
Short name T632
Test name
Test status
Simulation time 140994705 ps
CPU time 4.82 seconds
Started Jul 19 05:31:27 PM PDT 24
Finished Jul 19 05:31:32 PM PDT 24
Peak memory 207328 kb
Host smart-85924cab-50be-43f6-837f-cd5476e6da4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380231058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.3380231058
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.3720282442
Short name T64
Test name
Test status
Simulation time 898232434 ps
CPU time 3.68 seconds
Started Jul 19 05:31:29 PM PDT 24
Finished Jul 19 05:31:34 PM PDT 24
Peak memory 210160 kb
Host smart-561a935f-bcd9-49c9-a6a1-7985ffa5fbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720282442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3720282442
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.791477342
Short name T585
Test name
Test status
Simulation time 50513413 ps
CPU time 0.83 seconds
Started Jul 19 05:31:38 PM PDT 24
Finished Jul 19 05:31:40 PM PDT 24
Peak memory 205856 kb
Host smart-dec5303f-ce7e-4639-9f7f-c81ebfe9d47d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791477342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.791477342
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.2755862559
Short name T15
Test name
Test status
Simulation time 228383527 ps
CPU time 4.05 seconds
Started Jul 19 05:31:36 PM PDT 24
Finished Jul 19 05:31:42 PM PDT 24
Peak memory 208772 kb
Host smart-51177a99-e172-44d6-9041-f0344ff2b8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755862559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.2755862559
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.3146892855
Short name T869
Test name
Test status
Simulation time 50822070 ps
CPU time 1.89 seconds
Started Jul 19 05:31:27 PM PDT 24
Finished Jul 19 05:31:30 PM PDT 24
Peak memory 214004 kb
Host smart-82cbad96-47bf-4678-9304-910d84934969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146892855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.3146892855
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.4217548410
Short name T517
Test name
Test status
Simulation time 385223816 ps
CPU time 2.88 seconds
Started Jul 19 05:31:30 PM PDT 24
Finished Jul 19 05:31:34 PM PDT 24
Peak memory 215164 kb
Host smart-b925c7dd-5236-4b67-88c9-14de692d2cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217548410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.4217548410
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.522286809
Short name T474
Test name
Test status
Simulation time 213583545 ps
CPU time 4.94 seconds
Started Jul 19 05:31:36 PM PDT 24
Finished Jul 19 05:31:42 PM PDT 24
Peak memory 214080 kb
Host smart-69eef83d-3b70-427b-ae26-b5375309fefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522286809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.522286809
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.3824079676
Short name T593
Test name
Test status
Simulation time 253353391 ps
CPU time 4.66 seconds
Started Jul 19 05:31:29 PM PDT 24
Finished Jul 19 05:31:36 PM PDT 24
Peak memory 207800 kb
Host smart-84148839-39a6-4c01-9f6f-566640d5f29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824079676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.3824079676
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.1672859562
Short name T862
Test name
Test status
Simulation time 429420594 ps
CPU time 2.92 seconds
Started Jul 19 05:31:27 PM PDT 24
Finished Jul 19 05:31:31 PM PDT 24
Peak memory 206704 kb
Host smart-bc176c63-5bd0-41da-be09-66ead4a2ec02
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672859562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.1672859562
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.3070025007
Short name T586
Test name
Test status
Simulation time 117636660 ps
CPU time 2.45 seconds
Started Jul 19 05:31:29 PM PDT 24
Finished Jul 19 05:31:32 PM PDT 24
Peak memory 207252 kb
Host smart-8cccfafe-a37c-44c1-8ee3-e36d24cc97c0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070025007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.3070025007
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.2856779854
Short name T757
Test name
Test status
Simulation time 657084487 ps
CPU time 5.59 seconds
Started Jul 19 05:31:29 PM PDT 24
Finished Jul 19 05:31:36 PM PDT 24
Peak memory 208404 kb
Host smart-8cd73697-b72a-4f4c-973e-5658e848d8ed
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856779854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.2856779854
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.3748041141
Short name T512
Test name
Test status
Simulation time 196161783 ps
CPU time 1.94 seconds
Started Jul 19 05:31:38 PM PDT 24
Finished Jul 19 05:31:42 PM PDT 24
Peak memory 207956 kb
Host smart-088a13eb-c7c1-413b-8263-6a7bcaa38b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748041141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.3748041141
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.1700367802
Short name T652
Test name
Test status
Simulation time 79321408 ps
CPU time 3.08 seconds
Started Jul 19 05:31:27 PM PDT 24
Finished Jul 19 05:31:31 PM PDT 24
Peak memory 208416 kb
Host smart-0412f2e7-8094-4829-93f9-2c5b3e4c2751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700367802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.1700367802
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2754981980
Short name T325
Test name
Test status
Simulation time 853325819 ps
CPU time 24.26 seconds
Started Jul 19 05:31:39 PM PDT 24
Finished Jul 19 05:32:05 PM PDT 24
Peak memory 215848 kb
Host smart-ce784a4d-7d0b-4d10-99ef-1ddd297661de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754981980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2754981980
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.704571256
Short name T82
Test name
Test status
Simulation time 1110401065 ps
CPU time 18.38 seconds
Started Jul 19 05:31:36 PM PDT 24
Finished Jul 19 05:31:55 PM PDT 24
Peak memory 223700 kb
Host smart-6cbb22a7-ec79-488d-af26-b650082eee0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704571256 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.704571256
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.3278853657
Short name T649
Test name
Test status
Simulation time 287938178 ps
CPU time 5.4 seconds
Started Jul 19 05:31:30 PM PDT 24
Finished Jul 19 05:31:37 PM PDT 24
Peak memory 208628 kb
Host smart-fa096dcf-eb0b-435b-8637-0e441c77d6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278853657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.3278853657
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.857611078
Short name T525
Test name
Test status
Simulation time 12236905 ps
CPU time 0.89 seconds
Started Jul 19 05:31:47 PM PDT 24
Finished Jul 19 05:31:50 PM PDT 24
Peak memory 205888 kb
Host smart-53c94c47-1e0e-498b-ad48-7bd49e61cf53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857611078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.857611078
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.2927872708
Short name T385
Test name
Test status
Simulation time 653236492 ps
CPU time 15.61 seconds
Started Jul 19 05:31:38 PM PDT 24
Finished Jul 19 05:31:55 PM PDT 24
Peak memory 222320 kb
Host smart-8aa910f2-1811-4835-82e8-e5822acf7b75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2927872708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.2927872708
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.3942540102
Short name T680
Test name
Test status
Simulation time 877204278 ps
CPU time 11.13 seconds
Started Jul 19 05:31:37 PM PDT 24
Finished Jul 19 05:31:49 PM PDT 24
Peak memory 214328 kb
Host smart-136773b5-7da3-4103-aa8c-9c75eca11a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942540102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.3942540102
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.252277036
Short name T780
Test name
Test status
Simulation time 471436735 ps
CPU time 3.94 seconds
Started Jul 19 05:31:39 PM PDT 24
Finished Jul 19 05:31:44 PM PDT 24
Peak memory 214048 kb
Host smart-70880de5-22da-4edb-9fdf-a0c0dee53b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252277036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.252277036
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.3116259145
Short name T98
Test name
Test status
Simulation time 83834040 ps
CPU time 4.12 seconds
Started Jul 19 05:31:36 PM PDT 24
Finished Jul 19 05:31:42 PM PDT 24
Peak memory 209032 kb
Host smart-bc23f5b8-f239-4322-9f16-78810729959d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116259145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.3116259145
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.3726275656
Short name T222
Test name
Test status
Simulation time 701843721 ps
CPU time 3.34 seconds
Started Jul 19 05:31:39 PM PDT 24
Finished Jul 19 05:31:44 PM PDT 24
Peak memory 214668 kb
Host smart-baa8eaeb-d00f-4065-bfee-e6c20672fc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726275656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.3726275656
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_sideload.1215361247
Short name T286
Test name
Test status
Simulation time 3390890001 ps
CPU time 37.37 seconds
Started Jul 19 05:31:37 PM PDT 24
Finished Jul 19 05:32:16 PM PDT 24
Peak memory 208864 kb
Host smart-8f46a948-a3a6-4f4e-8e81-647eb1cae93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215361247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1215361247
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.3798997516
Short name T768
Test name
Test status
Simulation time 147319658 ps
CPU time 2.94 seconds
Started Jul 19 05:31:36 PM PDT 24
Finished Jul 19 05:31:40 PM PDT 24
Peak memory 206692 kb
Host smart-4569b0a9-8e52-4f32-8fce-56344adfba8e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798997516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.3798997516
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.1885368439
Short name T495
Test name
Test status
Simulation time 891242743 ps
CPU time 5.53 seconds
Started Jul 19 05:31:37 PM PDT 24
Finished Jul 19 05:31:44 PM PDT 24
Peak memory 207720 kb
Host smart-4531f2aa-3c31-4461-914f-663b2a458609
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885368439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.1885368439
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.3422400653
Short name T611
Test name
Test status
Simulation time 39409133 ps
CPU time 2.76 seconds
Started Jul 19 05:31:38 PM PDT 24
Finished Jul 19 05:31:43 PM PDT 24
Peak memory 208388 kb
Host smart-2e777595-4258-4780-a240-f6a21c1e48b3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422400653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.3422400653
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.2446170322
Short name T694
Test name
Test status
Simulation time 34612952 ps
CPU time 2.53 seconds
Started Jul 19 05:31:45 PM PDT 24
Finished Jul 19 05:31:49 PM PDT 24
Peak memory 214168 kb
Host smart-7ae64ded-58bf-433e-b6cf-f4edd1b39bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446170322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.2446170322
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.2790065653
Short name T836
Test name
Test status
Simulation time 57438882 ps
CPU time 2.58 seconds
Started Jul 19 05:31:37 PM PDT 24
Finished Jul 19 05:31:41 PM PDT 24
Peak memory 207848 kb
Host smart-929a994b-74e7-47f3-8c6f-9d30dfe16f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790065653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.2790065653
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.2668855015
Short name T880
Test name
Test status
Simulation time 3545042067 ps
CPU time 23.15 seconds
Started Jul 19 05:31:46 PM PDT 24
Finished Jul 19 05:32:11 PM PDT 24
Peak memory 214168 kb
Host smart-a6403137-4fba-4430-9de7-7a31d4f628f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668855015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.2668855015
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.3301725748
Short name T266
Test name
Test status
Simulation time 658486767 ps
CPU time 17.85 seconds
Started Jul 19 05:31:38 PM PDT 24
Finished Jul 19 05:31:58 PM PDT 24
Peak memory 214080 kb
Host smart-6661af9c-88ba-4231-8849-ecfe83f845f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301725748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.3301725748
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.1063266237
Short name T659
Test name
Test status
Simulation time 72670722 ps
CPU time 2.25 seconds
Started Jul 19 05:31:45 PM PDT 24
Finished Jul 19 05:31:48 PM PDT 24
Peak memory 210064 kb
Host smart-53da602d-74f8-44f3-b838-2c42c3102887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063266237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.1063266237
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.3720154719
Short name T773
Test name
Test status
Simulation time 32357437 ps
CPU time 0.77 seconds
Started Jul 19 05:31:45 PM PDT 24
Finished Jul 19 05:31:47 PM PDT 24
Peak memory 205992 kb
Host smart-e6160ae5-fb82-4521-b4d7-2cdd350745fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720154719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.3720154719
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.3634787688
Short name T32
Test name
Test status
Simulation time 88542358 ps
CPU time 3.76 seconds
Started Jul 19 05:31:46 PM PDT 24
Finished Jul 19 05:31:51 PM PDT 24
Peak memory 209856 kb
Host smart-34fcc59f-8987-4862-be96-206b54eaebe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634787688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.3634787688
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.2994848456
Short name T77
Test name
Test status
Simulation time 249861607 ps
CPU time 2.04 seconds
Started Jul 19 05:31:47 PM PDT 24
Finished Jul 19 05:31:51 PM PDT 24
Peak memory 206976 kb
Host smart-a251d920-092b-49cf-9341-7bb4f51b3f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994848456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2994848456
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.915910103
Short name T376
Test name
Test status
Simulation time 102840798 ps
CPU time 2.58 seconds
Started Jul 19 05:31:47 PM PDT 24
Finished Jul 19 05:31:51 PM PDT 24
Peak memory 220812 kb
Host smart-46485f2e-adf3-488f-a2ae-f42882268080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915910103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.915910103
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.1986171065
Short name T893
Test name
Test status
Simulation time 33960887 ps
CPU time 2.58 seconds
Started Jul 19 05:31:46 PM PDT 24
Finished Jul 19 05:31:50 PM PDT 24
Peak memory 220284 kb
Host smart-df872ee8-9925-4fc7-9e66-9539abfcb7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986171065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.1986171065
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.758956328
Short name T850
Test name
Test status
Simulation time 440956757 ps
CPU time 5.47 seconds
Started Jul 19 05:31:45 PM PDT 24
Finished Jul 19 05:31:51 PM PDT 24
Peak memory 209948 kb
Host smart-3206ff3b-c44b-47f6-a9f1-1fe8be773248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758956328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.758956328
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.3054222298
Short name T608
Test name
Test status
Simulation time 2118071924 ps
CPU time 28.24 seconds
Started Jul 19 05:31:48 PM PDT 24
Finished Jul 19 05:32:18 PM PDT 24
Peak memory 208340 kb
Host smart-9a63711b-31af-4053-a860-29571a2339d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054222298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.3054222298
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.3030801334
Short name T663
Test name
Test status
Simulation time 313259768 ps
CPU time 3.5 seconds
Started Jul 19 05:31:46 PM PDT 24
Finished Jul 19 05:31:52 PM PDT 24
Peak memory 207364 kb
Host smart-9f883936-a24d-46ff-9f55-6be994b0fd60
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030801334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.3030801334
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.2683292909
Short name T637
Test name
Test status
Simulation time 3756516670 ps
CPU time 19.94 seconds
Started Jul 19 05:31:46 PM PDT 24
Finished Jul 19 05:32:08 PM PDT 24
Peak memory 208236 kb
Host smart-6c453d88-79a8-40e3-961d-52d9c134eee5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683292909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.2683292909
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.1881086300
Short name T434
Test name
Test status
Simulation time 126496158 ps
CPU time 2.37 seconds
Started Jul 19 05:31:47 PM PDT 24
Finished Jul 19 05:31:51 PM PDT 24
Peak memory 206596 kb
Host smart-906927e8-a9de-4867-8f4a-ded9adb91f5b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881086300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.1881086300
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.2366563154
Short name T113
Test name
Test status
Simulation time 872936439 ps
CPU time 5.66 seconds
Started Jul 19 05:31:46 PM PDT 24
Finished Jul 19 05:31:53 PM PDT 24
Peak memory 208644 kb
Host smart-bd9e3f27-f541-4769-887a-4db39645b854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366563154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2366563154
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.1152598283
Short name T766
Test name
Test status
Simulation time 119989055 ps
CPU time 2.62 seconds
Started Jul 19 05:31:46 PM PDT 24
Finished Jul 19 05:31:51 PM PDT 24
Peak memory 206636 kb
Host smart-e2907645-1fbc-4d56-9724-c279b0b6f8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152598283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1152598283
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.353020112
Short name T705
Test name
Test status
Simulation time 306260219 ps
CPU time 4.52 seconds
Started Jul 19 05:31:44 PM PDT 24
Finished Jul 19 05:31:49 PM PDT 24
Peak memory 208016 kb
Host smart-d22e29f5-538c-4d52-9b19-dd150fc7f1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353020112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.353020112
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.1259780378
Short name T656
Test name
Test status
Simulation time 69202794 ps
CPU time 1.21 seconds
Started Jul 19 05:31:45 PM PDT 24
Finished Jul 19 05:31:47 PM PDT 24
Peak memory 209368 kb
Host smart-3c596221-9f7c-4b61-ba5e-0926ca1cfa91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259780378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.1259780378
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.3855052581
Short name T584
Test name
Test status
Simulation time 17751401 ps
CPU time 0.84 seconds
Started Jul 19 05:31:53 PM PDT 24
Finished Jul 19 05:31:55 PM PDT 24
Peak memory 205960 kb
Host smart-ad3503a3-1556-49bf-99e4-186e64c0ae32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855052581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3855052581
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.1463915549
Short name T408
Test name
Test status
Simulation time 149045892 ps
CPU time 3.02 seconds
Started Jul 19 05:31:53 PM PDT 24
Finished Jul 19 05:31:57 PM PDT 24
Peak memory 214088 kb
Host smart-c18d309e-c9d9-4126-835f-aecb7974711c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1463915549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.1463915549
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.3673226633
Short name T295
Test name
Test status
Simulation time 161407868 ps
CPU time 5.5 seconds
Started Jul 19 05:31:55 PM PDT 24
Finished Jul 19 05:32:03 PM PDT 24
Peak memory 209832 kb
Host smart-6c5c0e83-c5b6-4c84-8ba6-6535a4e108a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673226633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.3673226633
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.3556842035
Short name T48
Test name
Test status
Simulation time 77735340 ps
CPU time 4 seconds
Started Jul 19 05:31:54 PM PDT 24
Finished Jul 19 05:32:01 PM PDT 24
Peak memory 214148 kb
Host smart-21830af6-0c19-42bb-85c7-a17d26be1008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556842035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.3556842035
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.1799014144
Short name T853
Test name
Test status
Simulation time 31958520 ps
CPU time 2.5 seconds
Started Jul 19 05:31:52 PM PDT 24
Finished Jul 19 05:31:56 PM PDT 24
Peak memory 214072 kb
Host smart-05643994-b396-4c1b-b281-436985b3f4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799014144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.1799014144
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.3732030022
Short name T146
Test name
Test status
Simulation time 698544203 ps
CPU time 5.87 seconds
Started Jul 19 05:31:54 PM PDT 24
Finished Jul 19 05:32:02 PM PDT 24
Peak memory 214100 kb
Host smart-2fd9d43d-1f2b-4853-9a2c-af0fdc8a88c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732030022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.3732030022
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.1613405216
Short name T662
Test name
Test status
Simulation time 570943859 ps
CPU time 4.03 seconds
Started Jul 19 05:31:54 PM PDT 24
Finished Jul 19 05:32:01 PM PDT 24
Peak memory 207272 kb
Host smart-2330291c-7812-40be-ac83-cc25e1002f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613405216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.1613405216
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.499390157
Short name T493
Test name
Test status
Simulation time 117780870 ps
CPU time 2.95 seconds
Started Jul 19 05:31:47 PM PDT 24
Finished Jul 19 05:31:52 PM PDT 24
Peak memory 206612 kb
Host smart-ced6b8b7-dbcd-42d7-8f8d-9f39b5518119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499390157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.499390157
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.2705636570
Short name T350
Test name
Test status
Simulation time 71131782 ps
CPU time 3.31 seconds
Started Jul 19 05:31:53 PM PDT 24
Finished Jul 19 05:31:58 PM PDT 24
Peak memory 208456 kb
Host smart-4bac1de6-d3cd-4aba-82f0-cd9b4855c68d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705636570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.2705636570
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.2751828976
Short name T317
Test name
Test status
Simulation time 182613649 ps
CPU time 3.83 seconds
Started Jul 19 05:31:56 PM PDT 24
Finished Jul 19 05:32:02 PM PDT 24
Peak memory 206744 kb
Host smart-39a0ebc7-d1a5-42f0-8ae4-e7e1a9882ed9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751828976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.2751828976
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.3303401752
Short name T562
Test name
Test status
Simulation time 675523476 ps
CPU time 3.16 seconds
Started Jul 19 05:31:54 PM PDT 24
Finished Jul 19 05:32:00 PM PDT 24
Peak memory 206588 kb
Host smart-55d760af-4676-43b4-b760-a39b13816f32
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303401752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.3303401752
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.2220981028
Short name T688
Test name
Test status
Simulation time 185248550 ps
CPU time 2.16 seconds
Started Jul 19 05:31:53 PM PDT 24
Finished Jul 19 05:31:56 PM PDT 24
Peak memory 214324 kb
Host smart-41fefc0e-099f-4bde-a802-b9829654f798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220981028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.2220981028
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.2981822936
Short name T471
Test name
Test status
Simulation time 82237124 ps
CPU time 3.27 seconds
Started Jul 19 05:31:43 PM PDT 24
Finished Jul 19 05:31:47 PM PDT 24
Peak memory 208404 kb
Host smart-8fccc42b-541d-487e-9f3d-f16026988e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981822936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.2981822936
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.591464550
Short name T90
Test name
Test status
Simulation time 2308774880 ps
CPU time 25.07 seconds
Started Jul 19 05:31:59 PM PDT 24
Finished Jul 19 05:32:25 PM PDT 24
Peak memory 214176 kb
Host smart-34624824-927b-4e05-b50d-49034fd4b267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591464550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.591464550
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.2694680311
Short name T907
Test name
Test status
Simulation time 302704645 ps
CPU time 1.95 seconds
Started Jul 19 05:31:59 PM PDT 24
Finished Jul 19 05:32:02 PM PDT 24
Peak memory 210044 kb
Host smart-5b6112cd-610e-4054-b6f6-30ef65cb7eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694680311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.2694680311
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.3828098226
Short name T431
Test name
Test status
Simulation time 14078168 ps
CPU time 0.77 seconds
Started Jul 19 05:32:03 PM PDT 24
Finished Jul 19 05:32:05 PM PDT 24
Peak memory 205836 kb
Host smart-00871049-9e42-41df-a0a2-5e776ad60d69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828098226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.3828098226
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.2786576470
Short name T316
Test name
Test status
Simulation time 148442080 ps
CPU time 2.85 seconds
Started Jul 19 05:32:02 PM PDT 24
Finished Jul 19 05:32:06 PM PDT 24
Peak memory 215416 kb
Host smart-6c3abad5-0777-468a-b682-7bab2c19ae0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2786576470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.2786576470
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.128369264
Short name T38
Test name
Test status
Simulation time 237300786 ps
CPU time 4.34 seconds
Started Jul 19 05:32:04 PM PDT 24
Finished Jul 19 05:32:09 PM PDT 24
Peak memory 220364 kb
Host smart-0b684218-c4c1-4420-8e68-9ebe871cf686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128369264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.128369264
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.3615783813
Short name T829
Test name
Test status
Simulation time 101378096 ps
CPU time 2.74 seconds
Started Jul 19 05:32:01 PM PDT 24
Finished Jul 19 05:32:05 PM PDT 24
Peak memory 209276 kb
Host smart-af096471-6f5e-4862-98a3-9892bc8a22d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615783813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3615783813
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.2211895324
Short name T91
Test name
Test status
Simulation time 641574951 ps
CPU time 3.25 seconds
Started Jul 19 05:32:01 PM PDT 24
Finished Jul 19 05:32:06 PM PDT 24
Peak memory 214072 kb
Host smart-6d8464c7-1662-4751-b87b-259624bee704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211895324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.2211895324
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.3505966147
Short name T308
Test name
Test status
Simulation time 89430626 ps
CPU time 4.6 seconds
Started Jul 19 05:32:03 PM PDT 24
Finished Jul 19 05:32:08 PM PDT 24
Peak memory 221712 kb
Host smart-1caa25a0-2abc-4db3-bf2c-b7108a31d992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505966147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.3505966147
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.2860814252
Short name T220
Test name
Test status
Simulation time 171298766 ps
CPU time 2.77 seconds
Started Jul 19 05:32:03 PM PDT 24
Finished Jul 19 05:32:07 PM PDT 24
Peak memory 208176 kb
Host smart-2310c90e-23ae-4822-9895-ed4cc2256aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860814252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.2860814252
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.3431463853
Short name T138
Test name
Test status
Simulation time 971060341 ps
CPU time 6.66 seconds
Started Jul 19 05:32:00 PM PDT 24
Finished Jul 19 05:32:08 PM PDT 24
Peak memory 209484 kb
Host smart-a3bee739-9503-45f6-a995-526c2ae83517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431463853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.3431463853
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.4089354712
Short name T365
Test name
Test status
Simulation time 285840704 ps
CPU time 5.93 seconds
Started Jul 19 05:31:53 PM PDT 24
Finished Jul 19 05:32:01 PM PDT 24
Peak memory 208812 kb
Host smart-8f125998-128a-4c6b-8062-de0751b303ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089354712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.4089354712
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.4196790568
Short name T587
Test name
Test status
Simulation time 555057739 ps
CPU time 4.53 seconds
Started Jul 19 05:32:01 PM PDT 24
Finished Jul 19 05:32:07 PM PDT 24
Peak memory 208176 kb
Host smart-72423974-1aae-4eb8-931c-6da549aa2880
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196790568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.4196790568
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2334898339
Short name T727
Test name
Test status
Simulation time 220206627 ps
CPU time 3.62 seconds
Started Jul 19 05:31:54 PM PDT 24
Finished Jul 19 05:32:01 PM PDT 24
Peak memory 208720 kb
Host smart-48f9ac96-b673-4471-8f4d-80fefbe18349
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334898339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2334898339
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.4161774516
Short name T812
Test name
Test status
Simulation time 517726584 ps
CPU time 13.57 seconds
Started Jul 19 05:32:00 PM PDT 24
Finished Jul 19 05:32:15 PM PDT 24
Peak memory 207752 kb
Host smart-6210afc9-6609-4252-815d-4e1f128126e7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161774516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.4161774516
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.71277445
Short name T287
Test name
Test status
Simulation time 169759703 ps
CPU time 4.5 seconds
Started Jul 19 05:32:00 PM PDT 24
Finished Jul 19 05:32:06 PM PDT 24
Peak memory 218052 kb
Host smart-2b7c0364-8584-4f26-9506-b223cc772ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71277445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.71277445
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.1979561072
Short name T653
Test name
Test status
Simulation time 135752624 ps
CPU time 2.06 seconds
Started Jul 19 05:31:52 PM PDT 24
Finished Jul 19 05:31:55 PM PDT 24
Peak memory 206608 kb
Host smart-2a6713df-a86c-4697-b7fd-8148d507b0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979561072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.1979561072
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.2197042317
Short name T202
Test name
Test status
Simulation time 674889075 ps
CPU time 15.21 seconds
Started Jul 19 05:32:01 PM PDT 24
Finished Jul 19 05:32:18 PM PDT 24
Peak memory 208308 kb
Host smart-98986db8-8179-4478-8888-3695bf093bce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197042317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.2197042317
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.3860973817
Short name T213
Test name
Test status
Simulation time 378408526 ps
CPU time 6.08 seconds
Started Jul 19 05:32:04 PM PDT 24
Finished Jul 19 05:32:10 PM PDT 24
Peak memory 208956 kb
Host smart-28245cec-e1f6-421d-8346-dfafd5bb9edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860973817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.3860973817
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.1876196355
Short name T777
Test name
Test status
Simulation time 94847881 ps
CPU time 2.27 seconds
Started Jul 19 05:32:01 PM PDT 24
Finished Jul 19 05:32:05 PM PDT 24
Peak memory 209928 kb
Host smart-edb610fe-4cd9-4512-9d7b-c537b5137b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876196355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.1876196355
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.3819427844
Short name T760
Test name
Test status
Simulation time 44218953 ps
CPU time 0.77 seconds
Started Jul 19 05:32:11 PM PDT 24
Finished Jul 19 05:32:13 PM PDT 24
Peak memory 205792 kb
Host smart-bc3f099a-cab4-4f3d-a961-7bba461968c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819427844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.3819427844
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.3818206970
Short name T425
Test name
Test status
Simulation time 282737909 ps
CPU time 15.7 seconds
Started Jul 19 05:32:08 PM PDT 24
Finished Jul 19 05:32:24 PM PDT 24
Peak memory 214052 kb
Host smart-433cfd37-c9f6-4af0-bf9f-a82262d2539e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3818206970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.3818206970
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.894369216
Short name T718
Test name
Test status
Simulation time 49276344 ps
CPU time 1.93 seconds
Started Jul 19 05:32:09 PM PDT 24
Finished Jul 19 05:32:12 PM PDT 24
Peak memory 209972 kb
Host smart-b782213b-1b84-4bb7-9907-ee93459460d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894369216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.894369216
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.3195944931
Short name T47
Test name
Test status
Simulation time 96621739 ps
CPU time 2.03 seconds
Started Jul 19 05:32:11 PM PDT 24
Finished Jul 19 05:32:15 PM PDT 24
Peak memory 206796 kb
Host smart-c2bbfb38-1b1e-4643-ab78-19def68c6db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195944931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.3195944931
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.4170396734
Short name T103
Test name
Test status
Simulation time 45508679 ps
CPU time 3.05 seconds
Started Jul 19 05:32:09 PM PDT 24
Finished Jul 19 05:32:13 PM PDT 24
Peak memory 214104 kb
Host smart-ef7891f7-3db7-4cf7-9047-e9689ba0683d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170396734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.4170396734
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.975010
Short name T35
Test name
Test status
Simulation time 226661872 ps
CPU time 3.59 seconds
Started Jul 19 05:32:11 PM PDT 24
Finished Jul 19 05:32:17 PM PDT 24
Peak memory 214004 kb
Host smart-d7abc4c0-a3af-469f-8965-04a79d4d9fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.975010
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.2460251449
Short name T904
Test name
Test status
Simulation time 386290914 ps
CPU time 3.56 seconds
Started Jul 19 05:32:08 PM PDT 24
Finished Jul 19 05:32:12 PM PDT 24
Peak memory 219468 kb
Host smart-9d989a25-a24c-4817-a4f1-5384639fd6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460251449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.2460251449
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.3262074886
Short name T429
Test name
Test status
Simulation time 15469106004 ps
CPU time 24.98 seconds
Started Jul 19 05:32:10 PM PDT 24
Finished Jul 19 05:32:36 PM PDT 24
Peak memory 208324 kb
Host smart-088ca968-b388-4cdc-9378-5caf6eaf9d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262074886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.3262074886
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.3903914667
Short name T211
Test name
Test status
Simulation time 305723834 ps
CPU time 4.34 seconds
Started Jul 19 05:32:01 PM PDT 24
Finished Jul 19 05:32:07 PM PDT 24
Peak memory 206488 kb
Host smart-16572a51-396c-47e2-8e9a-6258aac13e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903914667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.3903914667
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.800051828
Short name T259
Test name
Test status
Simulation time 105066410 ps
CPU time 4.19 seconds
Started Jul 19 05:32:03 PM PDT 24
Finished Jul 19 05:32:08 PM PDT 24
Peak memory 206720 kb
Host smart-f64563bd-1160-4453-9191-48bf7f0bd3b4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800051828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.800051828
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.80822600
Short name T693
Test name
Test status
Simulation time 33559563 ps
CPU time 2.3 seconds
Started Jul 19 05:32:00 PM PDT 24
Finished Jul 19 05:32:04 PM PDT 24
Peak memory 208268 kb
Host smart-f6819e60-97e4-4726-a089-c419ad7b92a5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80822600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.80822600
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.3830787052
Short name T274
Test name
Test status
Simulation time 76229523 ps
CPU time 1.74 seconds
Started Jul 19 05:32:10 PM PDT 24
Finished Jul 19 05:32:13 PM PDT 24
Peak memory 215640 kb
Host smart-2845f3e4-d5f1-4ad1-8817-59ffabcdf63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830787052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.3830787052
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.2339832200
Short name T492
Test name
Test status
Simulation time 191966321 ps
CPU time 1.87 seconds
Started Jul 19 05:32:00 PM PDT 24
Finished Jul 19 05:32:03 PM PDT 24
Peak memory 206640 kb
Host smart-9e8c9c7b-44e6-44fa-80bd-d813ace613b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339832200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.2339832200
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.1027647150
Short name T329
Test name
Test status
Simulation time 126381930 ps
CPU time 3.37 seconds
Started Jul 19 05:32:12 PM PDT 24
Finished Jul 19 05:32:17 PM PDT 24
Peak memory 207368 kb
Host smart-825838ee-916e-4dd8-880c-132fabc860a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027647150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.1027647150
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.3835487861
Short name T888
Test name
Test status
Simulation time 214174629 ps
CPU time 3.59 seconds
Started Jul 19 05:32:11 PM PDT 24
Finished Jul 19 05:32:16 PM PDT 24
Peak memory 210004 kb
Host smart-1372fad7-3d24-4431-9b95-a1390a906966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835487861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.3835487861
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.1045057207
Short name T613
Test name
Test status
Simulation time 50994428 ps
CPU time 0.75 seconds
Started Jul 19 05:32:19 PM PDT 24
Finished Jul 19 05:32:21 PM PDT 24
Peak memory 205892 kb
Host smart-7b24969b-b0fb-4019-888e-439f1b724349
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045057207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.1045057207
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1342455788
Short name T902
Test name
Test status
Simulation time 216612306 ps
CPU time 3.95 seconds
Started Jul 19 05:32:10 PM PDT 24
Finished Jul 19 05:32:15 PM PDT 24
Peak memory 214068 kb
Host smart-5dfe2e18-fea7-4215-9014-a1213e7de5d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1342455788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1342455788
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.764900084
Short name T309
Test name
Test status
Simulation time 39912565 ps
CPU time 2.3 seconds
Started Jul 19 05:32:11 PM PDT 24
Finished Jul 19 05:32:15 PM PDT 24
Peak memory 214024 kb
Host smart-cfcee1d1-2734-4bd7-b1fd-0f745b7851c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764900084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.764900084
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.3892491835
Short name T341
Test name
Test status
Simulation time 80624167 ps
CPU time 3 seconds
Started Jul 19 05:32:11 PM PDT 24
Finished Jul 19 05:32:16 PM PDT 24
Peak memory 214164 kb
Host smart-15161631-6f66-46f5-8911-72888ba883f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892491835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.3892491835
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.835213195
Short name T234
Test name
Test status
Simulation time 189840938 ps
CPU time 3.08 seconds
Started Jul 19 05:32:13 PM PDT 24
Finished Jul 19 05:32:17 PM PDT 24
Peak memory 207800 kb
Host smart-397b3c76-3cee-4d6a-8e81-a8528e16270c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835213195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.835213195
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.1905451601
Short name T865
Test name
Test status
Simulation time 78270592 ps
CPU time 4.02 seconds
Started Jul 19 05:32:12 PM PDT 24
Finished Jul 19 05:32:18 PM PDT 24
Peak memory 218080 kb
Host smart-0a775e56-224f-4494-9cbd-5b61e97a84e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905451601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.1905451601
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.4276052744
Short name T508
Test name
Test status
Simulation time 640079313 ps
CPU time 5.94 seconds
Started Jul 19 05:32:09 PM PDT 24
Finished Jul 19 05:32:16 PM PDT 24
Peak memory 207884 kb
Host smart-6449be95-4651-472e-bc9a-c30651cf2421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276052744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.4276052744
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.2868883932
Short name T889
Test name
Test status
Simulation time 2905841600 ps
CPU time 28.59 seconds
Started Jul 19 05:32:11 PM PDT 24
Finished Jul 19 05:32:41 PM PDT 24
Peak memory 208536 kb
Host smart-5f729adc-5178-4877-815f-e7be62f11438
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868883932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2868883932
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.3803083741
Short name T644
Test name
Test status
Simulation time 8009126030 ps
CPU time 37.82 seconds
Started Jul 19 05:32:10 PM PDT 24
Finished Jul 19 05:32:49 PM PDT 24
Peak memory 208864 kb
Host smart-108e3d55-72ea-4e6a-91d0-a2940a339916
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803083741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.3803083741
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.3211384924
Short name T399
Test name
Test status
Simulation time 153559789 ps
CPU time 2.89 seconds
Started Jul 19 05:32:10 PM PDT 24
Finished Jul 19 05:32:14 PM PDT 24
Peak memory 208760 kb
Host smart-0ef66cf4-4957-470f-9ca2-b0a0bf077804
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211384924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.3211384924
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.835614506
Short name T826
Test name
Test status
Simulation time 108208870 ps
CPU time 3.34 seconds
Started Jul 19 05:32:20 PM PDT 24
Finished Jul 19 05:32:25 PM PDT 24
Peak memory 207408 kb
Host smart-ba8dcb7f-1ec2-4725-97b0-4557ecaf53d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835614506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.835614506
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.4219094073
Short name T456
Test name
Test status
Simulation time 72799542 ps
CPU time 3.33 seconds
Started Jul 19 05:32:12 PM PDT 24
Finished Jul 19 05:32:17 PM PDT 24
Peak memory 208012 kb
Host smart-d2b6ef1b-e08e-465e-aec1-6a3d2d417744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219094073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.4219094073
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.2070728956
Short name T131
Test name
Test status
Simulation time 537395498 ps
CPU time 19.81 seconds
Started Jul 19 05:32:20 PM PDT 24
Finished Jul 19 05:32:40 PM PDT 24
Peak memory 222252 kb
Host smart-d21b7ee4-0ca1-422b-8790-aff081dafdaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070728956 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.2070728956
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.4214152559
Short name T276
Test name
Test status
Simulation time 799699849 ps
CPU time 5.88 seconds
Started Jul 19 05:32:10 PM PDT 24
Finished Jul 19 05:32:16 PM PDT 24
Peak memory 214148 kb
Host smart-7f749c76-e701-410d-81d4-39b11bc551d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214152559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.4214152559
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.1997031390
Short name T597
Test name
Test status
Simulation time 3872003210 ps
CPU time 5.8 seconds
Started Jul 19 05:32:23 PM PDT 24
Finished Jul 19 05:32:29 PM PDT 24
Peak memory 210752 kb
Host smart-1281f07a-af99-45b1-a191-75c239d9b73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997031390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.1997031390
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.939039084
Short name T559
Test name
Test status
Simulation time 13466116 ps
CPU time 0.76 seconds
Started Jul 19 05:32:30 PM PDT 24
Finished Jul 19 05:32:32 PM PDT 24
Peak memory 205856 kb
Host smart-37d5c3a3-7e90-4d39-a6ce-0d19ed4ee2c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939039084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.939039084
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.2497683600
Short name T746
Test name
Test status
Simulation time 165455430 ps
CPU time 7.76 seconds
Started Jul 19 05:32:20 PM PDT 24
Finished Jul 19 05:32:30 PM PDT 24
Peak memory 209932 kb
Host smart-8c2077f4-0e6e-4da9-bf04-becb282fc04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497683600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.2497683600
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.1805973088
Short name T497
Test name
Test status
Simulation time 290905058 ps
CPU time 3.42 seconds
Started Jul 19 05:32:20 PM PDT 24
Finished Jul 19 05:32:24 PM PDT 24
Peak memory 209752 kb
Host smart-a8827aa0-412f-4fed-9083-a30b51b36b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805973088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.1805973088
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.4123963969
Short name T322
Test name
Test status
Simulation time 168043384 ps
CPU time 4.38 seconds
Started Jul 19 05:32:20 PM PDT 24
Finished Jul 19 05:32:25 PM PDT 24
Peak memory 214088 kb
Host smart-3da81e26-b514-48d4-bc9b-574daa95d618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123963969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.4123963969
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.2542685787
Short name T306
Test name
Test status
Simulation time 38991996 ps
CPU time 2.41 seconds
Started Jul 19 05:32:20 PM PDT 24
Finished Jul 19 05:32:24 PM PDT 24
Peak memory 219808 kb
Host smart-7306f47e-5239-48c4-9710-6fae2daab62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542685787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.2542685787
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.3931407643
Short name T221
Test name
Test status
Simulation time 626983576 ps
CPU time 4.86 seconds
Started Jul 19 05:32:21 PM PDT 24
Finished Jul 19 05:32:27 PM PDT 24
Peak memory 222132 kb
Host smart-5189d401-b9c2-4149-8ca4-72c87e85984a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931407643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.3931407643
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.1893177415
Short name T449
Test name
Test status
Simulation time 185676611 ps
CPU time 2.52 seconds
Started Jul 19 05:32:21 PM PDT 24
Finished Jul 19 05:32:25 PM PDT 24
Peak memory 206908 kb
Host smart-a29f5270-34f9-46da-9763-e3625d8e80bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893177415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1893177415
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.2619187454
Short name T482
Test name
Test status
Simulation time 68370674 ps
CPU time 2.69 seconds
Started Jul 19 05:32:17 PM PDT 24
Finished Jul 19 05:32:21 PM PDT 24
Peak memory 208240 kb
Host smart-95c47a23-e012-4202-a097-94e49da6b63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619187454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.2619187454
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.1857943716
Short name T739
Test name
Test status
Simulation time 181234885 ps
CPU time 2.83 seconds
Started Jul 19 05:32:20 PM PDT 24
Finished Jul 19 05:32:24 PM PDT 24
Peak memory 206796 kb
Host smart-871f4794-ff51-4b94-b659-ace4b8711aae
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857943716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.1857943716
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.1225778656
Short name T830
Test name
Test status
Simulation time 57122855 ps
CPU time 3.09 seconds
Started Jul 19 05:32:19 PM PDT 24
Finished Jul 19 05:32:23 PM PDT 24
Peak memory 206616 kb
Host smart-1fcefeaa-0feb-4db5-8dc6-283e8faf4e42
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225778656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.1225778656
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.3231488706
Short name T837
Test name
Test status
Simulation time 257818624 ps
CPU time 3.3 seconds
Started Jul 19 05:32:24 PM PDT 24
Finished Jul 19 05:32:28 PM PDT 24
Peak memory 206724 kb
Host smart-0fd0a1aa-dabb-4dca-b4d9-1b0721e609b0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231488706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.3231488706
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.1626811501
Short name T311
Test name
Test status
Simulation time 32927458 ps
CPU time 1.87 seconds
Started Jul 19 05:32:24 PM PDT 24
Finished Jul 19 05:32:27 PM PDT 24
Peak memory 208968 kb
Host smart-45fab072-03be-4c0a-8ca7-518b9311bf66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626811501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.1626811501
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.3016027771
Short name T679
Test name
Test status
Simulation time 135678057 ps
CPU time 2.93 seconds
Started Jul 19 05:32:18 PM PDT 24
Finished Jul 19 05:32:22 PM PDT 24
Peak memory 208496 kb
Host smart-8554f12e-95d8-4f7f-8722-79647118e47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016027771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.3016027771
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.2015313456
Short name T8
Test name
Test status
Simulation time 204439213 ps
CPU time 8.14 seconds
Started Jul 19 05:32:30 PM PDT 24
Finished Jul 19 05:32:39 PM PDT 24
Peak memory 222264 kb
Host smart-cf118cae-c736-4318-9328-417f70696bf0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015313456 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.2015313456
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.1880308438
Short name T892
Test name
Test status
Simulation time 444803421 ps
CPU time 5.17 seconds
Started Jul 19 05:32:19 PM PDT 24
Finished Jul 19 05:32:25 PM PDT 24
Peak memory 209640 kb
Host smart-866892cf-71ea-41f1-9ccb-0c8d37b118ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880308438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1880308438
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.1596420296
Short name T886
Test name
Test status
Simulation time 40507348 ps
CPU time 1.93 seconds
Started Jul 19 05:32:24 PM PDT 24
Finished Jul 19 05:32:27 PM PDT 24
Peak memory 209440 kb
Host smart-658186b8-9e1c-4aaf-9d88-fcec205bf7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596420296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.1596420296
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.4165756503
Short name T690
Test name
Test status
Simulation time 152920686 ps
CPU time 0.94 seconds
Started Jul 19 05:32:39 PM PDT 24
Finished Jul 19 05:32:43 PM PDT 24
Peak memory 205828 kb
Host smart-4de94dbc-1214-4d62-a6a8-016fd98b37c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165756503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.4165756503
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.3351177722
Short name T421
Test name
Test status
Simulation time 55537725 ps
CPU time 3.63 seconds
Started Jul 19 05:32:30 PM PDT 24
Finished Jul 19 05:32:35 PM PDT 24
Peak memory 214052 kb
Host smart-3b3b2be0-58cc-4851-89ed-fade7258c336
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3351177722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.3351177722
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.2324757502
Short name T513
Test name
Test status
Simulation time 43717237 ps
CPU time 2.76 seconds
Started Jul 19 05:32:29 PM PDT 24
Finished Jul 19 05:32:33 PM PDT 24
Peak memory 208648 kb
Host smart-6a152bfa-5d45-4247-a70c-16d9374385ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324757502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.2324757502
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.173902766
Short name T307
Test name
Test status
Simulation time 134254101 ps
CPU time 2.07 seconds
Started Jul 19 05:32:28 PM PDT 24
Finished Jul 19 05:32:31 PM PDT 24
Peak memory 214020 kb
Host smart-b755c281-d719-492f-9190-1ff4fbc0252f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173902766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.173902766
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.117354350
Short name T790
Test name
Test status
Simulation time 793104949 ps
CPU time 4.39 seconds
Started Jul 19 05:32:31 PM PDT 24
Finished Jul 19 05:32:36 PM PDT 24
Peak memory 211756 kb
Host smart-728e7848-8bbb-4190-8bc6-7525f146e73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117354350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.117354350
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.1177179307
Short name T45
Test name
Test status
Simulation time 80672956 ps
CPU time 3.38 seconds
Started Jul 19 05:32:31 PM PDT 24
Finished Jul 19 05:32:36 PM PDT 24
Peak memory 209544 kb
Host smart-1198cf7b-dc4f-41e8-ab59-ce2ba59b82b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177179307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.1177179307
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.2278089037
Short name T699
Test name
Test status
Simulation time 364906799 ps
CPU time 9.51 seconds
Started Jul 19 05:32:30 PM PDT 24
Finished Jul 19 05:32:40 PM PDT 24
Peak memory 214080 kb
Host smart-ed2322cf-8574-48b8-99b9-6d8f4e3f3bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278089037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.2278089037
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.3090508063
Short name T876
Test name
Test status
Simulation time 37204688 ps
CPU time 2.3 seconds
Started Jul 19 05:32:30 PM PDT 24
Finished Jul 19 05:32:33 PM PDT 24
Peak memory 205860 kb
Host smart-cdf71719-f4c8-47f9-a915-c45a0dbda97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090508063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.3090508063
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.70033381
Short name T748
Test name
Test status
Simulation time 267459925 ps
CPU time 4.89 seconds
Started Jul 19 05:32:30 PM PDT 24
Finished Jul 19 05:32:37 PM PDT 24
Peak memory 208244 kb
Host smart-0d873941-4605-4817-b8b5-871c5f876770
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70033381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.70033381
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.774897269
Short name T614
Test name
Test status
Simulation time 401890522 ps
CPU time 3.71 seconds
Started Jul 19 05:32:32 PM PDT 24
Finished Jul 19 05:32:37 PM PDT 24
Peak memory 206668 kb
Host smart-4659a406-572e-42b0-8554-0b68ac579bf7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774897269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.774897269
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.3413230237
Short name T288
Test name
Test status
Simulation time 124555742 ps
CPU time 4.33 seconds
Started Jul 19 05:32:29 PM PDT 24
Finished Jul 19 05:32:35 PM PDT 24
Peak memory 208284 kb
Host smart-5ae23d9c-30b3-4f9f-a365-802f0b164f8e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413230237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.3413230237
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.4088455249
Short name T891
Test name
Test status
Simulation time 51200783 ps
CPU time 2.1 seconds
Started Jul 19 05:32:28 PM PDT 24
Finished Jul 19 05:32:31 PM PDT 24
Peak memory 209204 kb
Host smart-0f00d532-ba0a-47c4-b0c7-710e2c9a63f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088455249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.4088455249
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.2067418240
Short name T678
Test name
Test status
Simulation time 68040938 ps
CPU time 2.52 seconds
Started Jul 19 05:32:33 PM PDT 24
Finished Jul 19 05:32:37 PM PDT 24
Peak memory 206984 kb
Host smart-3e3036c2-4e73-4634-84dd-f0acf2047ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067418240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.2067418240
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.1622105621
Short name T677
Test name
Test status
Simulation time 8985054666 ps
CPU time 113.01 seconds
Started Jul 19 05:32:28 PM PDT 24
Finished Jul 19 05:34:22 PM PDT 24
Peak memory 217284 kb
Host smart-61bf92da-8dc5-4fc6-9b9e-117506875891
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622105621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.1622105621
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.2646865597
Short name T803
Test name
Test status
Simulation time 90228479 ps
CPU time 3.11 seconds
Started Jul 19 05:32:28 PM PDT 24
Finished Jul 19 05:32:32 PM PDT 24
Peak memory 218192 kb
Host smart-69b93129-37f3-466d-9bfc-44ea1631333f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646865597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2646865597
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.1728205210
Short name T438
Test name
Test status
Simulation time 52930126 ps
CPU time 1.65 seconds
Started Jul 19 05:32:27 PM PDT 24
Finished Jul 19 05:32:30 PM PDT 24
Peak memory 209528 kb
Host smart-8df1a886-4e92-437a-8e2b-6ac38fe233ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728205210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.1728205210
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.1297811540
Short name T633
Test name
Test status
Simulation time 43575850 ps
CPU time 0.73 seconds
Started Jul 19 05:28:38 PM PDT 24
Finished Jul 19 05:28:40 PM PDT 24
Peak memory 205844 kb
Host smart-78306e32-6e98-4111-8e2c-f863c3bb8a48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297811540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.1297811540
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.1250018030
Short name T410
Test name
Test status
Simulation time 60939290 ps
CPU time 4.01 seconds
Started Jul 19 05:28:23 PM PDT 24
Finished Jul 19 05:28:29 PM PDT 24
Peak memory 215180 kb
Host smart-3e025a4b-3f05-4c0a-a2c4-cc5abc912988
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1250018030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.1250018030
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1621994858
Short name T504
Test name
Test status
Simulation time 62786527 ps
CPU time 3.59 seconds
Started Jul 19 05:28:29 PM PDT 24
Finished Jul 19 05:28:35 PM PDT 24
Peak memory 218228 kb
Host smart-8d5d35bb-6c1d-4c92-9335-751a90b7c813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621994858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1621994858
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.4283479136
Short name T645
Test name
Test status
Simulation time 249442076 ps
CPU time 3.25 seconds
Started Jul 19 05:28:28 PM PDT 24
Finished Jul 19 05:28:33 PM PDT 24
Peak memory 209140 kb
Host smart-19435f58-e2ef-4814-8f0f-50e80c5f690c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283479136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.4283479136
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.1646573600
Short name T799
Test name
Test status
Simulation time 293696508 ps
CPU time 3.66 seconds
Started Jul 19 05:28:30 PM PDT 24
Finished Jul 19 05:28:36 PM PDT 24
Peak memory 209296 kb
Host smart-7daec243-1c04-4e57-aef6-20b734fd5861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646573600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.1646573600
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.2011037707
Short name T550
Test name
Test status
Simulation time 307795934 ps
CPU time 3.96 seconds
Started Jul 19 05:28:31 PM PDT 24
Finished Jul 19 05:28:37 PM PDT 24
Peak memory 222140 kb
Host smart-51cb3825-48e8-41e8-9424-11b6c0aab3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011037707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.2011037707
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.408101652
Short name T713
Test name
Test status
Simulation time 181566401 ps
CPU time 4.35 seconds
Started Jul 19 05:28:30 PM PDT 24
Finished Jul 19 05:28:36 PM PDT 24
Peak memory 222144 kb
Host smart-417041a3-32f8-4060-81ef-4c7a9324b622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408101652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.408101652
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.2783288656
Short name T801
Test name
Test status
Simulation time 698561153 ps
CPU time 5.86 seconds
Started Jul 19 05:28:22 PM PDT 24
Finished Jul 19 05:28:29 PM PDT 24
Peak memory 217916 kb
Host smart-01aa2272-5bea-4309-b550-2acecabc0a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783288656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.2783288656
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.2517853738
Short name T731
Test name
Test status
Simulation time 170464034 ps
CPU time 4.06 seconds
Started Jul 19 05:28:29 PM PDT 24
Finished Jul 19 05:28:34 PM PDT 24
Peak memory 206684 kb
Host smart-bcb75d9e-2d90-472d-b9f4-e5fd614b17a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517853738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.2517853738
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.2774755419
Short name T541
Test name
Test status
Simulation time 810346935 ps
CPU time 7.17 seconds
Started Jul 19 05:28:23 PM PDT 24
Finished Jul 19 05:28:32 PM PDT 24
Peak memory 208500 kb
Host smart-994cd165-0846-44f8-ae89-276b75bca9d0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774755419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.2774755419
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.2159073300
Short name T534
Test name
Test status
Simulation time 5086613072 ps
CPU time 18.7 seconds
Started Jul 19 05:28:23 PM PDT 24
Finished Jul 19 05:28:43 PM PDT 24
Peak memory 208956 kb
Host smart-b5e99484-4151-412c-b93d-3b926f70ba3a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159073300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2159073300
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.831243260
Short name T16
Test name
Test status
Simulation time 59088274 ps
CPU time 3.05 seconds
Started Jul 19 05:28:24 PM PDT 24
Finished Jul 19 05:28:28 PM PDT 24
Peak memory 206728 kb
Host smart-468522e8-6c83-47c9-bca7-78a5ac90d3d4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831243260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.831243260
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.2945531271
Short name T700
Test name
Test status
Simulation time 275720661 ps
CPU time 2.92 seconds
Started Jul 19 05:28:29 PM PDT 24
Finished Jul 19 05:28:34 PM PDT 24
Peak memory 215300 kb
Host smart-87d30527-3e81-4cfc-b7e4-8c9173136b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945531271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.2945531271
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.2306707014
Short name T444
Test name
Test status
Simulation time 69479176 ps
CPU time 2.89 seconds
Started Jul 19 05:28:22 PM PDT 24
Finished Jul 19 05:28:26 PM PDT 24
Peak memory 208316 kb
Host smart-3743009c-72f5-4148-976f-881239e5766a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306707014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.2306707014
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.2853158739
Short name T330
Test name
Test status
Simulation time 108228821 ps
CPU time 4.85 seconds
Started Jul 19 05:28:30 PM PDT 24
Finished Jul 19 05:28:37 PM PDT 24
Peak memory 222132 kb
Host smart-6c1b6afa-e80d-42c6-8af2-6798c1380ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853158739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2853158739
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.1185276213
Short name T65
Test name
Test status
Simulation time 83427014 ps
CPU time 3.51 seconds
Started Jul 19 05:28:29 PM PDT 24
Finished Jul 19 05:28:34 PM PDT 24
Peak memory 209808 kb
Host smart-c83bcf5a-37bb-4f09-b8ed-1186926fa193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185276213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1185276213
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.642560834
Short name T487
Test name
Test status
Simulation time 18943682 ps
CPU time 0.8 seconds
Started Jul 19 05:32:39 PM PDT 24
Finished Jul 19 05:32:43 PM PDT 24
Peak memory 205852 kb
Host smart-b841d865-bb65-4047-b934-05162656fc85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642560834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.642560834
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.801894583
Short name T397
Test name
Test status
Simulation time 56927155 ps
CPU time 4 seconds
Started Jul 19 05:32:39 PM PDT 24
Finished Jul 19 05:32:46 PM PDT 24
Peak memory 214148 kb
Host smart-6e545b35-ace8-49f5-804a-af7d0cf3f435
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=801894583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.801894583
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.2236444712
Short name T28
Test name
Test status
Simulation time 113448514 ps
CPU time 3.06 seconds
Started Jul 19 05:32:39 PM PDT 24
Finished Jul 19 05:32:44 PM PDT 24
Peak memory 214412 kb
Host smart-b01191eb-7967-49dd-b8ff-ea5658bc216f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236444712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.2236444712
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.1611102761
Short name T643
Test name
Test status
Simulation time 148992171 ps
CPU time 3.89 seconds
Started Jul 19 05:32:39 PM PDT 24
Finished Jul 19 05:32:46 PM PDT 24
Peak memory 210172 kb
Host smart-718eb866-d522-498a-909e-7cb2089ab3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611102761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.1611102761
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.1757587887
Short name T804
Test name
Test status
Simulation time 205152732 ps
CPU time 3.29 seconds
Started Jul 19 05:32:39 PM PDT 24
Finished Jul 19 05:32:45 PM PDT 24
Peak memory 214032 kb
Host smart-4ed334e2-296e-4e1f-b552-775dd65f954f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757587887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.1757587887
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.3506380739
Short name T774
Test name
Test status
Simulation time 68203640 ps
CPU time 2.64 seconds
Started Jul 19 05:32:40 PM PDT 24
Finished Jul 19 05:32:45 PM PDT 24
Peak memory 214956 kb
Host smart-87bdf4ce-ee6b-4400-a481-26b85acaeae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506380739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.3506380739
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.2462675366
Short name T139
Test name
Test status
Simulation time 286964545 ps
CPU time 4.15 seconds
Started Jul 19 05:32:39 PM PDT 24
Finished Jul 19 05:32:45 PM PDT 24
Peak memory 207224 kb
Host smart-247e0adf-714a-45ec-9d31-684ca0e9efd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462675366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.2462675366
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.962680034
Short name T219
Test name
Test status
Simulation time 1835393424 ps
CPU time 56.18 seconds
Started Jul 19 05:32:39 PM PDT 24
Finished Jul 19 05:33:37 PM PDT 24
Peak memory 208784 kb
Host smart-137e2bbd-1a1d-40ad-ab29-bb268cfa624e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962680034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.962680034
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.3753164870
Short name T674
Test name
Test status
Simulation time 192048167 ps
CPU time 2.94 seconds
Started Jul 19 05:32:39 PM PDT 24
Finished Jul 19 05:32:45 PM PDT 24
Peak memory 206592 kb
Host smart-70c91cfa-aabe-4769-9a00-11d198e3ff9d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753164870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3753164870
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.3505396547
Short name T540
Test name
Test status
Simulation time 1872582204 ps
CPU time 14.75 seconds
Started Jul 19 05:32:38 PM PDT 24
Finished Jul 19 05:32:54 PM PDT 24
Peak memory 208332 kb
Host smart-da4fd700-0f75-452b-82c6-b126026dea21
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505396547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.3505396547
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.854893571
Short name T445
Test name
Test status
Simulation time 51643906 ps
CPU time 1.9 seconds
Started Jul 19 05:32:40 PM PDT 24
Finished Jul 19 05:32:44 PM PDT 24
Peak memory 207240 kb
Host smart-625aaeaa-5855-431b-874b-d0769082cff0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854893571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.854893571
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.3287689880
Short name T414
Test name
Test status
Simulation time 64865421 ps
CPU time 2.32 seconds
Started Jul 19 05:32:40 PM PDT 24
Finished Jul 19 05:32:44 PM PDT 24
Peak memory 215676 kb
Host smart-3485d28e-6d24-49d5-912d-3461a72a1b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287689880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3287689880
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.8931274
Short name T447
Test name
Test status
Simulation time 77563679 ps
CPU time 1.63 seconds
Started Jul 19 05:32:41 PM PDT 24
Finished Jul 19 05:32:44 PM PDT 24
Peak memory 206656 kb
Host smart-b27fe249-1939-46ba-bf1a-08b9d7bd9c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8931274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.8931274
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.2674752448
Short name T290
Test name
Test status
Simulation time 489937455 ps
CPU time 3.9 seconds
Started Jul 19 05:32:39 PM PDT 24
Finished Jul 19 05:32:46 PM PDT 24
Peak memory 218128 kb
Host smart-92be090e-c233-49b7-ae86-b08601f40c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674752448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.2674752448
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.3770342622
Short name T815
Test name
Test status
Simulation time 129234675 ps
CPU time 1.4 seconds
Started Jul 19 05:32:39 PM PDT 24
Finished Jul 19 05:32:43 PM PDT 24
Peak memory 209700 kb
Host smart-8bc81750-8642-418f-848f-90a46f8031ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770342622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3770342622
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.3651487042
Short name T105
Test name
Test status
Simulation time 63048543 ps
CPU time 0.77 seconds
Started Jul 19 05:32:48 PM PDT 24
Finished Jul 19 05:32:50 PM PDT 24
Peak memory 205840 kb
Host smart-80cf1b97-75c4-44a3-a340-65544e4ff22f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651487042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.3651487042
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.3137256241
Short name T225
Test name
Test status
Simulation time 2015472187 ps
CPU time 21.85 seconds
Started Jul 19 05:32:50 PM PDT 24
Finished Jul 19 05:33:13 PM PDT 24
Peak memory 209772 kb
Host smart-05b74a07-8a05-45b8-aa0b-8f105450aa70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137256241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.3137256241
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.3937298898
Short name T887
Test name
Test status
Simulation time 206095654 ps
CPU time 2.55 seconds
Started Jul 19 05:32:39 PM PDT 24
Finished Jul 19 05:32:44 PM PDT 24
Peak memory 209088 kb
Host smart-a3c2519b-f711-44ae-b69c-92a149e736bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937298898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.3937298898
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.3614710121
Short name T250
Test name
Test status
Simulation time 310282523 ps
CPU time 3.7 seconds
Started Jul 19 05:32:39 PM PDT 24
Finished Jul 19 05:32:44 PM PDT 24
Peak memory 214144 kb
Host smart-a4d4f29d-a82d-444b-892d-73f3762597f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614710121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.3614710121
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.729674415
Short name T568
Test name
Test status
Simulation time 434381337 ps
CPU time 3.92 seconds
Started Jul 19 05:32:39 PM PDT 24
Finished Jul 19 05:32:44 PM PDT 24
Peak memory 214096 kb
Host smart-2e8ddfe0-a734-4308-b321-46b05ba8d524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729674415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.729674415
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.1287972484
Short name T548
Test name
Test status
Simulation time 147291623 ps
CPU time 3.09 seconds
Started Jul 19 05:32:39 PM PDT 24
Finished Jul 19 05:32:43 PM PDT 24
Peak memory 209364 kb
Host smart-a1e9c8cd-b2a6-45f0-aa8e-d805951965f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287972484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.1287972484
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.2375475319
Short name T254
Test name
Test status
Simulation time 206084832 ps
CPU time 2.89 seconds
Started Jul 19 05:32:38 PM PDT 24
Finished Jul 19 05:32:42 PM PDT 24
Peak memory 208392 kb
Host smart-9e8adc05-f922-48a0-a4ba-3aa23023f162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375475319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.2375475319
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.543268430
Short name T485
Test name
Test status
Simulation time 97891524 ps
CPU time 3.26 seconds
Started Jul 19 05:32:40 PM PDT 24
Finished Jul 19 05:32:46 PM PDT 24
Peak memory 208192 kb
Host smart-a6347d86-61f4-4236-afd2-7dc0fdcefbc3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543268430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.543268430
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.1551281086
Short name T691
Test name
Test status
Simulation time 438206370 ps
CPU time 5.38 seconds
Started Jul 19 05:32:44 PM PDT 24
Finished Jul 19 05:32:51 PM PDT 24
Peak memory 208616 kb
Host smart-0846f761-46fb-4ab7-9831-9ba558c3cb6a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551281086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.1551281086
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.477566203
Short name T275
Test name
Test status
Simulation time 243303908 ps
CPU time 7.02 seconds
Started Jul 19 05:32:38 PM PDT 24
Finished Jul 19 05:32:47 PM PDT 24
Peak memory 206660 kb
Host smart-8ff03746-ced5-4de5-8ff8-92d209050ba0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477566203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.477566203
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.2682385189
Short name T648
Test name
Test status
Simulation time 184556664 ps
CPU time 2.74 seconds
Started Jul 19 05:32:47 PM PDT 24
Finished Jul 19 05:32:51 PM PDT 24
Peak memory 214104 kb
Host smart-2736f0f5-73c4-41b3-847b-ab760950e880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682385189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.2682385189
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.3924274558
Short name T500
Test name
Test status
Simulation time 422654638 ps
CPU time 3.28 seconds
Started Jul 19 05:32:39 PM PDT 24
Finished Jul 19 05:32:45 PM PDT 24
Peak memory 206516 kb
Host smart-1200f770-6075-4b6b-8f70-9c518c1cbda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924274558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.3924274558
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.1956142576
Short name T820
Test name
Test status
Simulation time 13845753932 ps
CPU time 39.29 seconds
Started Jul 19 05:32:50 PM PDT 24
Finished Jul 19 05:33:30 PM PDT 24
Peak memory 216156 kb
Host smart-7e807f70-feb3-4f5a-b896-82e0f880cc67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956142576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.1956142576
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.981611707
Short name T755
Test name
Test status
Simulation time 470226563 ps
CPU time 5.11 seconds
Started Jul 19 05:32:38 PM PDT 24
Finished Jul 19 05:32:45 PM PDT 24
Peak memory 209684 kb
Host smart-85f34e8d-f670-4068-9804-d3af5640e2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981611707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.981611707
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.1218671198
Short name T465
Test name
Test status
Simulation time 222056797 ps
CPU time 1.31 seconds
Started Jul 19 05:32:53 PM PDT 24
Finished Jul 19 05:32:55 PM PDT 24
Peak memory 209572 kb
Host smart-52a477aa-18a2-4458-8d30-4b92ac65e279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218671198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.1218671198
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.542475083
Short name T450
Test name
Test status
Simulation time 46601580 ps
CPU time 0.89 seconds
Started Jul 19 05:32:48 PM PDT 24
Finished Jul 19 05:32:50 PM PDT 24
Peak memory 205856 kb
Host smart-5519a779-8d52-4b2b-8974-aaa2fadf977e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542475083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.542475083
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.3657119768
Short name T427
Test name
Test status
Simulation time 590698241 ps
CPU time 7.52 seconds
Started Jul 19 05:32:47 PM PDT 24
Finished Jul 19 05:32:56 PM PDT 24
Peak memory 215072 kb
Host smart-cdbbdb65-3cfa-4b47-9268-e1d1598b2c21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3657119768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.3657119768
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.2218547294
Short name T883
Test name
Test status
Simulation time 139244136 ps
CPU time 2.92 seconds
Started Jul 19 05:32:47 PM PDT 24
Finished Jul 19 05:32:51 PM PDT 24
Peak memory 208644 kb
Host smart-21a94642-9527-480f-8fed-c1197ed1fd3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218547294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.2218547294
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.3752985341
Short name T260
Test name
Test status
Simulation time 602498984 ps
CPU time 7.41 seconds
Started Jul 19 05:32:46 PM PDT 24
Finished Jul 19 05:32:55 PM PDT 24
Peak memory 218308 kb
Host smart-db84ef1b-695a-459b-8e53-b22e340e27b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752985341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.3752985341
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.1775285583
Short name T792
Test name
Test status
Simulation time 875269653 ps
CPU time 2.98 seconds
Started Jul 19 05:32:48 PM PDT 24
Finished Jul 19 05:32:53 PM PDT 24
Peak memory 214040 kb
Host smart-b6cd763e-6d6c-47f8-b6b9-9af83253ccbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775285583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.1775285583
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.2342351705
Short name T321
Test name
Test status
Simulation time 132035380 ps
CPU time 2.72 seconds
Started Jul 19 05:32:47 PM PDT 24
Finished Jul 19 05:32:51 PM PDT 24
Peak memory 206796 kb
Host smart-4a2fcf18-5064-45e7-ab87-a08db3717318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342351705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.2342351705
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.2644745204
Short name T877
Test name
Test status
Simulation time 87799739 ps
CPU time 3.53 seconds
Started Jul 19 05:32:47 PM PDT 24
Finished Jul 19 05:32:52 PM PDT 24
Peak memory 208492 kb
Host smart-cb740a69-c9db-48fd-a0b8-9a809ad66b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644745204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.2644745204
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.717027657
Short name T838
Test name
Test status
Simulation time 351073273 ps
CPU time 7.5 seconds
Started Jul 19 05:32:48 PM PDT 24
Finished Jul 19 05:32:57 PM PDT 24
Peak memory 214096 kb
Host smart-4ca4a0a3-738e-483c-b1bd-287171276589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717027657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.717027657
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.4214178757
Short name T507
Test name
Test status
Simulation time 112148338 ps
CPU time 2.41 seconds
Started Jul 19 05:32:46 PM PDT 24
Finished Jul 19 05:32:49 PM PDT 24
Peak memory 206636 kb
Host smart-822a47b8-a07d-4d7d-90a6-e944bed494b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214178757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.4214178757
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.2204091080
Short name T872
Test name
Test status
Simulation time 297806811 ps
CPU time 2.64 seconds
Started Jul 19 05:32:48 PM PDT 24
Finished Jul 19 05:32:52 PM PDT 24
Peak memory 206668 kb
Host smart-97846866-ce7e-44b8-a5b7-9fd56e6b8a8b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204091080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.2204091080
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.3264753343
Short name T610
Test name
Test status
Simulation time 178080249 ps
CPU time 5.66 seconds
Started Jul 19 05:32:49 PM PDT 24
Finished Jul 19 05:32:56 PM PDT 24
Peak memory 207676 kb
Host smart-75b641a4-614a-4530-9e8a-8d24b3216ff8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264753343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3264753343
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.1933387716
Short name T140
Test name
Test status
Simulation time 272179166 ps
CPU time 3.87 seconds
Started Jul 19 05:32:48 PM PDT 24
Finished Jul 19 05:32:53 PM PDT 24
Peak memory 208328 kb
Host smart-1b6486f3-6f52-4dbc-ab35-f0a7567261a3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933387716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.1933387716
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.2040559293
Short name T722
Test name
Test status
Simulation time 582933117 ps
CPU time 4.49 seconds
Started Jul 19 05:32:47 PM PDT 24
Finished Jul 19 05:32:53 PM PDT 24
Peak memory 218024 kb
Host smart-946e2b6e-9090-4fc9-a62f-ccf25dd416b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040559293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2040559293
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.765287934
Short name T601
Test name
Test status
Simulation time 11861512101 ps
CPU time 26.11 seconds
Started Jul 19 05:32:47 PM PDT 24
Finished Jul 19 05:33:14 PM PDT 24
Peak memory 208144 kb
Host smart-4fcdb2cf-b7f7-46f5-878b-d4e072938427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765287934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.765287934
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.1915566512
Short name T856
Test name
Test status
Simulation time 1706743672 ps
CPU time 18.47 seconds
Started Jul 19 05:32:53 PM PDT 24
Finished Jul 19 05:33:12 PM PDT 24
Peak memory 219636 kb
Host smart-64626311-8acb-40e6-812a-88a7041aed97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915566512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.1915566512
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.3530138523
Short name T460
Test name
Test status
Simulation time 3406813231 ps
CPU time 62.57 seconds
Started Jul 19 05:32:46 PM PDT 24
Finished Jul 19 05:33:50 PM PDT 24
Peak memory 208620 kb
Host smart-ec5c3b67-6698-4deb-bb14-49dd181e0a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530138523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.3530138523
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.1942539006
Short name T110
Test name
Test status
Simulation time 84767614 ps
CPU time 1.58 seconds
Started Jul 19 05:32:50 PM PDT 24
Finished Jul 19 05:32:52 PM PDT 24
Peak memory 209388 kb
Host smart-61780740-7942-433e-80cd-09d57ed106ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942539006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.1942539006
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.3232364748
Short name T697
Test name
Test status
Simulation time 11328811 ps
CPU time 0.81 seconds
Started Jul 19 05:32:58 PM PDT 24
Finished Jul 19 05:33:00 PM PDT 24
Peak memory 205876 kb
Host smart-a9c96918-da45-40d2-943c-1ee782c5e32d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232364748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.3232364748
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.3570780031
Short name T302
Test name
Test status
Simulation time 636571759 ps
CPU time 8.55 seconds
Started Jul 19 05:32:56 PM PDT 24
Finished Jul 19 05:33:06 PM PDT 24
Peak memory 214036 kb
Host smart-52ea8b55-e5f8-400c-9090-40204f6d2880
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3570780031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.3570780031
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.482756519
Short name T735
Test name
Test status
Simulation time 258322792 ps
CPU time 7.04 seconds
Started Jul 19 05:32:55 PM PDT 24
Finished Jul 19 05:33:04 PM PDT 24
Peak memory 210788 kb
Host smart-2bb538c4-1c1d-45f2-9e49-a802043bde07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482756519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.482756519
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.1865326615
Short name T359
Test name
Test status
Simulation time 410768271 ps
CPU time 3.74 seconds
Started Jul 19 05:32:58 PM PDT 24
Finished Jul 19 05:33:03 PM PDT 24
Peak memory 214060 kb
Host smart-292dc730-ae04-4a50-a7c2-c2ad709df911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865326615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.1865326615
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.3920939679
Short name T374
Test name
Test status
Simulation time 100826193 ps
CPU time 3.18 seconds
Started Jul 19 05:32:57 PM PDT 24
Finished Jul 19 05:33:02 PM PDT 24
Peak memory 214060 kb
Host smart-3b668490-f6d9-4c83-8d98-b932ad77025c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920939679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.3920939679
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.648482792
Short name T263
Test name
Test status
Simulation time 115491154 ps
CPU time 3.85 seconds
Started Jul 19 05:32:59 PM PDT 24
Finished Jul 19 05:33:04 PM PDT 24
Peak memory 214300 kb
Host smart-38751120-092e-4e13-91dd-8d7233a512b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648482792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.648482792
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.77938096
Short name T789
Test name
Test status
Simulation time 75720584 ps
CPU time 3.52 seconds
Started Jul 19 05:32:56 PM PDT 24
Finished Jul 19 05:33:01 PM PDT 24
Peak memory 214148 kb
Host smart-f8ef2233-95b4-4788-b7c3-78a4925a636c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77938096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.77938096
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.3420237558
Short name T833
Test name
Test status
Simulation time 82006807 ps
CPU time 3.02 seconds
Started Jul 19 05:32:54 PM PDT 24
Finished Jul 19 05:32:58 PM PDT 24
Peak memory 209624 kb
Host smart-90501723-28f2-48e2-aef5-60c85ef5d699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420237558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.3420237558
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.4284124989
Short name T451
Test name
Test status
Simulation time 3724624498 ps
CPU time 53.82 seconds
Started Jul 19 05:32:56 PM PDT 24
Finished Jul 19 05:33:52 PM PDT 24
Peak memory 208756 kb
Host smart-1b29f660-a853-4a24-8f27-db61d4283f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284124989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.4284124989
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.664149686
Short name T582
Test name
Test status
Simulation time 111202973 ps
CPU time 3.58 seconds
Started Jul 19 05:32:56 PM PDT 24
Finished Jul 19 05:33:01 PM PDT 24
Peak memory 206680 kb
Host smart-24df882b-5696-44da-a039-2f4ad00ee5ab
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664149686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.664149686
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.2924947215
Short name T355
Test name
Test status
Simulation time 165188028 ps
CPU time 2.17 seconds
Started Jul 19 05:32:56 PM PDT 24
Finished Jul 19 05:33:00 PM PDT 24
Peak memory 206680 kb
Host smart-b71590d9-17d7-4b3d-80d4-59a92bb4592b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924947215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.2924947215
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.773674216
Short name T401
Test name
Test status
Simulation time 45373576 ps
CPU time 1.89 seconds
Started Jul 19 05:32:57 PM PDT 24
Finished Jul 19 05:33:00 PM PDT 24
Peak memory 207160 kb
Host smart-33907b76-273d-4b59-914b-971912444d0f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773674216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.773674216
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.1601888895
Short name T671
Test name
Test status
Simulation time 103212652 ps
CPU time 2.96 seconds
Started Jul 19 05:32:59 PM PDT 24
Finished Jul 19 05:33:04 PM PDT 24
Peak memory 208280 kb
Host smart-3f3fcad5-6714-4b3d-98d0-8a5ab865d4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601888895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1601888895
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.2764921121
Short name T142
Test name
Test status
Simulation time 483786429 ps
CPU time 11.49 seconds
Started Jul 19 05:32:59 PM PDT 24
Finished Jul 19 05:33:12 PM PDT 24
Peak memory 207860 kb
Host smart-9d333ffb-ec44-4039-b19a-6c9058883aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764921121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.2764921121
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.3038405011
Short name T300
Test name
Test status
Simulation time 697579358 ps
CPU time 16.17 seconds
Started Jul 19 05:32:54 PM PDT 24
Finished Jul 19 05:33:11 PM PDT 24
Peak memory 222252 kb
Host smart-1175115b-a145-45bd-bb13-422ae8e23c98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038405011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.3038405011
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.3392151492
Short name T537
Test name
Test status
Simulation time 195286184 ps
CPU time 6.59 seconds
Started Jul 19 05:32:57 PM PDT 24
Finished Jul 19 05:33:05 PM PDT 24
Peak memory 209300 kb
Host smart-45be8f8e-bd22-4483-ac36-91a4c86e399e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392151492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.3392151492
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.3784870186
Short name T50
Test name
Test status
Simulation time 822495593 ps
CPU time 12.29 seconds
Started Jul 19 05:32:55 PM PDT 24
Finished Jul 19 05:33:09 PM PDT 24
Peak memory 210900 kb
Host smart-15597e14-ed8a-4f0b-a7b2-efef9553b7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784870186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.3784870186
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.2067725035
Short name T481
Test name
Test status
Simulation time 26454377 ps
CPU time 0.96 seconds
Started Jul 19 05:33:02 PM PDT 24
Finished Jul 19 05:33:04 PM PDT 24
Peak memory 205920 kb
Host smart-fedde88a-9933-4971-b167-978136d1d1b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067725035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.2067725035
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.3133709413
Short name T411
Test name
Test status
Simulation time 36686383 ps
CPU time 2.39 seconds
Started Jul 19 05:32:55 PM PDT 24
Finished Jul 19 05:32:59 PM PDT 24
Peak memory 214068 kb
Host smart-811baf2d-a017-4cb2-9e4a-ea99c8438c9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3133709413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3133709413
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.246515964
Short name T669
Test name
Test status
Simulation time 177465619 ps
CPU time 5.29 seconds
Started Jul 19 05:33:07 PM PDT 24
Finished Jul 19 05:33:13 PM PDT 24
Peak memory 222508 kb
Host smart-e2a00ecb-1ec1-46bb-9537-4c081187e676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246515964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.246515964
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.3147399065
Short name T762
Test name
Test status
Simulation time 592259789 ps
CPU time 3.71 seconds
Started Jul 19 05:32:59 PM PDT 24
Finished Jul 19 05:33:04 PM PDT 24
Peak memory 209492 kb
Host smart-33032de2-5859-4fce-b85b-23644ab435b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147399065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.3147399065
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.1243792801
Short name T305
Test name
Test status
Simulation time 123137722 ps
CPU time 3.8 seconds
Started Jul 19 05:33:04 PM PDT 24
Finished Jul 19 05:33:10 PM PDT 24
Peak memory 214108 kb
Host smart-34604a3d-38f2-4530-a4b3-21fa9263e468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243792801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.1243792801
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.1860564743
Short name T388
Test name
Test status
Simulation time 332359455 ps
CPU time 3.53 seconds
Started Jul 19 05:33:04 PM PDT 24
Finished Jul 19 05:33:10 PM PDT 24
Peak memory 214024 kb
Host smart-696ee1fa-86fb-4e28-847a-b02a4c9141dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860564743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.1860564743
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.1304917774
Short name T581
Test name
Test status
Simulation time 408992367 ps
CPU time 5.09 seconds
Started Jul 19 05:32:59 PM PDT 24
Finished Jul 19 05:33:06 PM PDT 24
Peak memory 208760 kb
Host smart-7f86117a-e3d1-401e-98ec-5bc6531594ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304917774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.1304917774
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.3929409113
Short name T285
Test name
Test status
Simulation time 117717267 ps
CPU time 5.59 seconds
Started Jul 19 05:32:55 PM PDT 24
Finished Jul 19 05:33:03 PM PDT 24
Peak memory 217984 kb
Host smart-e2a412d2-0899-4939-8239-3f18d789ece5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929409113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.3929409113
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.739838212
Short name T384
Test name
Test status
Simulation time 114852407 ps
CPU time 3.07 seconds
Started Jul 19 05:32:55 PM PDT 24
Finished Jul 19 05:33:00 PM PDT 24
Peak memory 206676 kb
Host smart-a231eb2a-4837-4daa-a578-fd9fb1b0f6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739838212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.739838212
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.1332695391
Short name T289
Test name
Test status
Simulation time 88384637 ps
CPU time 3.43 seconds
Started Jul 19 05:33:00 PM PDT 24
Finished Jul 19 05:33:04 PM PDT 24
Peak memory 208328 kb
Host smart-219a3690-fc7d-48fc-8256-8ff0dd460c5f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332695391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.1332695391
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.3030309379
Short name T137
Test name
Test status
Simulation time 353563145 ps
CPU time 8.06 seconds
Started Jul 19 05:32:55 PM PDT 24
Finished Jul 19 05:33:05 PM PDT 24
Peak memory 208556 kb
Host smart-07437207-a215-4aa3-90b6-f8fc56d84d1c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030309379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.3030309379
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.3506326877
Short name T667
Test name
Test status
Simulation time 1297402322 ps
CPU time 32.22 seconds
Started Jul 19 05:32:59 PM PDT 24
Finished Jul 19 05:33:33 PM PDT 24
Peak memory 207724 kb
Host smart-84ff8adb-8350-4f21-94b3-caf5f034a11a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506326877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3506326877
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.2907771175
Short name T530
Test name
Test status
Simulation time 135781074 ps
CPU time 3 seconds
Started Jul 19 05:33:05 PM PDT 24
Finished Jul 19 05:33:09 PM PDT 24
Peak memory 207216 kb
Host smart-f1f33436-725e-4e1e-8e4e-80b148218c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907771175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.2907771175
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.363297880
Short name T603
Test name
Test status
Simulation time 139413912 ps
CPU time 4.29 seconds
Started Jul 19 05:32:59 PM PDT 24
Finished Jul 19 05:33:05 PM PDT 24
Peak memory 206396 kb
Host smart-bdd0608b-48dd-41be-8529-bc6b30b7a8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363297880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.363297880
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.3354744403
Short name T196
Test name
Test status
Simulation time 742517375 ps
CPU time 21.82 seconds
Started Jul 19 05:33:06 PM PDT 24
Finished Jul 19 05:33:29 PM PDT 24
Peak memory 222232 kb
Host smart-70ebb04f-0877-42c6-8a20-11caeb653c09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354744403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.3354744403
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3510869340
Short name T604
Test name
Test status
Simulation time 86420846 ps
CPU time 3.02 seconds
Started Jul 19 05:33:04 PM PDT 24
Finished Jul 19 05:33:08 PM PDT 24
Peak memory 207108 kb
Host smart-161f5d0a-ea29-4315-843a-cab8375fb5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510869340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3510869340
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1239920295
Short name T61
Test name
Test status
Simulation time 71262755 ps
CPU time 2.92 seconds
Started Jul 19 05:33:03 PM PDT 24
Finished Jul 19 05:33:07 PM PDT 24
Peak memory 209844 kb
Host smart-8065d9c4-3e33-4ef2-b741-b5a5e79c3cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239920295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1239920295
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.1094832154
Short name T553
Test name
Test status
Simulation time 19185826 ps
CPU time 0.75 seconds
Started Jul 19 05:33:11 PM PDT 24
Finished Jul 19 05:33:13 PM PDT 24
Peak memory 205836 kb
Host smart-cc6053bd-3cb7-4e84-8ca9-3cf99b633783
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094832154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1094832154
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.4020703592
Short name T395
Test name
Test status
Simulation time 34487305 ps
CPU time 3.12 seconds
Started Jul 19 05:33:01 PM PDT 24
Finished Jul 19 05:33:05 PM PDT 24
Peak memory 214052 kb
Host smart-1c48f14a-1b1a-4f8c-a1d0-6e2132f3aaae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4020703592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.4020703592
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.560141526
Short name T854
Test name
Test status
Simulation time 42605523 ps
CPU time 2.04 seconds
Started Jul 19 05:33:05 PM PDT 24
Finished Jul 19 05:33:09 PM PDT 24
Peak memory 207852 kb
Host smart-f5f3c980-97da-4cf4-b869-342172ecf60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560141526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.560141526
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.358019012
Short name T859
Test name
Test status
Simulation time 290734046 ps
CPU time 3.66 seconds
Started Jul 19 05:33:04 PM PDT 24
Finished Jul 19 05:33:10 PM PDT 24
Peak memory 214076 kb
Host smart-55c322df-2ee4-42f2-9bf4-13cc4c6f911a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358019012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.358019012
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.2974867059
Short name T542
Test name
Test status
Simulation time 793964866 ps
CPU time 5.67 seconds
Started Jul 19 05:33:02 PM PDT 24
Finished Jul 19 05:33:09 PM PDT 24
Peak memory 209944 kb
Host smart-b5841e6d-4793-413e-a5f0-34a6bbb67f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974867059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.2974867059
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.2448822921
Short name T686
Test name
Test status
Simulation time 102425543 ps
CPU time 3.02 seconds
Started Jul 19 05:33:04 PM PDT 24
Finished Jul 19 05:33:09 PM PDT 24
Peak memory 208136 kb
Host smart-8ef8e3f7-ac39-4263-ba5a-264e13801f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448822921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2448822921
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.1822275559
Short name T335
Test name
Test status
Simulation time 616849772 ps
CPU time 8.4 seconds
Started Jul 19 05:33:05 PM PDT 24
Finished Jul 19 05:33:15 PM PDT 24
Peak memory 208752 kb
Host smart-29cab9c7-60ae-4e95-956d-0c1264a164aa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822275559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.1822275559
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.629242662
Short name T871
Test name
Test status
Simulation time 41460967 ps
CPU time 2.52 seconds
Started Jul 19 05:33:04 PM PDT 24
Finished Jul 19 05:33:08 PM PDT 24
Peak memory 207036 kb
Host smart-cdb00a40-8a2c-47ff-a78d-99ea021978c2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629242662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.629242662
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.1838913343
Short name T778
Test name
Test status
Simulation time 318190143 ps
CPU time 3.41 seconds
Started Jul 19 05:33:04 PM PDT 24
Finished Jul 19 05:33:09 PM PDT 24
Peak memory 208564 kb
Host smart-468f1c63-bab6-4713-9b53-930aba11a1ac
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838913343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1838913343
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.1964393581
Short name T268
Test name
Test status
Simulation time 142009882 ps
CPU time 3.86 seconds
Started Jul 19 05:33:05 PM PDT 24
Finished Jul 19 05:33:11 PM PDT 24
Peak memory 208792 kb
Host smart-93662a79-3edd-4ce7-91d7-7a2346897151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964393581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.1964393581
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.442923201
Short name T701
Test name
Test status
Simulation time 683172676 ps
CPU time 6.92 seconds
Started Jul 19 05:33:06 PM PDT 24
Finished Jul 19 05:33:14 PM PDT 24
Peak memory 207696 kb
Host smart-211bbb84-60dd-4206-b541-babef0b5ccb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442923201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.442923201
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.219679410
Short name T43
Test name
Test status
Simulation time 1346222434 ps
CPU time 12.79 seconds
Started Jul 19 05:33:11 PM PDT 24
Finished Jul 19 05:33:25 PM PDT 24
Peak memory 222368 kb
Host smart-a92b1f6e-f253-4681-974f-a49253a49302
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219679410 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.219679410
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.2821074283
Short name T358
Test name
Test status
Simulation time 152240257 ps
CPU time 5.3 seconds
Started Jul 19 05:33:01 PM PDT 24
Finished Jul 19 05:33:08 PM PDT 24
Peak memory 209124 kb
Host smart-fdb86b29-a481-417c-836a-cea7c02e2526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821074283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.2821074283
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.3707119334
Short name T745
Test name
Test status
Simulation time 664284908 ps
CPU time 2.65 seconds
Started Jul 19 05:33:13 PM PDT 24
Finished Jul 19 05:33:16 PM PDT 24
Peak memory 210116 kb
Host smart-1145523b-d63f-4bad-8eca-e714be435bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707119334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.3707119334
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3089648868
Short name T539
Test name
Test status
Simulation time 29910052 ps
CPU time 0.92 seconds
Started Jul 19 05:33:23 PM PDT 24
Finished Jul 19 05:33:24 PM PDT 24
Peak memory 205864 kb
Host smart-d0fae57a-3769-450d-a669-bb9b470481c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089648868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3089648868
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.237653488
Short name T721
Test name
Test status
Simulation time 49705066 ps
CPU time 2.7 seconds
Started Jul 19 05:33:11 PM PDT 24
Finished Jul 19 05:33:15 PM PDT 24
Peak memory 222316 kb
Host smart-ceb30178-ac4a-405b-b2b7-fffa2d793a97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=237653488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.237653488
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.1923307845
Short name T36
Test name
Test status
Simulation time 334727915 ps
CPU time 3.33 seconds
Started Jul 19 05:33:11 PM PDT 24
Finished Jul 19 05:33:16 PM PDT 24
Peak memory 218260 kb
Host smart-34304e62-afc6-451c-9b7f-495a4ce78cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923307845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.1923307845
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.3749197302
Short name T655
Test name
Test status
Simulation time 24480593 ps
CPU time 1.3 seconds
Started Jul 19 05:33:09 PM PDT 24
Finished Jul 19 05:33:12 PM PDT 24
Peak memory 207448 kb
Host smart-53f8654a-0960-4912-953f-9e88994cfb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749197302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.3749197302
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.4195322589
Short name T279
Test name
Test status
Simulation time 190964898 ps
CPU time 3.91 seconds
Started Jul 19 05:33:14 PM PDT 24
Finished Jul 19 05:33:19 PM PDT 24
Peak memory 213952 kb
Host smart-cb90bfb5-0a20-4754-b744-dfc11be4484b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195322589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.4195322589
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.3714622960
Short name T894
Test name
Test status
Simulation time 113174691 ps
CPU time 2.87 seconds
Started Jul 19 05:33:09 PM PDT 24
Finished Jul 19 05:33:13 PM PDT 24
Peak memory 214068 kb
Host smart-f68cf128-8611-4869-a2bb-c4afcb269977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714622960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.3714622960
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.3293537476
Short name T577
Test name
Test status
Simulation time 1294509836 ps
CPU time 14.97 seconds
Started Jul 19 05:33:09 PM PDT 24
Finished Jul 19 05:33:25 PM PDT 24
Peak memory 209576 kb
Host smart-bc84eaf3-7b6b-4ea6-a9c9-51c69368ca5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293537476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.3293537476
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.2339546225
Short name T712
Test name
Test status
Simulation time 1927747429 ps
CPU time 45.48 seconds
Started Jul 19 05:33:11 PM PDT 24
Finished Jul 19 05:33:58 PM PDT 24
Peak memory 207728 kb
Host smart-2653ddcf-33da-4ab9-8098-57bb4f62b66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339546225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.2339546225
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.3649849767
Short name T343
Test name
Test status
Simulation time 205646031 ps
CPU time 7.4 seconds
Started Jul 19 05:33:10 PM PDT 24
Finished Jul 19 05:33:19 PM PDT 24
Peak memory 208420 kb
Host smart-4f8fd736-41aa-454d-87c1-4dbfce80485b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649849767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.3649849767
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.268231836
Short name T528
Test name
Test status
Simulation time 548337854 ps
CPU time 7.9 seconds
Started Jul 19 05:33:10 PM PDT 24
Finished Jul 19 05:33:20 PM PDT 24
Peak memory 208636 kb
Host smart-3816a6de-bb2c-4a24-b6fc-206edf2a7d64
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268231836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.268231836
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.2316798597
Short name T617
Test name
Test status
Simulation time 38525742 ps
CPU time 2.32 seconds
Started Jul 19 05:33:09 PM PDT 24
Finished Jul 19 05:33:13 PM PDT 24
Peak memory 207096 kb
Host smart-87be618c-ce36-413c-96e7-95d31849069b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316798597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.2316798597
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.2166376459
Short name T895
Test name
Test status
Simulation time 20644945 ps
CPU time 1.71 seconds
Started Jul 19 05:33:14 PM PDT 24
Finished Jul 19 05:33:17 PM PDT 24
Peak memory 214032 kb
Host smart-3e3667b8-1934-4997-a370-994ea3b33c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166376459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.2166376459
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.1192143107
Short name T458
Test name
Test status
Simulation time 285384806 ps
CPU time 3.03 seconds
Started Jul 19 05:33:15 PM PDT 24
Finished Jul 19 05:33:19 PM PDT 24
Peak memory 208216 kb
Host smart-1b4ac624-8c79-47a0-8fc5-3fc45e88ec05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192143107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.1192143107
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.1486994508
Short name T3
Test name
Test status
Simulation time 8976532093 ps
CPU time 33.11 seconds
Started Jul 19 05:33:14 PM PDT 24
Finished Jul 19 05:33:48 PM PDT 24
Peak memory 214232 kb
Host smart-0f073ef0-79e8-4c7a-b1ea-71b67f501acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486994508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.1486994508
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.1187944238
Short name T114
Test name
Test status
Simulation time 78060470 ps
CPU time 2 seconds
Started Jul 19 05:33:10 PM PDT 24
Finished Jul 19 05:33:14 PM PDT 24
Peak memory 209696 kb
Host smart-83a4193e-bf22-4679-81fb-af013cc292ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187944238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.1187944238
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.188548849
Short name T106
Test name
Test status
Simulation time 17415172 ps
CPU time 1.01 seconds
Started Jul 19 05:33:27 PM PDT 24
Finished Jul 19 05:33:30 PM PDT 24
Peak memory 205912 kb
Host smart-adf1af87-177d-4e45-a569-64ddabdb70db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188548849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.188548849
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.1444218653
Short name T134
Test name
Test status
Simulation time 152532810 ps
CPU time 3.27 seconds
Started Jul 19 05:33:18 PM PDT 24
Finished Jul 19 05:33:22 PM PDT 24
Peak memory 215068 kb
Host smart-dd39b311-f2e8-4daf-9c96-ed25cb486cb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1444218653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1444218653
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.4276306899
Short name T728
Test name
Test status
Simulation time 37001165 ps
CPU time 2.8 seconds
Started Jul 19 05:33:21 PM PDT 24
Finished Jul 19 05:33:24 PM PDT 24
Peak memory 221708 kb
Host smart-7a86caa2-c749-4821-a333-8a9260111acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276306899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.4276306899
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.3318486378
Short name T59
Test name
Test status
Simulation time 71643913 ps
CPU time 1.83 seconds
Started Jul 19 05:33:19 PM PDT 24
Finished Jul 19 05:33:22 PM PDT 24
Peak memory 206944 kb
Host smart-40035605-ee5c-463c-9096-eb66cd449c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318486378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.3318486378
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.864028936
Short name T390
Test name
Test status
Simulation time 3716918189 ps
CPU time 34.37 seconds
Started Jul 19 05:33:20 PM PDT 24
Finished Jul 19 05:33:56 PM PDT 24
Peak memory 214180 kb
Host smart-cb8f6367-ca53-4b31-af47-64ee7f378c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864028936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.864028936
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.1181092663
Short name T750
Test name
Test status
Simulation time 40365574 ps
CPU time 2.61 seconds
Started Jul 19 05:33:21 PM PDT 24
Finished Jul 19 05:33:24 PM PDT 24
Peak memory 220680 kb
Host smart-5eafbd81-9552-4d0c-a10e-5c9c4ca8e2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181092663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.1181092663
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.2717498530
Short name T62
Test name
Test status
Simulation time 92759573 ps
CPU time 4.91 seconds
Started Jul 19 05:33:21 PM PDT 24
Finished Jul 19 05:33:27 PM PDT 24
Peak memory 218996 kb
Host smart-47f9f0b2-61ec-462c-9334-99e2760e963e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717498530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2717498530
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_sideload.2100406997
Short name T366
Test name
Test status
Simulation time 186811606 ps
CPU time 7.24 seconds
Started Jul 19 05:33:22 PM PDT 24
Finished Jul 19 05:33:30 PM PDT 24
Peak memory 206492 kb
Host smart-442c63fe-2c9c-4839-ade1-4856c75eb2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100406997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2100406997
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.358870126
Short name T467
Test name
Test status
Simulation time 550192148 ps
CPU time 19.08 seconds
Started Jul 19 05:33:22 PM PDT 24
Finished Jul 19 05:33:42 PM PDT 24
Peak memory 207776 kb
Host smart-afe58e6b-c6bd-45ea-8aa9-61c5393a8a31
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358870126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.358870126
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.1077324153
Short name T576
Test name
Test status
Simulation time 57652571 ps
CPU time 2.87 seconds
Started Jul 19 05:33:19 PM PDT 24
Finished Jul 19 05:33:23 PM PDT 24
Peak memory 207888 kb
Host smart-c28bd972-d20e-4ed4-bba3-03c260071275
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077324153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.1077324153
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.820599395
Short name T661
Test name
Test status
Simulation time 26395196 ps
CPU time 2.19 seconds
Started Jul 19 05:33:19 PM PDT 24
Finished Jul 19 05:33:23 PM PDT 24
Peak memory 208612 kb
Host smart-630ac81d-1d40-46ff-b859-a8ec5a812cec
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820599395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.820599395
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.3870793307
Short name T428
Test name
Test status
Simulation time 618734242 ps
CPU time 15.29 seconds
Started Jul 19 05:33:20 PM PDT 24
Finished Jul 19 05:33:36 PM PDT 24
Peak memory 209292 kb
Host smart-dd297fe9-5349-46cd-a875-09d3f424749a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870793307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.3870793307
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.2703433608
Short name T205
Test name
Test status
Simulation time 138592652 ps
CPU time 2.35 seconds
Started Jul 19 05:33:22 PM PDT 24
Finished Jul 19 05:33:25 PM PDT 24
Peak memory 205844 kb
Host smart-d5726ea6-3e21-42b5-81a6-14b2646c80b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703433608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.2703433608
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.4111185655
Short name T744
Test name
Test status
Simulation time 536105874 ps
CPU time 15.25 seconds
Started Jul 19 05:33:32 PM PDT 24
Finished Jul 19 05:33:50 PM PDT 24
Peak memory 219784 kb
Host smart-31338bf1-92bb-4ab3-9e65-1d5dd9f65408
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111185655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.4111185655
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.2299154158
Short name T479
Test name
Test status
Simulation time 3881217379 ps
CPU time 60.27 seconds
Started Jul 19 05:33:20 PM PDT 24
Finished Jul 19 05:34:21 PM PDT 24
Peak memory 209656 kb
Host smart-ab7e020a-81bc-42da-96c4-57c9f38d5eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299154158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.2299154158
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1060818965
Short name T906
Test name
Test status
Simulation time 14118121 ps
CPU time 0.89 seconds
Started Jul 19 05:33:27 PM PDT 24
Finished Jul 19 05:33:29 PM PDT 24
Peak memory 205912 kb
Host smart-62d2c400-5b9a-4a13-ae7e-e0c06e0f8f74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060818965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1060818965
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.3556743346
Short name T422
Test name
Test status
Simulation time 51242319 ps
CPU time 3.81 seconds
Started Jul 19 05:33:27 PM PDT 24
Finished Jul 19 05:33:33 PM PDT 24
Peak memory 214560 kb
Host smart-a5e5ce63-a9be-4355-b34b-95863106944b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3556743346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.3556743346
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.418001102
Short name T21
Test name
Test status
Simulation time 231691882 ps
CPU time 2.53 seconds
Started Jul 19 05:33:29 PM PDT 24
Finished Jul 19 05:33:33 PM PDT 24
Peak memory 222556 kb
Host smart-ac6b000c-98cd-460b-be5c-457e24ecfec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418001102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.418001102
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.4009836980
Short name T88
Test name
Test status
Simulation time 171993791 ps
CPU time 4.09 seconds
Started Jul 19 05:33:30 PM PDT 24
Finished Jul 19 05:33:35 PM PDT 24
Peak memory 207044 kb
Host smart-90dc44b6-fc1c-46bd-9fd4-3522a9707ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009836980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.4009836980
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.1285767208
Short name T784
Test name
Test status
Simulation time 1631908214 ps
CPU time 4.75 seconds
Started Jul 19 05:33:31 PM PDT 24
Finished Jul 19 05:33:38 PM PDT 24
Peak memory 215216 kb
Host smart-93afd682-6313-4e6b-b567-a4d32068292a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285767208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.1285767208
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.3111652677
Short name T793
Test name
Test status
Simulation time 153412908 ps
CPU time 4.28 seconds
Started Jul 19 05:33:28 PM PDT 24
Finished Jul 19 05:33:35 PM PDT 24
Peak memory 222164 kb
Host smart-e3842245-bf47-41cb-8c6d-c06d0df655f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111652677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.3111652677
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.3209365158
Short name T864
Test name
Test status
Simulation time 1508942974 ps
CPU time 4.01 seconds
Started Jul 19 05:33:27 PM PDT 24
Finished Jul 19 05:33:34 PM PDT 24
Peak memory 208340 kb
Host smart-6756172b-bfd4-4334-bb0a-3c63e85a91b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209365158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.3209365158
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.3368966873
Short name T501
Test name
Test status
Simulation time 498070621 ps
CPU time 5.76 seconds
Started Jul 19 05:33:28 PM PDT 24
Finished Jul 19 05:33:36 PM PDT 24
Peak memory 206692 kb
Host smart-028cddd7-c3a8-47e6-a5e8-8bcc0fd85f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368966873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.3368966873
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.1566097633
Short name T367
Test name
Test status
Simulation time 3175207078 ps
CPU time 31.78 seconds
Started Jul 19 05:33:33 PM PDT 24
Finished Jul 19 05:34:07 PM PDT 24
Peak memory 208260 kb
Host smart-1d417232-5380-4eb0-98ae-3012ae742979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566097633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.1566097633
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.980881698
Short name T822
Test name
Test status
Simulation time 193171162 ps
CPU time 2.75 seconds
Started Jul 19 05:33:26 PM PDT 24
Finished Jul 19 05:33:30 PM PDT 24
Peak memory 206716 kb
Host smart-17e0774b-5efe-413d-bd49-a83cf8a2ffe6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980881698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.980881698
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.2129901676
Short name T842
Test name
Test status
Simulation time 264038476 ps
CPU time 2.91 seconds
Started Jul 19 05:33:28 PM PDT 24
Finished Jul 19 05:33:33 PM PDT 24
Peak memory 206752 kb
Host smart-7f1626be-dca7-4aa2-816d-62255f5a20db
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129901676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.2129901676
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.2963363259
Short name T111
Test name
Test status
Simulation time 247447282 ps
CPU time 4.8 seconds
Started Jul 19 05:33:26 PM PDT 24
Finished Jul 19 05:33:32 PM PDT 24
Peak memory 208592 kb
Host smart-c47afa9e-8384-46e5-aaae-19ba8a8a7e72
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963363259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.2963363259
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.569301202
Short name T328
Test name
Test status
Simulation time 35358902 ps
CPU time 2.11 seconds
Started Jul 19 05:33:31 PM PDT 24
Finished Jul 19 05:33:35 PM PDT 24
Peak memory 217932 kb
Host smart-74330467-e93c-4fb6-bc33-a400a3daf4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569301202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.569301202
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.2549901068
Short name T622
Test name
Test status
Simulation time 106125401 ps
CPU time 2.9 seconds
Started Jul 19 05:33:26 PM PDT 24
Finished Jul 19 05:33:31 PM PDT 24
Peak memory 208332 kb
Host smart-74b07ea6-8042-4204-9929-45e7078cb5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549901068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.2549901068
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.376604751
Short name T684
Test name
Test status
Simulation time 48412041 ps
CPU time 3.12 seconds
Started Jul 19 05:33:28 PM PDT 24
Finished Jul 19 05:33:33 PM PDT 24
Peak memory 207388 kb
Host smart-7479c767-acda-447c-9ec2-c10866b5b2df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376604751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.376604751
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.3820541439
Short name T759
Test name
Test status
Simulation time 1742333257 ps
CPU time 10.73 seconds
Started Jul 19 05:33:28 PM PDT 24
Finished Jul 19 05:33:41 PM PDT 24
Peak memory 214076 kb
Host smart-28d3712f-c454-4ecb-89c9-d349aaf9c3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820541439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.3820541439
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.117008485
Short name T751
Test name
Test status
Simulation time 2613608795 ps
CPU time 10.14 seconds
Started Jul 19 05:33:26 PM PDT 24
Finished Jul 19 05:33:37 PM PDT 24
Peak memory 210060 kb
Host smart-9e404a44-833f-49ba-811e-13e28dedf089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117008485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.117008485
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.3707955389
Short name T555
Test name
Test status
Simulation time 22405267 ps
CPU time 0.87 seconds
Started Jul 19 05:33:37 PM PDT 24
Finished Jul 19 05:33:39 PM PDT 24
Peak memory 205852 kb
Host smart-92518ceb-846e-4521-bc5d-709d3fe95797
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707955389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.3707955389
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.4153159125
Short name T352
Test name
Test status
Simulation time 437472098 ps
CPU time 6.6 seconds
Started Jul 19 05:33:26 PM PDT 24
Finished Jul 19 05:33:34 PM PDT 24
Peak memory 214148 kb
Host smart-c4fdbc29-4e4c-4a84-9d53-b43a19716231
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4153159125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.4153159125
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.4043035800
Short name T24
Test name
Test status
Simulation time 36465633 ps
CPU time 2.6 seconds
Started Jul 19 05:33:32 PM PDT 24
Finished Jul 19 05:33:37 PM PDT 24
Peak memory 210152 kb
Host smart-3d9d4767-b95d-498d-8f48-280478268873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043035800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.4043035800
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.1130102828
Short name T73
Test name
Test status
Simulation time 202504411 ps
CPU time 1.78 seconds
Started Jul 19 05:33:32 PM PDT 24
Finished Jul 19 05:33:36 PM PDT 24
Peak memory 208476 kb
Host smart-808cb3f5-ca43-44e9-98b1-7fcf9108bfc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130102828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.1130102828
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.2087842148
Short name T377
Test name
Test status
Simulation time 119444329 ps
CPU time 4.66 seconds
Started Jul 19 05:33:28 PM PDT 24
Finished Jul 19 05:33:35 PM PDT 24
Peak memory 222248 kb
Host smart-436c9770-c83e-4835-99cb-af71cd53909f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087842148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.2087842148
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.197665209
Short name T378
Test name
Test status
Simulation time 121794894 ps
CPU time 4.77 seconds
Started Jul 19 05:33:26 PM PDT 24
Finished Jul 19 05:33:32 PM PDT 24
Peak memory 214036 kb
Host smart-3ac5a0e6-2015-475c-b96c-e23d561c3d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197665209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.197665209
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.215581329
Short name T44
Test name
Test status
Simulation time 107292281 ps
CPU time 3.39 seconds
Started Jul 19 05:33:28 PM PDT 24
Finished Jul 19 05:33:33 PM PDT 24
Peak memory 209532 kb
Host smart-ce065ea4-b964-4c85-86fb-b3ecd2b090bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215581329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.215581329
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.3552305892
Short name T459
Test name
Test status
Simulation time 111371120 ps
CPU time 3.84 seconds
Started Jul 19 05:33:28 PM PDT 24
Finished Jul 19 05:33:34 PM PDT 24
Peak memory 214856 kb
Host smart-e0cdce72-ec80-47c8-8237-3541f010e826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552305892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.3552305892
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.1831769562
Short name T708
Test name
Test status
Simulation time 55388941 ps
CPU time 2.72 seconds
Started Jul 19 05:33:28 PM PDT 24
Finished Jul 19 05:33:32 PM PDT 24
Peak memory 208060 kb
Host smart-cf8628c2-2882-4b50-8fda-b845d2e187b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831769562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.1831769562
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.3595071520
Short name T572
Test name
Test status
Simulation time 161135599 ps
CPU time 4.72 seconds
Started Jul 19 05:33:29 PM PDT 24
Finished Jul 19 05:33:35 PM PDT 24
Peak memory 208464 kb
Host smart-898ade4a-a8bd-48cd-87c5-d9ba4d642977
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595071520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.3595071520
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.1524048268
Short name T546
Test name
Test status
Simulation time 32983008 ps
CPU time 2.41 seconds
Started Jul 19 05:33:31 PM PDT 24
Finished Jul 19 05:33:36 PM PDT 24
Peak memory 206548 kb
Host smart-7c09633a-39aa-4e5d-b421-43db219e71ee
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524048268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.1524048268
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.1453818731
Short name T107
Test name
Test status
Simulation time 349993621 ps
CPU time 3.25 seconds
Started Jul 19 05:33:27 PM PDT 24
Finished Jul 19 05:33:31 PM PDT 24
Peak memory 208580 kb
Host smart-fa84e9e7-c3d4-4780-b93a-316cdc4b11c4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453818731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.1453818731
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.2050271034
Short name T503
Test name
Test status
Simulation time 156458812 ps
CPU time 2.84 seconds
Started Jul 19 05:33:28 PM PDT 24
Finished Jul 19 05:33:33 PM PDT 24
Peak memory 215404 kb
Host smart-379c80cf-bb3e-4373-aef7-43ad882bc2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050271034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2050271034
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.2553472808
Short name T475
Test name
Test status
Simulation time 416180272 ps
CPU time 4.15 seconds
Started Jul 19 05:33:26 PM PDT 24
Finished Jul 19 05:33:32 PM PDT 24
Peak memory 208288 kb
Host smart-30aa931b-2b43-40c3-ba1e-9e8f741e86f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553472808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.2553472808
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.733230485
Short name T180
Test name
Test status
Simulation time 2609319496 ps
CPU time 17.77 seconds
Started Jul 19 05:33:34 PM PDT 24
Finished Jul 19 05:33:54 PM PDT 24
Peak memory 222428 kb
Host smart-8f207423-e49f-42d8-b044-f7112dec8917
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733230485 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.733230485
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.2735786546
Short name T787
Test name
Test status
Simulation time 168676921 ps
CPU time 5.43 seconds
Started Jul 19 05:33:30 PM PDT 24
Finished Jul 19 05:33:37 PM PDT 24
Peak memory 207424 kb
Host smart-bc97e144-54b5-4a40-be3a-7865086d730d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735786546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.2735786546
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.2271099678
Short name T658
Test name
Test status
Simulation time 330552885 ps
CPU time 3.77 seconds
Started Jul 19 05:33:34 PM PDT 24
Finished Jul 19 05:33:40 PM PDT 24
Peak memory 209988 kb
Host smart-4fe98326-6818-424d-9716-4cd7938c9955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271099678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.2271099678
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.4289638366
Short name T805
Test name
Test status
Simulation time 22649839 ps
CPU time 0.88 seconds
Started Jul 19 05:29:12 PM PDT 24
Finished Jul 19 05:29:14 PM PDT 24
Peak memory 205876 kb
Host smart-7f66f726-adfd-4a58-8564-d9dba407100e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289638366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.4289638366
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.3752172675
Short name T143
Test name
Test status
Simulation time 33345859 ps
CPU time 2.65 seconds
Started Jul 19 05:28:49 PM PDT 24
Finished Jul 19 05:28:53 PM PDT 24
Peak memory 214084 kb
Host smart-733c68dc-c01c-4374-aa5a-529348ab200c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3752172675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.3752172675
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.3100515643
Short name T9
Test name
Test status
Simulation time 344558947 ps
CPU time 2.65 seconds
Started Jul 19 05:28:54 PM PDT 24
Finished Jul 19 05:28:58 PM PDT 24
Peak memory 209000 kb
Host smart-7615b6a0-911d-4228-b82f-9bc7ee1115b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100515643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.3100515643
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.3831095589
Short name T478
Test name
Test status
Simulation time 455016058 ps
CPU time 4 seconds
Started Jul 19 05:28:45 PM PDT 24
Finished Jul 19 05:28:51 PM PDT 24
Peak memory 208052 kb
Host smart-db4a908e-02ba-4bd7-8d17-f4b17865960a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831095589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.3831095589
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.2798555285
Short name T782
Test name
Test status
Simulation time 145115183 ps
CPU time 3.86 seconds
Started Jul 19 05:28:47 PM PDT 24
Finished Jul 19 05:28:52 PM PDT 24
Peak memory 215192 kb
Host smart-418c8c25-a7d3-4644-8e54-95bffcf64d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798555285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.2798555285
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.2330641130
Short name T375
Test name
Test status
Simulation time 86193987 ps
CPU time 3.27 seconds
Started Jul 19 05:28:44 PM PDT 24
Finished Jul 19 05:28:49 PM PDT 24
Peak memory 222172 kb
Host smart-a80f3bb1-5ee7-4e34-9106-c2159a7ffa7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330641130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.2330641130
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_random.1283489061
Short name T641
Test name
Test status
Simulation time 910036810 ps
CPU time 16.82 seconds
Started Jul 19 05:28:47 PM PDT 24
Finished Jul 19 05:29:05 PM PDT 24
Peak memory 207260 kb
Host smart-917a38ed-699f-456f-bebc-50affcbd2b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283489061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.1283489061
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.1764511304
Short name T14
Test name
Test status
Simulation time 1028296976 ps
CPU time 9.54 seconds
Started Jul 19 05:28:55 PM PDT 24
Finished Jul 19 05:29:05 PM PDT 24
Peak memory 231172 kb
Host smart-a88bf068-1d49-4173-9358-085fe988a47f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764511304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.1764511304
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.803224148
Short name T499
Test name
Test status
Simulation time 75443396 ps
CPU time 3.53 seconds
Started Jul 19 05:28:39 PM PDT 24
Finished Jul 19 05:28:43 PM PDT 24
Peak memory 208528 kb
Host smart-60ce05ae-95cb-419e-8375-c376bccb6e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803224148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.803224148
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.987635255
Short name T573
Test name
Test status
Simulation time 410707055 ps
CPU time 3.51 seconds
Started Jul 19 05:28:47 PM PDT 24
Finished Jul 19 05:28:51 PM PDT 24
Peak memory 206496 kb
Host smart-3aa5fc05-5840-45a4-b764-c3d07d58f4c8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987635255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.987635255
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.4267236936
Short name T741
Test name
Test status
Simulation time 225589992 ps
CPU time 6.04 seconds
Started Jul 19 05:28:38 PM PDT 24
Finished Jul 19 05:28:45 PM PDT 24
Peak memory 208740 kb
Host smart-7b7cc49e-9242-4957-a1d5-77ff9e4fa84b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267236936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.4267236936
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.3170957240
Short name T631
Test name
Test status
Simulation time 178922303 ps
CPU time 3.43 seconds
Started Jul 19 05:28:47 PM PDT 24
Finished Jul 19 05:28:51 PM PDT 24
Peak memory 208116 kb
Host smart-68f2ce07-e15f-4fbe-adba-370086df4119
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170957240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.3170957240
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.147630290
Short name T711
Test name
Test status
Simulation time 561244249 ps
CPU time 4.24 seconds
Started Jul 19 05:28:56 PM PDT 24
Finished Jul 19 05:29:01 PM PDT 24
Peak memory 222332 kb
Host smart-98e3f32d-11e6-498b-aa91-537806ab01eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147630290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.147630290
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.1158015501
Short name T547
Test name
Test status
Simulation time 810672581 ps
CPU time 21 seconds
Started Jul 19 05:28:38 PM PDT 24
Finished Jul 19 05:28:59 PM PDT 24
Peak memory 207608 kb
Host smart-a899c0c8-c3e0-4af9-b012-f1d21c90b3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158015501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.1158015501
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.2136809603
Short name T371
Test name
Test status
Simulation time 858353353 ps
CPU time 31.37 seconds
Started Jul 19 05:28:56 PM PDT 24
Finished Jul 19 05:29:29 PM PDT 24
Peak memory 222220 kb
Host smart-9316f7f5-ea58-4a0b-99f2-f4d285f37622
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136809603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.2136809603
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.3619082807
Short name T647
Test name
Test status
Simulation time 65241290 ps
CPU time 3.51 seconds
Started Jul 19 05:28:46 PM PDT 24
Finished Jul 19 05:28:51 PM PDT 24
Peak memory 207312 kb
Host smart-563599dc-292c-4cbf-b4c7-85260c13ddd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619082807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.3619082807
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.1328143313
Short name T198
Test name
Test status
Simulation time 2189173664 ps
CPU time 7.93 seconds
Started Jul 19 05:28:53 PM PDT 24
Finished Jul 19 05:29:02 PM PDT 24
Peak memory 210040 kb
Host smart-cb596f9a-e2ca-4219-9e05-fd5f0d6bc8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328143313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.1328143313
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.2454037849
Short name T786
Test name
Test status
Simulation time 48057215 ps
CPU time 0.78 seconds
Started Jul 19 05:33:45 PM PDT 24
Finished Jul 19 05:33:47 PM PDT 24
Peak memory 205836 kb
Host smart-c0748796-239d-4aba-b2b6-2de6e91bf751
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454037849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.2454037849
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.202914837
Short name T144
Test name
Test status
Simulation time 438565142 ps
CPU time 13.8 seconds
Started Jul 19 05:33:33 PM PDT 24
Finished Jul 19 05:33:49 PM PDT 24
Peak memory 215144 kb
Host smart-1a0621ff-836d-4206-b60b-b09dcf075dd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=202914837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.202914837
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.1590305968
Short name T807
Test name
Test status
Simulation time 161226462 ps
CPU time 2.47 seconds
Started Jul 19 05:33:36 PM PDT 24
Finished Jul 19 05:33:40 PM PDT 24
Peak memory 222480 kb
Host smart-72dbe679-2f28-4c69-b3f5-5b5ef64098ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590305968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.1590305968
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.3931055103
Short name T387
Test name
Test status
Simulation time 185299197 ps
CPU time 2.26 seconds
Started Jul 19 05:33:34 PM PDT 24
Finished Jul 19 05:33:39 PM PDT 24
Peak memory 208912 kb
Host smart-38af1292-dc8e-4bed-90eb-9f7f231e96fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931055103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3931055103
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.1100102058
Short name T19
Test name
Test status
Simulation time 82013374 ps
CPU time 3.99 seconds
Started Jul 19 05:33:35 PM PDT 24
Finished Jul 19 05:33:41 PM PDT 24
Peak memory 222172 kb
Host smart-e767658d-643f-4a2f-8a48-6dae9d74e70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100102058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.1100102058
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.3546737156
Short name T226
Test name
Test status
Simulation time 217114359 ps
CPU time 3.61 seconds
Started Jul 19 05:33:36 PM PDT 24
Finished Jul 19 05:33:41 PM PDT 24
Peak memory 214860 kb
Host smart-a20f2ef2-0afa-4b9e-b718-1206ab4fa9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546737156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.3546737156
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.2114465953
Short name T816
Test name
Test status
Simulation time 147394599 ps
CPU time 3.23 seconds
Started Jul 19 05:33:42 PM PDT 24
Finished Jul 19 05:33:46 PM PDT 24
Peak memory 214284 kb
Host smart-ee02a904-8f65-42bd-b608-23f9ee84c967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114465953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.2114465953
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.2494465319
Short name T794
Test name
Test status
Simulation time 229419681 ps
CPU time 3.41 seconds
Started Jul 19 05:33:43 PM PDT 24
Finished Jul 19 05:33:47 PM PDT 24
Peak memory 208592 kb
Host smart-4f96af7b-c2d4-4a2b-960d-87a9396e66b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494465319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.2494465319
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.2750542211
Short name T840
Test name
Test status
Simulation time 387312131 ps
CPU time 10.32 seconds
Started Jul 19 05:33:38 PM PDT 24
Finished Jul 19 05:33:49 PM PDT 24
Peak memory 207548 kb
Host smart-fb66e23b-c5d7-4b49-90e3-a5964f64dc95
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750542211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2750542211
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.1086633747
Short name T716
Test name
Test status
Simulation time 71935781 ps
CPU time 3.09 seconds
Started Jul 19 05:33:34 PM PDT 24
Finished Jul 19 05:33:40 PM PDT 24
Peak memory 207728 kb
Host smart-e5c04e75-204f-4ad6-ab2f-78e1bf94e56d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086633747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.1086633747
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1615812204
Short name T707
Test name
Test status
Simulation time 1176853694 ps
CPU time 7.75 seconds
Started Jul 19 05:33:35 PM PDT 24
Finished Jul 19 05:33:45 PM PDT 24
Peak memory 207984 kb
Host smart-8561bb30-552d-4164-841a-081c6eb5b8c4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615812204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1615812204
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.3456777323
Short name T884
Test name
Test status
Simulation time 70685037 ps
CPU time 2.93 seconds
Started Jul 19 05:33:37 PM PDT 24
Finished Jul 19 05:33:41 PM PDT 24
Peak memory 218048 kb
Host smart-27bec36d-82a7-4051-b4f5-a38823051892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456777323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.3456777323
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.2103744914
Short name T440
Test name
Test status
Simulation time 203788377 ps
CPU time 4.4 seconds
Started Jul 19 05:33:38 PM PDT 24
Finished Jul 19 05:33:43 PM PDT 24
Peak memory 207980 kb
Host smart-0fa163e8-4802-4584-b2fa-141ede70366a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103744914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.2103744914
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.2160769441
Short name T646
Test name
Test status
Simulation time 978220761 ps
CPU time 10 seconds
Started Jul 19 05:33:41 PM PDT 24
Finished Jul 19 05:33:52 PM PDT 24
Peak memory 222344 kb
Host smart-db1d9c51-4c3b-48a1-94c8-e429c838bd95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160769441 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.2160769441
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.1835293172
Short name T473
Test name
Test status
Simulation time 618926798 ps
CPU time 5.23 seconds
Started Jul 19 05:33:43 PM PDT 24
Finished Jul 19 05:33:49 PM PDT 24
Peak memory 209232 kb
Host smart-d2b446c5-3721-4a76-ae4d-70993829b0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835293172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1835293172
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.2603840814
Short name T176
Test name
Test status
Simulation time 103117430 ps
CPU time 3.55 seconds
Started Jul 19 05:33:34 PM PDT 24
Finished Jul 19 05:33:40 PM PDT 24
Peak memory 210068 kb
Host smart-4d7ff95e-7d4f-4537-96f2-f8ca1b5ab03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603840814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.2603840814
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.2643667972
Short name T834
Test name
Test status
Simulation time 47989103 ps
CPU time 0.73 seconds
Started Jul 19 05:33:43 PM PDT 24
Finished Jul 19 05:33:45 PM PDT 24
Peak memory 205868 kb
Host smart-98f53a31-5ff6-4c41-8515-61acebec8124
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643667972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2643667972
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.223109318
Short name T621
Test name
Test status
Simulation time 71713051 ps
CPU time 3.25 seconds
Started Jul 19 05:33:42 PM PDT 24
Finished Jul 19 05:33:47 PM PDT 24
Peak memory 222460 kb
Host smart-63cb3957-6194-4f1f-b6b2-ab98a85586d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223109318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.223109318
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.2671500829
Short name T278
Test name
Test status
Simulation time 195337518 ps
CPU time 2.83 seconds
Started Jul 19 05:33:45 PM PDT 24
Finished Jul 19 05:33:49 PM PDT 24
Peak memory 218216 kb
Host smart-541a54a6-0b35-474c-8766-44dc12766850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671500829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.2671500829
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.1793806448
Short name T99
Test name
Test status
Simulation time 712988246 ps
CPU time 19.08 seconds
Started Jul 19 05:33:43 PM PDT 24
Finished Jul 19 05:34:03 PM PDT 24
Peak memory 222252 kb
Host smart-74a0bf27-0584-4ce0-a1b7-3c87c414ccc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793806448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.1793806448
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.256773061
Short name T242
Test name
Test status
Simulation time 233051234 ps
CPU time 4.53 seconds
Started Jul 19 05:33:44 PM PDT 24
Finished Jul 19 05:33:50 PM PDT 24
Peak memory 214032 kb
Host smart-2e01c9e7-e6db-4a42-adea-763ce5c01785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256773061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.256773061
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3533331418
Short name T310
Test name
Test status
Simulation time 263481822 ps
CPU time 6.99 seconds
Started Jul 19 05:33:40 PM PDT 24
Finished Jul 19 05:33:48 PM PDT 24
Peak memory 208496 kb
Host smart-4ebc8e4e-d132-4909-99bf-ff5eb1bbe97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533331418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3533331418
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.1502617044
Short name T890
Test name
Test status
Simulation time 322160920 ps
CPU time 3.26 seconds
Started Jul 19 05:33:42 PM PDT 24
Finished Jul 19 05:33:47 PM PDT 24
Peak memory 206600 kb
Host smart-0c9be67a-263a-4f13-b65f-4f90da75231d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502617044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.1502617044
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.4212361433
Short name T441
Test name
Test status
Simulation time 615495202 ps
CPU time 3.31 seconds
Started Jul 19 05:33:43 PM PDT 24
Finished Jul 19 05:33:48 PM PDT 24
Peak memory 208668 kb
Host smart-9b87ea56-7f07-4f91-a9d9-e44d79d70721
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212361433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.4212361433
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.3405841755
Short name T863
Test name
Test status
Simulation time 222613564 ps
CPU time 3.13 seconds
Started Jul 19 05:33:43 PM PDT 24
Finished Jul 19 05:33:48 PM PDT 24
Peak memory 206848 kb
Host smart-548eef2a-6b28-414b-9c37-f83c681c73cb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405841755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3405841755
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.2635923557
Short name T616
Test name
Test status
Simulation time 216870315 ps
CPU time 2.79 seconds
Started Jul 19 05:33:44 PM PDT 24
Finished Jul 19 05:33:48 PM PDT 24
Peak memory 206520 kb
Host smart-fd177513-b9ae-4b8f-8edd-eddd2a76ae8b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635923557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.2635923557
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.2504217725
Short name T246
Test name
Test status
Simulation time 77863720 ps
CPU time 3.26 seconds
Started Jul 19 05:33:44 PM PDT 24
Finished Jul 19 05:33:49 PM PDT 24
Peak memory 214072 kb
Host smart-5083fa27-2854-446c-bc6d-68cd1083ff0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504217725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.2504217725
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.2854445994
Short name T448
Test name
Test status
Simulation time 238838732 ps
CPU time 2.84 seconds
Started Jul 19 05:33:46 PM PDT 24
Finished Jul 19 05:33:50 PM PDT 24
Peak memory 206584 kb
Host smart-22eaeed0-f0f4-4c82-890b-91125eca5b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854445994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.2854445994
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.4091833074
Short name T797
Test name
Test status
Simulation time 16328622 ps
CPU time 0.74 seconds
Started Jul 19 05:33:40 PM PDT 24
Finished Jul 19 05:33:42 PM PDT 24
Peak memory 205772 kb
Host smart-a8336bf4-7859-4c41-a67f-b1191ff534a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091833074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.4091833074
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.1417347125
Short name T129
Test name
Test status
Simulation time 279734872 ps
CPU time 11.71 seconds
Started Jul 19 05:33:41 PM PDT 24
Finished Jul 19 05:33:54 PM PDT 24
Peak memory 221664 kb
Host smart-4813b46e-5232-4596-83fe-9c7d682abba7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417347125 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.1417347125
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.393280797
Short name T846
Test name
Test status
Simulation time 88464910 ps
CPU time 3.84 seconds
Started Jul 19 05:33:41 PM PDT 24
Finished Jul 19 05:33:46 PM PDT 24
Peak memory 206888 kb
Host smart-1b1db2ea-c30d-409d-b759-e5759096dba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393280797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.393280797
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.3658270385
Short name T772
Test name
Test status
Simulation time 294554303 ps
CPU time 2.82 seconds
Started Jul 19 05:33:44 PM PDT 24
Finished Jul 19 05:33:48 PM PDT 24
Peak memory 209824 kb
Host smart-cc9a2b88-55c9-40e0-bd28-2ab7de4f650c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658270385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.3658270385
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.1710895223
Short name T511
Test name
Test status
Simulation time 12744150 ps
CPU time 0.77 seconds
Started Jul 19 05:33:59 PM PDT 24
Finished Jul 19 05:34:01 PM PDT 24
Peak memory 205996 kb
Host smart-e9331305-b93f-487b-ba71-d976ab8b554b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710895223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1710895223
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.2758801907
Short name T423
Test name
Test status
Simulation time 339996505 ps
CPU time 9.98 seconds
Started Jul 19 05:33:52 PM PDT 24
Finished Jul 19 05:34:03 PM PDT 24
Peak memory 214072 kb
Host smart-2fac246b-b694-4af7-8786-8f8590eed86e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2758801907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2758801907
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.2924922405
Short name T49
Test name
Test status
Simulation time 388734428 ps
CPU time 4.31 seconds
Started Jul 19 05:33:49 PM PDT 24
Finished Jul 19 05:33:55 PM PDT 24
Peak memory 222436 kb
Host smart-0b59a9da-992d-41e9-910a-0777639cfb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924922405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2924922405
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.3924826478
Short name T336
Test name
Test status
Simulation time 512823474 ps
CPU time 3.96 seconds
Started Jul 19 05:33:54 PM PDT 24
Finished Jul 19 05:33:59 PM PDT 24
Peak memory 218140 kb
Host smart-450b318d-ab78-48f1-90c1-25f7a94321fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924826478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.3924826478
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.2741787410
Short name T565
Test name
Test status
Simulation time 157310066 ps
CPU time 4.23 seconds
Started Jul 19 05:33:50 PM PDT 24
Finished Jul 19 05:33:56 PM PDT 24
Peak memory 209436 kb
Host smart-4bd64fd0-27c8-4a0c-9ef2-7c28e24afbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741787410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.2741787410
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.3622996901
Short name T612
Test name
Test status
Simulation time 82702899 ps
CPU time 2.5 seconds
Started Jul 19 05:33:49 PM PDT 24
Finished Jul 19 05:33:53 PM PDT 24
Peak memory 214004 kb
Host smart-7b97bcda-15f4-4ef6-83a1-6b0815cf8523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622996901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.3622996901
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.3502619330
Short name T625
Test name
Test status
Simulation time 137156545 ps
CPU time 3.41 seconds
Started Jul 19 05:33:52 PM PDT 24
Finished Jul 19 05:33:57 PM PDT 24
Peak memory 209284 kb
Host smart-9e31ca87-4868-44c7-a673-16470129e8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502619330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.3502619330
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.1320703996
Short name T273
Test name
Test status
Simulation time 407107318 ps
CPU time 4.16 seconds
Started Jul 19 05:33:51 PM PDT 24
Finished Jul 19 05:33:56 PM PDT 24
Peak memory 207148 kb
Host smart-f2b83d8c-59c2-4585-8da1-c51bbe522f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320703996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.1320703996
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.4220185220
Short name T386
Test name
Test status
Simulation time 41164039 ps
CPU time 1.91 seconds
Started Jul 19 05:33:40 PM PDT 24
Finished Jul 19 05:33:43 PM PDT 24
Peak memory 206576 kb
Host smart-4b0d840c-e340-416d-9cd6-50a5f94dcab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220185220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.4220185220
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.368698518
Short name T726
Test name
Test status
Simulation time 27653799 ps
CPU time 2.15 seconds
Started Jul 19 05:33:43 PM PDT 24
Finished Jul 19 05:33:47 PM PDT 24
Peak memory 208776 kb
Host smart-ac3027a2-36b0-4516-a2e1-cb6cea76fde2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368698518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.368698518
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.1764893914
Short name T900
Test name
Test status
Simulation time 2738070874 ps
CPU time 18.18 seconds
Started Jul 19 05:33:44 PM PDT 24
Finished Jul 19 05:34:04 PM PDT 24
Peak memory 207712 kb
Host smart-c81bbb4b-ab2b-4e8b-b1c0-ed7029eaaa33
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764893914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.1764893914
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.1654882933
Short name T749
Test name
Test status
Simulation time 295033610 ps
CPU time 2.74 seconds
Started Jul 19 05:33:50 PM PDT 24
Finished Jul 19 05:33:54 PM PDT 24
Peak memory 206660 kb
Host smart-a61bb805-6540-46a0-aca6-7e2f370e113f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654882933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.1654882933
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.3965597561
Short name T331
Test name
Test status
Simulation time 101455200 ps
CPU time 2.6 seconds
Started Jul 19 05:33:49 PM PDT 24
Finished Jul 19 05:33:52 PM PDT 24
Peak memory 209564 kb
Host smart-0ea3d24d-77f2-4911-b760-018942e70264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965597561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.3965597561
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.1026701966
Short name T630
Test name
Test status
Simulation time 158011456 ps
CPU time 1.86 seconds
Started Jul 19 05:33:43 PM PDT 24
Finished Jul 19 05:33:46 PM PDT 24
Peak memory 205852 kb
Host smart-b509755f-bedf-4fc3-b750-8788969447e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026701966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.1026701966
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.3713608665
Short name T380
Test name
Test status
Simulation time 8874072935 ps
CPU time 106.44 seconds
Started Jul 19 05:33:51 PM PDT 24
Finished Jul 19 05:35:39 PM PDT 24
Peak memory 222372 kb
Host smart-a17346b7-4f1b-40a0-8a0c-8960073374bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713608665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.3713608665
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.304940317
Short name T191
Test name
Test status
Simulation time 1375826989 ps
CPU time 24.91 seconds
Started Jul 19 05:33:57 PM PDT 24
Finished Jul 19 05:34:22 PM PDT 24
Peak memory 220448 kb
Host smart-7cc373b7-32b8-4edb-8534-7997837ec702
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304940317 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.304940317
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.3429972286
Short name T204
Test name
Test status
Simulation time 54545049 ps
CPU time 2.37 seconds
Started Jul 19 05:33:59 PM PDT 24
Finished Jul 19 05:34:03 PM PDT 24
Peak memory 207396 kb
Host smart-c11f25b1-b3a4-4f39-baa6-ce5ed0c48f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429972286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.3429972286
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.3194368395
Short name T737
Test name
Test status
Simulation time 253561949 ps
CPU time 2.28 seconds
Started Jul 19 05:33:49 PM PDT 24
Finished Jul 19 05:33:52 PM PDT 24
Peak memory 209964 kb
Host smart-fa45e4bb-e6c9-48da-ba46-84f210a62a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194368395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.3194368395
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.3625182125
Short name T435
Test name
Test status
Simulation time 41069018 ps
CPU time 0.94 seconds
Started Jul 19 05:33:58 PM PDT 24
Finished Jul 19 05:34:01 PM PDT 24
Peak memory 205852 kb
Host smart-f8072872-8440-4bfa-ab41-ad4ab3108eca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625182125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.3625182125
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.4213087313
Short name T334
Test name
Test status
Simulation time 2707323576 ps
CPU time 31.47 seconds
Started Jul 19 05:33:50 PM PDT 24
Finished Jul 19 05:34:23 PM PDT 24
Peak memory 214956 kb
Host smart-223ecbcf-eaff-4724-8a63-958a0cc4c824
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4213087313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.4213087313
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.1685248825
Short name T33
Test name
Test status
Simulation time 467069590 ps
CPU time 3.17 seconds
Started Jul 19 05:33:50 PM PDT 24
Finished Jul 19 05:33:55 PM PDT 24
Peak memory 222500 kb
Host smart-da690eb5-954e-4062-8c71-beb664d0e192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685248825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.1685248825
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.1730386081
Short name T357
Test name
Test status
Simulation time 68209818 ps
CPU time 3.32 seconds
Started Jul 19 05:33:50 PM PDT 24
Finished Jul 19 05:33:55 PM PDT 24
Peak memory 214160 kb
Host smart-efca0c25-9ee6-4867-b498-88d315be7eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730386081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.1730386081
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.3395050553
Short name T323
Test name
Test status
Simulation time 404513136 ps
CPU time 5.19 seconds
Started Jul 19 05:33:50 PM PDT 24
Finished Jul 19 05:33:57 PM PDT 24
Peak memory 214040 kb
Host smart-73fe6301-a2a3-4f4e-b0e5-5a997ea9c1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395050553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.3395050553
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.3559087578
Short name T704
Test name
Test status
Simulation time 103284010 ps
CPU time 4.69 seconds
Started Jul 19 05:33:57 PM PDT 24
Finished Jul 19 05:34:04 PM PDT 24
Peak memory 221116 kb
Host smart-7d265eb6-50e9-4936-b5e6-bd5862bc5693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559087578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.3559087578
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.1700068102
Short name T908
Test name
Test status
Simulation time 1003168847 ps
CPU time 4.08 seconds
Started Jul 19 05:33:51 PM PDT 24
Finished Jul 19 05:33:57 PM PDT 24
Peak memory 214136 kb
Host smart-99b8d11d-c685-421c-aea5-f42264a7c505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700068102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.1700068102
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.665126098
Short name T566
Test name
Test status
Simulation time 149232557 ps
CPU time 3.77 seconds
Started Jul 19 05:33:49 PM PDT 24
Finished Jul 19 05:33:55 PM PDT 24
Peak memory 207336 kb
Host smart-c08e1faa-1598-4a49-970a-7c89e4937fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665126098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.665126098
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.67445707
Short name T293
Test name
Test status
Simulation time 649568310 ps
CPU time 5.6 seconds
Started Jul 19 05:33:49 PM PDT 24
Finished Jul 19 05:33:56 PM PDT 24
Peak memory 207608 kb
Host smart-d08705dc-3751-4f97-9a6d-1feee3833cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67445707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.67445707
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.858044977
Short name T589
Test name
Test status
Simulation time 32590255 ps
CPU time 2.4 seconds
Started Jul 19 05:33:51 PM PDT 24
Finished Jul 19 05:33:55 PM PDT 24
Peak memory 206652 kb
Host smart-13964e16-d1a3-438d-a84a-2e134fb125dc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858044977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.858044977
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.111147634
Short name T683
Test name
Test status
Simulation time 35718109 ps
CPU time 1.95 seconds
Started Jul 19 05:33:51 PM PDT 24
Finished Jul 19 05:33:54 PM PDT 24
Peak memory 207124 kb
Host smart-c7f20f20-a98f-4da2-827c-014f9b397d08
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111147634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.111147634
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.1415562834
Short name T518
Test name
Test status
Simulation time 49631950 ps
CPU time 2.8 seconds
Started Jul 19 05:33:50 PM PDT 24
Finished Jul 19 05:33:55 PM PDT 24
Peak memory 206680 kb
Host smart-43b84855-8162-4879-bab9-6d5d90e41c27
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415562834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.1415562834
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.1807973570
Short name T443
Test name
Test status
Simulation time 30284925 ps
CPU time 1.89 seconds
Started Jul 19 05:33:51 PM PDT 24
Finished Jul 19 05:33:55 PM PDT 24
Peak memory 208508 kb
Host smart-12e9e484-c385-4b81-b56b-bc924cf5a349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807973570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1807973570
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.3109278278
Short name T681
Test name
Test status
Simulation time 402959876 ps
CPU time 2.52 seconds
Started Jul 19 05:33:50 PM PDT 24
Finished Jul 19 05:33:54 PM PDT 24
Peak memory 206664 kb
Host smart-ba3f3056-ed0e-4826-8013-e472fda41080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109278278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.3109278278
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.4096663113
Short name T362
Test name
Test status
Simulation time 375611457 ps
CPU time 14.69 seconds
Started Jul 19 05:33:52 PM PDT 24
Finished Jul 19 05:34:08 PM PDT 24
Peak memory 216368 kb
Host smart-864332df-8298-4c59-bcd4-5a9924cff561
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096663113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.4096663113
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.615243380
Short name T775
Test name
Test status
Simulation time 3323408566 ps
CPU time 33.46 seconds
Started Jul 19 05:33:52 PM PDT 24
Finished Jul 19 05:34:27 PM PDT 24
Peak memory 209340 kb
Host smart-00662585-dd40-48f9-ae8c-0646a50ea950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615243380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.615243380
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.2233337998
Short name T132
Test name
Test status
Simulation time 81559203 ps
CPU time 3.21 seconds
Started Jul 19 05:33:48 PM PDT 24
Finished Jul 19 05:33:52 PM PDT 24
Peak memory 209552 kb
Host smart-136e481f-cd18-401f-b23d-67f135a8453d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233337998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.2233337998
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.1251213690
Short name T600
Test name
Test status
Simulation time 22956727 ps
CPU time 0.74 seconds
Started Jul 19 05:34:05 PM PDT 24
Finished Jul 19 05:34:06 PM PDT 24
Peak memory 205832 kb
Host smart-f9f8a5d7-02b3-4454-8380-ead37c200e8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251213690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.1251213690
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.3708817367
Short name T828
Test name
Test status
Simulation time 47800022 ps
CPU time 2.05 seconds
Started Jul 19 05:33:58 PM PDT 24
Finished Jul 19 05:34:02 PM PDT 24
Peak memory 207232 kb
Host smart-38775f8e-ebbf-4ff3-836a-9d180d335198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708817367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.3708817367
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.456818963
Short name T283
Test name
Test status
Simulation time 29172945 ps
CPU time 2 seconds
Started Jul 19 05:34:00 PM PDT 24
Finished Jul 19 05:34:03 PM PDT 24
Peak memory 214084 kb
Host smart-aa969ca1-fb80-4a49-b9a7-3ffc08dc7674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456818963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.456818963
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.110127279
Short name T873
Test name
Test status
Simulation time 482121978 ps
CPU time 4.72 seconds
Started Jul 19 05:33:57 PM PDT 24
Finished Jul 19 05:34:04 PM PDT 24
Peak memory 214100 kb
Host smart-b8918516-5570-4bac-887a-b64766280d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110127279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.110127279
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.3154179295
Short name T66
Test name
Test status
Simulation time 188040153 ps
CPU time 6.54 seconds
Started Jul 19 05:33:58 PM PDT 24
Finished Jul 19 05:34:06 PM PDT 24
Peak memory 214084 kb
Host smart-22fd5bff-fdb7-4ee1-b2dc-db97b2f60931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154179295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.3154179295
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.3113722855
Short name T839
Test name
Test status
Simulation time 288086122 ps
CPU time 6.75 seconds
Started Jul 19 05:34:00 PM PDT 24
Finished Jul 19 05:34:08 PM PDT 24
Peak memory 214084 kb
Host smart-c7fa3345-11c2-408f-91b2-5e20a0952396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113722855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.3113722855
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.1653226749
Short name T476
Test name
Test status
Simulation time 43587608 ps
CPU time 2.57 seconds
Started Jul 19 05:34:02 PM PDT 24
Finished Jul 19 05:34:05 PM PDT 24
Peak memory 208148 kb
Host smart-c2cd4f2c-1390-4048-bb0c-ae6341aaf34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653226749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.1653226749
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.525713580
Short name T557
Test name
Test status
Simulation time 119251256 ps
CPU time 4.49 seconds
Started Jul 19 05:34:01 PM PDT 24
Finished Jul 19 05:34:07 PM PDT 24
Peak memory 206628 kb
Host smart-55c5b0e2-14cb-4d55-be8f-95101dda5b0a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525713580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.525713580
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.2355459813
Short name T523
Test name
Test status
Simulation time 631089158 ps
CPU time 4.9 seconds
Started Jul 19 05:33:58 PM PDT 24
Finished Jul 19 05:34:04 PM PDT 24
Peak memory 207740 kb
Host smart-f210f5dc-9aa8-4b54-ba67-53c5cc73ee6a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355459813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.2355459813
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.22021169
Short name T527
Test name
Test status
Simulation time 48525992 ps
CPU time 2.53 seconds
Started Jul 19 05:33:58 PM PDT 24
Finished Jul 19 05:34:02 PM PDT 24
Peak memory 206560 kb
Host smart-93ae18fb-bff9-4a85-bb6a-fbe0fa292c7a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22021169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.22021169
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.3024209610
Short name T292
Test name
Test status
Simulation time 81037419 ps
CPU time 3.67 seconds
Started Jul 19 05:34:06 PM PDT 24
Finished Jul 19 05:34:10 PM PDT 24
Peak memory 209916 kb
Host smart-dd1b8ec7-e88a-4aa9-9db2-59fa74d96d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024209610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.3024209610
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.1903744756
Short name T858
Test name
Test status
Simulation time 108242698 ps
CPU time 2.73 seconds
Started Jul 19 05:34:00 PM PDT 24
Finished Jul 19 05:34:04 PM PDT 24
Peak memory 208184 kb
Host smart-f308dd57-5223-458a-b216-62cdf72d0ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903744756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.1903744756
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.4241693840
Short name T595
Test name
Test status
Simulation time 1599902170 ps
CPU time 16.6 seconds
Started Jul 19 05:34:07 PM PDT 24
Finished Jul 19 05:34:25 PM PDT 24
Peak memory 214964 kb
Host smart-536dea39-6027-4310-a7c1-2ad1d9f852c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241693840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.4241693840
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.1197255360
Short name T232
Test name
Test status
Simulation time 262744756 ps
CPU time 12.07 seconds
Started Jul 19 05:34:07 PM PDT 24
Finished Jul 19 05:34:21 PM PDT 24
Peak memory 222288 kb
Host smart-4d3a9d1b-6e74-4cb3-a8a0-7eb7336b6265
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197255360 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.1197255360
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.3382730422
Short name T594
Test name
Test status
Simulation time 1305816935 ps
CPU time 7.55 seconds
Started Jul 19 05:33:57 PM PDT 24
Finished Jul 19 05:34:06 PM PDT 24
Peak memory 207888 kb
Host smart-cd1bd6e8-bf23-416a-85da-c0319d9b46d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382730422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.3382730422
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.1020499871
Short name T870
Test name
Test status
Simulation time 58379488 ps
CPU time 1.22 seconds
Started Jul 19 05:34:09 PM PDT 24
Finished Jul 19 05:34:12 PM PDT 24
Peak memory 209612 kb
Host smart-cd0c2991-688c-4e47-be2f-95000a0ce9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020499871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.1020499871
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.1414892588
Short name T670
Test name
Test status
Simulation time 29962296 ps
CPU time 0.8 seconds
Started Jul 19 05:34:16 PM PDT 24
Finished Jul 19 05:34:20 PM PDT 24
Peak memory 205840 kb
Host smart-99a1ce38-dd1e-4db4-b880-806ffee7775b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414892588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.1414892588
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.253355654
Short name T298
Test name
Test status
Simulation time 500059775 ps
CPU time 7.8 seconds
Started Jul 19 05:34:09 PM PDT 24
Finished Jul 19 05:34:19 PM PDT 24
Peak memory 215036 kb
Host smart-c1638f4e-c74e-4fa1-869e-a52ddc631822
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=253355654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.253355654
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.4067550757
Short name T651
Test name
Test status
Simulation time 396868677 ps
CPU time 3.22 seconds
Started Jul 19 05:34:07 PM PDT 24
Finished Jul 19 05:34:12 PM PDT 24
Peak memory 208832 kb
Host smart-61cce7c0-d470-47e6-b399-9ea0308aa309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067550757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.4067550757
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.1393513885
Short name T209
Test name
Test status
Simulation time 3962644264 ps
CPU time 24.72 seconds
Started Jul 19 05:34:07 PM PDT 24
Finished Jul 19 05:34:33 PM PDT 24
Peak memory 218436 kb
Host smart-bdc2400b-ff40-49f2-97b1-09f576aa649a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393513885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.1393513885
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.1011145215
Short name T532
Test name
Test status
Simulation time 63069159 ps
CPU time 2.48 seconds
Started Jul 19 05:34:09 PM PDT 24
Finished Jul 19 05:34:13 PM PDT 24
Peak memory 222172 kb
Host smart-b5cf5ac8-6cd0-4d35-b7a3-0eb65d997d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011145215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1011145215
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.825065108
Short name T233
Test name
Test status
Simulation time 546952085 ps
CPU time 4.19 seconds
Started Jul 19 05:34:09 PM PDT 24
Finished Jul 19 05:34:16 PM PDT 24
Peak memory 219752 kb
Host smart-4a7180da-771c-4a1c-9961-d8e5e9d2314e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825065108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.825065108
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.672498072
Short name T18
Test name
Test status
Simulation time 464747556 ps
CPU time 8.32 seconds
Started Jul 19 05:34:05 PM PDT 24
Finished Jul 19 05:34:14 PM PDT 24
Peak memory 214060 kb
Host smart-45ec9861-6183-46be-8764-dbc8ebeaa236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672498072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.672498072
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.2628855198
Short name T296
Test name
Test status
Simulation time 328145520 ps
CPU time 6.03 seconds
Started Jul 19 05:34:09 PM PDT 24
Finished Jul 19 05:34:17 PM PDT 24
Peak memory 206692 kb
Host smart-c9d77318-12fd-4eb8-9e28-8ff3e49e3ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628855198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.2628855198
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.196756155
Short name T575
Test name
Test status
Simulation time 62900663 ps
CPU time 3.32 seconds
Started Jul 19 05:34:09 PM PDT 24
Finished Jul 19 05:34:14 PM PDT 24
Peak memory 207292 kb
Host smart-43f37625-b6df-444a-a378-84917bfb2ae5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196756155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.196756155
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.1181046331
Short name T216
Test name
Test status
Simulation time 4338941431 ps
CPU time 35.7 seconds
Started Jul 19 05:34:10 PM PDT 24
Finished Jul 19 05:34:47 PM PDT 24
Peak memory 208936 kb
Host smart-5dff3129-85c1-4cce-ae90-e7b570822536
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181046331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.1181046331
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.2455808028
Short name T217
Test name
Test status
Simulation time 976409509 ps
CPU time 4.14 seconds
Started Jul 19 05:34:07 PM PDT 24
Finished Jul 19 05:34:13 PM PDT 24
Peak memory 207708 kb
Host smart-2bdf814f-c276-4821-a63e-c07ab96fde48
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455808028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.2455808028
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.1973055482
Short name T719
Test name
Test status
Simulation time 77208856 ps
CPU time 2.1 seconds
Started Jul 19 05:34:06 PM PDT 24
Finished Jul 19 05:34:10 PM PDT 24
Peak memory 209020 kb
Host smart-9bf6376d-8810-470e-b5f7-545f34202c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973055482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.1973055482
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.1239288173
Short name T155
Test name
Test status
Simulation time 742351812 ps
CPU time 7.26 seconds
Started Jul 19 05:34:08 PM PDT 24
Finished Jul 19 05:34:17 PM PDT 24
Peak memory 208276 kb
Host smart-0c06366d-e088-494a-9699-e08485b9e619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239288173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.1239288173
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.2444902978
Short name T847
Test name
Test status
Simulation time 470791599 ps
CPU time 11.78 seconds
Started Jul 19 05:34:14 PM PDT 24
Finished Jul 19 05:34:28 PM PDT 24
Peak memory 215872 kb
Host smart-356b81ad-9a0e-4dd0-88ff-7765113689c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444902978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2444902978
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3232414797
Short name T761
Test name
Test status
Simulation time 812127840 ps
CPU time 3.52 seconds
Started Jul 19 05:34:06 PM PDT 24
Finished Jul 19 05:34:10 PM PDT 24
Peak memory 207632 kb
Host smart-8162ce08-1612-46a9-b084-6760ca4782b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232414797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3232414797
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.3485797218
Short name T672
Test name
Test status
Simulation time 14390402 ps
CPU time 0.91 seconds
Started Jul 19 05:34:16 PM PDT 24
Finished Jul 19 05:34:19 PM PDT 24
Peak memory 205940 kb
Host smart-23065bff-c26a-41d5-a0db-55767b049d30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485797218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.3485797218
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.1002203450
Short name T299
Test name
Test status
Simulation time 171318069 ps
CPU time 3.3 seconds
Started Jul 19 05:34:17 PM PDT 24
Finished Jul 19 05:34:23 PM PDT 24
Peak memory 214072 kb
Host smart-35909bd7-b800-463d-88e8-9dc3920eff65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1002203450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.1002203450
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.905177796
Short name T291
Test name
Test status
Simulation time 201841435 ps
CPU time 3.02 seconds
Started Jul 19 05:34:17 PM PDT 24
Finished Jul 19 05:34:23 PM PDT 24
Peak memory 221456 kb
Host smart-95ce4030-53a5-4230-8e4a-a45504ed0003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905177796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.905177796
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.2360017307
Short name T868
Test name
Test status
Simulation time 367355722 ps
CPU time 3.79 seconds
Started Jul 19 05:34:15 PM PDT 24
Finished Jul 19 05:34:21 PM PDT 24
Peak memory 214060 kb
Host smart-1284cdf0-852e-4ca7-a002-296dd222e9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360017307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.2360017307
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.3336955563
Short name T104
Test name
Test status
Simulation time 81216618 ps
CPU time 2.97 seconds
Started Jul 19 05:34:15 PM PDT 24
Finished Jul 19 05:34:20 PM PDT 24
Peak memory 221568 kb
Host smart-5511a895-4b54-4b4c-98c8-5dbd4b63e188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336955563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.3336955563
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.4277964081
Short name T848
Test name
Test status
Simulation time 88107496 ps
CPU time 2.7 seconds
Started Jul 19 05:34:15 PM PDT 24
Finished Jul 19 05:34:20 PM PDT 24
Peak memory 214068 kb
Host smart-1b311975-f559-45f3-9684-72fd2b588356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277964081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.4277964081
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.3748737004
Short name T200
Test name
Test status
Simulation time 45998865 ps
CPU time 3.21 seconds
Started Jul 19 05:34:17 PM PDT 24
Finished Jul 19 05:34:24 PM PDT 24
Peak memory 218000 kb
Host smart-c7822dd3-9b0a-49e5-b3bb-2002dadd466b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748737004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.3748737004
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.1293861228
Short name T265
Test name
Test status
Simulation time 587304831 ps
CPU time 4.98 seconds
Started Jul 19 05:34:15 PM PDT 24
Finished Jul 19 05:34:23 PM PDT 24
Peak memory 208448 kb
Host smart-5232283f-de07-4464-ac36-11ed2aa24c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293861228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.1293861228
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.1465748871
Short name T813
Test name
Test status
Simulation time 255860886 ps
CPU time 2.95 seconds
Started Jul 19 05:34:14 PM PDT 24
Finished Jul 19 05:34:19 PM PDT 24
Peak memory 206776 kb
Host smart-db5a96a2-faa4-41c6-a16f-f06c9dda3b2c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465748871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.1465748871
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.2312315942
Short name T494
Test name
Test status
Simulation time 585818916 ps
CPU time 13.96 seconds
Started Jul 19 05:34:14 PM PDT 24
Finished Jul 19 05:34:30 PM PDT 24
Peak memory 207700 kb
Host smart-f4691d75-58dc-405d-9fa0-c33394459c6f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312315942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.2312315942
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.448951573
Short name T516
Test name
Test status
Simulation time 184528633 ps
CPU time 2.54 seconds
Started Jul 19 05:34:12 PM PDT 24
Finished Jul 19 05:34:16 PM PDT 24
Peak memory 206744 kb
Host smart-5f8e7172-0849-43ed-8e3a-b0fcdc37ec83
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448951573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.448951573
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.20512062
Short name T635
Test name
Test status
Simulation time 663504584 ps
CPU time 3.05 seconds
Started Jul 19 05:34:13 PM PDT 24
Finished Jul 19 05:34:17 PM PDT 24
Peak memory 208952 kb
Host smart-24816e3d-92a7-4e29-a67c-bc47c0a40c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20512062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.20512062
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.971655100
Short name T452
Test name
Test status
Simulation time 688241191 ps
CPU time 2.64 seconds
Started Jul 19 05:34:17 PM PDT 24
Finished Jul 19 05:34:23 PM PDT 24
Peak memory 206544 kb
Host smart-25f02fff-98df-41b0-830f-74c9eb5b3c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971655100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.971655100
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.1066888963
Short name T569
Test name
Test status
Simulation time 286846655 ps
CPU time 3.89 seconds
Started Jul 19 05:34:14 PM PDT 24
Finished Jul 19 05:34:20 PM PDT 24
Peak memory 208328 kb
Host smart-a717bf58-3738-4b4c-b5e8-89efc3d64dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066888963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.1066888963
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.1404436606
Short name T491
Test name
Test status
Simulation time 87176901 ps
CPU time 2.73 seconds
Started Jul 19 05:34:16 PM PDT 24
Finished Jul 19 05:34:22 PM PDT 24
Peak memory 210144 kb
Host smart-2cf91e47-5957-4289-a9c8-250ff1326aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404436606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1404436606
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.4162573304
Short name T800
Test name
Test status
Simulation time 46342472 ps
CPU time 0.79 seconds
Started Jul 19 05:34:23 PM PDT 24
Finished Jul 19 05:34:27 PM PDT 24
Peak memory 205856 kb
Host smart-8efd5fb7-b748-4695-b4f4-a63ca84578d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162573304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.4162573304
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.3265089265
Short name T446
Test name
Test status
Simulation time 107195463 ps
CPU time 2.07 seconds
Started Jul 19 05:34:13 PM PDT 24
Finished Jul 19 05:34:16 PM PDT 24
Peak memory 215884 kb
Host smart-a76f125d-2d15-4edf-a7f3-4bf3b5700180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265089265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3265089265
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.2836067642
Short name T814
Test name
Test status
Simulation time 47813913 ps
CPU time 1.87 seconds
Started Jul 19 05:34:15 PM PDT 24
Finished Jul 19 05:34:19 PM PDT 24
Peak memory 214068 kb
Host smart-356b1350-9de0-4f1e-b0c4-d5015d48e0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836067642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.2836067642
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.101797559
Short name T85
Test name
Test status
Simulation time 69909219 ps
CPU time 3.22 seconds
Started Jul 19 05:34:14 PM PDT 24
Finished Jul 19 05:34:19 PM PDT 24
Peak memory 215344 kb
Host smart-1897a6d2-bdfe-4893-81ef-d2bbd72d1466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101797559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.101797559
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.583243224
Short name T698
Test name
Test status
Simulation time 241981458 ps
CPU time 3.39 seconds
Started Jul 19 05:34:18 PM PDT 24
Finished Jul 19 05:34:26 PM PDT 24
Peak memory 214052 kb
Host smart-d617ad46-d510-4a56-8e60-157dc5a7b21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583243224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.583243224
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.1734508429
Short name T42
Test name
Test status
Simulation time 1072717088 ps
CPU time 7.88 seconds
Started Jul 19 05:34:18 PM PDT 24
Finished Jul 19 05:34:31 PM PDT 24
Peak memory 209364 kb
Host smart-9e971c2f-3ccd-4c25-b775-3c481991a897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734508429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1734508429
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.3497238514
Short name T544
Test name
Test status
Simulation time 130161010 ps
CPU time 2.56 seconds
Started Jul 19 05:34:13 PM PDT 24
Finished Jul 19 05:34:17 PM PDT 24
Peak memory 207060 kb
Host smart-903fc7e9-b8d8-4f74-ae24-faedc81beb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497238514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.3497238514
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.673553327
Short name T488
Test name
Test status
Simulation time 103756312 ps
CPU time 3.05 seconds
Started Jul 19 05:34:19 PM PDT 24
Finished Jul 19 05:34:26 PM PDT 24
Peak memory 208592 kb
Host smart-52b6bcfe-3064-4108-829a-684304e1d3e0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673553327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.673553327
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.344384942
Short name T855
Test name
Test status
Simulation time 50352756 ps
CPU time 2.79 seconds
Started Jul 19 05:34:15 PM PDT 24
Finished Jul 19 05:34:21 PM PDT 24
Peak memory 206840 kb
Host smart-914a9c54-6a29-402c-91f6-d717df951bfc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344384942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.344384942
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.2495067519
Short name T736
Test name
Test status
Simulation time 1582145504 ps
CPU time 42.95 seconds
Started Jul 19 05:34:19 PM PDT 24
Finished Jul 19 05:35:07 PM PDT 24
Peak memory 208308 kb
Host smart-d28abd21-ed0b-4d3f-ab62-6bd4690e8b24
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495067519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2495067519
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.3068515666
Short name T201
Test name
Test status
Simulation time 2002505253 ps
CPU time 12.23 seconds
Started Jul 19 05:34:16 PM PDT 24
Finished Jul 19 05:34:31 PM PDT 24
Peak memory 208252 kb
Host smart-9bb27ee1-7287-4c70-baf7-7cf892158639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068515666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.3068515666
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.1032045634
Short name T882
Test name
Test status
Simulation time 4219541170 ps
CPU time 22.19 seconds
Started Jul 19 05:34:19 PM PDT 24
Finished Jul 19 05:34:45 PM PDT 24
Peak memory 208344 kb
Host smart-581f5de1-906a-4053-ba3a-3d83d661cb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032045634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.1032045634
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.2493457777
Short name T682
Test name
Test status
Simulation time 2744198949 ps
CPU time 65.88 seconds
Started Jul 19 05:34:25 PM PDT 24
Finished Jul 19 05:35:33 PM PDT 24
Peak memory 222304 kb
Host smart-6c22de3e-8209-4334-b1bc-ecf8642df181
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493457777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.2493457777
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.821761314
Short name T356
Test name
Test status
Simulation time 147333201 ps
CPU time 3.77 seconds
Started Jul 19 05:34:14 PM PDT 24
Finished Jul 19 05:34:19 PM PDT 24
Peak memory 214092 kb
Host smart-50b69d00-bdd4-45e4-9f68-fd1d3b9f9a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821761314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.821761314
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2727368802
Short name T40
Test name
Test status
Simulation time 327893388 ps
CPU time 2.68 seconds
Started Jul 19 05:34:23 PM PDT 24
Finished Jul 19 05:34:30 PM PDT 24
Peak memory 210056 kb
Host smart-f320a48a-deae-4d95-9fc2-df16bf4c894e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727368802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2727368802
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.2905947934
Short name T788
Test name
Test status
Simulation time 33968750 ps
CPU time 0.82 seconds
Started Jul 19 05:34:24 PM PDT 24
Finished Jul 19 05:34:28 PM PDT 24
Peak memory 205860 kb
Host smart-c63d8da3-3b2c-4400-a2bd-d34ec42b601f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905947934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2905947934
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.717213069
Short name T763
Test name
Test status
Simulation time 61025611 ps
CPU time 2.52 seconds
Started Jul 19 05:34:30 PM PDT 24
Finished Jul 19 05:34:33 PM PDT 24
Peak memory 207692 kb
Host smart-d302cb91-f249-4b4b-ba6e-a68bf3bf1c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717213069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.717213069
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.62084246
Short name T25
Test name
Test status
Simulation time 1347701774 ps
CPU time 29.87 seconds
Started Jul 19 05:34:30 PM PDT 24
Finished Jul 19 05:35:00 PM PDT 24
Peak memory 222132 kb
Host smart-aebf5b4f-6cf3-4b8a-8411-1f8fa5874878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62084246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.62084246
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.1179226083
Short name T785
Test name
Test status
Simulation time 56962882 ps
CPU time 2.45 seconds
Started Jul 19 05:34:24 PM PDT 24
Finished Jul 19 05:34:30 PM PDT 24
Peak memory 220696 kb
Host smart-b1f04fa2-4b6e-4455-be13-2aa2657aef41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179226083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.1179226083
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.3570770449
Short name T515
Test name
Test status
Simulation time 292255541 ps
CPU time 3.2 seconds
Started Jul 19 05:34:30 PM PDT 24
Finished Jul 19 05:34:34 PM PDT 24
Peak memory 218148 kb
Host smart-6e453bc7-ec59-4d85-a703-7c4bbec998a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570770449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.3570770449
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.3393951157
Short name T742
Test name
Test status
Simulation time 235467673 ps
CPU time 3.58 seconds
Started Jul 19 05:34:23 PM PDT 24
Finished Jul 19 05:34:30 PM PDT 24
Peak memory 207536 kb
Host smart-1fbe051f-5b54-4870-a553-a25a01ef26df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393951157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3393951157
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.1848363129
Short name T270
Test name
Test status
Simulation time 426333487 ps
CPU time 6.4 seconds
Started Jul 19 05:34:30 PM PDT 24
Finished Jul 19 05:34:37 PM PDT 24
Peak memory 208472 kb
Host smart-2abde58a-eb5b-416f-81a1-320a415d14df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848363129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1848363129
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1657323287
Short name T897
Test name
Test status
Simulation time 214012588 ps
CPU time 3 seconds
Started Jul 19 05:34:21 PM PDT 24
Finished Jul 19 05:34:28 PM PDT 24
Peak memory 206872 kb
Host smart-73df9c52-75b4-47ad-9032-4467b4d9a41d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657323287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1657323287
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.2231230758
Short name T844
Test name
Test status
Simulation time 219653600 ps
CPU time 6.15 seconds
Started Jul 19 05:34:23 PM PDT 24
Finished Jul 19 05:34:33 PM PDT 24
Peak memory 208284 kb
Host smart-bf9ec327-a020-41df-aae2-f834162c98d3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231230758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.2231230758
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3225900727
Short name T554
Test name
Test status
Simulation time 335709446 ps
CPU time 2.75 seconds
Started Jul 19 05:34:24 PM PDT 24
Finished Jul 19 05:34:30 PM PDT 24
Peak memory 208452 kb
Host smart-210c850c-1ddd-4f5a-bd11-5f444f19460f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225900727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3225900727
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.4207450452
Short name T490
Test name
Test status
Simulation time 78674004 ps
CPU time 2.68 seconds
Started Jul 19 05:34:24 PM PDT 24
Finished Jul 19 05:34:30 PM PDT 24
Peak memory 208440 kb
Host smart-f8f1e8d6-fcbb-43fd-a582-14f0061ecefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207450452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.4207450452
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.4085871443
Short name T650
Test name
Test status
Simulation time 1109545905 ps
CPU time 3.54 seconds
Started Jul 19 05:34:23 PM PDT 24
Finished Jul 19 05:34:30 PM PDT 24
Peak memory 208600 kb
Host smart-f95445e7-76ce-412e-9f05-ce4314c3ffb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085871443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.4085871443
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.696441166
Short name T192
Test name
Test status
Simulation time 315627522 ps
CPU time 11.93 seconds
Started Jul 19 05:34:24 PM PDT 24
Finished Jul 19 05:34:39 PM PDT 24
Peak memory 222296 kb
Host smart-c81daa27-7ece-448b-b239-caa0fd48abe4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696441166 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.696441166
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.774666057
Short name T687
Test name
Test status
Simulation time 393346477 ps
CPU time 4.87 seconds
Started Jul 19 05:34:23 PM PDT 24
Finished Jul 19 05:34:31 PM PDT 24
Peak memory 214036 kb
Host smart-90112777-1559-4736-ad4a-8845222b192c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774666057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.774666057
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.810813845
Short name T536
Test name
Test status
Simulation time 124525389 ps
CPU time 4.49 seconds
Started Jul 19 05:34:24 PM PDT 24
Finished Jul 19 05:34:32 PM PDT 24
Peak memory 209828 kb
Host smart-f95acf0f-b543-4164-9d1f-42b440c0f6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810813845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.810813845
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.1044741347
Short name T430
Test name
Test status
Simulation time 37461195 ps
CPU time 1.04 seconds
Started Jul 19 05:34:37 PM PDT 24
Finished Jul 19 05:34:54 PM PDT 24
Peak memory 205900 kb
Host smart-d20939c6-a150-482b-bd77-6ce06ebd3b73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044741347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.1044741347
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.2068698596
Short name T418
Test name
Test status
Simulation time 1502381821 ps
CPU time 39.93 seconds
Started Jul 19 05:34:36 PM PDT 24
Finished Jul 19 05:35:29 PM PDT 24
Peak memory 214432 kb
Host smart-4885f6c5-4486-414e-a2fe-fad24396c200
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2068698596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.2068698596
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.2344084530
Short name T229
Test name
Test status
Simulation time 104972439 ps
CPU time 4.86 seconds
Started Jul 19 05:34:38 PM PDT 24
Finished Jul 19 05:35:08 PM PDT 24
Peak memory 209220 kb
Host smart-6637e401-e995-4479-b159-5809431a2386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344084530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.2344084530
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.1644255048
Short name T347
Test name
Test status
Simulation time 2771602115 ps
CPU time 18.2 seconds
Started Jul 19 05:34:35 PM PDT 24
Finished Jul 19 05:34:58 PM PDT 24
Peak memory 214184 kb
Host smart-5e7abd6f-67c5-442d-bdac-1ff94d9aa117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644255048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1644255048
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.67425597
Short name T282
Test name
Test status
Simulation time 96996500 ps
CPU time 2.41 seconds
Started Jul 19 05:34:37 PM PDT 24
Finished Jul 19 05:34:53 PM PDT 24
Peak memory 214072 kb
Host smart-6f4d91a9-9dab-4c79-a8bd-d60facbceea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67425597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.67425597
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.3574032787
Short name T809
Test name
Test status
Simulation time 43007931 ps
CPU time 2.66 seconds
Started Jul 19 05:34:36 PM PDT 24
Finished Jul 19 05:34:53 PM PDT 24
Peak memory 220864 kb
Host smart-7173a706-bce0-4ca5-8f60-e8f4f079dfa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574032787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.3574032787
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.466025839
Short name T228
Test name
Test status
Simulation time 239882497 ps
CPU time 4.05 seconds
Started Jul 19 05:34:35 PM PDT 24
Finished Jul 19 05:34:44 PM PDT 24
Peak memory 216296 kb
Host smart-fb12af16-f006-41ac-bb35-0f5329c0adc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466025839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.466025839
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.4129802549
Short name T843
Test name
Test status
Simulation time 203793573 ps
CPU time 5.14 seconds
Started Jul 19 05:34:36 PM PDT 24
Finished Jul 19 05:34:48 PM PDT 24
Peak memory 207812 kb
Host smart-cedc323b-8fce-44ce-b912-7f4f31d19387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129802549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.4129802549
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.694203558
Short name T738
Test name
Test status
Simulation time 264734342 ps
CPU time 4.03 seconds
Started Jul 19 05:34:23 PM PDT 24
Finished Jul 19 05:34:31 PM PDT 24
Peak memory 208456 kb
Host smart-fae2b655-68b7-4474-ba93-915347caad0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694203558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.694203558
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.626236633
Short name T332
Test name
Test status
Simulation time 37315838 ps
CPU time 1.76 seconds
Started Jul 19 05:34:36 PM PDT 24
Finished Jul 19 05:34:47 PM PDT 24
Peak memory 206684 kb
Host smart-e8e2a79a-5001-4da2-a4fa-da81665b15a4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626236633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.626236633
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.4079952236
Short name T538
Test name
Test status
Simulation time 3230307121 ps
CPU time 31.31 seconds
Started Jul 19 05:34:23 PM PDT 24
Finished Jul 19 05:34:57 PM PDT 24
Peak memory 208568 kb
Host smart-56d2ed1d-6a26-44a5-a162-d5173c1ff367
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079952236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.4079952236
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.4014962236
Short name T463
Test name
Test status
Simulation time 277988703 ps
CPU time 3.35 seconds
Started Jul 19 05:34:37 PM PDT 24
Finished Jul 19 05:35:01 PM PDT 24
Peak memory 208600 kb
Host smart-aa8cfdc8-e48b-4ff0-ade9-5d42c9b5e9dc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014962236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.4014962236
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.673943845
Short name T407
Test name
Test status
Simulation time 1110638102 ps
CPU time 2.73 seconds
Started Jul 19 05:34:36 PM PDT 24
Finished Jul 19 05:34:52 PM PDT 24
Peak memory 208992 kb
Host smart-86cc8f36-0ef2-4ad6-97f5-5c61752a6666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673943845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.673943845
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.1380189160
Short name T706
Test name
Test status
Simulation time 192627659 ps
CPU time 3.05 seconds
Started Jul 19 05:34:23 PM PDT 24
Finished Jul 19 05:34:30 PM PDT 24
Peak memory 208120 kb
Host smart-77fd7734-df4b-4e03-a7f6-68a58e1287c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380189160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.1380189160
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.1508435699
Short name T241
Test name
Test status
Simulation time 639760239 ps
CPU time 21.64 seconds
Started Jul 19 05:34:37 PM PDT 24
Finished Jul 19 05:35:17 PM PDT 24
Peak memory 222300 kb
Host smart-7720a603-0c5b-4eb8-8784-a3e558509099
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508435699 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.1508435699
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.2226169492
Short name T454
Test name
Test status
Simulation time 281337985 ps
CPU time 7.25 seconds
Started Jul 19 05:34:36 PM PDT 24
Finished Jul 19 05:34:52 PM PDT 24
Peak memory 209140 kb
Host smart-33fe69e3-5bdb-4c82-a9d5-a3d15d3b10d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226169492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.2226169492
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.1399735003
Short name T740
Test name
Test status
Simulation time 272861973 ps
CPU time 2.04 seconds
Started Jul 19 05:34:37 PM PDT 24
Finished Jul 19 05:34:54 PM PDT 24
Peak memory 209884 kb
Host smart-330884a9-0851-41c8-a304-b8889428aeed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399735003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.1399735003
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.258930136
Short name T1
Test name
Test status
Simulation time 11045965 ps
CPU time 0.82 seconds
Started Jul 19 05:29:12 PM PDT 24
Finished Jul 19 05:29:14 PM PDT 24
Peak memory 205852 kb
Host smart-4dc24b28-0015-4504-bbd2-d9da6d7a96d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258930136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.258930136
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.4194022668
Short name T412
Test name
Test status
Simulation time 583384899 ps
CPU time 6.03 seconds
Started Jul 19 05:29:04 PM PDT 24
Finished Jul 19 05:29:11 PM PDT 24
Peak memory 214100 kb
Host smart-b1ab1668-6114-4b06-9692-3de182bae3d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4194022668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.4194022668
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.3499279994
Short name T326
Test name
Test status
Simulation time 45537464 ps
CPU time 2.43 seconds
Started Jul 19 05:29:02 PM PDT 24
Finished Jul 19 05:29:05 PM PDT 24
Peak memory 214096 kb
Host smart-34b10b86-9bdb-4b43-a830-9ac621d0ef1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499279994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.3499279994
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.17878513
Short name T280
Test name
Test status
Simulation time 45531238 ps
CPU time 3.07 seconds
Started Jul 19 05:29:05 PM PDT 24
Finished Jul 19 05:29:09 PM PDT 24
Peak memory 214056 kb
Host smart-6171c83b-ca65-4721-8fdb-db86335c52f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17878513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.17878513
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.1627317627
Short name T87
Test name
Test status
Simulation time 77264419 ps
CPU time 2.14 seconds
Started Jul 19 05:29:05 PM PDT 24
Finished Jul 19 05:29:08 PM PDT 24
Peak memory 215376 kb
Host smart-6c0043bf-f23f-4afc-8fa9-92f4f618b7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627317627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.1627317627
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.567269898
Short name T115
Test name
Test status
Simulation time 511578078 ps
CPU time 5.18 seconds
Started Jul 19 05:29:05 PM PDT 24
Finished Jul 19 05:29:11 PM PDT 24
Peak memory 214040 kb
Host smart-34fa2319-6d66-42eb-859c-250c728d08bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567269898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.567269898
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.2459048496
Short name T206
Test name
Test status
Simulation time 216702347 ps
CPU time 5.89 seconds
Started Jul 19 05:28:55 PM PDT 24
Finished Jul 19 05:29:02 PM PDT 24
Peak memory 208324 kb
Host smart-f5b92b86-56f1-471b-b4ce-0ec0f89be5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459048496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.2459048496
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.4066790950
Short name T406
Test name
Test status
Simulation time 195708404 ps
CPU time 7.1 seconds
Started Jul 19 05:28:54 PM PDT 24
Finished Jul 19 05:29:02 PM PDT 24
Peak memory 208600 kb
Host smart-8caefb9d-daa9-47bb-986b-a53b7637e021
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066790950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.4066790950
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.3834284241
Short name T715
Test name
Test status
Simulation time 62532506 ps
CPU time 3.3 seconds
Started Jul 19 05:28:56 PM PDT 24
Finished Jul 19 05:29:01 PM PDT 24
Peak memory 206504 kb
Host smart-3f2eee8f-559e-4a4a-bf17-fbfc457f9370
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834284241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.3834284241
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.1136544990
Short name T257
Test name
Test status
Simulation time 63032946 ps
CPU time 3.35 seconds
Started Jul 19 05:28:55 PM PDT 24
Finished Jul 19 05:28:59 PM PDT 24
Peak memory 208660 kb
Host smart-a861c8ac-09f3-48cc-8397-d000c58e64ae
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136544990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.1136544990
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.1835049868
Short name T398
Test name
Test status
Simulation time 36027210 ps
CPU time 1.45 seconds
Started Jul 19 05:29:05 PM PDT 24
Finished Jul 19 05:29:07 PM PDT 24
Peak memory 208076 kb
Host smart-bc7ec384-6693-4bbc-bb6a-681a585276c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835049868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1835049868
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.2806034977
Short name T514
Test name
Test status
Simulation time 1169055539 ps
CPU time 11.29 seconds
Started Jul 19 05:28:53 PM PDT 24
Finished Jul 19 05:29:05 PM PDT 24
Peak memory 207588 kb
Host smart-6f2531ee-b5c8-4e7c-841e-eead82375004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806034977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.2806034977
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.1206351335
Short name T112
Test name
Test status
Simulation time 1241530460 ps
CPU time 11.15 seconds
Started Jul 19 05:29:02 PM PDT 24
Finished Jul 19 05:29:14 PM PDT 24
Peak memory 208332 kb
Host smart-24177232-abc0-4dd2-891f-eae7ae4d30c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206351335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.1206351335
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.3045815755
Short name T469
Test name
Test status
Simulation time 101162904 ps
CPU time 4.2 seconds
Started Jul 19 05:29:04 PM PDT 24
Finished Jul 19 05:29:10 PM PDT 24
Peak memory 207444 kb
Host smart-cdb749eb-975d-439b-aba0-33e3512f60b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045815755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.3045815755
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.2230544318
Short name T824
Test name
Test status
Simulation time 95711561 ps
CPU time 1.65 seconds
Started Jul 19 05:29:02 PM PDT 24
Finished Jul 19 05:29:04 PM PDT 24
Peak memory 209332 kb
Host smart-788a8dae-9f19-4714-8015-dc31ef4aa5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230544318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.2230544318
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.3621159233
Short name T605
Test name
Test status
Simulation time 143222613 ps
CPU time 0.85 seconds
Started Jul 19 05:29:21 PM PDT 24
Finished Jul 19 05:29:23 PM PDT 24
Peak memory 205856 kb
Host smart-e2376775-2287-4a60-ba6e-e0e43979efcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621159233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.3621159233
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.508951062
Short name T147
Test name
Test status
Simulation time 1317503183 ps
CPU time 4.4 seconds
Started Jul 19 05:29:10 PM PDT 24
Finished Jul 19 05:29:15 PM PDT 24
Peak memory 222120 kb
Host smart-be04f543-1b55-40df-bd54-dcc3872e6718
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=508951062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.508951062
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.985142647
Short name T31
Test name
Test status
Simulation time 270184081 ps
CPU time 3.32 seconds
Started Jul 19 05:29:11 PM PDT 24
Finished Jul 19 05:29:16 PM PDT 24
Peak memory 208804 kb
Host smart-ac2d8038-594a-4093-be5f-f2066618f557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985142647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.985142647
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.2296903245
Short name T80
Test name
Test status
Simulation time 90448697 ps
CPU time 3.21 seconds
Started Jul 19 05:29:10 PM PDT 24
Finished Jul 19 05:29:15 PM PDT 24
Peak memory 218008 kb
Host smart-1ad06c93-c496-40a7-b4aa-90a9f30d2fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296903245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.2296903245
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.1311477888
Short name T340
Test name
Test status
Simulation time 423309638 ps
CPU time 3.55 seconds
Started Jul 19 05:29:10 PM PDT 24
Finished Jul 19 05:29:15 PM PDT 24
Peak memory 214068 kb
Host smart-8c786404-ab05-41c6-a570-b94b3d7e4f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311477888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.1311477888
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.2660573767
Short name T318
Test name
Test status
Simulation time 752935409 ps
CPU time 4.74 seconds
Started Jul 19 05:29:11 PM PDT 24
Finished Jul 19 05:29:17 PM PDT 24
Peak memory 221656 kb
Host smart-52a564db-12a9-472e-bbf9-c5da069f97b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660573767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.2660573767
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.956025665
Short name T472
Test name
Test status
Simulation time 559798509 ps
CPU time 3.57 seconds
Started Jul 19 05:29:09 PM PDT 24
Finished Jul 19 05:29:14 PM PDT 24
Peak memory 219640 kb
Host smart-a45798c1-4e2a-4366-b5dd-5dae3ea9637c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956025665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.956025665
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.1098294161
Short name T277
Test name
Test status
Simulation time 299658379 ps
CPU time 4.56 seconds
Started Jul 19 05:29:09 PM PDT 24
Finished Jul 19 05:29:14 PM PDT 24
Peak memory 207844 kb
Host smart-6a4c4ced-c710-4cd3-9da7-f4fd1bcbb069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098294161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.1098294161
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.1132236789
Short name T866
Test name
Test status
Simulation time 710840866 ps
CPU time 2.24 seconds
Started Jul 19 05:29:12 PM PDT 24
Finished Jul 19 05:29:15 PM PDT 24
Peak memory 206624 kb
Host smart-3067349d-4683-4420-ba83-56f5a58f4c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132236789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.1132236789
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.3582940960
Short name T823
Test name
Test status
Simulation time 1539341661 ps
CPU time 19.21 seconds
Started Jul 19 05:29:12 PM PDT 24
Finished Jul 19 05:29:32 PM PDT 24
Peak memory 207724 kb
Host smart-15aadfea-922d-45f7-839b-5cc9571ac214
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582940960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.3582940960
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.138280920
Short name T590
Test name
Test status
Simulation time 594387137 ps
CPU time 7.97 seconds
Started Jul 19 05:29:10 PM PDT 24
Finished Jul 19 05:29:19 PM PDT 24
Peak memory 206728 kb
Host smart-7ede2e17-9509-4705-92c3-5409c993e485
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138280920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.138280920
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.3989034898
Short name T668
Test name
Test status
Simulation time 102941486 ps
CPU time 2.87 seconds
Started Jul 19 05:29:11 PM PDT 24
Finished Jul 19 05:29:16 PM PDT 24
Peak memory 206716 kb
Host smart-eaab5754-1e88-4eb4-9620-e7aee8b27806
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989034898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.3989034898
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.2092931885
Short name T470
Test name
Test status
Simulation time 690992669 ps
CPU time 4.95 seconds
Started Jul 19 05:29:11 PM PDT 24
Finished Jul 19 05:29:17 PM PDT 24
Peak memory 208728 kb
Host smart-77a60422-e6db-4fed-8cc9-0c119e631815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092931885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.2092931885
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.4064472888
Short name T732
Test name
Test status
Simulation time 72266925 ps
CPU time 2.99 seconds
Started Jul 19 05:29:11 PM PDT 24
Finished Jul 19 05:29:15 PM PDT 24
Peak memory 208304 kb
Host smart-999f3464-b2c1-4e2a-934a-7129c20449a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064472888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.4064472888
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.3507799003
Short name T297
Test name
Test status
Simulation time 1041072171 ps
CPU time 20.25 seconds
Started Jul 19 05:29:20 PM PDT 24
Finished Jul 19 05:29:41 PM PDT 24
Peak memory 222348 kb
Host smart-649bfd0c-e616-4688-a460-1055e4e884f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507799003 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.3507799003
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.2390008960
Short name T618
Test name
Test status
Simulation time 139358206 ps
CPU time 2.37 seconds
Started Jul 19 05:29:21 PM PDT 24
Finished Jul 19 05:29:25 PM PDT 24
Peak memory 210272 kb
Host smart-b75d586d-1d2d-4166-b545-7c5a881696c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390008960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.2390008960
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.3286485123
Short name T821
Test name
Test status
Simulation time 23199808 ps
CPU time 0.79 seconds
Started Jul 19 05:29:28 PM PDT 24
Finished Jul 19 05:29:30 PM PDT 24
Peak memory 205808 kb
Host smart-f1e8b988-16b8-4625-974f-e558185d2349
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286485123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.3286485123
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.43143425
Short name T294
Test name
Test status
Simulation time 351308989 ps
CPU time 5.4 seconds
Started Jul 19 05:29:20 PM PDT 24
Finished Jul 19 05:29:26 PM PDT 24
Peak memory 215440 kb
Host smart-0670f733-1865-4884-a88f-84c7a79bc31d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=43143425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.43143425
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.2636463966
Short name T543
Test name
Test status
Simulation time 64771639 ps
CPU time 3.35 seconds
Started Jul 19 05:29:29 PM PDT 24
Finished Jul 19 05:29:34 PM PDT 24
Peak memory 208228 kb
Host smart-e82d7ce3-1318-48fb-81b1-83143bcd6ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636463966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.2636463966
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.3725614836
Short name T74
Test name
Test status
Simulation time 475875156 ps
CPU time 3.21 seconds
Started Jul 19 05:29:21 PM PDT 24
Finished Jul 19 05:29:25 PM PDT 24
Peak memory 217888 kb
Host smart-9f491566-5f4b-468c-972d-442d68b6856d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725614836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.3725614836
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.2627155192
Short name T477
Test name
Test status
Simulation time 214970076 ps
CPU time 2.18 seconds
Started Jul 19 05:29:27 PM PDT 24
Finished Jul 19 05:29:30 PM PDT 24
Peak memory 214000 kb
Host smart-00c40a39-dc33-43b1-a56e-8761e31d58a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627155192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.2627155192
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.330959751
Short name T303
Test name
Test status
Simulation time 512622529 ps
CPU time 3.3 seconds
Started Jul 19 05:29:28 PM PDT 24
Finished Jul 19 05:29:33 PM PDT 24
Peak memory 214160 kb
Host smart-f181d7aa-6c8e-4b48-a036-bdf12b59b3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330959751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.330959751
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.2585519331
Short name T521
Test name
Test status
Simulation time 2674566186 ps
CPU time 18.08 seconds
Started Jul 19 05:29:20 PM PDT 24
Finished Jul 19 05:29:38 PM PDT 24
Peak memory 208320 kb
Host smart-646d4ff9-b9cb-41ec-911f-4577c8de6eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585519331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.2585519331
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.1701088393
Short name T599
Test name
Test status
Simulation time 206068398 ps
CPU time 2.92 seconds
Started Jul 19 05:29:20 PM PDT 24
Finished Jul 19 05:29:24 PM PDT 24
Peak memory 206580 kb
Host smart-60279870-6ecf-4965-a04e-549d0eef450d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701088393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1701088393
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.2463238553
Short name T898
Test name
Test status
Simulation time 810889137 ps
CPU time 4.08 seconds
Started Jul 19 05:29:21 PM PDT 24
Finished Jul 19 05:29:26 PM PDT 24
Peak memory 208320 kb
Host smart-2a17aaba-edff-40d0-81bc-8758185f187c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463238553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2463238553
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.406891923
Short name T770
Test name
Test status
Simulation time 90491084 ps
CPU time 2.64 seconds
Started Jul 19 05:29:21 PM PDT 24
Finished Jul 19 05:29:24 PM PDT 24
Peak memory 206616 kb
Host smart-c2b50589-2e31-4b09-9eb2-45c4abb2b74a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406891923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.406891923
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.1672770839
Short name T403
Test name
Test status
Simulation time 110046509 ps
CPU time 2.36 seconds
Started Jul 19 05:29:20 PM PDT 24
Finished Jul 19 05:29:23 PM PDT 24
Peak memory 206644 kb
Host smart-7c345202-8ec8-4e09-9853-d87f18247b2b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672770839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.1672770839
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.4116408161
Short name T664
Test name
Test status
Simulation time 122254046 ps
CPU time 3.51 seconds
Started Jul 19 05:29:28 PM PDT 24
Finished Jul 19 05:29:32 PM PDT 24
Peak memory 208176 kb
Host smart-457f669e-0a46-438b-94ed-f42798a254be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116408161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.4116408161
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.1408146983
Short name T588
Test name
Test status
Simulation time 136205117 ps
CPU time 3.94 seconds
Started Jul 19 05:29:21 PM PDT 24
Finished Jul 19 05:29:26 PM PDT 24
Peak memory 206708 kb
Host smart-d3646561-5168-461d-a8f1-5e19f7f9fe4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408146983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1408146983
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.1484145459
Short name T76
Test name
Test status
Simulation time 8926933732 ps
CPU time 54.2 seconds
Started Jul 19 05:29:29 PM PDT 24
Finished Jul 19 05:30:24 PM PDT 24
Peak memory 215080 kb
Host smart-9ee1bcc3-845e-4d2a-8115-3273aafa65c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484145459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.1484145459
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.3745251202
Short name T818
Test name
Test status
Simulation time 881281228 ps
CPU time 11.36 seconds
Started Jul 19 05:29:29 PM PDT 24
Finished Jul 19 05:29:41 PM PDT 24
Peak memory 222356 kb
Host smart-344455b0-a739-45cb-9a60-37a36e4eb412
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745251202 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.3745251202
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.3866546329
Short name T372
Test name
Test status
Simulation time 4087383712 ps
CPU time 45.24 seconds
Started Jul 19 05:29:29 PM PDT 24
Finished Jul 19 05:30:15 PM PDT 24
Peak memory 208328 kb
Host smart-3c4e92e7-32d6-4bc0-9848-ade8d389a116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866546329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.3866546329
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.1190640105
Short name T675
Test name
Test status
Simulation time 334208236 ps
CPU time 3.18 seconds
Started Jul 19 05:29:28 PM PDT 24
Finished Jul 19 05:29:33 PM PDT 24
Peak memory 210448 kb
Host smart-594fd3d5-e7f8-4f56-bab9-b3c2c4126a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190640105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1190640105
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.798731875
Short name T730
Test name
Test status
Simulation time 46896542 ps
CPU time 0.86 seconds
Started Jul 19 05:29:45 PM PDT 24
Finished Jul 19 05:29:47 PM PDT 24
Peak memory 205844 kb
Host smart-db2a50a6-a613-4bd5-adec-35078ac75fdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798731875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.798731875
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.3531713648
Short name T244
Test name
Test status
Simulation time 54498732 ps
CPU time 2.52 seconds
Started Jul 19 05:29:38 PM PDT 24
Finished Jul 19 05:29:41 PM PDT 24
Peak memory 214132 kb
Host smart-56b8e2f7-0be5-4880-b2b8-2671819c2877
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3531713648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.3531713648
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.3939746984
Short name T795
Test name
Test status
Simulation time 66580471 ps
CPU time 2.79 seconds
Started Jul 19 05:29:37 PM PDT 24
Finished Jul 19 05:29:40 PM PDT 24
Peak memory 210124 kb
Host smart-3ae1ba50-0176-4973-9e64-a5999ae6d7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939746984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.3939746984
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.1244111652
Short name T27
Test name
Test status
Simulation time 286751778 ps
CPU time 3.93 seconds
Started Jul 19 05:29:40 PM PDT 24
Finished Jul 19 05:29:45 PM PDT 24
Peak memory 217252 kb
Host smart-bf5ed298-0dc9-4b71-8325-494fd6b8f742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244111652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1244111652
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.2972713108
Short name T502
Test name
Test status
Simulation time 40099304 ps
CPU time 1.92 seconds
Started Jul 19 05:29:38 PM PDT 24
Finished Jul 19 05:29:41 PM PDT 24
Peak memory 215088 kb
Host smart-aa22de5c-e485-4888-9773-c23dee2d31bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972713108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.2972713108
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.716075391
Short name T63
Test name
Test status
Simulation time 183241238 ps
CPU time 3.5 seconds
Started Jul 19 05:29:40 PM PDT 24
Finished Jul 19 05:29:45 PM PDT 24
Peak memory 208924 kb
Host smart-ee72432a-1d52-4628-b0ec-327c3f3e059e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716075391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.716075391
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.2970820607
Short name T405
Test name
Test status
Simulation time 281137421 ps
CPU time 3.96 seconds
Started Jul 19 05:29:36 PM PDT 24
Finished Jul 19 05:29:41 PM PDT 24
Peak memory 207364 kb
Host smart-1dc5c6a1-dbd0-4b70-ae4f-9f3d30efb15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970820607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2970820607
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.3345393130
Short name T810
Test name
Test status
Simulation time 223788949 ps
CPU time 2.2 seconds
Started Jul 19 05:29:28 PM PDT 24
Finished Jul 19 05:29:32 PM PDT 24
Peak memory 206648 kb
Host smart-505701ed-640a-4397-a903-c8f785b7f22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345393130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.3345393130
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.1839968
Short name T567
Test name
Test status
Simulation time 177971010 ps
CPU time 7 seconds
Started Jul 19 05:29:28 PM PDT 24
Finished Jul 19 05:29:36 PM PDT 24
Peak memory 208460 kb
Host smart-1baf4548-fe35-47a0-87eb-8886d9eea7cb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1839968
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.2536312267
Short name T509
Test name
Test status
Simulation time 56477915 ps
CPU time 2.65 seconds
Started Jul 19 05:29:28 PM PDT 24
Finished Jul 19 05:29:32 PM PDT 24
Peak memory 206688 kb
Host smart-720cff11-a350-4569-9bc5-a1dc80ab7266
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536312267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2536312267
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.2857592943
Short name T640
Test name
Test status
Simulation time 742098624 ps
CPU time 9.67 seconds
Started Jul 19 05:29:28 PM PDT 24
Finished Jul 19 05:29:40 PM PDT 24
Peak memory 207868 kb
Host smart-5d6eb512-e320-4d18-850d-45a966e9a78a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857592943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.2857592943
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.4213028665
Short name T758
Test name
Test status
Simulation time 47170833 ps
CPU time 2.59 seconds
Started Jul 19 05:29:36 PM PDT 24
Finished Jul 19 05:29:40 PM PDT 24
Peak memory 207360 kb
Host smart-6cd95146-2d46-4d4a-a345-3c6b44b35f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213028665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.4213028665
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.3525592746
Short name T852
Test name
Test status
Simulation time 95637552 ps
CPU time 2.55 seconds
Started Jul 19 05:29:30 PM PDT 24
Finished Jul 19 05:29:33 PM PDT 24
Peak memory 206552 kb
Host smart-e152b8f0-2c54-4c7e-b811-92af7842adb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525592746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3525592746
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.2909686789
Short name T592
Test name
Test status
Simulation time 2582204592 ps
CPU time 9.12 seconds
Started Jul 19 05:29:46 PM PDT 24
Finished Jul 19 05:29:57 PM PDT 24
Peak memory 215964 kb
Host smart-ae4af67b-55b0-4152-8993-251d342006d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909686789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.2909686789
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.3258416273
Short name T673
Test name
Test status
Simulation time 273106672 ps
CPU time 7.4 seconds
Started Jul 19 05:29:39 PM PDT 24
Finished Jul 19 05:29:47 PM PDT 24
Peak memory 207096 kb
Host smart-6df457b5-8120-4c5a-bb33-e170a906e64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258416273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.3258416273
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.3658081696
Short name T58
Test name
Test status
Simulation time 56321600 ps
CPU time 2.88 seconds
Started Jul 19 05:29:44 PM PDT 24
Finished Jul 19 05:29:47 PM PDT 24
Peak memory 209856 kb
Host smart-f582921d-f364-41bf-a579-a1cb6d55222f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658081696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.3658081696
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.1233671407
Short name T466
Test name
Test status
Simulation time 11068587 ps
CPU time 0.9 seconds
Started Jul 19 05:29:58 PM PDT 24
Finished Jul 19 05:30:00 PM PDT 24
Peak memory 205848 kb
Host smart-9c4dc40e-57ba-47f0-b1ea-89ae1323675a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233671407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.1233671407
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.850971606
Short name T764
Test name
Test status
Simulation time 379926274 ps
CPU time 2.77 seconds
Started Jul 19 05:29:55 PM PDT 24
Finished Jul 19 05:29:59 PM PDT 24
Peak memory 214404 kb
Host smart-7334d363-b7cc-476e-9c5c-0b4a6b17faae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850971606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.850971606
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.2144635929
Short name T811
Test name
Test status
Simulation time 57769405 ps
CPU time 3.13 seconds
Started Jul 19 05:29:45 PM PDT 24
Finished Jul 19 05:29:49 PM PDT 24
Peak memory 222204 kb
Host smart-b9b30b51-01b2-47be-975f-f49c35a67202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144635929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.2144635929
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.1090658738
Short name T733
Test name
Test status
Simulation time 163472316 ps
CPU time 2.2 seconds
Started Jul 19 05:29:46 PM PDT 24
Finished Jul 19 05:29:50 PM PDT 24
Peak memory 214024 kb
Host smart-a33c1a54-3692-45b5-80e6-e03bc622f361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090658738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.1090658738
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.2904846707
Short name T524
Test name
Test status
Simulation time 87067634 ps
CPU time 3.22 seconds
Started Jul 19 05:29:46 PM PDT 24
Finished Jul 19 05:29:50 PM PDT 24
Peak memory 222156 kb
Host smart-d6d97e8b-af90-4adf-8c66-1d9b2d28aeb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904846707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.2904846707
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.2385656315
Short name T236
Test name
Test status
Simulation time 286116271 ps
CPU time 3.14 seconds
Started Jul 19 05:29:44 PM PDT 24
Finished Jul 19 05:29:48 PM PDT 24
Peak memory 207960 kb
Host smart-0f009a93-ca7e-4bc4-8f19-f45fe95d60d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385656315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.2385656315
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.3229746020
Short name T535
Test name
Test status
Simulation time 414245063 ps
CPU time 5.84 seconds
Started Jul 19 05:29:47 PM PDT 24
Finished Jul 19 05:29:54 PM PDT 24
Peak memory 207088 kb
Host smart-af07f418-6530-4b64-b35d-e66484769cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229746020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.3229746020
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.3360822699
Short name T86
Test name
Test status
Simulation time 40993973 ps
CPU time 2.94 seconds
Started Jul 19 05:29:45 PM PDT 24
Finished Jul 19 05:29:49 PM PDT 24
Peak memory 208536 kb
Host smart-248b6062-775b-4311-b4f2-350b02937654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360822699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.3360822699
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.2967953444
Short name T867
Test name
Test status
Simulation time 204236719 ps
CPU time 4.23 seconds
Started Jul 19 05:29:45 PM PDT 24
Finished Jul 19 05:29:51 PM PDT 24
Peak memory 208788 kb
Host smart-43ff4004-b596-48df-8d62-2e50ff92ce60
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967953444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.2967953444
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.3604280329
Short name T381
Test name
Test status
Simulation time 228295894 ps
CPU time 5.81 seconds
Started Jul 19 05:29:44 PM PDT 24
Finished Jul 19 05:29:51 PM PDT 24
Peak memory 208588 kb
Host smart-e093ee9c-af2f-41ac-b90d-0edd1aa509e2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604280329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.3604280329
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3804283369
Short name T623
Test name
Test status
Simulation time 678501878 ps
CPU time 7.28 seconds
Started Jul 19 05:29:45 PM PDT 24
Finished Jul 19 05:29:53 PM PDT 24
Peak memory 206856 kb
Host smart-4b6172df-4686-47ec-a29a-3690c35fb9aa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804283369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3804283369
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.2660851177
Short name T779
Test name
Test status
Simulation time 129295785 ps
CPU time 3.27 seconds
Started Jul 19 05:29:54 PM PDT 24
Finished Jul 19 05:29:59 PM PDT 24
Peak memory 214052 kb
Host smart-737a22db-4109-44cc-8782-60d90acf5e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660851177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.2660851177
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.3673942148
Short name T526
Test name
Test status
Simulation time 428663990 ps
CPU time 5.09 seconds
Started Jul 19 05:29:45 PM PDT 24
Finished Jul 19 05:29:51 PM PDT 24
Peak memory 207652 kb
Host smart-aa1c9779-ffeb-4e74-b70d-3972943b4a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673942148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.3673942148
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.304550856
Short name T685
Test name
Test status
Simulation time 308152753 ps
CPU time 7.76 seconds
Started Jul 19 05:29:57 PM PDT 24
Finished Jul 19 05:30:06 PM PDT 24
Peak memory 220104 kb
Host smart-83827a16-09a6-497d-8b23-cb3d26902c50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304550856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.304550856
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.1873505464
Short name T896
Test name
Test status
Simulation time 119121859 ps
CPU time 7.22 seconds
Started Jul 19 05:29:54 PM PDT 24
Finished Jul 19 05:30:03 PM PDT 24
Peak memory 222356 kb
Host smart-5339a5b3-ab1e-48f3-9700-945f856700d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873505464 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.1873505464
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.1603963558
Short name T754
Test name
Test status
Simulation time 212144664 ps
CPU time 3.56 seconds
Started Jul 19 05:29:45 PM PDT 24
Finished Jul 19 05:29:49 PM PDT 24
Peak memory 218088 kb
Host smart-74697b52-d11c-425e-b407-ce8150640ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603963558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.1603963558
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.1222226786
Short name T556
Test name
Test status
Simulation time 275132942 ps
CPU time 3.29 seconds
Started Jul 19 05:29:57 PM PDT 24
Finished Jul 19 05:30:02 PM PDT 24
Peak memory 210244 kb
Host smart-c0d24522-8151-45b2-abda-790c709826b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222226786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1222226786
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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