Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
57959 |
1 |
|
|
T1 |
55 |
|
T2 |
49 |
|
T3 |
824 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
34187 |
1 |
|
|
T1 |
55 |
|
T2 |
49 |
|
T3 |
555 |
auto[1] |
23772 |
1 |
|
|
T3 |
269 |
|
T4 |
29 |
|
T12 |
9 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
28655 |
1 |
|
|
T1 |
28 |
|
T2 |
25 |
|
T3 |
448 |
auto[1] |
29304 |
1 |
|
|
T1 |
27 |
|
T2 |
24 |
|
T3 |
376 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
16642 |
1 |
|
|
T1 |
28 |
|
T2 |
25 |
|
T3 |
299 |
all_values[0] |
auto[0] |
auto[1] |
17545 |
1 |
|
|
T1 |
27 |
|
T2 |
24 |
|
T3 |
256 |
all_values[0] |
auto[1] |
auto[0] |
12013 |
1 |
|
|
T3 |
149 |
|
T4 |
15 |
|
T13 |
15 |
all_values[0] |
auto[1] |
auto[1] |
11759 |
1 |
|
|
T3 |
120 |
|
T4 |
14 |
|
T12 |
9 |