Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
74.60	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	15	34	69.39

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	14	21	60.00	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	35	1			T5	1		T40	1		T41	1
auto[OpGenId]	12	1			T3	1		T40	1		T35	1
auto[OpGenSwOut]	22	1			T5	1		T190	1		T191	1
auto[OpGenHwOut]	19	1			T3	1		T5	1		T6	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1751	1			T8	90		T15	6		T5	4
auto[StInit]	79	1			T32	1		T5	1		T95	1
auto[StCreatorRootKey]	52	1			T3	1		T12	1		T34	1
auto[StOwnerIntKey]	42	1			T3	1		T53	1		T27	1
auto[StOwnerKey]	33	1			T5	1		T6	1		T60	1
auto[StDisabled]	482	1			T3	14		T15	4		T57	1
auto[StInvalid]	50	1			T33	1		T47	1		T52	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3481

1

T1

1

T2

1

T3

15

auto[1]

88

1

T3

2

T5

3

T6

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1745	1			T8	90		T15	6		T5	4
auto[StReset]	auto[1]	6	1			T44	1		T192	1		T193	1
auto[StInit]	auto[0]	36	1			T32	1		T95	1		T49	1
auto[StInit]	auto[1]	43	1			T5	1		T136	1		T35	1
auto[StCreatorRootKey]	auto[0]	35	1			T12	1		T34	1		T18	1
auto[StCreatorRootKey]	auto[1]	17	1			T3	1		T5	1		T40	2
auto[StOwnerIntKey]	auto[0]	33	1			T53	1		T27	1		T54	1
auto[StOwnerIntKey]	auto[1]	9	1			T3	1		T5	1		T55	1
auto[StOwnerKey]	auto[0]	27	1			T5	1		T60	1		T56	1
auto[StOwnerKey]	auto[1]	6	1			T6	1		T41	1		T194	1
auto[StDisabled]	auto[0]	475	1			T3	14		T15	4		T57	1
auto[StDisabled]	auto[1]	7	1			T50	1		T195	1		T196	1
auto[StInvalid]	auto[0]	50	1			T33	1		T47	1		T52	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	14	21	60.00	14

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenSwOut]]	0	1	1
[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[StInit]]	[auto[OpDisable]]	0	1	1
[auto[StCreatorRootKey]]	[auto[OpGenHwOut] , auto[OpDisable]]	--	--	2
[auto[StOwnerIntKey]]	[auto[OpGenId]]	0	1	1
[auto[StOwnerIntKey]]	[auto[OpDisable]]	0	1	1
[auto[StOwnerKey] , auto[StDisabled]]	[auto[OpDisable]]	--	--	2

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	4	1			T44	1		T192	1		T45	1
auto[StReset]	auto[OpGenId]	1	1			T193	1		-	-		-	-
auto[StReset]	auto[OpGenHwOut]	1	1			T143	1		-	-		-	-
auto[StInit]	auto[OpAdvance]	15	1			T5	1		T136	1		T29	1
auto[StInit]	auto[OpGenId]	6	1			T35	1		T197	1		T198	1
auto[StInit]	auto[OpGenSwOut]	11	1			T190	1		T137	1		T199	1
auto[StInit]	auto[OpGenHwOut]	11	1			T28	1		T200	1		T175	1
auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T40	1		T201	1		T202	1
auto[StCreatorRootKey]	auto[OpGenId]	3	1			T3	1		T40	1		T49	1
auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T5	1		T191	1		T203	1
auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T55	1		T37	1		T19	1
auto[StOwnerIntKey]	auto[OpGenSwOut]	1	1			T204	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpGenHwOut]	5	1			T3	1		T5	1		T205	1
auto[StOwnerKey]	auto[OpAdvance]	3	1			T41	1		T194	1		T206	1
auto[StOwnerKey]	auto[OpGenId]	1	1			T26	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenSwOut]	1	1			T207	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	1	1			T6	1		-	-		-	-
auto[StDisabled]	auto[OpAdvance]	1	1			T50	1		-	-		-	-
auto[StDisabled]	auto[OpGenId]	1	1			T208	1		-	-		-	-
auto[StDisabled]	auto[OpGenSwOut]	4	1			T195	1		T178	1		T209	1
auto[StDisabled]	auto[OpGenHwOut]	1	1			T196	1		-	-		-	-