Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.58	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	74	256	77.58

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	55	225	80.36	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4936

1

T2

10

T3

53

T4

1

auto[1]

552

1

T2

1

T3

7

T78

3

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4936

1

T2

10

T3

53

T4

1

auto[1]

552

1

T2

1

T3

7

T78

3

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4910

1

T2

10

T3

58

T4

1

auto[1]

578

1

T2

1

T3

2

T14

2

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4910

1

T2

10

T3

58

T4

1

auto[1]

578

1

T2

1

T3

2

T14

2

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	421	1			T2	3		T3	8		T15	2
auto[OpGenId]	1209	1			T2	5		T3	20		T15	9
auto[OpGenSwOut]	1195	1			T2	1		T3	15		T11	1
auto[OpGenHwOut]	2569	1			T2	2		T3	15		T4	1
auto[OpDisable]	94	1			T3	2		T11	1		T15	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	421	1			T2	3		T3	8		T15	2
auto[OpGenId]	1209	1			T2	5		T3	20		T15	9
auto[OpGenSwOut]	1195	1			T2	1		T3	15		T11	1
auto[OpGenHwOut]	2569	1			T2	2		T3	15		T4	1
auto[OpDisable]	94	1			T3	2		T11	1		T15	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4916

1

T2

10

T3

53

T4

1

auto[1]

572

1

T2

1

T3

7

T11

1

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4916

1

T2

10

T3

53

T4

1

auto[1]

572

1

T2

1

T3

7

T11

1

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5195

1

T2

5

T3

60

T4

1

auto[1]

293

1

T2

6

T77

1

T78

3

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1878	1			T2	9		T3	23		T4	1
auto[1]	727	1			T2	2		T3	7		T13	1
auto[2]	717	1			T3	6		T13	1		T14	1
auto[3]	743	1			T3	5		T14	1		T15	4
auto[4]	376	1			T3	5		T15	1		T33	1
auto[5]	345	1			T3	1		T11	1		T13	2
auto[6]	329	1			T3	9		T14	3		T15	1
auto[7]	373	1			T3	4		T14	1		T15	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1423	1			T3	19		T11	1		T13	2
clear_one[1]	727	1			T2	2		T3	7		T13	1
clear_one[2]	717	1			T3	6		T13	1		T14	1
clear_one[3]	743	1			T3	5		T14	1		T15	4
clear_none	1878	1			T2	9		T3	23		T4	1

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1011	1			T3	7		T4	1		T13	2
auto[StInit]	674	1			T2	1		T3	10		T11	1
auto[StCreatorRootKey]	582	1			T2	3		T3	8		T13	1
auto[StOwnerIntKey]	535	1			T2	1		T3	3		T11	1
auto[StOwnerKey]	484	1			T2	2		T3	5		T14	1
auto[StDisabled]	1920	1			T2	4		T3	27		T11	1
auto[StInvalid]	282	1			T33	6		T47	4		T52	2

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1011	1			T3	7		T4	1		T13	2
auto[StInit]	674	1			T2	1		T3	10		T11	1
auto[StCreatorRootKey]	582	1			T2	3		T3	8		T13	1
auto[StOwnerIntKey]	535	1			T2	1		T3	3		T11	1
auto[StOwnerKey]	484	1			T2	2		T3	5		T14	1
auto[StDisabled]	1920	1			T2	4		T3	27		T11	1
auto[StInvalid]	282	1			T33	6		T47	4		T52	2

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	55	225	80.36	55

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	7
[auto[1] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	7
[auto[1] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	28
[auto[1] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	7

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	1	1			T124	1		-	-		-	-
auto[0]	auto[StReset]	auto[OpGenId]	165	1			T3	1		T15	1		T52	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	153	1			T3	1		T15	1		T33	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	266	1			T3	1		T4	1		T13	1
auto[0]	auto[StInit]	auto[OpAdvance]	44	1			T3	2		T216	1		T217	1
auto[0]	auto[StInit]	auto[OpGenId]	104	1			T3	2		T15	1		T78	2
auto[0]	auto[StInit]	auto[OpGenSwOut]	106	1			T3	3		T15	1		T118	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	174	1			T2	1		T3	2		T11	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	21	1			T2	1		T134	1		T50	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	54	1			T2	1		T3	1		T119	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	41	1			T2	1		T3	1		T120	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	90	1			T3	1		T113	1		T184	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	11	1			T40	1		T66	1		T218	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	37	1			T2	1		T78	1		T40	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	32	1			T3	1		T11	1		T40	2
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	48	1			T3	1		T78	1		T27	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T2	1		T3	1		T175	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	21	1			T2	1		T40	1		T183	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	20	1			T214	1		T67	1		T195	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	55	1			T71	1		T63	1		T219	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	23	1			T2	1		T3	1		T183	1
auto[0]	auto[StDisabled]	auto[OpGenId]	79	1			T3	3		T15	1		T5	2
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	60	1			T3	1		T119	1		T51	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	164	1			T2	1		T16	1		T188	2
auto[0]	auto[StDisabled]	auto[OpDisable]	24	1			T46	1		T60	1		T175	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	16	1			T82	1		T220	1		T221	1
auto[0]	auto[StInvalid]	auto[OpGenId]	27	1			T33	1		T47	1		T48	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	20	1			T42	1		T222	1		T223	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	14	1			T43	2		T224	1		T225	1
auto[1]	auto[StReset]	auto[OpGenId]	13	1			T226	1		T194	1		T137	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	21	1			T194	1		T227	1		T68	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	48	1			T13	1		T16	1		T189	1
auto[1]	auto[StInit]	auto[OpAdvance]	8	1			T23	1		T210	1		T17	1
auto[1]	auto[StInit]	auto[OpGenId]	8	1			T40	1		T228	1		T229	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	12	1			T5	2		T230	1		T94	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	19	1			T188	1		T231	1		T22	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	10	1			T3	1		T57	1		T232	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	21	1			T15	1		T60	1		T233	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	16	1			T3	1		T183	1		T234	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	29	1			T72	1		T5	2		T235	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	9	1			T40	1		T134	1		T236	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	20	1			T15	2		T51	1		T183	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	19	1			T182	1		T49	1		T237	2
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	39	1			T3	1		T64	1		T238	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	13	1			T40	1		T134	1		T183	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	17	1			T5	1		T60	2		T239	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	20	1			T236	1		T25	1		T194	2
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	29	1			T15	1		T188	1		T235	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	18	1			T240	1		T241	2		T213	1
auto[1]	auto[StDisabled]	auto[OpGenId]	57	1			T2	2		T3	2		T57	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	67	1			T3	2		T62	1		T5	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	151	1			T14	1		T189	2		T76	1
auto[1]	auto[StDisabled]	auto[OpDisable]	14	1			T194	1		T241	1		T242	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	3	1			T52	1		T216	1		T243	1
auto[1]	auto[StInvalid]	auto[OpGenId]	16	1			T33	1		T42	1		T220	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	12	1			T47	1		T222	1		T84	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	18	1			T42	1		T220	1		T224	1
auto[2]	auto[StReset]	auto[OpGenId]	20	1			T5	1		T216	2		T239	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	19	1			T51	2		T231	1		T60	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	50	1			T3	1		T16	1		T94	1
auto[2]	auto[StInit]	auto[OpAdvance]	4	1			T86	1		T244	1		T195	1
auto[2]	auto[StInit]	auto[OpGenId]	12	1			T5	1		T233	1		T245	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	13	1			T5	1		T40	1		T87	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	26	1			T75	1		T194	1		T246	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T6	1		T247	1		T248	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	21	1			T3	1		T78	1		T60	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	17	1			T13	1		T41	1		T244	3
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	42	1			T21	1		T188	1		T189	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	10	1			T122	2		T249	1		T37	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	18	1			T71	1		T64	1		T66	2
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	16	1			T5	1		T60	1		T63	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	39	1			T189	1		T75	1		T250	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T251	1		T237	1		T195	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	12	1			T64	1		T122	1		T245	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	20	1			T3	1		T49	1		T230	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	36	1			T3	1		T14	1		T57	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	27	1			T3	1		T77	1		T79	5
auto[2]	auto[StDisabled]	auto[OpGenId]	57	1			T15	1		T77	1		T118	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	56	1			T3	1		T79	2		T71	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	138	1			T79	1		T187	1		T72	1
auto[2]	auto[StDisabled]	auto[OpDisable]	14	1			T63	1		T49	2		T252	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	3	1			T83	1		T253	1		T254	1
auto[2]	auto[StInvalid]	auto[OpGenId]	10	1			T48	1		T82	1		T255	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	13	1			T82	1		T84	2		T225	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T52	1		T82	1		T84	1
auto[3]	auto[StReset]	auto[OpGenId]	16	1			T17	1		T256	1		T7	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	20	1			T33	1		T52	1		T121	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	50	1			T3	1		T52	1		T51	1
auto[3]	auto[StInit]	auto[OpAdvance]	5	1			T50	1		T212	1		T257	1
auto[3]	auto[StInit]	auto[OpGenId]	11	1			T21	1		T250	1		T64	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	7	1			T30	1		T195	1		T177	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	28	1			T51	1		T5	1		T258	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T79	1		T259	2		T36	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	14	1			T15	1		T183	2		T63	2
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	12	1			T60	1		T260	1		T227	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	43	1			T261	1		T262	1		T263	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	10	1			T259	1		T26	1		T264	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	14	1			T5	1		T183	1		T265	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	18	1			T62	1		T5	1		T194	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	36	1			T21	1		T188	1		T72	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T77	1		T259	1		T36	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	11	1			T183	1		T266	1		T107	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	19	1			T15	1		T182	1		T40	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	43	1			T187	1		T40	1		T265	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	33	1			T3	1		T15	1		T183	1
auto[3]	auto[StDisabled]	auto[OpGenId]	74	1			T3	2		T46	1		T40	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	60	1			T118	1		T267	1		T175	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	148	1			T14	1		T16	1		T188	1
auto[3]	auto[StDisabled]	auto[OpDisable]	10	1			T3	1		T15	1		T62	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	7	1			T48	1		T42	1		T94	1
auto[3]	auto[StInvalid]	auto[OpGenId]	10	1			T33	1		T43	1		T82	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	15	1			T33	1		T43	1		T222	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	13	1			T33	1		T217	1		T84	1
auto[4]	auto[StReset]	auto[OpGenId]	15	1			T3	1		T60	1		T50	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	15	1			T5	1		T216	1		T84	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	23	1			T5	1		T60	2		T268	1
auto[4]	auto[StInit]	auto[OpAdvance]	1	1			T269	1		-	-		-	-
auto[4]	auto[StInit]	auto[OpGenId]	2	1			T23	1		T270	1		-	-
auto[4]	auto[StInit]	auto[OpGenSwOut]	4	1			T22	1		T7	1		T271	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	12	1			T16	1		T272	1		T273	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T5	1		T274	1		T275	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T276	1		T277	1		T278	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T194	1		T279	1		T280	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	20	1			T16	1		T118	1		T187	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T281	1		T282	1		T283	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T5	1		T205	1		T207	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	11	1			T284	1		T108	1		T285	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	26	1			T286	1		T63	1		T287	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T15	1		T50	1		T178	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	10	1			T3	1		T124	3		T177	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T50	1		T232	1		T288	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	18	1			T5	1		T250	1		T289	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	10	1			T76	1		T290	1		T291	1
auto[4]	auto[StDisabled]	auto[OpGenId]	31	1			T3	1		T182	1		T5	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	30	1			T184	1		T40	1		T183	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	78	1			T3	2		T16	1		T188	1
auto[4]	auto[StDisabled]	auto[OpDisable]	5	1			T5	1		T60	1		T292	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	3	1			T216	1		T293	1		T294	1
auto[4]	auto[StInvalid]	auto[OpGenId]	8	1			T33	1		T217	1		T223	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T255	1		T220	1		T221	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T216	1		T224	1		T94	1
auto[5]	auto[StReset]	auto[OpGenId]	7	1			T63	1		T25	1		T211	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	10	1			T5	1		T245	1		T137	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	24	1			T75	1		T135	1		T258	1
auto[5]	auto[StInit]	auto[OpAdvance]	2	1			T295	1		T296	1		-	-
auto[5]	auto[StInit]	auto[OpGenId]	7	1			T121	1		T211	1		T70	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	3	1			T13	1		T297	1		T298	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	11	1			T287	1		T261	1		T203	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T122	1		T45	1		-	-
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T25	1		T88	1		T284	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T122	5		T205	1		T299	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	14	1			T186	1		T300	1		T301	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T122	1		T245	1		T302	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T303	1		T304	1		T305	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T13	1		T306	1		T307	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	17	1			T16	1		T187	1		T121	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T66	1		T308	1		T309	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	4	1			T310	1		T67	1		T311	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	4	1			T66	1		T209	1		T312	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	18	1			T121	1		T186	1		T75	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	16	1			T57	1		T5	1		T90	1
auto[5]	auto[StDisabled]	auto[OpGenId]	25	1			T78	1		T121	1		T251	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	28	1			T78	1		T121	1		T5	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	83	1			T3	1		T14	1		T187	1
auto[5]	auto[StDisabled]	auto[OpDisable]	11	1			T11	1		T67	1		T313	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	1	1			T314	1		-	-		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	6	1			T47	1		T315	1		T316	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T83	1		T249	1		T317	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T43	1		T83	1		T318	1
auto[6]	auto[StReset]	auto[OpGenId]	5	1			T3	1		T223	1		T66	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	7	1			T63	1		T233	1		T195	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	16	1			T75	1		T50	1		T210	1
auto[6]	auto[StInit]	auto[OpAdvance]	2	1			T3	1		T319	1		-	-
auto[6]	auto[StInit]	auto[OpGenId]	1	1			T320	1		-	-		-	-
auto[6]	auto[StInit]	auto[OpGenSwOut]	6	1			T86	1		T210	1		T264	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	12	1			T14	1		T23	1		T195	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	1	1			T135	1		-	-		-	-
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T231	1		T321	1		T66	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T5	1		T195	2		T322	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	18	1			T3	2		T14	1		T323	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T324	1		T270	1		-	-
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T90	1		T66	1		T279	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T135	4		T63	1		T325	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	24	1			T186	1		T326	1		T327	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	1	1			T77	1		-	-		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenId]	6	1			T5	2		T279	1		T328	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T228	1		T302	1		T312	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	18	1			T79	1		T189	1		T329	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	10	1			T79	1		T40	1		T259	1
auto[6]	auto[StDisabled]	auto[OpGenId]	23	1			T3	2		T15	1		T77	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	31	1			T3	2		T40	1		T135	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	85	1			T3	1		T14	1		T189	1
auto[6]	auto[StDisabled]	auto[OpDisable]	7	1			T66	2		T330	1		T288	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	4	1			T222	1		T331	1		T332	1
auto[6]	auto[StInvalid]	auto[OpGenId]	3	1			T222	1		T221	1		T333	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T42	1		T220	1		T224	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T47	1		T255	1		T222	1
auto[7]	auto[StReset]	auto[OpGenId]	10	1			T63	1		T88	1		T66	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	11	1			T40	1		T60	1		T86	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	26	1			T16	1		T258	1		T49	1
auto[7]	auto[StInit]	auto[OpAdvance]	4	1			T247	2		T334	1		T215	1
auto[7]	auto[StInit]	auto[OpGenId]	5	1			T21	1		T122	1		T303	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	7	1			T122	1		T205	1		T68	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	14	1			T15	1		T189	1		T122	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	1	1			T66	1		-	-		-	-
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T108	1		T109	1		T335	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T250	1		T230	1		T194	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	14	1			T75	1		T258	1		T329	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T183	1		T336	1		-	-
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T66	1		T337	1		T338	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	4	1			T234	1		T339	1		T340	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T14	1		T64	1		T262	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	1	1			T341	1		-	-		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenId]	10	1			T3	1		T226	1		T109	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T118	1		T51	1		T292	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	23	1			T16	1		T50	1		T262	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	16	1			T342	1		T64	1		T175	1
auto[7]	auto[StDisabled]	auto[OpGenId]	26	1			T3	1		T5	1		T60	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	30	1			T3	1		T57	1		T66	3
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	92	1			T16	1		T75	1		T258	1
auto[7]	auto[StDisabled]	auto[OpDisable]	9	1			T3	1		T5	1		T321	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	2	1			T343	1		T344	1		-	-
auto[7]	auto[StInvalid]	auto[OpGenId]	7	1			T255	1		T84	1		T345	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	2	1			T346	1		T347	1		-	-
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T225	1		T294	1		T348	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1423

1

T3

19

T11

1

T13

2

clear_one[1]

auto[0]

auto[0]

auto[0]

434

1

T2

1

T3

5

T13

1

clear_one[1]

auto[0]

auto[0]

auto[1]

117

1

T3

2

T189

2

T72

1

clear_one[1]

auto[0]

auto[1]

auto[0]

118

1

T14

1

T76

1

T5

2

clear_one[1]

auto[0]

auto[1]

auto[1]

58

1

T2

1

T51

1

T135

1

clear_one[2]

auto[0]

auto[0]

auto[0]

439

1

T3

5

T13

1

T14

1

clear_one[2]

auto[0]

auto[0]

auto[1]

123

1

T3

1

T21

1

T187

1

clear_one[2]

auto[1]

auto[0]

auto[0]

111

1

T78

1

T118

1

T188

1

clear_one[2]

auto[1]

auto[0]

auto[1]

44

1

T79

1

T40

1

T183

2

clear_one[3]

auto[0]

auto[0]

auto[0]

452

1

T3

4

T15

3

T33

4

clear_one[3]

auto[0]

auto[1]

auto[0]

130

1

T3

1

T14

1

T15

1

clear_one[3]

auto[1]

auto[0]

auto[0]

121

1

T21

1

T188

2

T121

1

clear_one[3]

auto[1]

auto[1]

auto[0]

40

1

T118

1

T265

1

T342

1

clear_none

auto[0]

auto[0]

auto[0]

1333

1

T2

8

T3

16

T4

1

clear_none

auto[0]

auto[0]

auto[1]

131

1

T11

1

T27

1

T71

1

clear_none

auto[0]

auto[1]

auto[0]

136

1

T16

1

T186

2

T51

1

clear_none

auto[0]

auto[1]

auto[1]

42

1

T5

1

T40

1

T239

1

clear_none

auto[1]

auto[0]

auto[0]

150

1

T2

1

T3

2

T78

2

clear_none

auto[1]

auto[0]

auto[1]

32

1

T3

4

T113

1

T120

1

clear_none

auto[1]

auto[1]

auto[0]

29

1

T3

1

T119

1

T86

1

clear_none

auto[1]

auto[1]

auto[1]

25

1

T5

1

T40

1

T183

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1334	1			T3	19		T11	1		T13	2
clear_all	auto[1]	89	1			T77	1		T78	1		T79	1
clear_one[1]	auto[0]	672	1			T2	1		T3	7		T13	1
clear_one[1]	auto[1]	55	1			T2	1		T134	1		T135	2
clear_one[2]	auto[0]	674	1			T3	6		T13	1		T14	1
clear_one[2]	auto[1]	43	1			T79	8		T134	1		T122	2
clear_one[3]	auto[0]	710	1			T3	5		T14	1		T15	4
clear_one[3]	auto[1]	33	1			T259	3		T290	2		T123	1
clear_none	auto[0]	1805	1			T2	4		T3	23		T4	1
clear_none	auto[1]	73	1			T2	5		T78	2		T134	3