Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11381

1

T1

15

T2

6

T3

127

auto[Attestation]

7666

1

T1

4

T2

10

T3

135

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2786	1			T1	3		T2	2		T3	47
auto[Aes]	3516	1			T1	1		T2	2		T3	44
auto[Kmac]	3405	1			T1	3		T2	2		T3	46
auto[Otbn]	3446	1			T1	4		T2	1		T3	33

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7732	1			T1	8		T2	8		T3	109
auto[OpGenId]	5894	1			T1	8		T2	9		T3	92
auto[OpGenSwOut]	6009	1			T1	11		T2	1		T3	87
auto[OpGenHwOut]	7144	1			T2	6		T3	83		T4	10
auto[OpDisable]	162	1			T3	3		T11	1		T15	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10719

1

T1

8

T2

12

T3

152

auto[OpDoneFail]

16222

1

T1

19

T2

12

T3

222

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6603	1			T1	12		T2	1		T3	52
auto[StInit]	3720	1			T1	2		T2	4		T3	50
auto[StCreatorRootKey]	3250	1			T1	2		T2	5		T3	50
auto[StOwnerIntKey]	2832	1			T1	2		T2	3		T3	38
auto[StOwnerKey]	2418	1			T1	2		T2	2		T3	36
auto[StDisabled]	8118	1			T1	7		T2	9		T3	148

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	327	1			T1	2		T3	1		T15	4
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	100	1			T34	1		T5	2		T40	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	81	1			T3	2		T12	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	73	1			T3	2		T11	1		T21	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	58	1			T3	1		T79	1		T182	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	219	1			T1	1		T3	4		T79	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	349	1			T15	2		T33	3		T77	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	93	1			T3	3		T13	1		T77	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	78	1			T2	1		T21	1		T51	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	70	1			T4	1		T51	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	58	1			T3	1		T21	1		T183	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	234	1			T1	1		T3	6		T77	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	362	1			T1	1		T3	1		T13	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	85	1			T5	1		T40	1		T134	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	92	1			T3	2		T12	1		T13	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	68	1			T3	2		T11	1		T13	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	62	1			T1	1		T3	2		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	189	1			T3	5		T51	2		T73	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	325	1			T1	3		T3	1		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	116	1			T15	1		T77	1		T120	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	91	1			T3	1		T15	1		T40	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	80	1			T27	1		T184	1		T62	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	69	1			T79	1		T5	2		T40	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	236	1			T1	1		T3	8		T78	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	90	1			T3	4		T51	3		T5	5
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	103	1			T3	3		T120	1		T34	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	87	1			T3	1		T4	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	79	1			T3	2		T73	1		T5	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	66	1			T15	1		T79	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	216	1			T3	2		T11	1		T78	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	85	1			T3	1		T51	2		T5	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	113	1			T78	1		T57	1		T40	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	80	1			T3	1		T12	1		T53	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	71	1			T3	1		T4	1		T77	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	58	1			T3	1		T21	1		T185	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	230	1			T3	4		T11	1		T15	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	73	1			T3	3		T5	2		T40	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	96	1			T3	3		T118	1		T53	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	93	1			T3	4		T21	1		T119	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	79	1			T1	1		T53	1		T121	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	61	1			T3	3		T119	1		T51	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	218	1			T3	5		T15	3		T119	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	78	1			T3	2		T5	4		T40	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	99	1			T3	1		T13	1		T120	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	81	1			T120	1		T74	1		T5	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	63	1			T182	1		T57	1		T76	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	65	1			T3	1		T79	1		T118	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	210	1			T3	3		T15	2		T78	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	288	1			T3	1		T15	1		T77	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	98	1			T3	3		T78	1		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	80	1			T2	1		T3	1		T15	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	70	1			T3	3		T77	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	59	1			T15	1		T121	1		T5	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	174	1			T3	3		T79	1		T57	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	520	1			T3	1		T4	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	122	1			T3	1		T11	1		T12	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	115	1			T3	1		T78	1		T120	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	82	1			T3	1		T4	1		T21	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	85	1			T3	2		T51	1		T5	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	305	1			T3	7		T78	1		T118	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	504	1			T4	2		T13	2		T14	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	111	1			T2	1		T3	2		T182	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	103	1			T3	1		T120	1		T186	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	93	1			T4	1		T14	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	86	1			T14	1		T16	1		T5	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	315	1			T3	4		T14	3		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	471	1			T11	1		T13	2		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	114	1			T13	1		T15	2		T77	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	121	1			T3	3		T21	2		T120	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	85	1			T3	1		T13	5		T118	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	73	1			T3	1		T79	1		T187	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	289	1			T2	1		T3	4		T118	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	60	1			T3	3		T51	2		T5	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	97	1			T3	3		T15	1		T77	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	79	1			T3	3		T51	1		T74	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	63	1			T2	1		T78	1		T40	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	51	1			T3	1		T5	1		T40	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	168	1			T3	4		T15	1		T78	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	48	1			T3	1		T5	1		T40	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	135	1			T15	1		T21	1		T188	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	116	1			T3	4		T113	1		T119	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	109	1			T3	2		T4	1		T113	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	78	1			T3	1		T78	1		T188	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	282	1			T2	1		T3	5		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	61	1			T3	1		T51	1		T5	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	108	1			T3	2		T14	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	103	1			T3	1		T14	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	100	1			T4	4		T113	2		T186	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	73	1			T121	1		T186	1		T5	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	270	1			T2	1		T3	5		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	77	1			T51	2		T5	3		T40	5
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	93	1			T3	1		T189	1		T5	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	110	1			T3	1		T11	2		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	113	1			T3	2		T187	1		T189	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	86	1			T189	1		T57	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	301	1			T3	3		T79	1		T187	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	197	1			T3	4		T11	1		T12	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	661	1			T1	3		T3	6		T15	4
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	187	1			T2	1		T4	1		T21	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	695	1			T1	1		T3	10		T13	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	204	1			T1	1		T3	6		T11	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	654	1			T1	1		T3	6		T13	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	216	1			T15	1		T79	1		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	701	1			T1	4		T3	10		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	216	1			T3	3		T4	1		T15	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	425	1			T3	9		T11	1		T78	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	191	1			T3	3		T4	1		T12	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	446	1			T3	5		T11	1		T15	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	216	1			T1	1		T3	7		T21	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	404	1			T3	11		T15	3		T118	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	196	1			T3	1		T79	1		T120	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	400	1			T3	6		T13	1		T15	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	191	1			T2	1		T3	3		T15	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	578	1			T3	8		T15	1		T77	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	266	1			T3	3		T4	1		T78	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	963	1			T3	10		T4	1		T11	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	268	1			T3	1		T4	1		T14	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	944	1			T2	1		T3	6		T4	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	273	1			T3	5		T13	5		T79	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	880	1			T2	1		T3	4		T11	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	176	1			T2	1		T3	4		T78	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	342	1			T3	10		T15	2		T77	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	283	1			T3	6		T4	1		T78	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	485	1			T2	1		T3	7		T15	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	263	1			T3	1		T4	4		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	452	1			T2	1		T3	8		T14	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	288	1			T3	3		T11	2		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	492	1			T3	4		T79	1		T21	1