Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33048

1

T1

32

T2

27

T3

432

auto[1]

300

1

T2

8

T77

1

T78

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	33054	1			T1	32		T2	27		T3	432
auto[134217728:268435455]	11	1			T79	1		T122	1		T290	1
auto[268435456:402653183]	11	1			T121	1		T244	1		T240	1
auto[402653184:536870911]	9	1			T78	1		T121	2		T124	1
auto[536870912:671088639]	6	1			T240	1		T274	1		T381	1
auto[671088640:805306367]	14	1			T79	1		T134	1		T135	1
auto[805306368:939524095]	2	1			T135	1		T237	1		-	-
auto[939524096:1073741823]	10	1			T2	2		T79	1		T240	2
auto[1073741824:1207959551]	12	1			T78	2		T259	1		T124	1
auto[1207959552:1342177279]	5	1			T290	1		T124	1		T308	1
auto[1342177280:1476395007]	10	1			T123	2		T274	1		T382	1
auto[1476395008:1610612735]	14	1			T2	1		T79	1		T121	1
auto[1610612736:1744830463]	9	1			T2	1		T382	2		T334	1
auto[1744830464:1879048191]	9	1			T134	2		T244	2		T240	1
auto[1879048192:2013265919]	6	1			T78	1		T244	1		T123	1
auto[2013265920:2147483647]	15	1			T2	1		T134	1		T122	1
auto[2147483648:2281701375]	10	1			T123	1		T360	2		T247	1
auto[2281701376:2415919103]	16	1			T2	1		T77	1		T79	2
auto[2415919104:2550136831]	11	1			T79	1		T259	1		T244	1
auto[2550136832:2684354559]	9	1			T79	1		T123	1		T240	1
auto[2684354560:2818572287]	10	1			T2	2		T79	1		T122	1
auto[2818572288:2952790015]	6	1			T244	2		T123	1		T382	1
auto[2952790016:3087007743]	6	1			T359	1		T280	2		T283	1
auto[3087007744:3221225471]	8	1			T79	1		T244	1		T124	1
auto[3221225472:3355443199]	8	1			T247	2		T382	1		T359	1
auto[3355443200:3489660927]	7	1			T78	1		T360	1		T279	1
auto[3489660928:3623878655]	11	1			T79	1		T134	1		T135	1
auto[3623878656:3758096383]	12	1			T79	2		T244	2		T290	1
auto[3758096384:3892314111]	4	1			T134	1		T123	1		T295	1
auto[3892314112:4026531839]	14	1			T79	2		T121	2		T259	1
auto[4026531840:4160749567]	13	1			T244	1		T240	1		T308	1
auto[4160749568:4294967295]	6	1			T121	1		T124	1		T328	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	33048	1			T1	32		T2	27		T3	432
auto[0:134217727]	auto[1]	6	1			T237	1		T328	1		T334	1
auto[134217728:268435455]	auto[1]	11	1			T79	1		T122	1		T290	1
auto[268435456:402653183]	auto[1]	11	1			T121	1		T244	1		T240	1
auto[402653184:536870911]	auto[1]	9	1			T78	1		T121	2		T124	1
auto[536870912:671088639]	auto[1]	6	1			T240	1		T274	1		T381	1
auto[671088640:805306367]	auto[1]	14	1			T79	1		T134	1		T135	1
auto[805306368:939524095]	auto[1]	2	1			T135	1		T237	1		-	-
auto[939524096:1073741823]	auto[1]	10	1			T2	2		T79	1		T240	2
auto[1073741824:1207959551]	auto[1]	12	1			T78	2		T259	1		T124	1
auto[1207959552:1342177279]	auto[1]	5	1			T290	1		T124	1		T308	1
auto[1342177280:1476395007]	auto[1]	10	1			T123	2		T274	1		T382	1
auto[1476395008:1610612735]	auto[1]	14	1			T2	1		T79	1		T121	1
auto[1610612736:1744830463]	auto[1]	9	1			T2	1		T382	2		T334	1
auto[1744830464:1879048191]	auto[1]	9	1			T134	2		T244	2		T240	1
auto[1879048192:2013265919]	auto[1]	6	1			T78	1		T244	1		T123	1
auto[2013265920:2147483647]	auto[1]	15	1			T2	1		T134	1		T122	1
auto[2147483648:2281701375]	auto[1]	10	1			T123	1		T360	2		T247	1
auto[2281701376:2415919103]	auto[1]	16	1			T2	1		T77	1		T79	2
auto[2415919104:2550136831]	auto[1]	11	1			T79	1		T259	1		T244	1
auto[2550136832:2684354559]	auto[1]	9	1			T79	1		T123	1		T240	1
auto[2684354560:2818572287]	auto[1]	10	1			T2	2		T79	1		T122	1
auto[2818572288:2952790015]	auto[1]	6	1			T244	2		T123	1		T382	1
auto[2952790016:3087007743]	auto[1]	6	1			T359	1		T280	2		T283	1
auto[3087007744:3221225471]	auto[1]	8	1			T79	1		T244	1		T124	1
auto[3221225472:3355443199]	auto[1]	8	1			T247	2		T382	1		T359	1
auto[3355443200:3489660927]	auto[1]	7	1			T78	1		T360	1		T279	1
auto[3489660928:3623878655]	auto[1]	11	1			T79	1		T134	1		T135	1
auto[3623878656:3758096383]	auto[1]	12	1			T79	2		T244	2		T290	1
auto[3758096384:3892314111]	auto[1]	4	1			T134	1		T123	1		T295	1
auto[3892314112:4026531839]	auto[1]	14	1			T79	2		T121	2		T259	1
auto[4026531840:4160749567]	auto[1]	13	1			T244	1		T240	1		T308	1
auto[4160749568:4294967295]	auto[1]	6	1			T121	1		T124	1		T328	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1669

1

T2

2

T3

23

T4

3

auto[1]

1697

1

T2

3

T3

28

T4

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	99	1			T15	1		T77	1		T5	1
auto[134217728:268435455]	89	1			T3	2		T113	1		T119	1
auto[268435456:402653183]	109	1			T3	1		T15	1		T21	1
auto[402653184:536870911]	110	1			T2	1		T5	3		T183	1
auto[536870912:671088639]	102	1			T47	1		T121	1		T5	1
auto[671088640:805306367]	115	1			T3	4		T4	1		T15	1
auto[805306368:939524095]	94	1			T3	1		T4	1		T15	1
auto[939524096:1073741823]	95	1			T3	3		T4	1		T77	1
auto[1073741824:1207959551]	107	1			T15	1		T33	1		T51	1
auto[1207959552:1342177279]	86	1			T3	1		T79	1		T76	1
auto[1342177280:1476395007]	100	1			T3	1		T15	1		T79	1
auto[1476395008:1610612735]	117	1			T2	1		T3	3		T77	1
auto[1610612736:1744830463]	90	1			T3	2		T11	1		T15	1
auto[1744830464:1879048191]	115	1			T15	2		T33	1		T51	1
auto[1879048192:2013265919]	109	1			T119	2		T52	1		T51	1
auto[2013265920:2147483647]	125	1			T2	1		T3	2		T11	1
auto[2147483648:2281701375]	91	1			T3	1		T15	1		T21	1
auto[2281701376:2415919103]	96	1			T3	2		T13	1		T121	1
auto[2415919104:2550136831]	127	1			T3	4		T13	1		T119	1
auto[2550136832:2684354559]	117	1			T3	1		T15	1		T33	1
auto[2684354560:2818572287]	112	1			T3	2		T46	1		T74	1
auto[2818572288:2952790015]	118	1			T3	1		T21	1		T52	3
auto[2952790016:3087007743]	102	1			T2	1		T3	2		T11	1
auto[3087007744:3221225471]	101	1			T5	4		T60	1		T134	1
auto[3221225472:3355443199]	97	1			T3	2		T15	1		T33	2
auto[3355443200:3489660927]	108	1			T3	3		T15	1		T78	1
auto[3489660928:3623878655]	83	1			T3	1		T13	1		T15	1
auto[3623878656:3758096383]	108	1			T47	1		T52	1		T5	2
auto[3758096384:3892314111]	104	1			T3	1		T77	1		T79	1
auto[3892314112:4026531839]	106	1			T3	6		T4	1		T15	2
auto[4026531840:4160749567]	122	1			T2	1		T3	4		T15	1
auto[4160749568:4294967295]	112	1			T3	1		T13	1		T57	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	46	1			T5	1		T40	1		T251	1
auto[0:134217727]	auto[1]	53	1			T15	1		T77	1		T6	1
auto[134217728:268435455]	auto[0]	40	1			T3	2		T113	1		T22	1
auto[134217728:268435455]	auto[1]	49	1			T119	1		T52	1		T5	1
auto[268435456:402653183]	auto[0]	60	1			T3	1		T21	1		T60	1
auto[268435456:402653183]	auto[1]	49	1			T15	1		T74	1		T5	1
auto[402653184:536870911]	auto[0]	54	1			T2	1		T5	2		T222	1
auto[402653184:536870911]	auto[1]	56	1			T5	1		T183	1		T83	1
auto[536870912:671088639]	auto[0]	51	1			T47	1		T121	1		T183	1
auto[536870912:671088639]	auto[1]	51	1			T5	1		T183	1		T58	1
auto[671088640:805306367]	auto[0]	50	1			T3	2		T4	1		T5	1
auto[671088640:805306367]	auto[1]	65	1			T3	2		T15	1		T76	1
auto[805306368:939524095]	auto[0]	49	1			T15	1		T40	1		T63	1
auto[805306368:939524095]	auto[1]	45	1			T3	1		T4	1		T57	1
auto[939524096:1073741823]	auto[0]	45	1			T4	1		T183	2		T216	1
auto[939524096:1073741823]	auto[1]	50	1			T3	3		T77	1		T60	2
auto[1073741824:1207959551]	auto[0]	49	1			T15	1		T51	1		T18	1
auto[1073741824:1207959551]	auto[1]	58	1			T33	1		T5	1		T219	1
auto[1207959552:1342177279]	auto[0]	39	1			T79	1		T5	1		T55	1
auto[1207959552:1342177279]	auto[1]	47	1			T3	1		T76	1		T5	1
auto[1342177280:1476395007]	auto[0]	53	1			T79	1		T40	1		T183	1
auto[1342177280:1476395007]	auto[1]	47	1			T3	1		T15	1		T5	2
auto[1476395008:1610612735]	auto[0]	67	1			T3	2		T77	1		T5	1
auto[1476395008:1610612735]	auto[1]	50	1			T2	1		T3	1		T121	1
auto[1610612736:1744830463]	auto[0]	48	1			T3	2		T11	1		T5	3
auto[1610612736:1744830463]	auto[1]	42	1			T15	1		T118	1		T46	1
auto[1744830464:1879048191]	auto[0]	49	1			T15	1		T33	1		T51	1
auto[1744830464:1879048191]	auto[1]	66	1			T15	1		T76	1		T5	1
auto[1879048192:2013265919]	auto[0]	51	1			T119	1		T51	1		T183	2
auto[1879048192:2013265919]	auto[1]	58	1			T119	1		T52	1		T42	1
auto[2013265920:2147483647]	auto[0]	55	1			T3	2		T15	1		T57	2
auto[2013265920:2147483647]	auto[1]	70	1			T2	1		T11	1		T78	1
auto[2147483648:2281701375]	auto[0]	49	1			T5	1		T40	1		T216	1
auto[2147483648:2281701375]	auto[1]	42	1			T3	1		T15	1		T21	1
auto[2281701376:2415919103]	auto[0]	41	1			T121	1		T51	1		T40	2
auto[2281701376:2415919103]	auto[1]	55	1			T3	2		T13	1		T51	1
auto[2415919104:2550136831]	auto[0]	68	1			T3	2		T13	1		T119	1
auto[2415919104:2550136831]	auto[1]	59	1			T3	2		T27	1		T183	1
auto[2550136832:2684354559]	auto[0]	70	1			T3	1		T118	1		T51	1
auto[2550136832:2684354559]	auto[1]	47	1			T15	1		T33	1		T79	1
auto[2684354560:2818572287]	auto[0]	54	1			T3	1		T5	4		T49	1
auto[2684354560:2818572287]	auto[1]	58	1			T3	1		T46	1		T74	1
auto[2818572288:2952790015]	auto[0]	53	1			T52	2		T5	1		T40	1
auto[2818572288:2952790015]	auto[1]	65	1			T3	1		T21	1		T52	1
auto[2952790016:3087007743]	auto[0]	47	1			T2	1		T3	1		T47	1
auto[2952790016:3087007743]	auto[1]	55	1			T3	1		T11	1		T15	1
auto[3087007744:3221225471]	auto[0]	51	1			T5	3		T41	1		T49	1
auto[3087007744:3221225471]	auto[1]	50	1			T5	1		T60	1		T134	1
auto[3221225472:3355443199]	auto[0]	51	1			T15	1		T33	1		T77	1
auto[3221225472:3355443199]	auto[1]	46	1			T3	2		T33	1		T78	1
auto[3355443200:3489660927]	auto[0]	51	1			T3	1		T15	1		T5	1
auto[3355443200:3489660927]	auto[1]	57	1			T3	2		T78	1		T5	1
auto[3489660928:3623878655]	auto[0]	43	1			T47	1		T5	1		T40	1
auto[3489660928:3623878655]	auto[1]	40	1			T3	1		T13	1		T15	1
auto[3623878656:3758096383]	auto[0]	60	1			T47	1		T52	1		T48	1
auto[3623878656:3758096383]	auto[1]	48	1			T5	2		T40	1		T183	1
auto[3758096384:3892314111]	auto[0]	50	1			T3	1		T118	1		T52	1
auto[3758096384:3892314111]	auto[1]	54	1			T77	1		T79	1		T113	1
auto[3892314112:4026531839]	auto[0]	51	1			T3	4		T4	1		T15	2
auto[3892314112:4026531839]	auto[1]	55	1			T3	2		T47	1		T121	1
auto[4026531840:4160749567]	auto[0]	64	1			T3	1		T21	1		T5	1
auto[4026531840:4160749567]	auto[1]	58	1			T2	1		T3	3		T15	1
auto[4160749568:4294967295]	auto[0]	60	1			T57	1		T18	1		T40	1
auto[4160749568:4294967295]	auto[1]	52	1			T3	1		T13	1		T6	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1671

1

T2

2

T3

20

T4

3

auto[1]

1696

1

T2

3

T3

31

T4

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	110	1			T3	3		T13	1		T51	1
auto[134217728:268435455]	119	1			T3	2		T77	1		T51	1
auto[268435456:402653183]	92	1			T2	1		T3	1		T4	1
auto[402653184:536870911]	105	1			T15	1		T33	1		T121	1
auto[536870912:671088639]	84	1			T11	1		T77	1		T40	2
auto[671088640:805306367]	107	1			T15	1		T77	1		T118	1
auto[805306368:939524095]	113	1			T3	2		T15	1		T77	1
auto[939524096:1073741823]	103	1			T3	1		T15	2		T78	2
auto[1073741824:1207959551]	116	1			T3	3		T15	1		T78	1
auto[1207959552:1342177279]	97	1			T3	3		T15	1		T47	1
auto[1342177280:1476395007]	114	1			T3	2		T46	1		T62	1
auto[1476395008:1610612735]	114	1			T3	2		T4	1		T11	1
auto[1610612736:1744830463]	105	1			T13	1		T113	1		T52	1
auto[1744830464:1879048191]	97	1			T3	1		T15	1		T52	1
auto[1879048192:2013265919]	118	1			T3	2		T52	2		T5	1
auto[2013265920:2147483647]	113	1			T2	1		T15	1		T79	1
auto[2147483648:2281701375]	98	1			T3	1		T13	1		T46	1
auto[2281701376:2415919103]	101	1			T3	4		T119	1		T52	1
auto[2415919104:2550136831]	97	1			T13	1		T15	1		T79	1
auto[2550136832:2684354559]	102	1			T3	1		T33	1		T77	1
auto[2684354560:2818572287]	118	1			T2	1		T3	2		T33	1
auto[2818572288:2952790015]	109	1			T3	3		T15	1		T119	1
auto[2952790016:3087007743]	88	1			T57	2		T51	1		T18	1
auto[3087007744:3221225471]	103	1			T3	1		T4	1		T11	1
auto[3221225472:3355443199]	110	1			T3	3		T47	1		T5	2
auto[3355443200:3489660927]	108	1			T79	1		T51	1		T40	3
auto[3489660928:3623878655]	111	1			T2	1		T3	2		T15	2
auto[3623878656:3758096383]	120	1			T3	3		T4	1		T15	2
auto[3758096384:3892314111]	96	1			T2	1		T3	2		T15	1
auto[3892314112:4026531839]	108	1			T3	1		T15	1		T74	1
auto[4026531840:4160749567]	105	1			T3	2		T5	2		T183	4
auto[4160749568:4294967295]	86	1			T3	4		T15	1		T120	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	58	1			T3	3		T51	1		T183	2
auto[0:134217727]	auto[1]	52	1			T13	1		T5	2		T35	1
auto[134217728:268435455]	auto[0]	56	1			T51	1		T5	1		T183	1
auto[134217728:268435455]	auto[1]	63	1			T3	2		T77	1		T5	2
auto[268435456:402653183]	auto[0]	53	1			T4	1		T5	1		T41	1
auto[268435456:402653183]	auto[1]	39	1			T2	1		T3	1		T15	1
auto[402653184:536870911]	auto[0]	56	1			T15	1		T33	1		T121	1
auto[402653184:536870911]	auto[1]	49	1			T5	1		T40	1		T222	1
auto[536870912:671088639]	auto[0]	44	1			T77	1		T40	1		T183	1
auto[536870912:671088639]	auto[1]	40	1			T11	1		T40	1		T63	2
auto[671088640:805306367]	auto[0]	62	1			T77	1		T118	1		T47	1
auto[671088640:805306367]	auto[1]	45	1			T15	1		T40	1		T60	1
auto[805306368:939524095]	auto[0]	50	1			T3	1		T51	1		T40	1
auto[805306368:939524095]	auto[1]	63	1			T3	1		T15	1		T77	1
auto[939524096:1073741823]	auto[0]	53	1			T3	1		T15	1		T52	1
auto[939524096:1073741823]	auto[1]	50	1			T15	1		T78	2		T119	1
auto[1073741824:1207959551]	auto[0]	58	1			T3	2		T15	1		T119	1
auto[1073741824:1207959551]	auto[1]	58	1			T3	1		T78	1		T79	2
auto[1207959552:1342177279]	auto[0]	43	1			T3	1		T90	1		T84	1
auto[1207959552:1342177279]	auto[1]	54	1			T3	2		T15	1		T47	1
auto[1342177280:1476395007]	auto[0]	53	1			T5	1		T63	1		T50	1
auto[1342177280:1476395007]	auto[1]	61	1			T3	2		T46	1		T62	1
auto[1476395008:1610612735]	auto[0]	60	1			T3	2		T4	1		T11	1
auto[1476395008:1610612735]	auto[1]	54	1			T74	1		T40	2		T60	1
auto[1610612736:1744830463]	auto[0]	53	1			T13	1		T113	1		T5	1
auto[1610612736:1744830463]	auto[1]	52	1			T52	1		T342	1		T255	1
auto[1744830464:1879048191]	auto[0]	51	1			T52	1		T5	1		T90	1
auto[1744830464:1879048191]	auto[1]	46	1			T3	1		T15	1		T27	2
auto[1879048192:2013265919]	auto[0]	65	1			T3	1		T52	2		T5	1
auto[1879048192:2013265919]	auto[1]	53	1			T3	1		T6	1		T41	1
auto[2013265920:2147483647]	auto[0]	54	1			T2	1		T51	1		T5	2
auto[2013265920:2147483647]	auto[1]	59	1			T15	1		T79	1		T113	1
auto[2147483648:2281701375]	auto[0]	49	1			T46	1		T57	1		T40	1
auto[2147483648:2281701375]	auto[1]	49	1			T3	1		T13	1		T52	1
auto[2281701376:2415919103]	auto[0]	51	1			T3	2		T119	1		T23	1
auto[2281701376:2415919103]	auto[1]	50	1			T3	2		T52	1		T231	1
auto[2415919104:2550136831]	auto[0]	52	1			T52	1		T5	2		T90	1
auto[2415919104:2550136831]	auto[1]	45	1			T13	1		T15	1		T79	1
auto[2550136832:2684354559]	auto[0]	45	1			T33	1		T121	1		T5	2
auto[2550136832:2684354559]	auto[1]	57	1			T3	1		T77	1		T21	1
auto[2684354560:2818572287]	auto[0]	58	1			T2	1		T3	1		T119	1
auto[2684354560:2818572287]	auto[1]	60	1			T3	1		T33	1		T76	1
auto[2818572288:2952790015]	auto[0]	54	1			T3	1		T15	1		T18	1
auto[2818572288:2952790015]	auto[1]	55	1			T3	2		T119	1		T51	1
auto[2952790016:3087007743]	auto[0]	51	1			T57	1		T51	1		T18	1
auto[2952790016:3087007743]	auto[1]	37	1			T57	1		T183	1		T55	1
auto[3087007744:3221225471]	auto[0]	43	1			T3	1		T4	1		T47	1
auto[3087007744:3221225471]	auto[1]	60	1			T11	1		T33	1		T77	1
auto[3221225472:3355443199]	auto[0]	54	1			T47	1		T5	2		T40	1
auto[3221225472:3355443199]	auto[1]	56	1			T3	3		T231	1		T183	2
auto[3355443200:3489660927]	auto[0]	53	1			T40	2		T216	1		T342	1
auto[3355443200:3489660927]	auto[1]	55	1			T79	1		T51	1		T40	1
auto[3489660928:3623878655]	auto[0]	50	1			T3	1		T51	1		T183	2
auto[3489660928:3623878655]	auto[1]	61	1			T2	1		T3	1		T15	2
auto[3623878656:3758096383]	auto[0]	60	1			T3	1		T15	2		T118	1
auto[3623878656:3758096383]	auto[1]	60	1			T3	2		T4	1		T33	1
auto[3758096384:3892314111]	auto[0]	45	1			T21	1		T5	2		T41	1
auto[3758096384:3892314111]	auto[1]	51	1			T2	1		T3	2		T15	1
auto[3892314112:4026531839]	auto[0]	46	1			T15	1		T40	1		T60	1
auto[3892314112:4026531839]	auto[1]	62	1			T3	1		T74	1		T40	1
auto[4026531840:4160749567]	auto[0]	56	1			T3	1		T183	1		T217	1
auto[4026531840:4160749567]	auto[1]	49	1			T3	1		T5	2		T183	3
auto[4160749568:4294967295]	auto[0]	35	1			T3	1		T15	1		T120	1
auto[4160749568:4294967295]	auto[1]	51	1			T3	3		T121	1		T183	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1661

1

T2

1

T3

23

T4

3

auto[1]

1707

1

T2

4

T3

28

T4

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	99	1			T3	2		T15	1		T121	1
auto[134217728:268435455]	110	1			T118	1		T46	1		T57	1
auto[268435456:402653183]	117	1			T3	3		T47	1		T5	1
auto[402653184:536870911]	122	1			T3	4		T13	1		T77	1
auto[536870912:671088639]	113	1			T3	2		T15	1		T57	1
auto[671088640:805306367]	124	1			T3	3		T15	1		T121	1
auto[805306368:939524095]	92	1			T2	1		T15	2		T79	1
auto[939524096:1073741823]	92	1			T3	1		T52	1		T27	1
auto[1073741824:1207959551]	91	1			T78	1		T21	1		T52	1
auto[1207959552:1342177279]	96	1			T3	3		T21	1		T118	1
auto[1342177280:1476395007]	104	1			T3	4		T77	2		T27	1
auto[1476395008:1610612735]	103	1			T2	1		T33	1		T5	4
auto[1610612736:1744830463]	112	1			T3	1		T15	1		T79	2
auto[1744830464:1879048191]	98	1			T77	1		T21	1		T120	1
auto[1879048192:2013265919]	91	1			T2	1		T3	1		T15	3
auto[2013265920:2147483647]	109	1			T3	1		T33	1		T119	1
auto[2147483648:2281701375]	91	1			T13	1		T15	1		T57	1
auto[2281701376:2415919103]	123	1			T13	2		T33	1		T79	1
auto[2415919104:2550136831]	90	1			T3	3		T4	1		T15	1
auto[2550136832:2684354559]	95	1			T2	1		T3	2		T15	1
auto[2684354560:2818572287]	110	1			T15	2		T62	1		T5	3
auto[2818572288:2952790015]	120	1			T3	2		T4	1		T11	1
auto[2952790016:3087007743]	110	1			T3	3		T15	1		T113	1
auto[3087007744:3221225471]	112	1			T3	2		T33	1		T5	1
auto[3221225472:3355443199]	104	1			T3	1		T15	1		T78	1
auto[3355443200:3489660927]	118	1			T3	2		T77	1		T52	2
auto[3489660928:3623878655]	115	1			T3	2		T46	1		T121	1
auto[3623878656:3758096383]	100	1			T3	2		T4	1		T11	2
auto[3758096384:3892314111]	87	1			T3	1		T15	1		T119	1
auto[3892314112:4026531839]	95	1			T2	1		T3	2		T118	1
auto[4026531840:4160749567]	104	1			T3	3		T4	1		T47	1
auto[4160749568:4294967295]	121	1			T3	1		T113	1		T51	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	57	1			T15	1		T121	1		T5	1
auto[0:134217727]	auto[1]	42	1			T3	2		T5	1		T60	1
auto[134217728:268435455]	auto[0]	58	1			T118	1		T57	1		T51	1
auto[134217728:268435455]	auto[1]	52	1			T46	1		T60	1		T63	2
auto[268435456:402653183]	auto[0]	55	1			T47	1		T183	1		T22	1
auto[268435456:402653183]	auto[1]	62	1			T3	3		T5	1		T40	1
auto[402653184:536870911]	auto[0]	61	1			T3	3		T77	1		T21	1
auto[402653184:536870911]	auto[1]	61	1			T3	1		T13	1		T5	1
auto[536870912:671088639]	auto[0]	55	1			T3	1		T51	1		T5	1
auto[536870912:671088639]	auto[1]	58	1			T3	1		T15	1		T57	1
auto[671088640:805306367]	auto[0]	68	1			T3	2		T5	1		T183	3
auto[671088640:805306367]	auto[1]	56	1			T3	1		T15	1		T121	1
auto[805306368:939524095]	auto[0]	40	1			T79	1		T175	1		T194	1
auto[805306368:939524095]	auto[1]	52	1			T2	1		T15	2		T118	1
auto[939524096:1073741823]	auto[0]	44	1			T51	1		T5	1		T40	1
auto[939524096:1073741823]	auto[1]	48	1			T3	1		T52	1		T27	1
auto[1073741824:1207959551]	auto[0]	52	1			T52	1		T40	1		T64	1
auto[1073741824:1207959551]	auto[1]	39	1			T78	1		T21	1		T40	1
auto[1207959552:1342177279]	auto[0]	51	1			T3	2		T118	1		T119	1
auto[1207959552:1342177279]	auto[1]	45	1			T3	1		T21	1		T5	2
auto[1342177280:1476395007]	auto[0]	49	1			T3	1		T18	1		T40	1
auto[1342177280:1476395007]	auto[1]	55	1			T3	3		T77	2		T27	1
auto[1476395008:1610612735]	auto[0]	49	1			T2	1		T33	1		T5	2
auto[1476395008:1610612735]	auto[1]	54	1			T5	2		T135	1		T216	1
auto[1610612736:1744830463]	auto[0]	55	1			T3	1		T15	1		T60	1
auto[1610612736:1744830463]	auto[1]	57	1			T79	2		T5	1		T216	1
auto[1744830464:1879048191]	auto[0]	52	1			T21	1		T120	1		T121	1
auto[1744830464:1879048191]	auto[1]	46	1			T77	1		T5	1		T40	1
auto[1879048192:2013265919]	auto[0]	48	1			T3	1		T15	2		T74	1
auto[1879048192:2013265919]	auto[1]	43	1			T2	1		T15	1		T78	1
auto[2013265920:2147483647]	auto[0]	53	1			T3	1		T47	1		T52	1
auto[2013265920:2147483647]	auto[1]	56	1			T33	1		T119	1		T63	2
auto[2147483648:2281701375]	auto[0]	40	1			T40	1		T183	1		T42	1
auto[2147483648:2281701375]	auto[1]	51	1			T13	1		T15	1		T57	1
auto[2281701376:2415919103]	auto[0]	53	1			T13	1		T183	1		T135	1
auto[2281701376:2415919103]	auto[1]	70	1			T13	1		T33	1		T79	1
auto[2415919104:2550136831]	auto[0]	52	1			T3	2		T4	1		T40	2
auto[2415919104:2550136831]	auto[1]	38	1			T3	1		T15	1		T77	1
auto[2550136832:2684354559]	auto[0]	48	1			T47	1		T22	1		T63	1
auto[2550136832:2684354559]	auto[1]	47	1			T2	1		T3	2		T15	1
auto[2684354560:2818572287]	auto[0]	46	1			T15	1		T5	2		T60	1
auto[2684354560:2818572287]	auto[1]	64	1			T15	1		T62	1		T5	1
auto[2818572288:2952790015]	auto[0]	52	1			T33	1		T5	1		T22	1
auto[2818572288:2952790015]	auto[1]	68	1			T3	2		T4	1		T11	1
auto[2952790016:3087007743]	auto[0]	52	1			T3	2		T113	1		T57	1
auto[2952790016:3087007743]	auto[1]	58	1			T3	1		T15	1		T51	1
auto[3087007744:3221225471]	auto[0]	54	1			T3	1		T183	1		T63	1
auto[3087007744:3221225471]	auto[1]	58	1			T3	1		T33	1		T5	1
auto[3221225472:3355443199]	auto[0]	47	1			T15	1		T52	1		T18	1
auto[3221225472:3355443199]	auto[1]	57	1			T3	1		T78	1		T119	1
auto[3355443200:3489660927]	auto[0]	59	1			T3	1		T52	1		T51	1
auto[3355443200:3489660927]	auto[1]	59	1			T3	1		T77	1		T52	1
auto[3489660928:3623878655]	auto[0]	58	1			T3	1		T5	1		T40	3
auto[3489660928:3623878655]	auto[1]	57	1			T3	1		T46	1		T121	1
auto[3623878656:3758096383]	auto[0]	58	1			T3	1		T4	1		T11	2
auto[3623878656:3758096383]	auto[1]	42	1			T3	1		T15	1		T183	1
auto[3758096384:3892314111]	auto[0]	44	1			T119	1		T40	1		T183	1
auto[3758096384:3892314111]	auto[1]	43	1			T3	1		T15	1		T121	1
auto[3892314112:4026531839]	auto[0]	44	1			T3	1		T52	1		T5	1
auto[3892314112:4026531839]	auto[1]	51	1			T2	1		T3	1		T118	1
auto[4026531840:4160749567]	auto[0]	51	1			T3	2		T4	1		T51	1
auto[4026531840:4160749567]	auto[1]	53	1			T3	1		T47	1		T76	1
auto[4160749568:4294967295]	auto[0]	56	1			T51	1		T40	1		T60	1
auto[4160749568:4294967295]	auto[1]	65	1			T3	1		T113	1		T18	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1640

1

T2

2

T3

16

T4

3

auto[1]

1727

1

T2

3

T3

35

T4

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	92	1			T3	2		T15	2		T119	1
auto[134217728:268435455]	115	1			T2	1		T3	5		T51	2
auto[268435456:402653183]	107	1			T3	5		T4	1		T15	1
auto[402653184:536870911]	113	1			T3	2		T51	1		T5	1
auto[536870912:671088639]	108	1			T3	2		T79	1		T118	1
auto[671088640:805306367]	115	1			T3	3		T21	1		T121	1
auto[805306368:939524095]	99	1			T3	1		T79	1		T47	1
auto[939524096:1073741823]	113	1			T5	2		T40	1		T60	1
auto[1073741824:1207959551]	107	1			T2	1		T11	1		T77	1
auto[1207959552:1342177279]	66	1			T3	2		T15	1		T77	1
auto[1342177280:1476395007]	100	1			T4	1		T13	1		T15	1
auto[1476395008:1610612735]	115	1			T3	3		T15	1		T79	1
auto[1610612736:1744830463]	90	1			T2	1		T3	1		T15	2
auto[1744830464:1879048191]	101	1			T15	2		T33	2		T118	1
auto[1879048192:2013265919]	104	1			T2	1		T3	1		T15	1
auto[2013265920:2147483647]	95	1			T3	1		T13	1		T78	1
auto[2147483648:2281701375]	131	1			T2	1		T3	3		T15	1
auto[2281701376:2415919103]	110	1			T4	1		T77	1		T79	1
auto[2415919104:2550136831]	121	1			T3	2		T15	1		T51	1
auto[2550136832:2684354559]	112	1			T3	2		T15	1		T76	1
auto[2684354560:2818572287]	109	1			T3	2		T33	1		T52	1
auto[2818572288:2952790015]	127	1			T3	1		T11	2		T15	1
auto[2952790016:3087007743]	113	1			T3	2		T15	1		T52	1
auto[3087007744:3221225471]	105	1			T3	2		T5	1		T6	1
auto[3221225472:3355443199]	106	1			T3	1		T52	1		T51	2
auto[3355443200:3489660927]	95	1			T3	1		T15	1		T51	1
auto[3489660928:3623878655]	94	1			T3	2		T13	1		T78	1
auto[3623878656:3758096383]	94	1			T3	1		T15	1		T33	1
auto[3758096384:3892314111]	123	1			T4	1		T33	1		T52	1
auto[3892314112:4026531839]	100	1			T3	2		T76	1		T5	2
auto[4026531840:4160749567]	86	1			T3	1		T13	1		T79	1
auto[4160749568:4294967295]	101	1			T3	1		T15	1		T77	1