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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4561 1 T2 6 T3 72 T4 6
auto[1] 2176 1 T2 4 T3 30 T4 2



Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 220 1 T3 2 T78 2 T46 2
auto[134217728:268435455] 194 1 T3 6 T119 2 T120 2
auto[268435456:402653183] 200 1 T3 4 T15 2 T33 2
auto[402653184:536870911] 176 1 T3 2 T77 2 T57 2
auto[536870912:671088639] 212 1 T2 4 T3 4 T5 4
auto[671088640:805306367] 182 1 T119 2 T121 2 T5 2
auto[805306368:939524095] 214 1 T2 2 T33 2 T78 2
auto[939524096:1073741823] 246 1 T3 2 T13 2 T47 2
auto[1073741824:1207959551] 201 1 T3 2 T15 2 T183 2
auto[1207959552:1342177279] 252 1 T13 2 T79 2 T27 2
auto[1342177280:1476395007] 218 1 T3 8 T33 2 T77 4
auto[1476395008:1610612735] 186 1 T3 2 T118 2 T52 2
auto[1610612736:1744830463] 186 1 T4 2 T15 2 T33 2
auto[1744830464:1879048191] 206 1 T3 10 T4 2 T13 2
auto[1879048192:2013265919] 208 1 T77 2 T78 2 T21 2
auto[2013265920:2147483647] 226 1 T3 4 T15 2 T77 2
auto[2147483648:2281701375] 220 1 T3 2 T57 2 T5 2
auto[2281701376:2415919103] 196 1 T3 2 T4 2 T118 2
auto[2415919104:2550136831] 202 1 T3 6 T15 4 T77 2
auto[2550136832:2684354559] 186 1 T52 2 T5 6 T63 2
auto[2684354560:2818572287] 224 1 T3 4 T15 2 T113 2
auto[2818572288:2952790015] 196 1 T15 4 T5 4 T6 4
auto[2952790016:3087007743] 212 1 T11 6 T5 4 T6 2
auto[3087007744:3221225471] 170 1 T3 4 T79 2 T121 2
auto[3221225472:3355443199] 228 1 T3 6 T15 4 T79 2
auto[3355443200:3489660927] 242 1 T3 2 T46 2 T57 2
auto[3489660928:3623878655] 204 1 T2 2 T3 4 T47 2
auto[3623878656:3758096383] 232 1 T3 8 T15 4 T21 2
auto[3758096384:3892314111] 230 1 T2 2 T3 4 T13 2
auto[3892314112:4026531839] 186 1 T3 6 T15 2 T33 2
auto[4026531840:4160749567] 230 1 T3 8 T4 2 T15 2
auto[4160749568:4294967295] 252 1 T15 2 T52 2 T5 8



Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 168 1 T3 2 T78 2 T46 2
auto[0:134217727] auto[1] 52 1 T5 2 T48 2 T82 2
auto[134217728:268435455] auto[0] 124 1 T3 4 T119 2 T40 2
auto[134217728:268435455] auto[1] 70 1 T3 2 T120 2 T5 2
auto[268435456:402653183] auto[0] 124 1 T3 4 T33 2 T21 2
auto[268435456:402653183] auto[1] 76 1 T15 2 T74 2 T40 2
auto[402653184:536870911] auto[0] 112 1 T3 2 T77 2 T5 2
auto[402653184:536870911] auto[1] 64 1 T57 2 T62 2 T60 2
auto[536870912:671088639] auto[0] 144 1 T2 2 T3 4 T5 2
auto[536870912:671088639] auto[1] 68 1 T2 2 T5 2 T6 2
auto[671088640:805306367] auto[0] 110 1 T121 2 T222 2 T175 2
auto[671088640:805306367] auto[1] 72 1 T119 2 T5 2 T60 2
auto[805306368:939524095] auto[0] 144 1 T2 2 T78 2 T121 2
auto[805306368:939524095] auto[1] 70 1 T33 2 T5 4 T40 2
auto[939524096:1073741823] auto[0] 158 1 T3 2 T13 2 T27 2
auto[939524096:1073741823] auto[1] 88 1 T47 2 T52 2 T5 2
auto[1073741824:1207959551] auto[0] 151 1 T15 2 T183 2 T216 2
auto[1073741824:1207959551] auto[1] 50 1 T3 2 T375 2 T94 2
auto[1207959552:1342177279] auto[0] 156 1 T79 2 T5 2 T40 2
auto[1207959552:1342177279] auto[1] 96 1 T13 2 T27 2 T51 2
auto[1342177280:1476395007] auto[0] 152 1 T3 8 T77 4 T57 2
auto[1342177280:1476395007] auto[1] 66 1 T33 2 T118 2 T5 2
auto[1476395008:1610612735] auto[0] 120 1 T76 2 T18 2 T183 2
auto[1476395008:1610612735] auto[1] 66 1 T3 2 T118 2 T52 2
auto[1610612736:1744830463] auto[0] 142 1 T4 2 T15 2 T33 2
auto[1610612736:1744830463] auto[1] 44 1 T84 2 T49 2 T50 2
auto[1744830464:1879048191] auto[0] 140 1 T3 4 T13 2 T15 2
auto[1744830464:1879048191] auto[1] 66 1 T3 6 T4 2 T49 2
auto[1879048192:2013265919] auto[0] 144 1 T78 2 T21 2 T76 2
auto[1879048192:2013265919] auto[1] 64 1 T77 2 T118 2 T5 4
auto[2013265920:2147483647] auto[0] 162 1 T3 4 T15 2 T77 2
auto[2013265920:2147483647] auto[1] 64 1 T42 2 T250 2 T239 2
auto[2147483648:2281701375] auto[0] 130 1 T3 2 T57 2 T40 2
auto[2147483648:2281701375] auto[1] 90 1 T5 2 T40 2 T60 2
auto[2281701376:2415919103] auto[0] 138 1 T3 2 T4 2 T52 2
auto[2281701376:2415919103] auto[1] 58 1 T118 2 T41 2 T230 2
auto[2415919104:2550136831] auto[0] 130 1 T3 6 T15 4 T77 2
auto[2415919104:2550136831] auto[1] 72 1 T40 4 T60 2 T134 2
auto[2550136832:2684354559] auto[0] 114 1 T5 4 T58 2 T223 2
auto[2550136832:2684354559] auto[1] 72 1 T52 2 T5 2 T63 2
auto[2684354560:2818572287] auto[0] 156 1 T3 4 T15 2 T113 2
auto[2684354560:2818572287] auto[1] 68 1 T18 2 T183 2 T22 2
auto[2818572288:2952790015] auto[0] 152 1 T15 2 T5 4 T6 4
auto[2818572288:2952790015] auto[1] 44 1 T15 2 T183 2 T49 4
auto[2952790016:3087007743] auto[0] 152 1 T11 4 T5 4 T6 2
auto[2952790016:3087007743] auto[1] 60 1 T11 2 T63 2 T194 2
auto[3087007744:3221225471] auto[0] 120 1 T3 2 T121 2 T5 2
auto[3087007744:3221225471] auto[1] 50 1 T3 2 T79 2 T40 4
auto[3221225472:3355443199] auto[0] 148 1 T3 6 T15 4 T79 2
auto[3221225472:3355443199] auto[1] 80 1 T21 2 T40 4 T63 2
auto[3355443200:3489660927] auto[0] 168 1 T3 2 T51 2 T183 2
auto[3355443200:3489660927] auto[1] 74 1 T46 2 T57 2 T60 2
auto[3489660928:3623878655] auto[0] 132 1 T3 2 T47 2 T183 2
auto[3489660928:3623878655] auto[1] 72 1 T2 2 T3 2 T51 2
auto[3623878656:3758096383] auto[0] 158 1 T3 6 T21 2 T47 2
auto[3623878656:3758096383] auto[1] 74 1 T3 2 T15 4 T76 2
auto[3758096384:3892314111] auto[0] 150 1 T2 2 T3 2 T13 2
auto[3758096384:3892314111] auto[1] 80 1 T3 2 T15 2 T40 2
auto[3892314112:4026531839] auto[0] 124 1 T3 2 T15 2 T33 2
auto[3892314112:4026531839] auto[1] 62 1 T3 4 T183 2 T234 4
auto[4026531840:4160749567] auto[0] 166 1 T3 2 T4 2 T15 2
auto[4026531840:4160749567] auto[1] 64 1 T3 6 T5 2 T41 2
auto[4160749568:4294967295] auto[0] 172 1 T15 2 T52 2 T5 8
auto[4160749568:4294967295] auto[1] 80 1 T60 2 T42 2 T63 2

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