Unified Coverage Report :: Group Instance : salt_4

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2976

1

T2

5

T3

47

T4

4

auto[1]

300

1

T2

6

T77

1

T78

10

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	101	1			T3	2		T21	1		T121	1
auto[134217728:268435455]	109	1			T2	2		T3	1		T11	1
auto[268435456:402653183]	119	1			T3	3		T77	1		T78	1
auto[402653184:536870911]	106	1			T2	1		T4	1		T15	1
auto[536870912:671088639]	98	1			T3	1		T78	1		T119	1
auto[671088640:805306367]	103	1			T3	3		T15	1		T52	2
auto[805306368:939524095]	94	1			T3	1		T4	1		T79	2
auto[939524096:1073741823]	122	1			T2	1		T4	1		T77	1
auto[1073741824:1207959551]	105	1			T3	3		T15	1		T113	1
auto[1207959552:1342177279]	85	1			T15	1		T134	2		T183	2
auto[1342177280:1476395007]	105	1			T33	1		T78	1		T79	1
auto[1476395008:1610612735]	90	1			T3	2		T15	1		T79	1
auto[1610612736:1744830463]	87	1			T78	1		T18	1		T5	1
auto[1744830464:1879048191]	96	1			T2	1		T3	2		T13	1
auto[1879048192:2013265919]	111	1			T2	1		T3	1		T11	1
auto[2013265920:2147483647]	110	1			T3	4		T15	2		T33	1
auto[2147483648:2281701375]	109	1			T3	1		T77	1		T47	1
auto[2281701376:2415919103]	87	1			T3	2		T4	1		T78	1
auto[2415919104:2550136831]	103	1			T2	1		T3	3		T15	1
auto[2550136832:2684354559]	103	1			T13	1		T78	1		T21	1
auto[2684354560:2818572287]	108	1			T3	3		T51	1		T60	1
auto[2818572288:2952790015]	88	1			T121	1		T62	1		T5	1
auto[2952790016:3087007743]	105	1			T3	2		T15	1		T78	3
auto[3087007744:3221225471]	126	1			T2	2		T33	1		T77	2
auto[3221225472:3355443199]	106	1			T15	1		T77	2		T78	1
auto[3355443200:3489660927]	98	1			T3	2		T11	1		T15	1
auto[3489660928:3623878655]	91	1			T2	1		T3	1		T33	1
auto[3623878656:3758096383]	107	1			T3	1		T13	1		T47	1
auto[3758096384:3892314111]	88	1			T3	1		T6	2		T40	1
auto[3892314112:4026531839]	99	1			T3	2		T78	1		T79	1
auto[4026531840:4160749567]	117	1			T3	4		T79	1		T21	1
auto[4160749568:4294967295]	100	1			T2	1		T3	2		T15	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	93	1			T3	2		T21	1		T51	1
auto[0:134217727]	auto[1]	8	1			T121	1		T122	1		T244	1
auto[134217728:268435455]	auto[0]	98	1			T2	1		T3	1		T11	1
auto[134217728:268435455]	auto[1]	11	1			T2	1		T78	1		T121	1
auto[268435456:402653183]	auto[0]	111	1			T3	3		T77	1		T5	2
auto[268435456:402653183]	auto[1]	8	1			T78	1		T244	1		T360	1
auto[402653184:536870911]	auto[0]	92	1			T4	1		T15	1		T113	1
auto[402653184:536870911]	auto[1]	14	1			T2	1		T135	1		T244	1
auto[536870912:671088639]	auto[0]	90	1			T3	1		T119	1		T183	3
auto[536870912:671088639]	auto[1]	8	1			T78	1		T135	1		T244	1
auto[671088640:805306367]	auto[0]	94	1			T3	3		T15	1		T52	2
auto[671088640:805306367]	auto[1]	9	1			T121	1		T290	1		T123	1
auto[805306368:939524095]	auto[0]	90	1			T3	1		T4	1		T21	1
auto[805306368:939524095]	auto[1]	4	1			T79	2		T295	1		T392	1
auto[939524096:1073741823]	auto[0]	112	1			T2	1		T4	1		T77	1
auto[939524096:1073741823]	auto[1]	10	1			T240	1		T124	1		T279	1
auto[1073741824:1207959551]	auto[0]	94	1			T3	3		T15	1		T113	1
auto[1073741824:1207959551]	auto[1]	11	1			T290	1		T124	1		T247	1
auto[1207959552:1342177279]	auto[0]	73	1			T15	1		T183	2		T383	1
auto[1207959552:1342177279]	auto[1]	12	1			T134	2		T244	1		T240	3
auto[1342177280:1476395007]	auto[0]	99	1			T33	1		T79	1		T118	1
auto[1342177280:1476395007]	auto[1]	6	1			T78	1		T244	1		T123	1
auto[1476395008:1610612735]	auto[0]	83	1			T3	2		T15	1		T79	1
auto[1476395008:1610612735]	auto[1]	7	1			T244	1		T123	1		T308	1
auto[1610612736:1744830463]	auto[0]	73	1			T78	1		T18	1		T5	1
auto[1610612736:1744830463]	auto[1]	14	1			T240	2		T247	1		T386	1
auto[1744830464:1879048191]	auto[0]	92	1			T3	2		T13	1		T52	1
auto[1744830464:1879048191]	auto[1]	4	1			T2	1		T244	1		T281	1
auto[1879048192:2013265919]	auto[0]	104	1			T2	1		T3	1		T11	1
auto[1879048192:2013265919]	auto[1]	7	1			T237	1		T290	1		T368	1
auto[2013265920:2147483647]	auto[0]	98	1			T3	4		T15	2		T33	1
auto[2013265920:2147483647]	auto[1]	12	1			T121	1		T122	1		T244	1
auto[2147483648:2281701375]	auto[0]	102	1			T3	1		T77	1		T47	1
auto[2147483648:2281701375]	auto[1]	7	1			T240	1		T124	1		T247	1
auto[2281701376:2415919103]	auto[0]	74	1			T3	2		T4	1		T79	1
auto[2281701376:2415919103]	auto[1]	13	1			T78	1		T121	1		T244	1
auto[2415919104:2550136831]	auto[0]	95	1			T3	3		T15	1		T33	1
auto[2415919104:2550136831]	auto[1]	8	1			T2	1		T122	1		T259	1
auto[2550136832:2684354559]	auto[0]	93	1			T13	1		T21	1		T57	1
auto[2550136832:2684354559]	auto[1]	10	1			T78	1		T259	2		T123	1
auto[2684354560:2818572287]	auto[0]	96	1			T3	3		T51	1		T60	1
auto[2684354560:2818572287]	auto[1]	12	1			T244	1		T237	1		T240	1
auto[2818572288:2952790015]	auto[0]	74	1			T62	1		T5	1		T60	2
auto[2818572288:2952790015]	auto[1]	14	1			T121	1		T134	1		T122	1
auto[2952790016:3087007743]	auto[0]	96	1			T3	2		T15	1		T74	1
auto[2952790016:3087007743]	auto[1]	9	1			T78	3		T79	1		T240	1
auto[3087007744:3221225471]	auto[0]	117	1			T33	1		T77	1		T79	1
auto[3087007744:3221225471]	auto[1]	9	1			T2	2		T77	1		T79	1
auto[3221225472:3355443199]	auto[0]	97	1			T15	1		T77	2		T47	1
auto[3221225472:3355443199]	auto[1]	9	1			T78	1		T135	2		T240	1
auto[3355443200:3489660927]	auto[0]	84	1			T3	2		T11	1		T15	1
auto[3355443200:3489660927]	auto[1]	14	1			T79	1		T135	1		T244	1
auto[3489660928:3623878655]	auto[0]	81	1			T2	1		T3	1		T33	1
auto[3489660928:3623878655]	auto[1]	10	1			T122	1		T123	3		T382	1
auto[3623878656:3758096383]	auto[0]	98	1			T3	1		T13	1		T47	1
auto[3623878656:3758096383]	auto[1]	9	1			T244	1		T240	1		T359	1
auto[3758096384:3892314111]	auto[0]	82	1			T3	1		T6	2		T40	1
auto[3758096384:3892314111]	auto[1]	6	1			T123	2		T385	1		T391	1
auto[3892314112:4026531839]	auto[0]	90	1			T3	2		T78	1		T79	1
auto[3892314112:4026531839]	auto[1]	9	1			T135	1		T124	1		T368	1
auto[4026531840:4160749567]	auto[0]	105	1			T3	4		T21	1		T118	1
auto[4026531840:4160749567]	auto[1]	12	1			T79	1		T121	1		T240	2
auto[4160749568:4294967295]	auto[0]	96	1			T2	1		T3	2		T15	1
auto[4160749568:4294967295]	auto[1]	4	1			T328	1		T390	2		T397	1