Unified Coverage Report :: Group Instance : sealing_sw_binding_2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1657

1

T2

2

T3

19

T4

3

auto[1]

1710

1

T2

3

T3

32

T4

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	114	1			T15	2		T33	1		T78	1
auto[134217728:268435455]	118	1			T3	2		T5	2		T40	1
auto[268435456:402653183]	102	1			T3	4		T15	1		T119	2
auto[402653184:536870911]	102	1			T3	1		T15	1		T77	1
auto[536870912:671088639]	106	1			T3	2		T4	2		T15	1
auto[671088640:805306367]	102	1			T4	1		T15	1		T77	1
auto[805306368:939524095]	110	1			T2	1		T3	1		T15	1
auto[939524096:1073741823]	113	1			T3	3		T15	1		T113	1
auto[1073741824:1207959551]	117	1			T3	2		T52	1		T51	2
auto[1207959552:1342177279]	112	1			T3	1		T79	1		T46	1
auto[1342177280:1476395007]	91	1			T3	2		T33	1		T77	1
auto[1476395008:1610612735]	96	1			T3	1		T13	1		T15	1
auto[1610612736:1744830463]	114	1			T2	1		T11	1		T33	2
auto[1744830464:1879048191]	112	1			T3	5		T77	1		T5	2
auto[1879048192:2013265919]	100	1			T3	2		T47	1		T121	1
auto[2013265920:2147483647]	112	1			T3	3		T13	1		T27	1
auto[2147483648:2281701375]	102	1			T15	2		T118	1		T52	1
auto[2281701376:2415919103]	109	1			T15	1		T21	1		T118	1
auto[2415919104:2550136831]	96	1			T2	1		T3	1		T15	1
auto[2550136832:2684354559]	97	1			T3	2		T11	1		T15	1
auto[2684354560:2818572287]	117	1			T3	2		T15	1		T77	1
auto[2818572288:2952790015]	110	1			T3	3		T79	1		T121	1
auto[2952790016:3087007743]	97	1			T2	1		T3	1		T231	1
auto[3087007744:3221225471]	99	1			T3	4		T11	1		T33	1
auto[3221225472:3355443199]	99	1			T3	2		T15	1		T119	2
auto[3355443200:3489660927]	100	1			T78	1		T21	1		T47	1
auto[3489660928:3623878655]	108	1			T3	1		T13	1		T46	1
auto[3623878656:3758096383]	97	1			T119	1		T47	1		T52	1
auto[3758096384:3892314111]	113	1			T3	2		T4	1		T46	1
auto[3892314112:4026531839]	105	1			T3	1		T13	1		T15	1
auto[4026531840:4160749567]	97	1			T2	1		T3	1		T15	1
auto[4160749568:4294967295]	100	1			T3	2		T15	1		T21	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	63	1			T15	1		T33	1		T51	1
auto[0:134217727]	auto[1]	51	1			T15	1		T78	1		T40	2
auto[134217728:268435455]	auto[0]	58	1			T3	1		T5	1		T64	2
auto[134217728:268435455]	auto[1]	60	1			T3	1		T5	1		T40	1
auto[268435456:402653183]	auto[0]	45	1			T3	2		T119	2		T183	1
auto[268435456:402653183]	auto[1]	57	1			T3	2		T15	1		T60	1
auto[402653184:536870911]	auto[0]	54	1			T3	1		T62	1		T5	2
auto[402653184:536870911]	auto[1]	48	1			T15	1		T77	1		T79	1
auto[536870912:671088639]	auto[0]	58	1			T4	1		T15	1		T5	2
auto[536870912:671088639]	auto[1]	48	1			T3	2		T4	1		T74	1
auto[671088640:805306367]	auto[0]	52	1			T4	1		T18	1		T183	1
auto[671088640:805306367]	auto[1]	50	1			T15	1		T77	1		T5	1
auto[805306368:939524095]	auto[0]	57	1			T2	1		T60	1		T22	1
auto[805306368:939524095]	auto[1]	53	1			T3	1		T15	1		T78	1
auto[939524096:1073741823]	auto[0]	56	1			T113	1		T40	1		T183	1
auto[939524096:1073741823]	auto[1]	57	1			T3	3		T15	1		T121	1
auto[1073741824:1207959551]	auto[0]	59	1			T52	1		T51	1		T5	1
auto[1073741824:1207959551]	auto[1]	58	1			T3	2		T51	1		T5	1
auto[1207959552:1342177279]	auto[0]	55	1			T51	3		T5	1		T183	2
auto[1207959552:1342177279]	auto[1]	57	1			T3	1		T79	1		T46	1
auto[1342177280:1476395007]	auto[0]	40	1			T118	1		T51	1		T5	1
auto[1342177280:1476395007]	auto[1]	51	1			T3	2		T33	1		T77	1
auto[1476395008:1610612735]	auto[0]	54	1			T3	1		T118	1		T47	1
auto[1476395008:1610612735]	auto[1]	42	1			T13	1		T15	1		T27	1
auto[1610612736:1744830463]	auto[0]	52	1			T11	1		T33	1		T21	1
auto[1610612736:1744830463]	auto[1]	62	1			T2	1		T33	1		T79	2
auto[1744830464:1879048191]	auto[0]	55	1			T3	2		T77	1		T5	1
auto[1744830464:1879048191]	auto[1]	57	1			T3	3		T5	1		T40	1
auto[1879048192:2013265919]	auto[0]	60	1			T3	2		T47	1		T57	1
auto[1879048192:2013265919]	auto[1]	40	1			T121	1		T57	1		T5	2
auto[2013265920:2147483647]	auto[0]	55	1			T3	1		T5	1		T223	1
auto[2013265920:2147483647]	auto[1]	57	1			T3	2		T13	1		T27	1
auto[2147483648:2281701375]	auto[0]	52	1			T15	1		T135	1		T84	1
auto[2147483648:2281701375]	auto[1]	50	1			T15	1		T118	1		T52	1
auto[2281701376:2415919103]	auto[0]	54	1			T118	1		T120	1		T51	1
auto[2281701376:2415919103]	auto[1]	55	1			T15	1		T21	1		T76	1
auto[2415919104:2550136831]	auto[0]	37	1			T2	1		T5	1		T135	1
auto[2415919104:2550136831]	auto[1]	59	1			T3	1		T15	1		T52	1
auto[2550136832:2684354559]	auto[0]	46	1			T3	1		T15	1		T22	1
auto[2550136832:2684354559]	auto[1]	51	1			T3	1		T11	1		T5	2
auto[2684354560:2818572287]	auto[0]	55	1			T3	1		T77	1		T5	1
auto[2684354560:2818572287]	auto[1]	62	1			T3	1		T15	1		T5	2
auto[2818572288:2952790015]	auto[0]	60	1			T3	1		T121	1		T57	1
auto[2818572288:2952790015]	auto[1]	50	1			T3	2		T79	1		T5	2
auto[2952790016:3087007743]	auto[0]	39	1			T3	1		T60	1		T48	1
auto[2952790016:3087007743]	auto[1]	58	1			T2	1		T231	1		T183	2
auto[3087007744:3221225471]	auto[0]	47	1			T3	2		T11	1		T40	2
auto[3087007744:3221225471]	auto[1]	52	1			T3	2		T33	1		T183	3
auto[3221225472:3355443199]	auto[0]	47	1			T63	1		T49	1		T230	1
auto[3221225472:3355443199]	auto[1]	52	1			T3	2		T15	1		T119	2
auto[3355443200:3489660927]	auto[0]	55	1			T47	1		T5	2		T183	1
auto[3355443200:3489660927]	auto[1]	45	1			T78	1		T21	1		T5	1
auto[3489660928:3623878655]	auto[0]	54	1			T3	1		T52	1		T121	1
auto[3489660928:3623878655]	auto[1]	54	1			T13	1		T46	1		T134	1
auto[3623878656:3758096383]	auto[0]	47	1			T119	1		T47	1		T40	1
auto[3623878656:3758096383]	auto[1]	50	1			T52	1		T5	3		T63	1
auto[3758096384:3892314111]	auto[0]	52	1			T4	1		T5	1		T183	2
auto[3758096384:3892314111]	auto[1]	61	1			T3	2		T46	1		T18	1
auto[3892314112:4026531839]	auto[0]	43	1			T3	1		T13	1		T15	1
auto[3892314112:4026531839]	auto[1]	62	1			T40	1		T183	1		T63	1
auto[4026531840:4160749567]	auto[0]	46	1			T15	1		T183	1		T42	1
auto[4026531840:4160749567]	auto[1]	51	1			T2	1		T3	1		T77	1
auto[4160749568:4294967295]	auto[0]	50	1			T3	1		T21	1		T40	1
auto[4160749568:4294967295]	auto[1]	50	1			T3	1		T15	1		T47	1