Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.76 99.04 98.15 98.52 100.00 99.02 98.41 91.19


Total test records in report: 1080
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1007 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3206033832 Jul 20 07:15:11 PM PDT 24 Jul 20 07:15:13 PM PDT 24 16324395 ps
T1008 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3338727569 Jul 20 07:12:56 PM PDT 24 Jul 20 07:13:04 PM PDT 24 248835853 ps
T1009 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2165203219 Jul 20 07:12:58 PM PDT 24 Jul 20 07:13:01 PM PDT 24 302908720 ps
T1010 /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3733085457 Jul 20 07:15:03 PM PDT 24 Jul 20 07:15:05 PM PDT 24 188140197 ps
T1011 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1445955126 Jul 20 07:14:44 PM PDT 24 Jul 20 07:14:45 PM PDT 24 10355369 ps
T1012 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2342837352 Jul 20 07:15:12 PM PDT 24 Jul 20 07:15:14 PM PDT 24 24391560 ps
T1013 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.131587109 Jul 20 07:13:13 PM PDT 24 Jul 20 07:13:15 PM PDT 24 29545373 ps
T1014 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1007135496 Jul 20 07:14:05 PM PDT 24 Jul 20 07:14:08 PM PDT 24 109392915 ps
T1015 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1626047912 Jul 20 07:12:32 PM PDT 24 Jul 20 07:12:59 PM PDT 24 3884953971 ps
T1016 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.367380962 Jul 20 07:13:12 PM PDT 24 Jul 20 07:13:13 PM PDT 24 19168851 ps
T1017 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2674394748 Jul 20 07:14:44 PM PDT 24 Jul 20 07:14:47 PM PDT 24 100049778 ps
T1018 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.93099469 Jul 20 07:14:56 PM PDT 24 Jul 20 07:14:58 PM PDT 24 32478785 ps
T1019 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.3470836101 Jul 20 07:14:23 PM PDT 24 Jul 20 07:14:26 PM PDT 24 198308512 ps
T156 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2419025716 Jul 20 07:13:30 PM PDT 24 Jul 20 07:13:39 PM PDT 24 401570934 ps
T1020 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3477662480 Jul 20 07:13:17 PM PDT 24 Jul 20 07:13:22 PM PDT 24 119294399 ps
T1021 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1144988085 Jul 20 07:14:06 PM PDT 24 Jul 20 07:14:10 PM PDT 24 172321191 ps
T1022 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2635393087 Jul 20 07:14:13 PM PDT 24 Jul 20 07:14:15 PM PDT 24 51326863 ps
T1023 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2599946741 Jul 20 07:12:55 PM PDT 24 Jul 20 07:12:57 PM PDT 24 64039939 ps
T1024 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2721368433 Jul 20 07:14:23 PM PDT 24 Jul 20 07:14:25 PM PDT 24 25959554 ps
T1025 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2391975928 Jul 20 07:14:25 PM PDT 24 Jul 20 07:14:27 PM PDT 24 25828786 ps
T154 /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.3668348932 Jul 20 07:13:57 PM PDT 24 Jul 20 07:14:01 PM PDT 24 221421707 ps
T1026 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.4162698682 Jul 20 07:13:56 PM PDT 24 Jul 20 07:14:03 PM PDT 24 257726439 ps
T1027 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.287491070 Jul 20 07:13:55 PM PDT 24 Jul 20 07:13:58 PM PDT 24 291259599 ps
T1028 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.275398257 Jul 20 07:14:42 PM PDT 24 Jul 20 07:14:45 PM PDT 24 227534574 ps
T1029 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.386887243 Jul 20 07:14:06 PM PDT 24 Jul 20 07:14:07 PM PDT 24 70546125 ps
T1030 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.637709159 Jul 20 07:14:51 PM PDT 24 Jul 20 07:14:52 PM PDT 24 10194081 ps
T153 /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.216145650 Jul 20 07:13:38 PM PDT 24 Jul 20 07:13:46 PM PDT 24 1119864044 ps
T1031 /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.2931605757 Jul 20 07:14:42 PM PDT 24 Jul 20 07:14:44 PM PDT 24 41365332 ps
T1032 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.3439587102 Jul 20 07:14:06 PM PDT 24 Jul 20 07:14:08 PM PDT 24 91303880 ps
T1033 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2713141712 Jul 20 07:14:25 PM PDT 24 Jul 20 07:14:27 PM PDT 24 136784121 ps
T1034 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2883107491 Jul 20 07:12:32 PM PDT 24 Jul 20 07:12:34 PM PDT 24 11994778 ps
T1035 /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1500721122 Jul 20 07:13:03 PM PDT 24 Jul 20 07:13:07 PM PDT 24 127129356 ps
T1036 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.108663143 Jul 20 07:12:48 PM PDT 24 Jul 20 07:12:49 PM PDT 24 69428162 ps
T1037 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.865435347 Jul 20 07:14:52 PM PDT 24 Jul 20 07:14:56 PM PDT 24 122468603 ps
T155 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.2900821721 Jul 20 07:12:33 PM PDT 24 Jul 20 07:12:41 PM PDT 24 1071395813 ps
T1038 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3188754939 Jul 20 07:13:13 PM PDT 24 Jul 20 07:13:16 PM PDT 24 424109871 ps
T1039 /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2703148511 Jul 20 07:13:34 PM PDT 24 Jul 20 07:13:38 PM PDT 24 199609833 ps
T1040 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.2568635195 Jul 20 07:12:34 PM PDT 24 Jul 20 07:12:36 PM PDT 24 108480701 ps
T1041 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3100867920 Jul 20 07:12:58 PM PDT 24 Jul 20 07:13:00 PM PDT 24 319907590 ps
T1042 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1155032428 Jul 20 07:13:13 PM PDT 24 Jul 20 07:13:16 PM PDT 24 554280303 ps
T1043 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3795816538 Jul 20 07:13:19 PM PDT 24 Jul 20 07:13:27 PM PDT 24 1165554523 ps
T1044 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2841303585 Jul 20 07:14:07 PM PDT 24 Jul 20 07:14:09 PM PDT 24 41336783 ps
T1045 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.3803721317 Jul 20 07:14:07 PM PDT 24 Jul 20 07:14:09 PM PDT 24 65336210 ps
T1046 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1894917785 Jul 20 07:13:11 PM PDT 24 Jul 20 07:13:21 PM PDT 24 1849039628 ps
T1047 /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.994970998 Jul 20 07:13:50 PM PDT 24 Jul 20 07:13:53 PM PDT 24 54257204 ps
T1048 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3985930394 Jul 20 07:14:42 PM PDT 24 Jul 20 07:14:49 PM PDT 24 275594634 ps
T1049 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.1356527159 Jul 20 07:13:11 PM PDT 24 Jul 20 07:13:17 PM PDT 24 383027792 ps
T1050 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.638385737 Jul 20 07:15:01 PM PDT 24 Jul 20 07:15:03 PM PDT 24 9823086 ps
T1051 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2214521816 Jul 20 07:14:53 PM PDT 24 Jul 20 07:14:54 PM PDT 24 50733610 ps
T1052 /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.374329945 Jul 20 07:14:15 PM PDT 24 Jul 20 07:14:17 PM PDT 24 163471583 ps
T1053 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.534924139 Jul 20 07:13:19 PM PDT 24 Jul 20 07:13:28 PM PDT 24 446667346 ps
T1054 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1087150774 Jul 20 07:14:36 PM PDT 24 Jul 20 07:14:43 PM PDT 24 616410415 ps
T1055 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1020299817 Jul 20 07:13:43 PM PDT 24 Jul 20 07:13:45 PM PDT 24 44303914 ps
T1056 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1779636681 Jul 20 07:12:40 PM PDT 24 Jul 20 07:12:45 PM PDT 24 495739047 ps
T1057 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1955129254 Jul 20 07:13:56 PM PDT 24 Jul 20 07:13:57 PM PDT 24 128271969 ps
T1058 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.695736888 Jul 20 07:14:44 PM PDT 24 Jul 20 07:14:50 PM PDT 24 177990429 ps
T1059 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1784150061 Jul 20 07:14:36 PM PDT 24 Jul 20 07:14:38 PM PDT 24 206804515 ps
T1060 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1098289242 Jul 20 07:14:37 PM PDT 24 Jul 20 07:14:38 PM PDT 24 34118231 ps
T1061 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2217113313 Jul 20 07:14:35 PM PDT 24 Jul 20 07:14:37 PM PDT 24 35436430 ps
T1062 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.1822410168 Jul 20 07:12:46 PM PDT 24 Jul 20 07:12:52 PM PDT 24 262926358 ps
T1063 /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1921899081 Jul 20 07:14:26 PM PDT 24 Jul 20 07:14:28 PM PDT 24 28605297 ps
T1064 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3286328864 Jul 20 07:14:45 PM PDT 24 Jul 20 07:14:47 PM PDT 24 53061545 ps
T1065 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.64622770 Jul 20 07:14:15 PM PDT 24 Jul 20 07:14:19 PM PDT 24 46774095 ps
T1066 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2220466283 Jul 20 07:12:56 PM PDT 24 Jul 20 07:13:02 PM PDT 24 666802996 ps
T1067 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1671367945 Jul 20 07:14:24 PM PDT 24 Jul 20 07:14:34 PM PDT 24 466123023 ps
T1068 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3333044168 Jul 20 07:14:27 PM PDT 24 Jul 20 07:14:32 PM PDT 24 341344994 ps
T1069 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1910100867 Jul 20 07:12:48 PM PDT 24 Jul 20 07:12:49 PM PDT 24 9032582 ps
T1070 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.702771981 Jul 20 07:13:35 PM PDT 24 Jul 20 07:13:37 PM PDT 24 51908369 ps
T1071 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2004171529 Jul 20 07:14:52 PM PDT 24 Jul 20 07:15:01 PM PDT 24 1253039867 ps
T1072 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1573058893 Jul 20 07:14:23 PM PDT 24 Jul 20 07:14:27 PM PDT 24 105926900 ps
T1073 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.3121646971 Jul 20 07:13:56 PM PDT 24 Jul 20 07:14:01 PM PDT 24 205918300 ps
T160 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1782340313 Jul 20 07:14:25 PM PDT 24 Jul 20 07:14:29 PM PDT 24 208831796 ps
T1074 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1309909129 Jul 20 07:13:42 PM PDT 24 Jul 20 07:13:45 PM PDT 24 197242889 ps
T1075 /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2674667756 Jul 20 07:14:52 PM PDT 24 Jul 20 07:14:54 PM PDT 24 48807674 ps
T1076 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1319778090 Jul 20 07:13:57 PM PDT 24 Jul 20 07:14:12 PM PDT 24 735142539 ps
T1077 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.2186144244 Jul 20 07:15:18 PM PDT 24 Jul 20 07:15:19 PM PDT 24 33934664 ps
T1078 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.3713385752 Jul 20 07:15:02 PM PDT 24 Jul 20 07:15:03 PM PDT 24 16461231 ps
T1079 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3515435942 Jul 20 07:15:01 PM PDT 24 Jul 20 07:15:02 PM PDT 24 14500173 ps
T150 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.4125355911 Jul 20 07:14:15 PM PDT 24 Jul 20 07:14:21 PM PDT 24 134290933 ps
T1080 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.634059477 Jul 20 07:13:04 PM PDT 24 Jul 20 07:13:05 PM PDT 24 10590940 ps

Test location /workspace/coverage/default/34.keymgr_stress_all.458226351
Short name T3
Test name
Test status
Simulation time 3020049959 ps
CPU time 61.35 seconds
Started Jul 20 07:19:35 PM PDT 24
Finished Jul 20 07:21:15 PM PDT 24
Peak memory 215564 kb
Host smart-d9fa5770-adfb-4ede-b583-f05142b876d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458226351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.458226351
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.2586578643
Short name T15
Test name
Test status
Simulation time 3066353497 ps
CPU time 18 seconds
Started Jul 20 07:18:05 PM PDT 24
Finished Jul 20 07:18:39 PM PDT 24
Peak memory 222480 kb
Host smart-cda949ab-2b2c-40be-91c9-1d01e6759429
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586578643 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.2586578643
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.3570451800
Short name T5
Test name
Test status
Simulation time 3006116240 ps
CPU time 100.59 seconds
Started Jul 20 07:19:43 PM PDT 24
Finished Jul 20 07:22:03 PM PDT 24
Peak memory 216400 kb
Host smart-ecb95f66-9d7e-4810-a906-52e8b8042306
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570451800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.3570451800
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.2773356851
Short name T8
Test name
Test status
Simulation time 576513170 ps
CPU time 8.66 seconds
Started Jul 20 07:15:42 PM PDT 24
Finished Jul 20 07:15:52 PM PDT 24
Peak memory 230228 kb
Host smart-c5d5d082-cca8-4583-82a8-7358a1ddbbf5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773356851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.2773356851
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.268587423
Short name T60
Test name
Test status
Simulation time 833975107 ps
CPU time 16.44 seconds
Started Jul 20 07:16:22 PM PDT 24
Finished Jul 20 07:16:40 PM PDT 24
Peak memory 220684 kb
Host smart-0cb60627-9b8e-41f0-93a2-9fb95d13e7cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268587423 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.268587423
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.1133652058
Short name T79
Test name
Test status
Simulation time 801865607 ps
CPU time 11.42 seconds
Started Jul 20 07:18:58 PM PDT 24
Finished Jul 20 07:19:39 PM PDT 24
Peak memory 214024 kb
Host smart-28e7a9a5-4552-49ff-add8-41f3f545b4f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1133652058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.1133652058
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.1730370798
Short name T7
Test name
Test status
Simulation time 195144043 ps
CPU time 2.87 seconds
Started Jul 20 07:17:31 PM PDT 24
Finished Jul 20 07:17:36 PM PDT 24
Peak memory 210632 kb
Host smart-029cab7f-7907-4891-ae29-e94508f3a09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730370798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1730370798
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.2277162947
Short name T84
Test name
Test status
Simulation time 80863023 ps
CPU time 2.69 seconds
Started Jul 20 07:16:33 PM PDT 24
Finished Jul 20 07:16:37 PM PDT 24
Peak memory 214044 kb
Host smart-272f88ee-7025-492e-b7dc-76af67c57399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277162947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.2277162947
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.3714575618
Short name T50
Test name
Test status
Simulation time 1756484534 ps
CPU time 26.72 seconds
Started Jul 20 07:16:49 PM PDT 24
Finished Jul 20 07:17:17 PM PDT 24
Peak memory 222988 kb
Host smart-80717ce8-0f86-4479-98b8-29c11a81d314
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714575618 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.3714575618
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.2838990941
Short name T124
Test name
Test status
Simulation time 2858846383 ps
CPU time 60.63 seconds
Started Jul 20 07:16:17 PM PDT 24
Finished Jul 20 07:17:19 PM PDT 24
Peak memory 214208 kb
Host smart-b57c071f-51a7-434d-982e-8668739c2021
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2838990941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.2838990941
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.4045129290
Short name T102
Test name
Test status
Simulation time 119543720 ps
CPU time 2.49 seconds
Started Jul 20 07:12:33 PM PDT 24
Finished Jul 20 07:12:36 PM PDT 24
Peak memory 214636 kb
Host smart-b1a1daf3-55bd-4f50-8f67-c89f4f4b5423
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045129290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.4045129290
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.250116915
Short name T144
Test name
Test status
Simulation time 77857978 ps
CPU time 3.31 seconds
Started Jul 20 07:14:06 PM PDT 24
Finished Jul 20 07:14:10 PM PDT 24
Peak memory 214352 kb
Host smart-83c5bc77-f8b3-4daf-9240-eec86c208ab5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250116915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err
.250116915
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.1881391919
Short name T244
Test name
Test status
Simulation time 3979970954 ps
CPU time 108.34 seconds
Started Jul 20 07:19:19 PM PDT 24
Finished Jul 20 07:21:43 PM PDT 24
Peak memory 217444 kb
Host smart-ad6de5c7-7468-45fe-a058-cd04345509b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1881391919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.1881391919
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.1579657160
Short name T66
Test name
Test status
Simulation time 123622820711 ps
CPU time 308.46 seconds
Started Jul 20 07:19:08 PM PDT 24
Finished Jul 20 07:24:50 PM PDT 24
Peak memory 215428 kb
Host smart-fd3cdcad-0ee0-4890-8a65-a90ea775da8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579657160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.1579657160
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.4078855695
Short name T22
Test name
Test status
Simulation time 37374871 ps
CPU time 2.56 seconds
Started Jul 20 07:20:13 PM PDT 24
Finished Jul 20 07:20:52 PM PDT 24
Peak memory 209252 kb
Host smart-5f8935e6-7d53-4c94-ac99-1ca77134277c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078855695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.4078855695
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.1218119270
Short name T121
Test name
Test status
Simulation time 3537216663 ps
CPU time 97.9 seconds
Started Jul 20 07:20:27 PM PDT 24
Finished Jul 20 07:22:38 PM PDT 24
Peak memory 217620 kb
Host smart-332c4d36-9a4b-4681-b099-d40b1fba7f62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1218119270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.1218119270
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.47423236
Short name T216
Test name
Test status
Simulation time 130372876 ps
CPU time 6.27 seconds
Started Jul 20 07:21:37 PM PDT 24
Finished Jul 20 07:21:45 PM PDT 24
Peak memory 214104 kb
Host smart-1b2d2899-29fc-49a5-ac03-a37927d117a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47423236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.47423236
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.238640600
Short name T123
Test name
Test status
Simulation time 263804289 ps
CPU time 13.8 seconds
Started Jul 20 07:19:59 PM PDT 24
Finished Jul 20 07:20:54 PM PDT 24
Peak memory 214072 kb
Host smart-865f3682-9edd-4171-9a0b-a35b29fdb760
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=238640600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.238640600
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.2057828592
Short name T36
Test name
Test status
Simulation time 97881789 ps
CPU time 3.88 seconds
Started Jul 20 07:16:22 PM PDT 24
Finished Jul 20 07:16:27 PM PDT 24
Peak memory 220220 kb
Host smart-b31d9f03-eb5c-4e27-b4e6-9729132581d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057828592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.2057828592
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.2525950763
Short name T908
Test name
Test status
Simulation time 134288267 ps
CPU time 3.98 seconds
Started Jul 20 07:18:41 PM PDT 24
Finished Jul 20 07:19:12 PM PDT 24
Peak memory 222516 kb
Host smart-ff7b75f2-5a8e-4015-b1aa-76f050c8699e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525950763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.2525950763
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.794812832
Short name T27
Test name
Test status
Simulation time 60908117 ps
CPU time 3.17 seconds
Started Jul 20 07:15:42 PM PDT 24
Finished Jul 20 07:15:48 PM PDT 24
Peak memory 208168 kb
Host smart-8da9fe70-f84a-44d2-931b-7ef30aa3dfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794812832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.794812832
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.3629909320
Short name T136
Test name
Test status
Simulation time 69379707 ps
CPU time 3.63 seconds
Started Jul 20 07:18:40 PM PDT 24
Finished Jul 20 07:19:10 PM PDT 24
Peak memory 216108 kb
Host smart-38a2bee6-f416-4458-af06-23b90be7833c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629909320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.3629909320
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.35598214
Short name T98
Test name
Test status
Simulation time 643188074 ps
CPU time 6.58 seconds
Started Jul 20 07:13:26 PM PDT 24
Finished Jul 20 07:13:33 PM PDT 24
Peak memory 221548 kb
Host smart-3fee2135-4485-4bd2-a135-32018f188a36
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35598214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.ke
ymgr_shadow_reg_errors_with_csr_rw.35598214
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.495457466
Short name T63
Test name
Test status
Simulation time 207353017 ps
CPU time 11.21 seconds
Started Jul 20 07:21:36 PM PDT 24
Finished Jul 20 07:21:49 PM PDT 24
Peak memory 214524 kb
Host smart-6aad0dda-7a0c-4ed6-a405-4618abceb442
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495457466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.495457466
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.1216201681
Short name T240
Test name
Test status
Simulation time 5706355611 ps
CPU time 76.71 seconds
Started Jul 20 07:16:42 PM PDT 24
Finished Jul 20 07:18:00 PM PDT 24
Peak memory 214196 kb
Host smart-7bde6aae-ff14-4d03-8e31-2d2acd7ddf18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1216201681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.1216201681
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.1282431365
Short name T32
Test name
Test status
Simulation time 108961382 ps
CPU time 1.56 seconds
Started Jul 20 07:16:55 PM PDT 24
Finished Jul 20 07:16:57 PM PDT 24
Peak memory 210048 kb
Host smart-3c6a3312-7ec4-4065-a9fc-e7b8f86c018b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282431365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.1282431365
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.96069841
Short name T89
Test name
Test status
Simulation time 595833494 ps
CPU time 6.76 seconds
Started Jul 20 07:17:29 PM PDT 24
Finished Jul 20 07:17:39 PM PDT 24
Peak memory 214144 kb
Host smart-b7a483ae-828b-4451-8832-3b3e1aa7484e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96069841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.96069841
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.218765797
Short name T183
Test name
Test status
Simulation time 419045714 ps
CPU time 21.45 seconds
Started Jul 20 07:18:06 PM PDT 24
Finished Jul 20 07:18:44 PM PDT 24
Peak memory 220792 kb
Host smart-1653660e-3438-448b-b9e1-2b73ffc6a2f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218765797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.218765797
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.1433436423
Short name T45
Test name
Test status
Simulation time 361045380 ps
CPU time 18.28 seconds
Started Jul 20 07:17:07 PM PDT 24
Finished Jul 20 07:17:26 PM PDT 24
Peak memory 216148 kb
Host smart-40b1d9ed-b8d7-4700-9511-6d5328cf8142
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433436423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.1433436423
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.2132516404
Short name T247
Test name
Test status
Simulation time 157579036 ps
CPU time 3.62 seconds
Started Jul 20 07:18:15 PM PDT 24
Finished Jul 20 07:18:39 PM PDT 24
Peak memory 214096 kb
Host smart-1db33a91-5e4a-4356-a64e-0e03d0badaf6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2132516404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.2132516404
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.629908297
Short name T194
Test name
Test status
Simulation time 1716937865 ps
CPU time 32.17 seconds
Started Jul 20 07:20:08 PM PDT 24
Finished Jul 20 07:21:19 PM PDT 24
Peak memory 216476 kb
Host smart-bef76d80-bf27-46cb-b2b7-b88e92ba4dca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629908297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.629908297
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.464619448
Short name T334
Test name
Test status
Simulation time 34210333248 ps
CPU time 139.96 seconds
Started Jul 20 07:18:42 PM PDT 24
Finished Jul 20 07:21:29 PM PDT 24
Peak memory 214956 kb
Host smart-e1dfdfed-e99b-4074-87c7-5ebbdc030d66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=464619448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.464619448
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.4033193384
Short name T91
Test name
Test status
Simulation time 53276960 ps
CPU time 0.75 seconds
Started Jul 20 07:17:58 PM PDT 24
Finished Jul 20 07:18:08 PM PDT 24
Peak memory 205828 kb
Host smart-8638f4e2-a75d-4a54-a07f-f9289dc5e66c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033193384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.4033193384
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.3980118046
Short name T23
Test name
Test status
Simulation time 872576782 ps
CPU time 7.63 seconds
Started Jul 20 07:15:32 PM PDT 24
Finished Jul 20 07:15:40 PM PDT 24
Peak memory 214064 kb
Host smart-5cb7da3f-07ee-4f96-af37-26a8bbd1d6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980118046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.3980118046
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.1093378727
Short name T269
Test name
Test status
Simulation time 16130752304 ps
CPU time 96.25 seconds
Started Jul 20 07:16:51 PM PDT 24
Finished Jul 20 07:18:28 PM PDT 24
Peak memory 215084 kb
Host smart-d5ce181c-3e70-457d-87d5-f43a83eb67c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093378727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.1093378727
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.4033949824
Short name T135
Test name
Test status
Simulation time 73183048 ps
CPU time 4.85 seconds
Started Jul 20 07:18:22 PM PDT 24
Finished Jul 20 07:18:49 PM PDT 24
Peak memory 215248 kb
Host smart-5f3a523e-e838-4d8f-92cb-391dbfaa97a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4033949824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.4033949824
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.3942991256
Short name T78
Test name
Test status
Simulation time 144296693 ps
CPU time 7.63 seconds
Started Jul 20 07:19:39 PM PDT 24
Finished Jul 20 07:20:24 PM PDT 24
Peak memory 214072 kb
Host smart-e1e2b1b9-69a7-40fc-954d-db4dbc3d310f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3942991256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.3942991256
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.71774511
Short name T147
Test name
Test status
Simulation time 349835958 ps
CPU time 5.1 seconds
Started Jul 20 07:14:53 PM PDT 24
Finished Jul 20 07:14:59 PM PDT 24
Peak memory 206472 kb
Host smart-19394310-63e9-4531-9689-cead6b143b69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71774511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err.71774511
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.39453128
Short name T33
Test name
Test status
Simulation time 126510593 ps
CPU time 2.69 seconds
Started Jul 20 07:16:03 PM PDT 24
Finished Jul 20 07:16:06 PM PDT 24
Peak memory 214208 kb
Host smart-de31f6fa-23bd-4df4-adca-38ce9f38b7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39453128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.39453128
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.2683937390
Short name T112
Test name
Test status
Simulation time 2775629389 ps
CPU time 20.6 seconds
Started Jul 20 07:15:26 PM PDT 24
Finished Jul 20 07:15:47 PM PDT 24
Peak memory 222388 kb
Host smart-c6918c75-8776-40e5-8a5f-1105afb64163
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683937390 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.2683937390
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.421041155
Short name T122
Test name
Test status
Simulation time 1412322264 ps
CPU time 19.96 seconds
Started Jul 20 07:17:07 PM PDT 24
Finished Jul 20 07:17:28 PM PDT 24
Peak memory 215164 kb
Host smart-0d57f196-6c24-43cf-8eb5-c289634a0d4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=421041155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.421041155
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.793088568
Short name T280
Test name
Test status
Simulation time 450178087 ps
CPU time 12.4 seconds
Started Jul 20 07:17:49 PM PDT 24
Finished Jul 20 07:18:11 PM PDT 24
Peak memory 214648 kb
Host smart-2a955c8f-c872-4129-a3de-846f634ff0e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=793088568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.793088568
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.505279852
Short name T221
Test name
Test status
Simulation time 545819381 ps
CPU time 2.85 seconds
Started Jul 20 07:21:22 PM PDT 24
Finished Jul 20 07:21:26 PM PDT 24
Peak memory 222124 kb
Host smart-1735acae-3647-4f37-93ae-496e192f73dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505279852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.505279852
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.2687672710
Short name T88
Test name
Test status
Simulation time 475370692 ps
CPU time 5.91 seconds
Started Jul 20 07:15:32 PM PDT 24
Finished Jul 20 07:15:38 PM PDT 24
Peak memory 214036 kb
Host smart-47789b3b-882a-487b-b078-bca0073d9e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687672710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.2687672710
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.4278726010
Short name T143
Test name
Test status
Simulation time 151378029 ps
CPU time 4.83 seconds
Started Jul 20 07:19:19 PM PDT 24
Finished Jul 20 07:19:59 PM PDT 24
Peak memory 217284 kb
Host smart-024379dd-5ff0-43f7-9621-9514915d3299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278726010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.4278726010
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.4125355911
Short name T150
Test name
Test status
Simulation time 134290933 ps
CPU time 4.9 seconds
Started Jul 20 07:14:15 PM PDT 24
Finished Jul 20 07:14:21 PM PDT 24
Peak memory 214368 kb
Host smart-c04e7cba-b49a-4c27-9b6e-f5b445ef8224
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125355911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.4125355911
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.1849852160
Short name T380
Test name
Test status
Simulation time 146052838 ps
CPU time 2.1 seconds
Started Jul 20 07:18:41 PM PDT 24
Finished Jul 20 07:19:09 PM PDT 24
Peak memory 210032 kb
Host smart-cfab1eae-e1fa-41c2-ba5a-3e44741618a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849852160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.1849852160
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.4010994999
Short name T30
Test name
Test status
Simulation time 351307783 ps
CPU time 5.45 seconds
Started Jul 20 07:16:26 PM PDT 24
Finished Jul 20 07:16:32 PM PDT 24
Peak memory 209144 kb
Host smart-8c367dec-dc08-40f5-ba70-8a9931448a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010994999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.4010994999
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.2826241813
Short name T141
Test name
Test status
Simulation time 69252190 ps
CPU time 1.58 seconds
Started Jul 20 07:17:48 PM PDT 24
Finished Jul 20 07:17:59 PM PDT 24
Peak memory 216992 kb
Host smart-305e8c8e-c519-42d8-a0c1-8021c7941cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826241813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2826241813
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.1092108124
Short name T142
Test name
Test status
Simulation time 348027767 ps
CPU time 4.45 seconds
Started Jul 20 07:16:07 PM PDT 24
Finished Jul 20 07:16:12 PM PDT 24
Peak memory 218196 kb
Host smart-cb476f32-96fa-4d2d-a09b-6ff7cabcf3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092108124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.1092108124
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.3335592970
Short name T346
Test name
Test status
Simulation time 144513486 ps
CPU time 2.35 seconds
Started Jul 20 07:15:32 PM PDT 24
Finished Jul 20 07:15:35 PM PDT 24
Peak memory 214000 kb
Host smart-1f4813b7-d151-4d6c-aa92-11820de4fda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335592970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.3335592970
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.74938818
Short name T393
Test name
Test status
Simulation time 48433120 ps
CPU time 3.37 seconds
Started Jul 20 07:17:01 PM PDT 24
Finished Jul 20 07:17:06 PM PDT 24
Peak memory 214084 kb
Host smart-a7ad2ad5-8f64-4ac8-8fb3-2e5c74912527
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=74938818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.74938818
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.1880906874
Short name T305
Test name
Test status
Simulation time 1586078897 ps
CPU time 39.09 seconds
Started Jul 20 07:16:59 PM PDT 24
Finished Jul 20 07:17:40 PM PDT 24
Peak memory 222080 kb
Host smart-e7a68d78-4eff-4534-80d3-c2d2894653c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880906874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.1880906874
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.1939472781
Short name T49
Test name
Test status
Simulation time 2531625490 ps
CPU time 43.1 seconds
Started Jul 20 07:17:38 PM PDT 24
Finished Jul 20 07:18:25 PM PDT 24
Peak memory 216652 kb
Host smart-a09ff9b2-1e53-451c-ab3c-3e8bbc285682
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939472781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.1939472781
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.166488893
Short name T390
Test name
Test status
Simulation time 3139981263 ps
CPU time 8.45 seconds
Started Jul 20 07:21:07 PM PDT 24
Finished Jul 20 07:21:23 PM PDT 24
Peak memory 214244 kb
Host smart-344ac582-b507-4e57-9ac2-64ee06cfc6ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=166488893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.166488893
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3694926305
Short name T964
Test name
Test status
Simulation time 119555321 ps
CPU time 2.05 seconds
Started Jul 20 07:12:48 PM PDT 24
Finished Jul 20 07:12:51 PM PDT 24
Peak memory 214664 kb
Host smart-2b0c9dd7-2285-4f56-bf1f-8806f5c8452c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694926305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.3694926305
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2132760944
Short name T158
Test name
Test status
Simulation time 516619585 ps
CPU time 6.28 seconds
Started Jul 20 07:14:23 PM PDT 24
Finished Jul 20 07:14:29 PM PDT 24
Peak memory 214340 kb
Host smart-aae044cd-0439-4454-8050-28ae613acf15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132760944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.2132760944
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.898194294
Short name T149
Test name
Test status
Simulation time 1391767527 ps
CPU time 12.22 seconds
Started Jul 20 07:14:53 PM PDT 24
Finished Jul 20 07:15:06 PM PDT 24
Peak memory 214492 kb
Host smart-1a20142c-4c2b-4954-b5bb-0fc920af9410
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898194294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err
.898194294
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2192112985
Short name T152
Test name
Test status
Simulation time 265994223 ps
CPU time 5.77 seconds
Started Jul 20 07:13:13 PM PDT 24
Finished Jul 20 07:13:19 PM PDT 24
Peak memory 214376 kb
Host smart-795622d0-09cc-43dc-9922-8176c0a97c7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192112985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.2192112985
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2419025716
Short name T156
Test name
Test status
Simulation time 401570934 ps
CPU time 8.36 seconds
Started Jul 20 07:13:30 PM PDT 24
Finished Jul 20 07:13:39 PM PDT 24
Peak memory 214560 kb
Host smart-77770003-6c3c-420a-8540-3fea14e6ad71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419025716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.2419025716
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.787813842
Short name T31
Test name
Test status
Simulation time 85833013 ps
CPU time 2.3 seconds
Started Jul 20 07:20:26 PM PDT 24
Finished Jul 20 07:21:01 PM PDT 24
Peak memory 218332 kb
Host smart-3e427982-89ee-4f31-970d-d6470f9a1166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787813842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.787813842
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.2953171427
Short name T343
Test name
Test status
Simulation time 94053525 ps
CPU time 2.12 seconds
Started Jul 20 07:16:49 PM PDT 24
Finished Jul 20 07:16:53 PM PDT 24
Peak memory 214336 kb
Host smart-980ec258-babe-4794-b6ce-5d3ed86206ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953171427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.2953171427
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.1636047541
Short name T261
Test name
Test status
Simulation time 41087730 ps
CPU time 2.61 seconds
Started Jul 20 07:18:31 PM PDT 24
Finished Jul 20 07:18:59 PM PDT 24
Peak memory 208456 kb
Host smart-c7bc13ed-c078-4a84-915a-2a747e47d162
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636047541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.1636047541
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.2490422433
Short name T278
Test name
Test status
Simulation time 80644879 ps
CPU time 3.24 seconds
Started Jul 20 07:20:56 PM PDT 24
Finished Jul 20 07:21:13 PM PDT 24
Peak memory 215268 kb
Host smart-3adf1114-3ad0-46f9-ace1-261f022e5d47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2490422433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.2490422433
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.122596073
Short name T42
Test name
Test status
Simulation time 85625756 ps
CPU time 1.8 seconds
Started Jul 20 07:21:34 PM PDT 24
Finished Jul 20 07:21:36 PM PDT 24
Peak memory 214000 kb
Host smart-fc6c04d6-ba21-4f60-819e-a83182fb08fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122596073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.122596073
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.1987276021
Short name T137
Test name
Test status
Simulation time 275838652 ps
CPU time 4.45 seconds
Started Jul 20 07:17:42 PM PDT 24
Finished Jul 20 07:17:55 PM PDT 24
Peak memory 217452 kb
Host smart-899e6e5f-5694-423e-b71e-1f34b6e33f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987276021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1987276021
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.133578109
Short name T140
Test name
Test status
Simulation time 80110566 ps
CPU time 3.13 seconds
Started Jul 20 07:19:40 PM PDT 24
Finished Jul 20 07:20:21 PM PDT 24
Peak memory 216340 kb
Host smart-12a79085-aca4-4c16-a411-9b7069e33b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133578109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.133578109
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2266862534
Short name T138
Test name
Test status
Simulation time 293025035 ps
CPU time 4.87 seconds
Started Jul 20 07:19:53 PM PDT 24
Finished Jul 20 07:20:36 PM PDT 24
Peak memory 222376 kb
Host smart-3d2aebd9-fe32-490b-91c8-e24bd734336a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266862534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2266862534
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.918052325
Short name T139
Test name
Test status
Simulation time 49777376 ps
CPU time 2.67 seconds
Started Jul 20 07:21:24 PM PDT 24
Finished Jul 20 07:21:28 PM PDT 24
Peak memory 222520 kb
Host smart-17439082-058e-4da4-a85a-07bd871e0fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918052325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.918052325
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.3815005542
Short name T26
Test name
Test status
Simulation time 297492718 ps
CPU time 6.03 seconds
Started Jul 20 07:16:49 PM PDT 24
Finished Jul 20 07:16:57 PM PDT 24
Peak memory 209760 kb
Host smart-5ebab5fc-715f-47ca-bb06-976416c831af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815005542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.3815005542
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.1758560181
Short name T314
Test name
Test status
Simulation time 78284664 ps
CPU time 1.76 seconds
Started Jul 20 07:16:49 PM PDT 24
Finished Jul 20 07:16:53 PM PDT 24
Peak memory 214060 kb
Host smart-4b8b895b-e048-458a-8175-8b08d17c46d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758560181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.1758560181
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.3782819718
Short name T282
Test name
Test status
Simulation time 1766350880 ps
CPU time 89.08 seconds
Started Jul 20 07:17:18 PM PDT 24
Finished Jul 20 07:18:48 PM PDT 24
Peak memory 214592 kb
Host smart-ced2348e-06f4-4da3-8e47-d6114a682288
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3782819718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.3782819718
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.666201887
Short name T386
Test name
Test status
Simulation time 96363582 ps
CPU time 3.79 seconds
Started Jul 20 07:17:27 PM PDT 24
Finished Jul 20 07:17:33 PM PDT 24
Peak memory 214456 kb
Host smart-1b460ca8-2bb4-4f5e-af3b-2b5dc8baeb46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=666201887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.666201887
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.2268975488
Short name T234
Test name
Test status
Simulation time 298563956 ps
CPU time 4.08 seconds
Started Jul 20 07:15:31 PM PDT 24
Finished Jul 20 07:15:36 PM PDT 24
Peak memory 207132 kb
Host smart-f119ed92-a697-4577-bd20-ee3229b6d088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268975488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.2268975488
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.3745476101
Short name T13
Test name
Test status
Simulation time 62213083 ps
CPU time 3.16 seconds
Started Jul 20 07:18:42 PM PDT 24
Finished Jul 20 07:19:13 PM PDT 24
Peak memory 209628 kb
Host smart-03672692-7ea2-4d07-937b-889f67c59cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745476101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.3745476101
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.2821989746
Short name T83
Test name
Test status
Simulation time 34761070 ps
CPU time 1.52 seconds
Started Jul 20 07:19:37 PM PDT 24
Finished Jul 20 07:20:17 PM PDT 24
Peak memory 214076 kb
Host smart-1539f26f-f527-4250-afb0-6a9fc6e6c7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821989746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.2821989746
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.2900821721
Short name T155
Test name
Test status
Simulation time 1071395813 ps
CPU time 7.17 seconds
Started Jul 20 07:12:33 PM PDT 24
Finished Jul 20 07:12:41 PM PDT 24
Peak memory 214368 kb
Host smart-60dda3d6-627d-4ef3-bd33-b3e3cfed3b81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900821721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.2900821721
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1782340313
Short name T160
Test name
Test status
Simulation time 208831796 ps
CPU time 3.41 seconds
Started Jul 20 07:14:25 PM PDT 24
Finished Jul 20 07:14:29 PM PDT 24
Peak memory 206524 kb
Host smart-622f6e0e-29f2-4cce-958c-77a92f4ded9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782340313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.1782340313
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.749360161
Short name T159
Test name
Test status
Simulation time 610419963 ps
CPU time 8.98 seconds
Started Jul 20 07:14:44 PM PDT 24
Finished Jul 20 07:14:54 PM PDT 24
Peak memory 206140 kb
Host smart-ed7690f9-6dfc-4459-bac6-6b339585e8f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749360161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_err
.749360161
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.216145650
Short name T153
Test name
Test status
Simulation time 1119864044 ps
CPU time 8.08 seconds
Started Jul 20 07:13:38 PM PDT 24
Finished Jul 20 07:13:46 PM PDT 24
Peak memory 214412 kb
Host smart-c8f65b1f-c70c-4e0d-ba82-7e41a81035ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216145650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.
216145650
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.3931883182
Short name T39
Test name
Test status
Simulation time 1090040834 ps
CPU time 12.25 seconds
Started Jul 20 07:15:25 PM PDT 24
Finished Jul 20 07:15:38 PM PDT 24
Peak memory 237508 kb
Host smart-da757a7f-377b-44e3-9b40-25d12c2b5de1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931883182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.3931883182
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.2109057097
Short name T162
Test name
Test status
Simulation time 1081401221 ps
CPU time 5.21 seconds
Started Jul 20 07:17:29 PM PDT 24
Finished Jul 20 07:17:36 PM PDT 24
Peak memory 210092 kb
Host smart-ce9aa9a7-9bf5-4436-ac8c-9d1a1afd394c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109057097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.2109057097
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.3422056097
Short name T163
Test name
Test status
Simulation time 82497594 ps
CPU time 2.29 seconds
Started Jul 20 07:20:43 PM PDT 24
Finished Jul 20 07:21:08 PM PDT 24
Peak memory 209976 kb
Host smart-14566b70-63ff-41a6-9d30-5b027802d9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422056097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.3422056097
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.2881419936
Short name T55
Test name
Test status
Simulation time 110649655 ps
CPU time 3.97 seconds
Started Jul 20 07:15:17 PM PDT 24
Finished Jul 20 07:15:22 PM PDT 24
Peak memory 209276 kb
Host smart-53623409-ef97-4782-9077-03f4c3328c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881419936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.2881419936
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.3592695
Short name T392
Test name
Test status
Simulation time 447635506 ps
CPU time 6.29 seconds
Started Jul 20 07:15:28 PM PDT 24
Finished Jul 20 07:15:35 PM PDT 24
Peak memory 214076 kb
Host smart-bff177fa-591c-438b-8767-3c39fe809241
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3592695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.3592695
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.4578915
Short name T180
Test name
Test status
Simulation time 626332234 ps
CPU time 3.33 seconds
Started Jul 20 07:16:40 PM PDT 24
Finished Jul 20 07:16:44 PM PDT 24
Peak memory 209788 kb
Host smart-9c328dc0-555d-45c5-bd91-132ac4ef252a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4578915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.4578915
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.2421692813
Short name T348
Test name
Test status
Simulation time 57275464 ps
CPU time 3 seconds
Started Jul 20 07:16:48 PM PDT 24
Finished Jul 20 07:16:52 PM PDT 24
Peak memory 220308 kb
Host smart-702b9413-4533-4c27-948a-61a269a45e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421692813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.2421692813
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.3963478401
Short name T370
Test name
Test status
Simulation time 213866277 ps
CPU time 2.84 seconds
Started Jul 20 07:16:49 PM PDT 24
Finished Jul 20 07:16:53 PM PDT 24
Peak memory 208392 kb
Host smart-77fc7edd-a29f-4453-9e74-a55b8cea9e8a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963478401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.3963478401
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.3983276544
Short name T193
Test name
Test status
Simulation time 24507780 ps
CPU time 1.48 seconds
Started Jul 20 07:17:20 PM PDT 24
Finished Jul 20 07:17:23 PM PDT 24
Peak memory 206092 kb
Host smart-53270730-6152-4f10-8c5c-22fbfc79d69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983276544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.3983276544
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.291486969
Short name T479
Test name
Test status
Simulation time 1118266877 ps
CPU time 14.48 seconds
Started Jul 20 07:17:21 PM PDT 24
Finished Jul 20 07:17:37 PM PDT 24
Peak memory 207996 kb
Host smart-7186dcf3-96a7-48c6-8f32-9fff5c5dfd55
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291486969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.291486969
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.1160237469
Short name T178
Test name
Test status
Simulation time 8056194585 ps
CPU time 26.23 seconds
Started Jul 20 07:17:21 PM PDT 24
Finished Jul 20 07:17:48 PM PDT 24
Peak memory 214948 kb
Host smart-bdcd7ffb-3a90-4773-9669-b07dafadc651
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160237469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.1160237469
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.691030232
Short name T6
Test name
Test status
Simulation time 70771618 ps
CPU time 3.35 seconds
Started Jul 20 07:17:39 PM PDT 24
Finished Jul 20 07:17:49 PM PDT 24
Peak memory 214072 kb
Host smart-52278705-dc8c-41fc-ab68-804681d73fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691030232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.691030232
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.1970309527
Short name T77
Test name
Test status
Simulation time 67679395 ps
CPU time 3.12 seconds
Started Jul 20 07:15:32 PM PDT 24
Finished Jul 20 07:15:36 PM PDT 24
Peak memory 214772 kb
Host smart-b1e70b93-5ed1-41ac-9cb2-bc621d73f123
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1970309527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.1970309527
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.2663121473
Short name T311
Test name
Test status
Simulation time 338432394 ps
CPU time 3.82 seconds
Started Jul 20 07:18:06 PM PDT 24
Finished Jul 20 07:18:26 PM PDT 24
Peak memory 215788 kb
Host smart-3bada47b-b564-4663-b1bf-f59ba44cbab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663121473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.2663121473
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.1836073310
Short name T21
Test name
Test status
Simulation time 295289621 ps
CPU time 6.29 seconds
Started Jul 20 07:18:05 PM PDT 24
Finished Jul 20 07:18:27 PM PDT 24
Peak memory 222228 kb
Host smart-a9fa7dea-85f4-43f7-a802-6616d28bc474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836073310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.1836073310
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.474586968
Short name T320
Test name
Test status
Simulation time 2197206527 ps
CPU time 22.69 seconds
Started Jul 20 07:18:07 PM PDT 24
Finished Jul 20 07:18:46 PM PDT 24
Peak memory 222244 kb
Host smart-434bda15-04b5-4f62-a294-055b4222bf97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474586968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.474586968
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.3978416684
Short name T296
Test name
Test status
Simulation time 178374482 ps
CPU time 5.61 seconds
Started Jul 20 07:18:34 PM PDT 24
Finished Jul 20 07:19:04 PM PDT 24
Peak memory 222076 kb
Host smart-c6f16ee8-c795-457f-9554-eab52b4f7c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978416684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.3978416684
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.3931023550
Short name T196
Test name
Test status
Simulation time 749883695 ps
CPU time 7.45 seconds
Started Jul 20 07:18:42 PM PDT 24
Finished Jul 20 07:19:16 PM PDT 24
Peak memory 210316 kb
Host smart-5f5f1503-ff5a-406a-82bc-5852c1f346c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931023550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.3931023550
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.2697639683
Short name T270
Test name
Test status
Simulation time 24075938843 ps
CPU time 74.34 seconds
Started Jul 20 07:19:09 PM PDT 24
Finished Jul 20 07:20:57 PM PDT 24
Peak memory 215564 kb
Host smart-f536cd3d-9ae4-4b1e-a4b3-611c06244c18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697639683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2697639683
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.3556358783
Short name T208
Test name
Test status
Simulation time 142665615 ps
CPU time 6.29 seconds
Started Jul 20 07:19:36 PM PDT 24
Finished Jul 20 07:20:21 PM PDT 24
Peak memory 209380 kb
Host smart-ee032247-aa34-4f3b-bddb-65a3b065332d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556358783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.3556358783
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.1775396408
Short name T207
Test name
Test status
Simulation time 2099961608 ps
CPU time 13.36 seconds
Started Jul 20 07:19:54 PM PDT 24
Finished Jul 20 07:20:45 PM PDT 24
Peak memory 220072 kb
Host smart-255bc9ad-e04b-49d7-a8f8-473df5f5ee19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775396408 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.1775396408
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.3085698238
Short name T204
Test name
Test status
Simulation time 68714176 ps
CPU time 2.12 seconds
Started Jul 20 07:20:13 PM PDT 24
Finished Jul 20 07:20:52 PM PDT 24
Peak memory 208788 kb
Host smart-a30320c9-50c7-4ea3-9d22-c88cc109b322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085698238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.3085698238
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.3781439338
Short name T341
Test name
Test status
Simulation time 279008777 ps
CPU time 2.88 seconds
Started Jul 20 07:16:33 PM PDT 24
Finished Jul 20 07:16:36 PM PDT 24
Peak memory 208940 kb
Host smart-93f95f27-c110-48f2-9086-78c6317a8fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781439338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.3781439338
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1779636681
Short name T1056
Test name
Test status
Simulation time 495739047 ps
CPU time 4.06 seconds
Started Jul 20 07:12:40 PM PDT 24
Finished Jul 20 07:12:45 PM PDT 24
Peak memory 206276 kb
Host smart-7defd6ba-d576-4b07-b301-308fa10158a6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779636681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1
779636681
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1626047912
Short name T1015
Test name
Test status
Simulation time 3884953971 ps
CPU time 27.1 seconds
Started Jul 20 07:12:32 PM PDT 24
Finished Jul 20 07:12:59 PM PDT 24
Peak memory 206288 kb
Host smart-7a1c0762-f707-4efb-b623-38286d68496a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626047912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.1
626047912
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2840855374
Short name T973
Test name
Test status
Simulation time 29137540 ps
CPU time 1.41 seconds
Started Jul 20 07:12:33 PM PDT 24
Finished Jul 20 07:12:35 PM PDT 24
Peak memory 206096 kb
Host smart-dbd5c5fe-caff-40fe-8503-8266d6720a9f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840855374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.2
840855374
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1081701628
Short name T168
Test name
Test status
Simulation time 32654522 ps
CPU time 1.61 seconds
Started Jul 20 07:12:39 PM PDT 24
Finished Jul 20 07:12:41 PM PDT 24
Peak memory 214544 kb
Host smart-a8006b4c-eb5c-49a8-9867-d88373dc6486
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081701628 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.1081701628
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.990028702
Short name T963
Test name
Test status
Simulation time 10947225 ps
CPU time 0.94 seconds
Started Jul 20 07:12:33 PM PDT 24
Finished Jul 20 07:12:35 PM PDT 24
Peak memory 205996 kb
Host smart-76f1012c-21be-4579-a991-2b34e25a1ddf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990028702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.990028702
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2883107491
Short name T1034
Test name
Test status
Simulation time 11994778 ps
CPU time 0.7 seconds
Started Jul 20 07:12:32 PM PDT 24
Finished Jul 20 07:12:34 PM PDT 24
Peak memory 205928 kb
Host smart-bec6ec6b-4f26-45c8-bf51-7168e13abdef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883107491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.2883107491
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3815071246
Short name T951
Test name
Test status
Simulation time 22445185 ps
CPU time 1.37 seconds
Started Jul 20 07:12:42 PM PDT 24
Finished Jul 20 07:12:44 PM PDT 24
Peak memory 206160 kb
Host smart-ae396b9a-fb9e-4027-82a0-d65fa45d8264
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815071246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.3815071246
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1790564941
Short name T104
Test name
Test status
Simulation time 755255373 ps
CPU time 14.75 seconds
Started Jul 20 07:12:31 PM PDT 24
Finished Jul 20 07:12:47 PM PDT 24
Peak memory 220688 kb
Host smart-8754b207-0002-486b-ad4f-849646a4b864
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790564941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.1790564941
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.2568635195
Short name T1040
Test name
Test status
Simulation time 108480701 ps
CPU time 1.84 seconds
Started Jul 20 07:12:34 PM PDT 24
Finished Jul 20 07:12:36 PM PDT 24
Peak memory 214452 kb
Host smart-0f16040c-660b-409b-8d0d-df12b30163d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568635195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.2568635195
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3338727569
Short name T1008
Test name
Test status
Simulation time 248835853 ps
CPU time 7.42 seconds
Started Jul 20 07:12:56 PM PDT 24
Finished Jul 20 07:13:04 PM PDT 24
Peak memory 206160 kb
Host smart-9a2db068-e4db-412f-83da-d5654d4122fb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338727569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.3
338727569
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3338370058
Short name T169
Test name
Test status
Simulation time 650394294 ps
CPU time 10.04 seconds
Started Jul 20 07:12:47 PM PDT 24
Finished Jul 20 07:12:58 PM PDT 24
Peak memory 206276 kb
Host smart-9d68dc46-37bb-4a73-b332-0dcfbb2c93a7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338370058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.3
338370058
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1047441868
Short name T941
Test name
Test status
Simulation time 96806080 ps
CPU time 1.06 seconds
Started Jul 20 07:12:48 PM PDT 24
Finished Jul 20 07:12:50 PM PDT 24
Peak memory 206192 kb
Host smart-c049c2f5-1b73-431d-80fa-6dfad32705f3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047441868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.1
047441868
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3100867920
Short name T1041
Test name
Test status
Simulation time 319907590 ps
CPU time 1.59 seconds
Started Jul 20 07:12:58 PM PDT 24
Finished Jul 20 07:13:00 PM PDT 24
Peak memory 214536 kb
Host smart-19f9de7b-1e9b-471a-8284-ac8800d2cc99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100867920 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.3100867920
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.108663143
Short name T1036
Test name
Test status
Simulation time 69428162 ps
CPU time 1.11 seconds
Started Jul 20 07:12:48 PM PDT 24
Finished Jul 20 07:12:49 PM PDT 24
Peak memory 206220 kb
Host smart-28f825eb-9d1e-45e1-b123-610eddab3394
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108663143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.108663143
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1910100867
Short name T1069
Test name
Test status
Simulation time 9032582 ps
CPU time 0.7 seconds
Started Jul 20 07:12:48 PM PDT 24
Finished Jul 20 07:12:49 PM PDT 24
Peak memory 205928 kb
Host smart-36539113-2b93-489f-a54b-0cc31a294c21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910100867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1910100867
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2599946741
Short name T1023
Test name
Test status
Simulation time 64039939 ps
CPU time 1.54 seconds
Started Jul 20 07:12:55 PM PDT 24
Finished Jul 20 07:12:57 PM PDT 24
Peak memory 206228 kb
Host smart-a2bc6f2f-b561-4a30-a145-c22c46beb6e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599946741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.2599946741
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.1822410168
Short name T1062
Test name
Test status
Simulation time 262926358 ps
CPU time 5.75 seconds
Started Jul 20 07:12:46 PM PDT 24
Finished Jul 20 07:12:52 PM PDT 24
Peak memory 214664 kb
Host smart-c5368772-0109-417a-983a-3e6d3b503c58
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822410168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.1822410168
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.848345579
Short name T1000
Test name
Test status
Simulation time 402292248 ps
CPU time 2.64 seconds
Started Jul 20 07:12:48 PM PDT 24
Finished Jul 20 07:12:51 PM PDT 24
Peak memory 214472 kb
Host smart-5334b47e-f9d1-431c-b93f-966cf612cbae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848345579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.848345579
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.573850856
Short name T161
Test name
Test status
Simulation time 735259212 ps
CPU time 5.56 seconds
Started Jul 20 07:12:47 PM PDT 24
Finished Jul 20 07:12:53 PM PDT 24
Peak memory 214412 kb
Host smart-63a211f6-dd7f-4a8b-84ae-3d31709a0585
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573850856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.
573850856
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1543782899
Short name T976
Test name
Test status
Simulation time 33045591 ps
CPU time 2.07 seconds
Started Jul 20 07:14:07 PM PDT 24
Finished Jul 20 07:14:10 PM PDT 24
Peak memory 214496 kb
Host smart-109cef32-c9a3-49d5-84fc-e4e957d7909e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543782899 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1543782899
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.1490735797
Short name T982
Test name
Test status
Simulation time 13765269 ps
CPU time 1.05 seconds
Started Jul 20 07:14:08 PM PDT 24
Finished Jul 20 07:14:09 PM PDT 24
Peak memory 206244 kb
Host smart-5e31c3c6-456f-4555-9ed4-816fcd764b79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490735797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.1490735797
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.386887243
Short name T1029
Test name
Test status
Simulation time 70546125 ps
CPU time 0.75 seconds
Started Jul 20 07:14:06 PM PDT 24
Finished Jul 20 07:14:07 PM PDT 24
Peak memory 206016 kb
Host smart-74c5c95b-e4d8-4159-b3d1-a4e3884b839a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386887243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.386887243
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.3439587102
Short name T1032
Test name
Test status
Simulation time 91303880 ps
CPU time 2.19 seconds
Started Jul 20 07:14:06 PM PDT 24
Finished Jul 20 07:14:08 PM PDT 24
Peak memory 206308 kb
Host smart-fc4b62f7-f29a-4b7a-8047-00d7b4d005f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439587102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.3439587102
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3217560874
Short name T97
Test name
Test status
Simulation time 260066048 ps
CPU time 2.83 seconds
Started Jul 20 07:14:06 PM PDT 24
Finished Jul 20 07:14:10 PM PDT 24
Peak memory 219156 kb
Host smart-81b8e23f-ada1-4008-b875-baa337b533b9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217560874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.3217560874
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1561215580
Short name T986
Test name
Test status
Simulation time 343125943 ps
CPU time 6.4 seconds
Started Jul 20 07:14:08 PM PDT 24
Finished Jul 20 07:14:15 PM PDT 24
Peak memory 214604 kb
Host smart-c154b0ee-254b-4261-b180-a1c6d751e114
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561215580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.1561215580
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1007135496
Short name T1014
Test name
Test status
Simulation time 109392915 ps
CPU time 1.65 seconds
Started Jul 20 07:14:05 PM PDT 24
Finished Jul 20 07:14:08 PM PDT 24
Peak memory 214500 kb
Host smart-90d7a614-85fd-4ff9-9954-5bb852e373c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007135496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.1007135496
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.2509871807
Short name T351
Test name
Test status
Simulation time 110591346 ps
CPU time 4.85 seconds
Started Jul 20 07:14:07 PM PDT 24
Finished Jul 20 07:14:12 PM PDT 24
Peak memory 214220 kb
Host smart-0b2ca3e3-92fc-4324-8d5b-709aa56d688c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509871807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.2509871807
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.374329945
Short name T1052
Test name
Test status
Simulation time 163471583 ps
CPU time 1.57 seconds
Started Jul 20 07:14:15 PM PDT 24
Finished Jul 20 07:14:17 PM PDT 24
Peak memory 214520 kb
Host smart-e7708e47-e7c6-4c9b-ae9a-b8af56355400
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374329945 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.374329945
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2495283733
Short name T969
Test name
Test status
Simulation time 66389370 ps
CPU time 1.1 seconds
Started Jul 20 07:14:14 PM PDT 24
Finished Jul 20 07:14:16 PM PDT 24
Peak memory 206240 kb
Host smart-4f4c7116-5d14-4e05-a8d4-8db19b15c4d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495283733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.2495283733
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.1729412147
Short name T919
Test name
Test status
Simulation time 37078008 ps
CPU time 0.7 seconds
Started Jul 20 07:14:15 PM PDT 24
Finished Jul 20 07:14:16 PM PDT 24
Peak memory 206056 kb
Host smart-15a83562-f5f9-48c5-90f5-daa619284bee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729412147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.1729412147
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1278107663
Short name T960
Test name
Test status
Simulation time 42003501 ps
CPU time 1.46 seconds
Started Jul 20 07:14:15 PM PDT 24
Finished Jul 20 07:14:17 PM PDT 24
Peak memory 206264 kb
Host smart-2e337894-c506-4c06-b580-1b60de986841
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278107663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.1278107663
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1144988085
Short name T1021
Test name
Test status
Simulation time 172321191 ps
CPU time 3.25 seconds
Started Jul 20 07:14:06 PM PDT 24
Finished Jul 20 07:14:10 PM PDT 24
Peak memory 214664 kb
Host smart-d13fc0f3-4ccf-4135-9953-b7c47edcebf3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144988085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.1144988085
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.1805161882
Short name T972
Test name
Test status
Simulation time 288985132 ps
CPU time 6.93 seconds
Started Jul 20 07:14:07 PM PDT 24
Finished Jul 20 07:14:14 PM PDT 24
Peak memory 222884 kb
Host smart-0925213e-6353-426d-98d3-2eec747742fd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805161882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.1805161882
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.3894598198
Short name T958
Test name
Test status
Simulation time 31376209 ps
CPU time 2.3 seconds
Started Jul 20 07:14:06 PM PDT 24
Finished Jul 20 07:14:09 PM PDT 24
Peak memory 216572 kb
Host smart-f8c75b2a-8ae0-433d-ab8d-1c49725c333c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894598198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.3894598198
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2635393087
Short name T1022
Test name
Test status
Simulation time 51326863 ps
CPU time 1.58 seconds
Started Jul 20 07:14:13 PM PDT 24
Finished Jul 20 07:14:15 PM PDT 24
Peak memory 214452 kb
Host smart-94927fd0-8cc1-4669-ab9e-22cc392235da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635393087 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.2635393087
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.4256436729
Short name T975
Test name
Test status
Simulation time 13057465 ps
CPU time 1.09 seconds
Started Jul 20 07:14:14 PM PDT 24
Finished Jul 20 07:14:16 PM PDT 24
Peak memory 206232 kb
Host smart-3ecfde03-6f55-41af-ab37-12877af4a510
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256436729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.4256436729
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3519277161
Short name T961
Test name
Test status
Simulation time 101888699 ps
CPU time 0.69 seconds
Started Jul 20 07:14:13 PM PDT 24
Finished Jul 20 07:14:14 PM PDT 24
Peak memory 205936 kb
Host smart-708c2c38-27a3-485d-ac3b-b11bce52536d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519277161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3519277161
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3933067062
Short name T128
Test name
Test status
Simulation time 62826873 ps
CPU time 1.89 seconds
Started Jul 20 07:14:14 PM PDT 24
Finished Jul 20 07:14:17 PM PDT 24
Peak memory 206260 kb
Host smart-4a305541-3d14-4ebf-85f9-38beb3053fca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933067062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3933067062
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2370489032
Short name T991
Test name
Test status
Simulation time 86633101 ps
CPU time 1.76 seconds
Started Jul 20 07:14:14 PM PDT 24
Finished Jul 20 07:14:16 PM PDT 24
Peak memory 214584 kb
Host smart-951598e1-14ce-4f84-bfd9-c05a66b5ce4b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370489032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.2370489032
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2809657166
Short name T967
Test name
Test status
Simulation time 710793777 ps
CPU time 5.83 seconds
Started Jul 20 07:14:14 PM PDT 24
Finished Jul 20 07:14:21 PM PDT 24
Peak memory 214636 kb
Host smart-763a40bd-9b3b-403e-99f3-070b76987491
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809657166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.2809657166
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.64622770
Short name T1065
Test name
Test status
Simulation time 46774095 ps
CPU time 3.21 seconds
Started Jul 20 07:14:15 PM PDT 24
Finished Jul 20 07:14:19 PM PDT 24
Peak memory 217564 kb
Host smart-de8fd7da-7237-4a48-9d53-30641055ab90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64622770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.64622770
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2391975928
Short name T1025
Test name
Test status
Simulation time 25828786 ps
CPU time 1.25 seconds
Started Jul 20 07:14:25 PM PDT 24
Finished Jul 20 07:14:27 PM PDT 24
Peak memory 206348 kb
Host smart-14f18abb-3818-4952-9216-5af343f029c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391975928 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.2391975928
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2713141712
Short name T1033
Test name
Test status
Simulation time 136784121 ps
CPU time 1.32 seconds
Started Jul 20 07:14:25 PM PDT 24
Finished Jul 20 07:14:27 PM PDT 24
Peak memory 206216 kb
Host smart-ddc9bf19-edd7-4597-9d4d-20d3532d2eef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713141712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.2713141712
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.1616738036
Short name T920
Test name
Test status
Simulation time 11270547 ps
CPU time 0.78 seconds
Started Jul 20 07:14:23 PM PDT 24
Finished Jul 20 07:14:24 PM PDT 24
Peak memory 205928 kb
Host smart-29eb8cfb-b127-4ce5-91bf-2450bdd1aa58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616738036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.1616738036
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3065992176
Short name T943
Test name
Test status
Simulation time 36659388 ps
CPU time 2.54 seconds
Started Jul 20 07:14:23 PM PDT 24
Finished Jul 20 07:14:26 PM PDT 24
Peak memory 206240 kb
Host smart-d98ac603-511f-4b13-9a9a-c6b5aa306cc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065992176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.3065992176
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.3470836101
Short name T1019
Test name
Test status
Simulation time 198308512 ps
CPU time 2.42 seconds
Started Jul 20 07:14:23 PM PDT 24
Finished Jul 20 07:14:26 PM PDT 24
Peak memory 214664 kb
Host smart-613f67a3-dcd2-4420-b5c0-7e457b78cc1a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470836101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.3470836101
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3333044168
Short name T1068
Test name
Test status
Simulation time 341344994 ps
CPU time 4.1 seconds
Started Jul 20 07:14:27 PM PDT 24
Finished Jul 20 07:14:32 PM PDT 24
Peak memory 214664 kb
Host smart-804546f2-0606-42bd-8ffa-211eef14448d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333044168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3333044168
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.2739394821
Short name T932
Test name
Test status
Simulation time 464475379 ps
CPU time 3.3 seconds
Started Jul 20 07:14:23 PM PDT 24
Finished Jul 20 07:14:27 PM PDT 24
Peak memory 217052 kb
Host smart-2f13286d-bfb6-4c9d-a7b5-310c4f2eaab6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739394821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.2739394821
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1921899081
Short name T1063
Test name
Test status
Simulation time 28605297 ps
CPU time 1.62 seconds
Started Jul 20 07:14:26 PM PDT 24
Finished Jul 20 07:14:28 PM PDT 24
Peak memory 214496 kb
Host smart-fd91f2bb-8556-4a13-ae63-cf299d902b2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921899081 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.1921899081
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2721368433
Short name T1024
Test name
Test status
Simulation time 25959554 ps
CPU time 1.25 seconds
Started Jul 20 07:14:23 PM PDT 24
Finished Jul 20 07:14:25 PM PDT 24
Peak memory 206128 kb
Host smart-2d11d4c6-fda2-42ec-ab2b-89e172dece29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721368433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.2721368433
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.1965653774
Short name T955
Test name
Test status
Simulation time 35037467 ps
CPU time 0.73 seconds
Started Jul 20 07:14:23 PM PDT 24
Finished Jul 20 07:14:25 PM PDT 24
Peak memory 206012 kb
Host smart-db2d7998-279e-43ff-9c7b-0f959968d137
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965653774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.1965653774
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.716700409
Short name T996
Test name
Test status
Simulation time 29975111 ps
CPU time 1.74 seconds
Started Jul 20 07:14:24 PM PDT 24
Finished Jul 20 07:14:26 PM PDT 24
Peak memory 206264 kb
Host smart-7ad4fbb8-3904-41ca-b167-81e9ed14b41c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716700409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_sa
me_csr_outstanding.716700409
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3760627301
Short name T985
Test name
Test status
Simulation time 1024443958 ps
CPU time 2.99 seconds
Started Jul 20 07:14:23 PM PDT 24
Finished Jul 20 07:14:27 PM PDT 24
Peak memory 214692 kb
Host smart-dc12277e-d025-4213-ad43-73904555d6d0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760627301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.3760627301
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1671367945
Short name T1067
Test name
Test status
Simulation time 466123023 ps
CPU time 9.23 seconds
Started Jul 20 07:14:24 PM PDT 24
Finished Jul 20 07:14:34 PM PDT 24
Peak memory 214684 kb
Host smart-3c0f8eb8-a252-4a8e-8b47-b20ccd7fa9a0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671367945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.1671367945
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1573058893
Short name T1072
Test name
Test status
Simulation time 105926900 ps
CPU time 2.81 seconds
Started Jul 20 07:14:23 PM PDT 24
Finished Jul 20 07:14:27 PM PDT 24
Peak memory 214400 kb
Host smart-9a335f9e-c553-45a2-bb8d-90d822bdfe18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573058893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.1573058893
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2217113313
Short name T1061
Test name
Test status
Simulation time 35436430 ps
CPU time 1.23 seconds
Started Jul 20 07:14:35 PM PDT 24
Finished Jul 20 07:14:37 PM PDT 24
Peak memory 206304 kb
Host smart-18b49db5-c994-4226-9bd5-90d927fd22aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217113313 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.2217113313
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1098289242
Short name T1060
Test name
Test status
Simulation time 34118231 ps
CPU time 0.98 seconds
Started Jul 20 07:14:37 PM PDT 24
Finished Jul 20 07:14:38 PM PDT 24
Peak memory 205996 kb
Host smart-fd87caee-da6f-44bf-a1f2-eeb04b6d1860
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098289242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1098289242
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.1932493611
Short name T927
Test name
Test status
Simulation time 18394086 ps
CPU time 0.83 seconds
Started Jul 20 07:14:37 PM PDT 24
Finished Jul 20 07:14:38 PM PDT 24
Peak memory 205928 kb
Host smart-7b482ddc-6b94-4c84-95ce-bf0365a85e0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932493611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.1932493611
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1346632475
Short name T131
Test name
Test status
Simulation time 191396255 ps
CPU time 2.26 seconds
Started Jul 20 07:14:35 PM PDT 24
Finished Jul 20 07:14:38 PM PDT 24
Peak memory 206232 kb
Host smart-f61082d4-cb2d-4176-909f-51177812c242
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346632475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.1346632475
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3835553129
Short name T105
Test name
Test status
Simulation time 190258835 ps
CPU time 5.21 seconds
Started Jul 20 07:14:36 PM PDT 24
Finished Jul 20 07:14:41 PM PDT 24
Peak memory 214588 kb
Host smart-54546219-45ed-48e2-9577-5adcbc0e99f3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835553129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.3835553129
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1087150774
Short name T1054
Test name
Test status
Simulation time 616410415 ps
CPU time 7.35 seconds
Started Jul 20 07:14:36 PM PDT 24
Finished Jul 20 07:14:43 PM PDT 24
Peak memory 214680 kb
Host smart-da8ee848-4bd8-4db3-9d3b-ff064d0da32b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087150774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.1087150774
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2462344446
Short name T928
Test name
Test status
Simulation time 22639075 ps
CPU time 1.44 seconds
Started Jul 20 07:14:36 PM PDT 24
Finished Jul 20 07:14:38 PM PDT 24
Peak memory 216696 kb
Host smart-34fb0f54-91db-43c3-a789-2329a3838dc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462344446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.2462344446
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.2939586240
Short name T165
Test name
Test status
Simulation time 105495946 ps
CPU time 2.52 seconds
Started Jul 20 07:14:38 PM PDT 24
Finished Jul 20 07:14:41 PM PDT 24
Peak memory 214412 kb
Host smart-d400cbaf-b65f-43e9-8e6c-935d336a24ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939586240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.2939586240
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1268122977
Short name T936
Test name
Test status
Simulation time 21748159 ps
CPU time 1.05 seconds
Started Jul 20 07:14:42 PM PDT 24
Finished Jul 20 07:14:43 PM PDT 24
Peak memory 206168 kb
Host smart-b4196a1a-085b-4dc3-87cc-24164df21ed8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268122977 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.1268122977
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.2931605757
Short name T1031
Test name
Test status
Simulation time 41365332 ps
CPU time 0.91 seconds
Started Jul 20 07:14:42 PM PDT 24
Finished Jul 20 07:14:44 PM PDT 24
Peak memory 205940 kb
Host smart-66727b32-1c1d-4fd7-891a-2d9d9a75941b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931605757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.2931605757
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1445955126
Short name T1011
Test name
Test status
Simulation time 10355369 ps
CPU time 0.77 seconds
Started Jul 20 07:14:44 PM PDT 24
Finished Jul 20 07:14:45 PM PDT 24
Peak memory 205924 kb
Host smart-99877f06-e7f4-449d-9acd-bce87674ff42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445955126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1445955126
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3692629383
Short name T952
Test name
Test status
Simulation time 128557637 ps
CPU time 2.21 seconds
Started Jul 20 07:14:44 PM PDT 24
Finished Jul 20 07:14:46 PM PDT 24
Peak memory 206260 kb
Host smart-fa268c0c-bb95-419f-925b-ddb09b5f2e9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692629383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.3692629383
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1784150061
Short name T1059
Test name
Test status
Simulation time 206804515 ps
CPU time 1.73 seconds
Started Jul 20 07:14:36 PM PDT 24
Finished Jul 20 07:14:38 PM PDT 24
Peak memory 214756 kb
Host smart-c3883204-3444-4c4d-8a39-6d0fb1918de2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784150061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.1784150061
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3985930394
Short name T1048
Test name
Test status
Simulation time 275594634 ps
CPU time 5.71 seconds
Started Jul 20 07:14:42 PM PDT 24
Finished Jul 20 07:14:49 PM PDT 24
Peak memory 214636 kb
Host smart-8fa8723b-cade-4be5-a4e5-b53fd83aa0c2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985930394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3985930394
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2674394748
Short name T1017
Test name
Test status
Simulation time 100049778 ps
CPU time 2.42 seconds
Started Jul 20 07:14:44 PM PDT 24
Finished Jul 20 07:14:47 PM PDT 24
Peak memory 214400 kb
Host smart-a4f7af94-b3dc-4c96-be99-10fa8e1ead2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674394748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.2674394748
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2639744270
Short name T148
Test name
Test status
Simulation time 345363549 ps
CPU time 4.44 seconds
Started Jul 20 07:14:43 PM PDT 24
Finished Jul 20 07:14:48 PM PDT 24
Peak memory 214480 kb
Host smart-e9eee600-f115-450e-abad-0bef743e5748
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639744270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.2639744270
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3286328864
Short name T1064
Test name
Test status
Simulation time 53061545 ps
CPU time 1.21 seconds
Started Jul 20 07:14:45 PM PDT 24
Finished Jul 20 07:14:47 PM PDT 24
Peak memory 214560 kb
Host smart-8aa7a1c6-534a-4a13-bedd-10c597a9bec2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286328864 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.3286328864
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2344273411
Short name T923
Test name
Test status
Simulation time 49403185 ps
CPU time 1.13 seconds
Started Jul 20 07:14:43 PM PDT 24
Finished Jul 20 07:14:45 PM PDT 24
Peak memory 206148 kb
Host smart-2e238f27-e8de-454c-ba52-19e3a0f59e5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344273411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.2344273411
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.749386427
Short name T1004
Test name
Test status
Simulation time 40293658 ps
CPU time 0.85 seconds
Started Jul 20 07:14:45 PM PDT 24
Finished Jul 20 07:14:46 PM PDT 24
Peak memory 205984 kb
Host smart-6c1b9773-c765-4f6e-b166-d11baf84cc2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749386427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.749386427
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.793293076
Short name T130
Test name
Test status
Simulation time 21506617 ps
CPU time 1.64 seconds
Started Jul 20 07:14:44 PM PDT 24
Finished Jul 20 07:14:46 PM PDT 24
Peak memory 206212 kb
Host smart-96cbeb4f-cbf0-4d07-8f0f-0c64d0799717
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793293076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_sa
me_csr_outstanding.793293076
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.695736888
Short name T1058
Test name
Test status
Simulation time 177990429 ps
CPU time 5.04 seconds
Started Jul 20 07:14:44 PM PDT 24
Finished Jul 20 07:14:50 PM PDT 24
Peak memory 214676 kb
Host smart-eb1daf8e-eb36-423c-92c5-bcf7e01abd2a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695736888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shado
w_reg_errors.695736888
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.234544171
Short name T979
Test name
Test status
Simulation time 668017222 ps
CPU time 9.03 seconds
Started Jul 20 07:14:44 PM PDT 24
Finished Jul 20 07:14:54 PM PDT 24
Peak memory 214728 kb
Host smart-902e3b0c-8339-4e6a-8a23-3c5a3c1e6aaf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234544171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_shadow_reg_errors_with_csr_rw.234544171
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.275398257
Short name T1028
Test name
Test status
Simulation time 227534574 ps
CPU time 1.74 seconds
Started Jul 20 07:14:42 PM PDT 24
Finished Jul 20 07:14:45 PM PDT 24
Peak memory 214464 kb
Host smart-c56a8156-1d3c-4244-8fff-bb69a734bfb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275398257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.275398257
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1034980300
Short name T962
Test name
Test status
Simulation time 30611921 ps
CPU time 1.4 seconds
Started Jul 20 07:14:55 PM PDT 24
Finished Jul 20 07:14:57 PM PDT 24
Peak memory 214528 kb
Host smart-ff92125e-9622-4692-a0c6-884cee042822
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034980300 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.1034980300
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2481011305
Short name T127
Test name
Test status
Simulation time 26763893 ps
CPU time 0.99 seconds
Started Jul 20 07:14:53 PM PDT 24
Finished Jul 20 07:14:54 PM PDT 24
Peak memory 205876 kb
Host smart-dd38537c-f12e-4f95-b208-f9abd9848dea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481011305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2481011305
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.2202025398
Short name T948
Test name
Test status
Simulation time 12208574 ps
CPU time 0.9 seconds
Started Jul 20 07:14:52 PM PDT 24
Finished Jul 20 07:14:54 PM PDT 24
Peak memory 206016 kb
Host smart-46728b8c-4390-4db4-b19f-5c29813cd6df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202025398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.2202025398
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1218371031
Short name T133
Test name
Test status
Simulation time 116201673 ps
CPU time 4.04 seconds
Started Jul 20 07:14:52 PM PDT 24
Finished Jul 20 07:14:57 PM PDT 24
Peak memory 206144 kb
Host smart-6c16577e-bd40-4863-81bc-046020d55662
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218371031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.1218371031
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.230778307
Short name T103
Test name
Test status
Simulation time 218392528 ps
CPU time 3.66 seconds
Started Jul 20 07:14:43 PM PDT 24
Finished Jul 20 07:14:47 PM PDT 24
Peak memory 219184 kb
Host smart-275ba74d-d472-43d6-ae88-afde87022477
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230778307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shado
w_reg_errors.230778307
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2004171529
Short name T1071
Test name
Test status
Simulation time 1253039867 ps
CPU time 8.07 seconds
Started Jul 20 07:14:52 PM PDT 24
Finished Jul 20 07:15:01 PM PDT 24
Peak memory 220756 kb
Host smart-55f259e9-c0ef-4117-aee8-6e24758155f5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004171529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2004171529
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2917561219
Short name T944
Test name
Test status
Simulation time 413046264 ps
CPU time 3.17 seconds
Started Jul 20 07:14:54 PM PDT 24
Finished Jul 20 07:14:58 PM PDT 24
Peak memory 216784 kb
Host smart-1a4e0651-e31c-43f0-8115-8c72cc989b56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917561219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.2917561219
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.93099469
Short name T1018
Test name
Test status
Simulation time 32478785 ps
CPU time 1.23 seconds
Started Jul 20 07:14:56 PM PDT 24
Finished Jul 20 07:14:58 PM PDT 24
Peak memory 214476 kb
Host smart-92260066-b0c4-4abc-acac-e9c55a6067a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93099469 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.93099469
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.736913029
Short name T977
Test name
Test status
Simulation time 47832595 ps
CPU time 1.06 seconds
Started Jul 20 07:14:51 PM PDT 24
Finished Jul 20 07:14:52 PM PDT 24
Peak memory 206076 kb
Host smart-54b9087a-2e96-4464-8533-c21499f277ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736913029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.736913029
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.4070927182
Short name T992
Test name
Test status
Simulation time 80422533 ps
CPU time 0.74 seconds
Started Jul 20 07:14:51 PM PDT 24
Finished Jul 20 07:14:53 PM PDT 24
Peak memory 206020 kb
Host smart-4e3dd770-3a04-4909-9895-e4d297a15a2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070927182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.4070927182
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.865435347
Short name T1037
Test name
Test status
Simulation time 122468603 ps
CPU time 2.74 seconds
Started Jul 20 07:14:52 PM PDT 24
Finished Jul 20 07:14:56 PM PDT 24
Peak memory 206324 kb
Host smart-067a80aa-67e0-4974-90b0-2fef08f23ff7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865435347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_sa
me_csr_outstanding.865435347
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2318146734
Short name T100
Test name
Test status
Simulation time 224746225 ps
CPU time 3.64 seconds
Started Jul 20 07:14:52 PM PDT 24
Finished Jul 20 07:14:56 PM PDT 24
Peak memory 214668 kb
Host smart-0515e48c-b820-48eb-a592-0fa4bdbcd661
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318146734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.2318146734
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1212768772
Short name T999
Test name
Test status
Simulation time 1627256786 ps
CPU time 14.23 seconds
Started Jul 20 07:14:53 PM PDT 24
Finished Jul 20 07:15:08 PM PDT 24
Peak memory 214524 kb
Host smart-33475b88-04bf-4ddd-8239-4da8a51b7d59
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212768772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.1212768772
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.1624871365
Short name T938
Test name
Test status
Simulation time 84799730 ps
CPU time 3.43 seconds
Started Jul 20 07:14:52 PM PDT 24
Finished Jul 20 07:14:56 PM PDT 24
Peak memory 214512 kb
Host smart-f300cd04-42f6-438d-b966-81c5b29bcd64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624871365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.1624871365
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.1356527159
Short name T1049
Test name
Test status
Simulation time 383027792 ps
CPU time 5.52 seconds
Started Jul 20 07:13:11 PM PDT 24
Finished Jul 20 07:13:17 PM PDT 24
Peak memory 206192 kb
Host smart-7defb37d-9b40-4960-aef5-feca733e16ca
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356527159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.1
356527159
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.1138649398
Short name T170
Test name
Test status
Simulation time 2491296395 ps
CPU time 9.53 seconds
Started Jul 20 07:13:12 PM PDT 24
Finished Jul 20 07:13:22 PM PDT 24
Peak memory 206304 kb
Host smart-4244b4b1-46bc-458d-81d6-87732f833566
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138649398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.1
138649398
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.367380962
Short name T1016
Test name
Test status
Simulation time 19168851 ps
CPU time 0.94 seconds
Started Jul 20 07:13:12 PM PDT 24
Finished Jul 20 07:13:13 PM PDT 24
Peak memory 206072 kb
Host smart-2a84a329-94fb-4168-89fe-e55671d3a121
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367380962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.367380962
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.55584602
Short name T931
Test name
Test status
Simulation time 89746068 ps
CPU time 1.56 seconds
Started Jul 20 07:13:12 PM PDT 24
Finished Jul 20 07:13:14 PM PDT 24
Peak memory 214500 kb
Host smart-741d982d-37fe-453b-a83f-5c1ab7a115c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55584602 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.55584602
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.131587109
Short name T1013
Test name
Test status
Simulation time 29545373 ps
CPU time 0.93 seconds
Started Jul 20 07:13:13 PM PDT 24
Finished Jul 20 07:13:15 PM PDT 24
Peak memory 206040 kb
Host smart-54ad6990-0e7b-4e3d-b401-8ffd110cfbd7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131587109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.131587109
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.634059477
Short name T1080
Test name
Test status
Simulation time 10590940 ps
CPU time 0.73 seconds
Started Jul 20 07:13:04 PM PDT 24
Finished Jul 20 07:13:05 PM PDT 24
Peak memory 206004 kb
Host smart-09ee6011-1ad1-4e44-9bd1-3657307e5bdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634059477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.634059477
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3188754939
Short name T1038
Test name
Test status
Simulation time 424109871 ps
CPU time 2.19 seconds
Started Jul 20 07:13:13 PM PDT 24
Finished Jul 20 07:13:16 PM PDT 24
Peak memory 206320 kb
Host smart-0c84b8c9-e2ba-4268-8b9f-5fe2431270cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188754939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.3188754939
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2165203219
Short name T1009
Test name
Test status
Simulation time 302908720 ps
CPU time 2.61 seconds
Started Jul 20 07:12:58 PM PDT 24
Finished Jul 20 07:13:01 PM PDT 24
Peak memory 214564 kb
Host smart-307bfe9b-54fb-432c-ad30-4283fabd0312
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165203219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.2165203219
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.1991477801
Short name T957
Test name
Test status
Simulation time 459692732 ps
CPU time 7.99 seconds
Started Jul 20 07:12:57 PM PDT 24
Finished Jul 20 07:13:05 PM PDT 24
Peak memory 214724 kb
Host smart-73428b12-1efe-4d96-9747-81ba1afa77ca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991477801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.1991477801
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2220466283
Short name T1066
Test name
Test status
Simulation time 666802996 ps
CPU time 5.59 seconds
Started Jul 20 07:12:56 PM PDT 24
Finished Jul 20 07:13:02 PM PDT 24
Peak memory 214424 kb
Host smart-e9dd588e-918a-4b2b-81c1-9560f741ebe0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220466283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.2220466283
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1500721122
Short name T1035
Test name
Test status
Simulation time 127129356 ps
CPU time 3.03 seconds
Started Jul 20 07:13:03 PM PDT 24
Finished Jul 20 07:13:07 PM PDT 24
Peak memory 214416 kb
Host smart-7975018a-1e1d-4622-aea8-aa3f76af210c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500721122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.1500721122
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2101648025
Short name T929
Test name
Test status
Simulation time 83060263 ps
CPU time 0.78 seconds
Started Jul 20 07:14:52 PM PDT 24
Finished Jul 20 07:14:53 PM PDT 24
Peak memory 206016 kb
Host smart-b5d4f5fe-c4f2-47de-ac35-95ad45551577
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101648025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.2101648025
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3063294691
Short name T956
Test name
Test status
Simulation time 26312109 ps
CPU time 0.75 seconds
Started Jul 20 07:14:52 PM PDT 24
Finished Jul 20 07:14:53 PM PDT 24
Peak memory 206020 kb
Host smart-b5559210-4f60-416c-9413-8d8c2b774020
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063294691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.3063294691
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2674667756
Short name T1075
Test name
Test status
Simulation time 48807674 ps
CPU time 0.84 seconds
Started Jul 20 07:14:52 PM PDT 24
Finished Jul 20 07:14:54 PM PDT 24
Peak memory 206012 kb
Host smart-c73165be-645f-4b69-a7bb-92f1b1c95aa5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674667756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2674667756
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2214521816
Short name T1051
Test name
Test status
Simulation time 50733610 ps
CPU time 0.69 seconds
Started Jul 20 07:14:53 PM PDT 24
Finished Jul 20 07:14:54 PM PDT 24
Peak memory 205908 kb
Host smart-a6e2da33-2584-4501-8fa2-94096d250457
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214521816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2214521816
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.3427171133
Short name T945
Test name
Test status
Simulation time 37569080 ps
CPU time 0.79 seconds
Started Jul 20 07:14:53 PM PDT 24
Finished Jul 20 07:14:55 PM PDT 24
Peak memory 206012 kb
Host smart-fd64557e-65ef-421c-8f17-c2bb13b3f274
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427171133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.3427171133
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.637709159
Short name T1030
Test name
Test status
Simulation time 10194081 ps
CPU time 0.8 seconds
Started Jul 20 07:14:51 PM PDT 24
Finished Jul 20 07:14:52 PM PDT 24
Peak memory 205940 kb
Host smart-55794cef-9216-4751-9221-97cc8181d413
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637709159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.637709159
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1596577535
Short name T953
Test name
Test status
Simulation time 17638689 ps
CPU time 0.73 seconds
Started Jul 20 07:14:56 PM PDT 24
Finished Jul 20 07:14:58 PM PDT 24
Peak memory 206020 kb
Host smart-edde90eb-0c78-4033-b241-40ff6d65ebe0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596577535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.1596577535
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3900995349
Short name T974
Test name
Test status
Simulation time 61975299 ps
CPU time 0.71 seconds
Started Jul 20 07:15:01 PM PDT 24
Finished Jul 20 07:15:03 PM PDT 24
Peak memory 206056 kb
Host smart-3e333566-3684-4849-9867-412cd941727b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900995349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3900995349
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.3713385752
Short name T1078
Test name
Test status
Simulation time 16461231 ps
CPU time 0.77 seconds
Started Jul 20 07:15:02 PM PDT 24
Finished Jul 20 07:15:03 PM PDT 24
Peak memory 206056 kb
Host smart-a940471d-fae4-4c59-a854-708ad94be2d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713385752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.3713385752
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.4200460505
Short name T954
Test name
Test status
Simulation time 38228072 ps
CPU time 0.73 seconds
Started Jul 20 07:15:02 PM PDT 24
Finished Jul 20 07:15:03 PM PDT 24
Peak memory 206000 kb
Host smart-2c4e5d07-aa0e-45a1-ab3f-d9a6810d6eea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200460505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.4200460505
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3795816538
Short name T1043
Test name
Test status
Simulation time 1165554523 ps
CPU time 7.02 seconds
Started Jul 20 07:13:19 PM PDT 24
Finished Jul 20 07:13:27 PM PDT 24
Peak memory 206280 kb
Host smart-339b390f-dbf2-4ad6-a029-2e977c862e6d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795816538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.3
795816538
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.534924139
Short name T1053
Test name
Test status
Simulation time 446667346 ps
CPU time 8.07 seconds
Started Jul 20 07:13:19 PM PDT 24
Finished Jul 20 07:13:28 PM PDT 24
Peak memory 206180 kb
Host smart-e2ac3026-2e8d-4b99-88d0-495396174324
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534924139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.534924139
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2641014047
Short name T172
Test name
Test status
Simulation time 103835743 ps
CPU time 1.42 seconds
Started Jul 20 07:13:11 PM PDT 24
Finished Jul 20 07:13:13 PM PDT 24
Peak memory 206164 kb
Host smart-4344e43d-a83a-4841-8116-b2f0b22da4e0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641014047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.2
641014047
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.755286242
Short name T930
Test name
Test status
Simulation time 29117654 ps
CPU time 1.57 seconds
Started Jul 20 07:13:19 PM PDT 24
Finished Jul 20 07:13:22 PM PDT 24
Peak memory 222624 kb
Host smart-3b7453a7-86d8-4236-b888-8bb3cf5eded7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755286242 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.755286242
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.2510735036
Short name T994
Test name
Test status
Simulation time 18330651 ps
CPU time 1.07 seconds
Started Jul 20 07:13:13 PM PDT 24
Finished Jul 20 07:13:15 PM PDT 24
Peak memory 206140 kb
Host smart-4c91801e-907a-4fcf-9848-7a9d113ec22f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510735036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.2510735036
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.617992433
Short name T965
Test name
Test status
Simulation time 37172899 ps
CPU time 0.75 seconds
Started Jul 20 07:13:13 PM PDT 24
Finished Jul 20 07:13:14 PM PDT 24
Peak memory 205920 kb
Host smart-1444dd9d-507b-4ebf-98fd-bd0d192e6a6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617992433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.617992433
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3477662480
Short name T1020
Test name
Test status
Simulation time 119294399 ps
CPU time 4.19 seconds
Started Jul 20 07:13:17 PM PDT 24
Finished Jul 20 07:13:22 PM PDT 24
Peak memory 206168 kb
Host smart-4546d146-5f01-466c-ac0b-5d772862e670
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477662480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.3477662480
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1155032428
Short name T1042
Test name
Test status
Simulation time 554280303 ps
CPU time 2.6 seconds
Started Jul 20 07:13:13 PM PDT 24
Finished Jul 20 07:13:16 PM PDT 24
Peak memory 214672 kb
Host smart-ba4daef4-b12d-4023-8dcf-ad51226309a6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155032428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.1155032428
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1894917785
Short name T1046
Test name
Test status
Simulation time 1849039628 ps
CPU time 10.02 seconds
Started Jul 20 07:13:11 PM PDT 24
Finished Jul 20 07:13:21 PM PDT 24
Peak memory 222856 kb
Host smart-b3bb5c0d-8cb2-4b3c-8063-50422fa48993
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894917785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1894917785
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.2508200726
Short name T984
Test name
Test status
Simulation time 65565347 ps
CPU time 2.63 seconds
Started Jul 20 07:13:12 PM PDT 24
Finished Jul 20 07:13:15 PM PDT 24
Peak memory 214428 kb
Host smart-59f411e2-b07c-4cb9-98a6-bf93e70aa803
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508200726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.2508200726
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3658686411
Short name T939
Test name
Test status
Simulation time 13193922 ps
CPU time 0.87 seconds
Started Jul 20 07:15:01 PM PDT 24
Finished Jul 20 07:15:02 PM PDT 24
Peak memory 206028 kb
Host smart-289d1e70-a6f9-47cd-805f-df2394e28ba2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658686411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3658686411
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.1595293784
Short name T940
Test name
Test status
Simulation time 169941182 ps
CPU time 0.69 seconds
Started Jul 20 07:15:03 PM PDT 24
Finished Jul 20 07:15:04 PM PDT 24
Peak memory 205984 kb
Host smart-9355c9dd-f7c1-4475-8c10-c2bc43c1d035
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595293784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.1595293784
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.1970708367
Short name T970
Test name
Test status
Simulation time 33752319 ps
CPU time 0.69 seconds
Started Jul 20 07:15:00 PM PDT 24
Finished Jul 20 07:15:01 PM PDT 24
Peak memory 206004 kb
Host smart-1b0a47cb-b4de-42ef-92af-7b035daacc66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970708367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.1970708367
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.468902216
Short name T933
Test name
Test status
Simulation time 15345077 ps
CPU time 0.82 seconds
Started Jul 20 07:15:03 PM PDT 24
Finished Jul 20 07:15:04 PM PDT 24
Peak memory 206004 kb
Host smart-1380c25e-c8bc-49d9-9884-30eb97072d5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468902216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.468902216
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3515435942
Short name T1079
Test name
Test status
Simulation time 14500173 ps
CPU time 0.7 seconds
Started Jul 20 07:15:01 PM PDT 24
Finished Jul 20 07:15:02 PM PDT 24
Peak memory 205928 kb
Host smart-735a31a3-323c-4204-84b1-a877b3a11296
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515435942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.3515435942
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.4193237818
Short name T980
Test name
Test status
Simulation time 29490775 ps
CPU time 0.9 seconds
Started Jul 20 07:15:03 PM PDT 24
Finished Jul 20 07:15:05 PM PDT 24
Peak memory 206004 kb
Host smart-35f5d00f-82d3-4cbe-9834-72545d93287c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193237818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.4193237818
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.706474740
Short name T978
Test name
Test status
Simulation time 112556301 ps
CPU time 0.75 seconds
Started Jul 20 07:15:00 PM PDT 24
Finished Jul 20 07:15:02 PM PDT 24
Peak memory 205980 kb
Host smart-1f8e4e58-e1ee-48dd-976f-485d7242709d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706474740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.706474740
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.970637369
Short name T921
Test name
Test status
Simulation time 43648489 ps
CPU time 0.73 seconds
Started Jul 20 07:15:01 PM PDT 24
Finished Jul 20 07:15:03 PM PDT 24
Peak memory 205988 kb
Host smart-73e0d6bc-8277-4032-b3e3-f6775e0fd277
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970637369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.970637369
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3733085457
Short name T1010
Test name
Test status
Simulation time 188140197 ps
CPU time 0.87 seconds
Started Jul 20 07:15:03 PM PDT 24
Finished Jul 20 07:15:05 PM PDT 24
Peak memory 205940 kb
Host smart-d58a6521-8875-409c-9553-5d5706b3a6b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733085457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.3733085457
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.638385737
Short name T1050
Test name
Test status
Simulation time 9823086 ps
CPU time 0.77 seconds
Started Jul 20 07:15:01 PM PDT 24
Finished Jul 20 07:15:03 PM PDT 24
Peak memory 205940 kb
Host smart-23953a57-89b9-45ed-bcb5-4eec41cbc9c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638385737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.638385737
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.1648283845
Short name T949
Test name
Test status
Simulation time 284997236 ps
CPU time 3.77 seconds
Started Jul 20 07:13:35 PM PDT 24
Finished Jul 20 07:13:40 PM PDT 24
Peak memory 206236 kb
Host smart-6b2c6442-795c-4081-8fa2-0ee26b3c5663
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648283845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.1
648283845
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2697280496
Short name T1003
Test name
Test status
Simulation time 1560269451 ps
CPU time 13.88 seconds
Started Jul 20 07:13:28 PM PDT 24
Finished Jul 20 07:13:42 PM PDT 24
Peak memory 206248 kb
Host smart-addd768a-0543-410c-96c2-716fb048de45
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697280496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2
697280496
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3458297241
Short name T946
Test name
Test status
Simulation time 84001218 ps
CPU time 1.17 seconds
Started Jul 20 07:13:26 PM PDT 24
Finished Jul 20 07:13:28 PM PDT 24
Peak memory 206212 kb
Host smart-b67df6c3-329b-45c9-b479-b4e5f6a27b10
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458297241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.3
458297241
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.989454462
Short name T989
Test name
Test status
Simulation time 26771878 ps
CPU time 1.3 seconds
Started Jul 20 07:13:38 PM PDT 24
Finished Jul 20 07:13:40 PM PDT 24
Peak memory 206216 kb
Host smart-c4e03a45-2baf-4473-9ac6-cca55bbe7cc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989454462 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.989454462
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.3530888610
Short name T126
Test name
Test status
Simulation time 11745502 ps
CPU time 0.86 seconds
Started Jul 20 07:13:28 PM PDT 24
Finished Jul 20 07:13:29 PM PDT 24
Peak memory 206000 kb
Host smart-2ed21b8f-6167-4f3f-8559-94a22d411d7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530888610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.3530888610
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.435232834
Short name T959
Test name
Test status
Simulation time 12516249 ps
CPU time 0.79 seconds
Started Jul 20 07:13:30 PM PDT 24
Finished Jul 20 07:13:31 PM PDT 24
Peak memory 206012 kb
Host smart-1fd11fe1-9e12-4951-abe5-ab0814d1baca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435232834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.435232834
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.702771981
Short name T1070
Test name
Test status
Simulation time 51908369 ps
CPU time 1.52 seconds
Started Jul 20 07:13:35 PM PDT 24
Finished Jul 20 07:13:37 PM PDT 24
Peak memory 206304 kb
Host smart-07646c33-08a6-4efc-83c4-f409026e775e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702771981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sam
e_csr_outstanding.702771981
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1943573683
Short name T96
Test name
Test status
Simulation time 62149520 ps
CPU time 1.68 seconds
Started Jul 20 07:13:27 PM PDT 24
Finished Jul 20 07:13:29 PM PDT 24
Peak memory 214660 kb
Host smart-8eea5711-ab65-4991-84b9-3fa82dd88cf9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943573683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1943573683
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.4050558055
Short name T171
Test name
Test status
Simulation time 134794430 ps
CPU time 3.28 seconds
Started Jul 20 07:13:27 PM PDT 24
Finished Jul 20 07:13:31 PM PDT 24
Peak memory 214412 kb
Host smart-c2a6e6a9-a856-4c5d-a8e3-ad2e550cc0a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050558055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.4050558055
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.257370531
Short name T1002
Test name
Test status
Simulation time 51795360 ps
CPU time 0.8 seconds
Started Jul 20 07:15:03 PM PDT 24
Finished Jul 20 07:15:05 PM PDT 24
Peak memory 206004 kb
Host smart-26ee0004-b7d3-497e-94ca-80acdcf351b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257370531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.257370531
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.1220486838
Short name T922
Test name
Test status
Simulation time 14484577 ps
CPU time 0.92 seconds
Started Jul 20 07:15:01 PM PDT 24
Finished Jul 20 07:15:02 PM PDT 24
Peak memory 206088 kb
Host smart-44575595-7e51-4661-a185-d32c63386c3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220486838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.1220486838
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2544899315
Short name T925
Test name
Test status
Simulation time 46923506 ps
CPU time 0.71 seconds
Started Jul 20 07:15:13 PM PDT 24
Finished Jul 20 07:15:15 PM PDT 24
Peak memory 206012 kb
Host smart-2cf07832-c2b4-438f-9321-7db2df87dd7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544899315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2544899315
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.4196719787
Short name T935
Test name
Test status
Simulation time 10287863 ps
CPU time 0.73 seconds
Started Jul 20 07:15:13 PM PDT 24
Finished Jul 20 07:15:15 PM PDT 24
Peak memory 205944 kb
Host smart-e46760f6-0ab7-4d43-97f3-13f753bfa971
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196719787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.4196719787
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2342837352
Short name T1012
Test name
Test status
Simulation time 24391560 ps
CPU time 0.76 seconds
Started Jul 20 07:15:12 PM PDT 24
Finished Jul 20 07:15:14 PM PDT 24
Peak memory 205964 kb
Host smart-6ea25907-597f-467b-af67-a48c5c4ac4ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342837352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.2342837352
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3206033832
Short name T1007
Test name
Test status
Simulation time 16324395 ps
CPU time 0.77 seconds
Started Jul 20 07:15:11 PM PDT 24
Finished Jul 20 07:15:13 PM PDT 24
Peak memory 206008 kb
Host smart-7e5ba657-9cc2-43f0-bdc3-f0b3c5cb6af8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206033832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.3206033832
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.3619374156
Short name T988
Test name
Test status
Simulation time 62679381 ps
CPU time 0.78 seconds
Started Jul 20 07:15:15 PM PDT 24
Finished Jul 20 07:15:17 PM PDT 24
Peak memory 206016 kb
Host smart-1d5732b0-9af9-43ce-9e44-30c7003a7f0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619374156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.3619374156
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1493988124
Short name T968
Test name
Test status
Simulation time 12220676 ps
CPU time 0.86 seconds
Started Jul 20 07:15:15 PM PDT 24
Finished Jul 20 07:15:17 PM PDT 24
Peak memory 205940 kb
Host smart-72d81212-86ff-41ac-b3da-c968cba1fb9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493988124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.1493988124
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.662811560
Short name T981
Test name
Test status
Simulation time 113661779 ps
CPU time 0.88 seconds
Started Jul 20 07:15:12 PM PDT 24
Finished Jul 20 07:15:14 PM PDT 24
Peak memory 206016 kb
Host smart-b0f0a7b9-005b-4b6a-b54d-3b5b9e825be4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662811560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.662811560
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.2186144244
Short name T1077
Test name
Test status
Simulation time 33934664 ps
CPU time 0.94 seconds
Started Jul 20 07:15:18 PM PDT 24
Finished Jul 20 07:15:19 PM PDT 24
Peak memory 206208 kb
Host smart-006855a6-0e30-4ab2-8257-25b417a70101
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186144244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.2186144244
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1020299817
Short name T1055
Test name
Test status
Simulation time 44303914 ps
CPU time 1.06 seconds
Started Jul 20 07:13:43 PM PDT 24
Finished Jul 20 07:13:45 PM PDT 24
Peak memory 206280 kb
Host smart-f750e8ab-ecab-462e-b926-c8851bd86b40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020299817 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.1020299817
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.1430154233
Short name T997
Test name
Test status
Simulation time 52434574 ps
CPU time 1.57 seconds
Started Jul 20 07:13:42 PM PDT 24
Finished Jul 20 07:13:45 PM PDT 24
Peak memory 206216 kb
Host smart-3de60d1f-4536-4fca-bdcb-5c1ee3b36221
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430154233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.1430154233
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.2831828818
Short name T926
Test name
Test status
Simulation time 7949195 ps
CPU time 0.69 seconds
Started Jul 20 07:13:34 PM PDT 24
Finished Jul 20 07:13:36 PM PDT 24
Peak memory 206000 kb
Host smart-906b836b-dc64-416c-a46e-6ee573feadf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831828818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.2831828818
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3509228133
Short name T950
Test name
Test status
Simulation time 133219609 ps
CPU time 2.63 seconds
Started Jul 20 07:13:42 PM PDT 24
Finished Jul 20 07:13:45 PM PDT 24
Peak memory 206304 kb
Host smart-6492a54b-f4cf-4a37-94ba-32477fc35938
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509228133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.3509228133
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.487720647
Short name T937
Test name
Test status
Simulation time 541924361 ps
CPU time 3.85 seconds
Started Jul 20 07:13:38 PM PDT 24
Finished Jul 20 07:13:42 PM PDT 24
Peak memory 214708 kb
Host smart-d0fb60ed-13dc-4cef-8cbc-b19d1166e542
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487720647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow
_reg_errors.487720647
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1080214514
Short name T987
Test name
Test status
Simulation time 217630756 ps
CPU time 5.71 seconds
Started Jul 20 07:13:34 PM PDT 24
Finished Jul 20 07:13:40 PM PDT 24
Peak memory 214708 kb
Host smart-28627e6a-5f5a-40df-a64e-47ccb767ff9e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080214514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.1080214514
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2703148511
Short name T1039
Test name
Test status
Simulation time 199609833 ps
CPU time 3.87 seconds
Started Jul 20 07:13:34 PM PDT 24
Finished Jul 20 07:13:38 PM PDT 24
Peak memory 214308 kb
Host smart-01b43e55-7cf4-4e1a-b663-86a1c1aa334d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703148511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.2703148511
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.994466521
Short name T934
Test name
Test status
Simulation time 43880572 ps
CPU time 1.49 seconds
Started Jul 20 07:13:53 PM PDT 24
Finished Jul 20 07:13:55 PM PDT 24
Peak memory 214492 kb
Host smart-fd4c252a-ff3c-449e-a755-70d118013196
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994466521 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.994466521
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.4166246228
Short name T947
Test name
Test status
Simulation time 114964404 ps
CPU time 1.57 seconds
Started Jul 20 07:13:43 PM PDT 24
Finished Jul 20 07:13:45 PM PDT 24
Peak memory 206236 kb
Host smart-4d055fe1-08f7-4751-addc-be55907cdafc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166246228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.4166246228
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.562190362
Short name T983
Test name
Test status
Simulation time 146935287 ps
CPU time 0.89 seconds
Started Jul 20 07:13:41 PM PDT 24
Finished Jul 20 07:13:42 PM PDT 24
Peak memory 205964 kb
Host smart-55acccc9-317b-47f1-9d6a-b7d6f6467c5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562190362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.562190362
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1309909129
Short name T1074
Test name
Test status
Simulation time 197242889 ps
CPU time 2.29 seconds
Started Jul 20 07:13:42 PM PDT 24
Finished Jul 20 07:13:45 PM PDT 24
Peak memory 206220 kb
Host smart-6b7ed3c0-1c18-4662-8c89-530a228a7faa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309909129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.1309909129
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2351927153
Short name T993
Test name
Test status
Simulation time 419397985 ps
CPU time 3.3 seconds
Started Jul 20 07:13:43 PM PDT 24
Finished Jul 20 07:13:47 PM PDT 24
Peak memory 214648 kb
Host smart-bb44b651-3928-4e30-82a2-0410a365cfa2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351927153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.2351927153
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.295345353
Short name T942
Test name
Test status
Simulation time 1646628136 ps
CPU time 5.17 seconds
Started Jul 20 07:13:43 PM PDT 24
Finished Jul 20 07:13:49 PM PDT 24
Peak memory 214668 kb
Host smart-3d6a2ece-5ef1-4e01-8e98-1fec20c0c2d3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295345353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_shadow_reg_errors_with_csr_rw.295345353
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3058065808
Short name T1006
Test name
Test status
Simulation time 23696703 ps
CPU time 1.8 seconds
Started Jul 20 07:13:41 PM PDT 24
Finished Jul 20 07:13:43 PM PDT 24
Peak memory 216580 kb
Host smart-912c98d6-3ad2-439a-8247-5b3903fb8e33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058065808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.3058065808
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3813350574
Short name T146
Test name
Test status
Simulation time 133907616 ps
CPU time 5.37 seconds
Started Jul 20 07:13:41 PM PDT 24
Finished Jul 20 07:13:47 PM PDT 24
Peak memory 206240 kb
Host smart-7a73733b-65fa-4e84-84a2-07ab833abc74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813350574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.3813350574
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2866022797
Short name T166
Test name
Test status
Simulation time 55893307 ps
CPU time 1.51 seconds
Started Jul 20 07:13:55 PM PDT 24
Finished Jul 20 07:13:58 PM PDT 24
Peak memory 206216 kb
Host smart-431c64f8-ebdd-4d94-b2e5-88fe81e96d23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866022797 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.2866022797
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1821005875
Short name T966
Test name
Test status
Simulation time 82301370 ps
CPU time 1.18 seconds
Started Jul 20 07:13:50 PM PDT 24
Finished Jul 20 07:13:52 PM PDT 24
Peak memory 206192 kb
Host smart-7bb3d81d-0ad1-4804-8aae-e8070f10b3fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821005875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.1821005875
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2955546570
Short name T990
Test name
Test status
Simulation time 90177721 ps
CPU time 0.72 seconds
Started Jul 20 07:13:50 PM PDT 24
Finished Jul 20 07:13:51 PM PDT 24
Peak memory 205940 kb
Host smart-ee0ee855-4482-4d97-b33e-a564cba836ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955546570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2955546570
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.925392213
Short name T1005
Test name
Test status
Simulation time 116978245 ps
CPU time 2.33 seconds
Started Jul 20 07:13:51 PM PDT 24
Finished Jul 20 07:13:54 PM PDT 24
Peak memory 206196 kb
Host smart-d393a594-7a1e-4a4e-bc7f-79aba796eba4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925392213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sam
e_csr_outstanding.925392213
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3070835441
Short name T101
Test name
Test status
Simulation time 691685047 ps
CPU time 2.88 seconds
Started Jul 20 07:13:51 PM PDT 24
Finished Jul 20 07:13:55 PM PDT 24
Peak memory 214708 kb
Host smart-d05591a6-6980-4540-b3d7-c50e4e3342b9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070835441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.3070835441
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3335857144
Short name T971
Test name
Test status
Simulation time 240350181 ps
CPU time 7.12 seconds
Started Jul 20 07:13:51 PM PDT 24
Finished Jul 20 07:13:58 PM PDT 24
Peak memory 214664 kb
Host smart-40df64ab-eccf-4b35-b1fe-75c1ecc9269d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335857144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.3335857144
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.994970998
Short name T1047
Test name
Test status
Simulation time 54257204 ps
CPU time 2.94 seconds
Started Jul 20 07:13:50 PM PDT 24
Finished Jul 20 07:13:53 PM PDT 24
Peak memory 216992 kb
Host smart-d922759c-90e6-4c07-8537-a81fb5988f89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994970998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.994970998
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.425219682
Short name T357
Test name
Test status
Simulation time 134736390 ps
CPU time 4.83 seconds
Started Jul 20 07:13:52 PM PDT 24
Finished Jul 20 07:13:58 PM PDT 24
Peak memory 214380 kb
Host smart-9b607c7f-41c4-4c28-8ae8-90278611cee2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425219682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.
425219682
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1236744238
Short name T924
Test name
Test status
Simulation time 53153836 ps
CPU time 1.73 seconds
Started Jul 20 07:13:59 PM PDT 24
Finished Jul 20 07:14:02 PM PDT 24
Peak memory 214540 kb
Host smart-5d32864e-7989-418f-8697-bfce7d9ef6ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236744238 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.1236744238
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.781278739
Short name T132
Test name
Test status
Simulation time 13712594 ps
CPU time 1.28 seconds
Started Jul 20 07:13:59 PM PDT 24
Finished Jul 20 07:14:01 PM PDT 24
Peak memory 206236 kb
Host smart-9fd5c939-51b8-4e48-bb73-9830f2634f44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781278739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.781278739
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1955129254
Short name T1057
Test name
Test status
Simulation time 128271969 ps
CPU time 0.72 seconds
Started Jul 20 07:13:56 PM PDT 24
Finished Jul 20 07:13:57 PM PDT 24
Peak memory 206004 kb
Host smart-52de0a33-e696-459c-b5ac-0bc27ad29684
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955129254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.1955129254
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1508868425
Short name T129
Test name
Test status
Simulation time 23054693 ps
CPU time 1.3 seconds
Started Jul 20 07:13:55 PM PDT 24
Finished Jul 20 07:13:57 PM PDT 24
Peak memory 206240 kb
Host smart-93dc123d-03e4-41c8-9ee7-db1c4d94b04e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508868425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.1508868425
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.287491070
Short name T1027
Test name
Test status
Simulation time 291259599 ps
CPU time 2.86 seconds
Started Jul 20 07:13:55 PM PDT 24
Finished Jul 20 07:13:58 PM PDT 24
Peak memory 214628 kb
Host smart-4607c06c-ab15-4d7f-83dd-1898a827cb91
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287491070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow
_reg_errors.287491070
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1319778090
Short name T1076
Test name
Test status
Simulation time 735142539 ps
CPU time 14.04 seconds
Started Jul 20 07:13:57 PM PDT 24
Finished Jul 20 07:14:12 PM PDT 24
Peak memory 221476 kb
Host smart-6618bd2b-59a3-4b39-84d9-0e442fe03492
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319778090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.1319778090
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.3290722970
Short name T174
Test name
Test status
Simulation time 89736174 ps
CPU time 1.88 seconds
Started Jul 20 07:13:57 PM PDT 24
Finished Jul 20 07:14:00 PM PDT 24
Peak memory 214432 kb
Host smart-bfe6afaf-2eb1-419e-8e31-8690068291a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290722970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.3290722970
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.3668348932
Short name T154
Test name
Test status
Simulation time 221421707 ps
CPU time 3.72 seconds
Started Jul 20 07:13:57 PM PDT 24
Finished Jul 20 07:14:01 PM PDT 24
Peak memory 206224 kb
Host smart-7b880659-ed42-414f-8820-529d74988d6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668348932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.3668348932
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2841303585
Short name T1044
Test name
Test status
Simulation time 41336783 ps
CPU time 1.34 seconds
Started Jul 20 07:14:07 PM PDT 24
Finished Jul 20 07:14:09 PM PDT 24
Peak memory 214460 kb
Host smart-5798de79-cb67-4958-873c-8090c4909d1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841303585 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.2841303585
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1052349212
Short name T125
Test name
Test status
Simulation time 13046722 ps
CPU time 1.03 seconds
Started Jul 20 07:14:06 PM PDT 24
Finished Jul 20 07:14:07 PM PDT 24
Peak memory 206004 kb
Host smart-b05aba59-fdfb-400d-a8a2-767e04143e01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052349212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.1052349212
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1157995900
Short name T995
Test name
Test status
Simulation time 9420650 ps
CPU time 0.82 seconds
Started Jul 20 07:13:57 PM PDT 24
Finished Jul 20 07:13:58 PM PDT 24
Peak memory 206024 kb
Host smart-12df1050-827b-4ce3-8add-8b6e025d0ba2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157995900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.1157995900
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.3803721317
Short name T1045
Test name
Test status
Simulation time 65336210 ps
CPU time 1.52 seconds
Started Jul 20 07:14:07 PM PDT 24
Finished Jul 20 07:14:09 PM PDT 24
Peak memory 206184 kb
Host smart-e0469692-7ec1-4adb-a137-1d73359a7cc2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803721317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.3803721317
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2480175310
Short name T998
Test name
Test status
Simulation time 94327592 ps
CPU time 1.68 seconds
Started Jul 20 07:13:59 PM PDT 24
Finished Jul 20 07:14:01 PM PDT 24
Peak memory 214648 kb
Host smart-dae71802-4430-44fa-8d74-847a3dc25e22
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480175310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.2480175310
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.3121646971
Short name T1073
Test name
Test status
Simulation time 205918300 ps
CPU time 4.78 seconds
Started Jul 20 07:13:56 PM PDT 24
Finished Jul 20 07:14:01 PM PDT 24
Peak memory 214704 kb
Host smart-f59b9d30-ef47-4f9b-8f8b-609cd6bd8436
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121646971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.3121646971
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.2767539815
Short name T1001
Test name
Test status
Simulation time 256235901 ps
CPU time 2.66 seconds
Started Jul 20 07:14:02 PM PDT 24
Finished Jul 20 07:14:06 PM PDT 24
Peak memory 215532 kb
Host smart-e264d79a-5989-43d3-b607-6e5a54ef5b77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767539815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.2767539815
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.4162698682
Short name T1026
Test name
Test status
Simulation time 257726439 ps
CPU time 6.77 seconds
Started Jul 20 07:13:56 PM PDT 24
Finished Jul 20 07:14:03 PM PDT 24
Peak memory 215812 kb
Host smart-91b6e7b5-49e9-4fc6-a1ff-849ebabec66b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162698682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.4162698682
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.3046790212
Short name T556
Test name
Test status
Simulation time 52090881 ps
CPU time 0.9 seconds
Started Jul 20 07:15:24 PM PDT 24
Finished Jul 20 07:15:26 PM PDT 24
Peak memory 205936 kb
Host smart-25cb33bc-d09d-44f2-b57d-26e0bb1dea0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046790212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.3046790212
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.128611435
Short name T391
Test name
Test status
Simulation time 840519494 ps
CPU time 4.14 seconds
Started Jul 20 07:15:13 PM PDT 24
Finished Jul 20 07:15:18 PM PDT 24
Peak memory 215080 kb
Host smart-373e32bb-df53-4300-9b68-6ebc2b7c37cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=128611435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.128611435
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.2286096922
Short name T665
Test name
Test status
Simulation time 61958512 ps
CPU time 2.61 seconds
Started Jul 20 07:15:28 PM PDT 24
Finished Jul 20 07:15:31 PM PDT 24
Peak memory 218328 kb
Host smart-cfcb889a-d25a-47d5-b43a-cdadb5723171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286096922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.2286096922
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.1814946135
Short name T817
Test name
Test status
Simulation time 3016800863 ps
CPU time 18.58 seconds
Started Jul 20 07:15:13 PM PDT 24
Finished Jul 20 07:15:32 PM PDT 24
Peak memory 208308 kb
Host smart-6c31ef97-bb6b-4017-82ee-3bfb74f0857f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814946135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.1814946135
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.2142703139
Short name T211
Test name
Test status
Simulation time 92197936 ps
CPU time 4.71 seconds
Started Jul 20 07:15:26 PM PDT 24
Finished Jul 20 07:15:31 PM PDT 24
Peak memory 218828 kb
Host smart-84397d54-3594-440e-9547-966f8cadb5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142703139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.2142703139
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.1125436170
Short name T621
Test name
Test status
Simulation time 283222832 ps
CPU time 3.05 seconds
Started Jul 20 07:15:23 PM PDT 24
Finished Jul 20 07:15:26 PM PDT 24
Peak memory 214036 kb
Host smart-6ec66238-1de2-47ec-8f6e-ff59f1156d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125436170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.1125436170
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_random.538429964
Short name T340
Test name
Test status
Simulation time 42516431 ps
CPU time 3.1 seconds
Started Jul 20 07:15:13 PM PDT 24
Finished Jul 20 07:15:17 PM PDT 24
Peak memory 208128 kb
Host smart-c891c146-0dbb-46b7-8ec5-80db43238eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538429964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.538429964
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.544880601
Short name T265
Test name
Test status
Simulation time 156950611 ps
CPU time 5.25 seconds
Started Jul 20 07:15:13 PM PDT 24
Finished Jul 20 07:15:20 PM PDT 24
Peak memory 206600 kb
Host smart-c48de844-b16f-4104-b301-2dc7f782cd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544880601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.544880601
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.2446222342
Short name T877
Test name
Test status
Simulation time 91032324 ps
CPU time 2.61 seconds
Started Jul 20 07:15:17 PM PDT 24
Finished Jul 20 07:15:21 PM PDT 24
Peak memory 206808 kb
Host smart-63f8234e-cc72-437e-89a7-b546f2c404f5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446222342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.2446222342
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.3092909675
Short name T459
Test name
Test status
Simulation time 84940887 ps
CPU time 2.02 seconds
Started Jul 20 07:15:13 PM PDT 24
Finished Jul 20 07:15:16 PM PDT 24
Peak memory 208388 kb
Host smart-6e6af793-0cf4-4ad8-8a2f-ea2af62affd7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092909675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.3092909675
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.2272887593
Short name T262
Test name
Test status
Simulation time 364019482 ps
CPU time 3.49 seconds
Started Jul 20 07:15:13 PM PDT 24
Finished Jul 20 07:15:17 PM PDT 24
Peak memory 208476 kb
Host smart-76a17725-d8c0-4732-8afb-b55c88132333
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272887593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.2272887593
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.1839931916
Short name T741
Test name
Test status
Simulation time 2346302245 ps
CPU time 12.99 seconds
Started Jul 20 07:15:24 PM PDT 24
Finished Jul 20 07:15:38 PM PDT 24
Peak memory 214196 kb
Host smart-66790360-fa39-4795-bff2-ab8f8a3d0cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839931916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.1839931916
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.1878338877
Short name T672
Test name
Test status
Simulation time 117284634 ps
CPU time 3.73 seconds
Started Jul 20 07:15:14 PM PDT 24
Finished Jul 20 07:15:18 PM PDT 24
Peak memory 207652 kb
Host smart-e15243dd-116d-4c36-a274-87ba83eecdbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878338877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.1878338877
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.3239874319
Short name T176
Test name
Test status
Simulation time 3475654785 ps
CPU time 25.11 seconds
Started Jul 20 07:15:24 PM PDT 24
Finished Jul 20 07:15:50 PM PDT 24
Peak memory 221908 kb
Host smart-d6669079-648e-41c0-9583-3b17e87deff8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239874319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.3239874319
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.1370731106
Short name T673
Test name
Test status
Simulation time 3770759437 ps
CPU time 38.12 seconds
Started Jul 20 07:15:17 PM PDT 24
Finished Jul 20 07:15:56 PM PDT 24
Peak memory 214184 kb
Host smart-837a36fb-e981-46fc-a81a-12ce97a0bf80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370731106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.1370731106
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.2313471802
Short name T748
Test name
Test status
Simulation time 45882568 ps
CPU time 2.24 seconds
Started Jul 20 07:15:25 PM PDT 24
Finished Jul 20 07:15:28 PM PDT 24
Peak memory 209744 kb
Host smart-3545e7b8-b148-4bfa-8979-d7c7b8729edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313471802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.2313471802
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.1337126752
Short name T416
Test name
Test status
Simulation time 37708262 ps
CPU time 0.77 seconds
Started Jul 20 07:15:33 PM PDT 24
Finished Jul 20 07:15:34 PM PDT 24
Peak memory 205856 kb
Host smart-70fe6c26-d881-40b5-8abf-cabb79889429
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337126752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.1337126752
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.2130643526
Short name T525
Test name
Test status
Simulation time 61632691 ps
CPU time 3.7 seconds
Started Jul 20 07:15:34 PM PDT 24
Finished Jul 20 07:15:39 PM PDT 24
Peak memory 209080 kb
Host smart-3a6b5307-5763-441e-9268-57445bf8f9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130643526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2130643526
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.2097020134
Short name T61
Test name
Test status
Simulation time 494316332 ps
CPU time 10.9 seconds
Started Jul 20 07:15:22 PM PDT 24
Finished Jul 20 07:15:33 PM PDT 24
Peak memory 208436 kb
Host smart-4ff35a48-f683-40e1-ad78-6b8461059a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097020134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.2097020134
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.3269218099
Short name T581
Test name
Test status
Simulation time 693698650 ps
CPU time 3.75 seconds
Started Jul 20 07:15:33 PM PDT 24
Finished Jul 20 07:15:38 PM PDT 24
Peak memory 214100 kb
Host smart-817b88c8-56ac-4472-ad99-b52dec80ad55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269218099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.3269218099
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.1375692664
Short name T229
Test name
Test status
Simulation time 1353385166 ps
CPU time 7.96 seconds
Started Jul 20 07:15:22 PM PDT 24
Finished Jul 20 07:15:31 PM PDT 24
Peak memory 209668 kb
Host smart-02075aa0-418e-46e9-a7a3-5b08862367ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375692664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1375692664
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.116432208
Short name T9
Test name
Test status
Simulation time 2873578475 ps
CPU time 6.94 seconds
Started Jul 20 07:15:34 PM PDT 24
Finished Jul 20 07:15:41 PM PDT 24
Peak memory 233564 kb
Host smart-e533f99a-118c-43e2-a20d-f0b2b5be3021
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116432208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.116432208
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.1614528987
Short name T546
Test name
Test status
Simulation time 69795104 ps
CPU time 3.58 seconds
Started Jul 20 07:15:24 PM PDT 24
Finished Jul 20 07:15:28 PM PDT 24
Peak memory 208432 kb
Host smart-15e0036d-6315-409b-9f31-5550b34d6b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614528987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.1614528987
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.3831597151
Short name T893
Test name
Test status
Simulation time 786826604 ps
CPU time 9.23 seconds
Started Jul 20 07:15:24 PM PDT 24
Finished Jul 20 07:15:35 PM PDT 24
Peak memory 208404 kb
Host smart-036b7f1f-272e-432e-b382-8e3a949d2b1f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831597151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.3831597151
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.2837733330
Short name T903
Test name
Test status
Simulation time 7138329282 ps
CPU time 20.85 seconds
Started Jul 20 07:15:25 PM PDT 24
Finished Jul 20 07:15:47 PM PDT 24
Peak memory 208284 kb
Host smart-d3b176c3-2021-4dd2-9b7d-9fc008d2c8bf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837733330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.2837733330
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.2516056212
Short name T746
Test name
Test status
Simulation time 151237541 ps
CPU time 1.9 seconds
Started Jul 20 07:15:25 PM PDT 24
Finished Jul 20 07:15:28 PM PDT 24
Peak memory 207128 kb
Host smart-83000cb0-c013-4a61-ac66-276040645e35
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516056212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.2516056212
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.3148974660
Short name T491
Test name
Test status
Simulation time 557751684 ps
CPU time 3.81 seconds
Started Jul 20 07:15:35 PM PDT 24
Finished Jul 20 07:15:40 PM PDT 24
Peak memory 208628 kb
Host smart-b54b2699-cca7-4b79-a872-bb1bf5198a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148974660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.3148974660
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.3442428020
Short name T564
Test name
Test status
Simulation time 230576332 ps
CPU time 3.04 seconds
Started Jul 20 07:15:23 PM PDT 24
Finished Jul 20 07:15:27 PM PDT 24
Peak memory 206572 kb
Host smart-9290386e-2403-43f6-a818-34e5c2991ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442428020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.3442428020
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.381244193
Short name T309
Test name
Test status
Simulation time 910511374 ps
CPU time 30.73 seconds
Started Jul 20 07:15:33 PM PDT 24
Finished Jul 20 07:16:05 PM PDT 24
Peak memory 214116 kb
Host smart-ece2e1a5-4fb4-48ff-a7ba-d744f6863f6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381244193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.381244193
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.90187001
Short name T723
Test name
Test status
Simulation time 496550936 ps
CPU time 5.16 seconds
Started Jul 20 07:15:34 PM PDT 24
Finished Jul 20 07:15:41 PM PDT 24
Peak memory 208148 kb
Host smart-71fb0175-5d99-4239-b738-ae1ded5dc79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90187001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.90187001
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.3418844152
Short name T99
Test name
Test status
Simulation time 94299618 ps
CPU time 3.45 seconds
Started Jul 20 07:15:32 PM PDT 24
Finished Jul 20 07:15:36 PM PDT 24
Peak memory 209792 kb
Host smart-6d3811d9-ba65-4d1a-bac3-d7e2c80da7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418844152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.3418844152
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.3663224848
Short name T662
Test name
Test status
Simulation time 11391044 ps
CPU time 0.86 seconds
Started Jul 20 07:16:41 PM PDT 24
Finished Jul 20 07:16:43 PM PDT 24
Peak memory 205840 kb
Host smart-1ab12775-925d-4708-89f1-f2284b748c36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663224848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.3663224848
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.1928561124
Short name T59
Test name
Test status
Simulation time 540911504 ps
CPU time 3.2 seconds
Started Jul 20 07:16:44 PM PDT 24
Finished Jul 20 07:16:48 PM PDT 24
Peak memory 209280 kb
Host smart-b9ca1182-c55a-45bb-a39e-f7213392e4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928561124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.1928561124
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.2292055143
Short name T811
Test name
Test status
Simulation time 511744492 ps
CPU time 3.89 seconds
Started Jul 20 07:16:41 PM PDT 24
Finished Jul 20 07:16:45 PM PDT 24
Peak memory 214060 kb
Host smart-09d28cff-6171-458e-add0-0e1a7c225fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292055143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.2292055143
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.4287463081
Short name T293
Test name
Test status
Simulation time 95291179 ps
CPU time 1.67 seconds
Started Jul 20 07:16:40 PM PDT 24
Finished Jul 20 07:16:42 PM PDT 24
Peak memory 214124 kb
Host smart-cd434e53-d5ab-4db1-842f-ccb396779faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287463081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.4287463081
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.3233693630
Short name T783
Test name
Test status
Simulation time 86846748 ps
CPU time 3.17 seconds
Started Jul 20 07:16:40 PM PDT 24
Finished Jul 20 07:16:44 PM PDT 24
Peak memory 207216 kb
Host smart-4adc20ba-0ecb-4c37-add2-25a5ce786d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233693630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.3233693630
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.1342183744
Short name T897
Test name
Test status
Simulation time 462229116 ps
CPU time 5.78 seconds
Started Jul 20 07:16:42 PM PDT 24
Finished Jul 20 07:16:49 PM PDT 24
Peak memory 209540 kb
Host smart-be28e10f-0d01-4120-92e1-08c547a33b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342183744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.1342183744
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.486501896
Short name T277
Test name
Test status
Simulation time 211253690 ps
CPU time 5.85 seconds
Started Jul 20 07:16:43 PM PDT 24
Finished Jul 20 07:16:50 PM PDT 24
Peak memory 207620 kb
Host smart-d93d3ba5-0590-48dd-9148-6bb37d255c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486501896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.486501896
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.2922359468
Short name T611
Test name
Test status
Simulation time 2481691575 ps
CPU time 22.55 seconds
Started Jul 20 07:16:42 PM PDT 24
Finished Jul 20 07:17:06 PM PDT 24
Peak memory 208848 kb
Host smart-863f0153-c4b7-4d80-80bb-6383edaf281d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922359468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.2922359468
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.4213245044
Short name T447
Test name
Test status
Simulation time 34064173 ps
CPU time 2.37 seconds
Started Jul 20 07:16:43 PM PDT 24
Finished Jul 20 07:16:46 PM PDT 24
Peak memory 206728 kb
Host smart-0981a72b-9144-446b-8459-e2a613975478
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213245044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.4213245044
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.839687024
Short name T915
Test name
Test status
Simulation time 26275374 ps
CPU time 1.91 seconds
Started Jul 20 07:16:49 PM PDT 24
Finished Jul 20 07:16:52 PM PDT 24
Peak memory 207068 kb
Host smart-bc91d041-32d9-4152-9b5e-820283190f23
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839687024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.839687024
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.379225244
Short name T433
Test name
Test status
Simulation time 333687896 ps
CPU time 5.13 seconds
Started Jul 20 07:16:49 PM PDT 24
Finished Jul 20 07:16:55 PM PDT 24
Peak memory 207976 kb
Host smart-ccfeae7b-60b0-43c6-a102-8aa4f3d2f6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379225244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.379225244
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.4224694216
Short name T571
Test name
Test status
Simulation time 644910499 ps
CPU time 4.24 seconds
Started Jul 20 07:16:33 PM PDT 24
Finished Jul 20 07:16:38 PM PDT 24
Peak memory 206476 kb
Host smart-14202c39-6c7f-4ff4-97b3-9d75f04799b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224694216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.4224694216
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.3916650454
Short name T788
Test name
Test status
Simulation time 972124074 ps
CPU time 7.12 seconds
Started Jul 20 07:16:44 PM PDT 24
Finished Jul 20 07:16:51 PM PDT 24
Peak memory 206936 kb
Host smart-cecc4785-569a-4d9b-b581-d08853a0a05a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916650454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.3916650454
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.3143077518
Short name T807
Test name
Test status
Simulation time 483244155 ps
CPU time 8.35 seconds
Started Jul 20 07:16:43 PM PDT 24
Finished Jul 20 07:16:52 PM PDT 24
Peak memory 220284 kb
Host smart-1025e957-b163-4b27-a9e4-27639043e214
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143077518 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.3143077518
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.1070394341
Short name T248
Test name
Test status
Simulation time 70338424 ps
CPU time 3.77 seconds
Started Jul 20 07:16:41 PM PDT 24
Finished Jul 20 07:16:46 PM PDT 24
Peak memory 208604 kb
Host smart-7e200cab-3efc-40ee-9335-90161268bdb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070394341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.1070394341
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.3780264569
Short name T548
Test name
Test status
Simulation time 23236408 ps
CPU time 0.86 seconds
Started Jul 20 07:16:49 PM PDT 24
Finished Jul 20 07:16:50 PM PDT 24
Peak memory 205848 kb
Host smart-143e4d0f-3565-439d-bfbf-09232f30eb78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780264569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.3780264569
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.1014472684
Short name T368
Test name
Test status
Simulation time 106587216 ps
CPU time 3.97 seconds
Started Jul 20 07:16:51 PM PDT 24
Finished Jul 20 07:16:56 PM PDT 24
Peak memory 214824 kb
Host smart-9954c7a2-dbff-426e-9f2b-6606a71acedf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1014472684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1014472684
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.1469852425
Short name T559
Test name
Test status
Simulation time 102547615 ps
CPU time 3.92 seconds
Started Jul 20 07:16:49 PM PDT 24
Finished Jul 20 07:16:54 PM PDT 24
Peak memory 210128 kb
Host smart-18fb46db-09c1-4ce6-ad53-83682bd49775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469852425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.1469852425
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.3968713519
Short name T899
Test name
Test status
Simulation time 194463800 ps
CPU time 3.41 seconds
Started Jul 20 07:16:50 PM PDT 24
Finished Jul 20 07:16:55 PM PDT 24
Peak memory 214668 kb
Host smart-27228382-fb2f-4201-8ed5-15fe8401303f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968713519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.3968713519
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.2525124509
Short name T864
Test name
Test status
Simulation time 291287329 ps
CPU time 7.15 seconds
Started Jul 20 07:16:50 PM PDT 24
Finished Jul 20 07:16:59 PM PDT 24
Peak memory 214056 kb
Host smart-1487b50f-be30-4104-a8e6-301f4f9faf5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525124509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.2525124509
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.4040492062
Short name T707
Test name
Test status
Simulation time 92321841 ps
CPU time 3.78 seconds
Started Jul 20 07:16:42 PM PDT 24
Finished Jul 20 07:16:47 PM PDT 24
Peak memory 206992 kb
Host smart-4d450bed-c981-4776-9bd8-a494d995f1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040492062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.4040492062
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.3992748203
Short name T235
Test name
Test status
Simulation time 348165889 ps
CPU time 2.98 seconds
Started Jul 20 07:16:51 PM PDT 24
Finished Jul 20 07:16:55 PM PDT 24
Peak memory 207052 kb
Host smart-1b7f4b2c-b250-4b76-9aef-755d383d2e48
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992748203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3992748203
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.1135877509
Short name T538
Test name
Test status
Simulation time 754456203 ps
CPU time 8.26 seconds
Started Jul 20 07:16:54 PM PDT 24
Finished Jul 20 07:17:03 PM PDT 24
Peak memory 208336 kb
Host smart-4e636dd5-59c4-44f1-8ffa-cdf8475c74ce
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135877509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.1135877509
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.3695791533
Short name T460
Test name
Test status
Simulation time 78825100 ps
CPU time 2.24 seconds
Started Jul 20 07:16:54 PM PDT 24
Finished Jul 20 07:16:57 PM PDT 24
Peak memory 220144 kb
Host smart-e6323fc7-21f5-4972-95a9-1f011ab0fb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695791533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3695791533
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.3889011242
Short name T73
Test name
Test status
Simulation time 209719548 ps
CPU time 4.56 seconds
Started Jul 20 07:16:42 PM PDT 24
Finished Jul 20 07:16:48 PM PDT 24
Peak memory 206624 kb
Host smart-68c40901-bdf4-4a54-a1cb-a5cf4040f383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889011242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3889011242
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.3465401853
Short name T458
Test name
Test status
Simulation time 145241429 ps
CPU time 3.8 seconds
Started Jul 20 07:16:49 PM PDT 24
Finished Jul 20 07:16:55 PM PDT 24
Peak memory 207248 kb
Host smart-ae9481eb-817f-4ac2-aee2-0f6419765622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465401853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.3465401853
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.2479331483
Short name T573
Test name
Test status
Simulation time 14370382 ps
CPU time 0.77 seconds
Started Jul 20 07:16:57 PM PDT 24
Finished Jul 20 07:16:58 PM PDT 24
Peak memory 205800 kb
Host smart-0c02f114-b4a7-4170-90b9-33defcccd77e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479331483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.2479331483
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.553117548
Short name T290
Test name
Test status
Simulation time 131563186 ps
CPU time 7.32 seconds
Started Jul 20 07:16:50 PM PDT 24
Finished Jul 20 07:16:58 PM PDT 24
Peak memory 222244 kb
Host smart-df44358d-5f70-4e03-a95d-5dc2b9e2c1e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=553117548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.553117548
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.3911380129
Short name T28
Test name
Test status
Simulation time 76956564 ps
CPU time 1.54 seconds
Started Jul 20 07:17:02 PM PDT 24
Finished Jul 20 07:17:04 PM PDT 24
Peak memory 214108 kb
Host smart-e4454540-a0b5-43bf-bd7c-86e4bcb11e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911380129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.3911380129
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.3301895571
Short name T303
Test name
Test status
Simulation time 139221424 ps
CPU time 3.43 seconds
Started Jul 20 07:16:49 PM PDT 24
Finished Jul 20 07:16:53 PM PDT 24
Peak memory 209804 kb
Host smart-2c1ae23c-a9d5-4baf-8457-3b1a1cd131b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301895571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.3301895571
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.4129479127
Short name T85
Test name
Test status
Simulation time 1283868048 ps
CPU time 28.18 seconds
Started Jul 20 07:16:58 PM PDT 24
Finished Jul 20 07:17:28 PM PDT 24
Peak memory 214092 kb
Host smart-6b42f91f-0fe1-4e80-895f-9e891e317e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129479127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.4129479127
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.1192540708
Short name T550
Test name
Test status
Simulation time 470792414 ps
CPU time 7.14 seconds
Started Jul 20 07:16:59 PM PDT 24
Finished Jul 20 07:17:07 PM PDT 24
Peak memory 214060 kb
Host smart-e6f05377-5036-4f01-8cd3-97bed66c8ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192540708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1192540708
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.2275583262
Short name T197
Test name
Test status
Simulation time 270220479 ps
CPU time 2.45 seconds
Started Jul 20 07:16:55 PM PDT 24
Finished Jul 20 07:16:58 PM PDT 24
Peak memory 219756 kb
Host smart-7a385cbf-af15-4df1-97a3-34512a27fa37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275583262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.2275583262
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.844119936
Short name T633
Test name
Test status
Simulation time 532142256 ps
CPU time 4.48 seconds
Started Jul 20 07:16:48 PM PDT 24
Finished Jul 20 07:16:53 PM PDT 24
Peak memory 207368 kb
Host smart-5d25f365-0bf2-488b-8f6f-3603d925ceb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844119936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.844119936
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.1811475228
Short name T514
Test name
Test status
Simulation time 41840916 ps
CPU time 1.76 seconds
Started Jul 20 07:16:48 PM PDT 24
Finished Jul 20 07:16:50 PM PDT 24
Peak memory 206648 kb
Host smart-457892ad-aba4-43c4-8230-30e8d12606ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811475228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.1811475228
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.2282191103
Short name T501
Test name
Test status
Simulation time 1926335144 ps
CPU time 19.26 seconds
Started Jul 20 07:16:51 PM PDT 24
Finished Jul 20 07:17:11 PM PDT 24
Peak memory 207792 kb
Host smart-a8fcda6e-5a77-476d-90f9-c7501a561f93
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282191103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.2282191103
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.69958945
Short name T601
Test name
Test status
Simulation time 54983871 ps
CPU time 2.89 seconds
Started Jul 20 07:16:50 PM PDT 24
Finished Jul 20 07:16:54 PM PDT 24
Peak memory 207408 kb
Host smart-3829b788-519e-43a9-8055-992e5e798abc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69958945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.69958945
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.3251575904
Short name T540
Test name
Test status
Simulation time 46922769 ps
CPU time 2.63 seconds
Started Jul 20 07:16:49 PM PDT 24
Finished Jul 20 07:16:53 PM PDT 24
Peak memory 207904 kb
Host smart-f7788455-a63b-4af5-9af7-978dcf9034a7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251575904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.3251575904
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.4119807750
Short name T671
Test name
Test status
Simulation time 278930864 ps
CPU time 2.17 seconds
Started Jul 20 07:16:58 PM PDT 24
Finished Jul 20 07:17:02 PM PDT 24
Peak memory 218072 kb
Host smart-f52a9697-5540-4cf5-b7ec-828e0c697820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119807750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.4119807750
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.692740696
Short name T468
Test name
Test status
Simulation time 926348233 ps
CPU time 13.37 seconds
Started Jul 20 07:16:49 PM PDT 24
Finished Jul 20 07:17:03 PM PDT 24
Peak memory 207844 kb
Host smart-5b332b0b-4a28-4b68-beec-19f43ce9a93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692740696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.692740696
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.1136689425
Short name T175
Test name
Test status
Simulation time 3618603664 ps
CPU time 26.88 seconds
Started Jul 20 07:16:58 PM PDT 24
Finished Jul 20 07:17:27 PM PDT 24
Peak memory 222248 kb
Host smart-debfae15-245e-4707-9196-97d07f4c0739
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136689425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.1136689425
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.1028328760
Short name T239
Test name
Test status
Simulation time 636928857 ps
CPU time 9.67 seconds
Started Jul 20 07:16:58 PM PDT 24
Finished Jul 20 07:17:10 PM PDT 24
Peak memory 218172 kb
Host smart-b47c9b0e-367a-4a44-8226-47b5de9fad8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028328760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.1028328760
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.407295992
Short name T439
Test name
Test status
Simulation time 158015030 ps
CPU time 2.21 seconds
Started Jul 20 07:16:58 PM PDT 24
Finished Jul 20 07:17:02 PM PDT 24
Peak memory 209992 kb
Host smart-58972ee8-6fd4-46f8-a02d-35af1ab2b93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407295992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.407295992
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.2421917676
Short name T757
Test name
Test status
Simulation time 14174485 ps
CPU time 0.89 seconds
Started Jul 20 07:17:00 PM PDT 24
Finished Jul 20 07:17:03 PM PDT 24
Peak memory 205936 kb
Host smart-81e05969-12dd-451b-bb57-7447068b4092
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421917676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2421917676
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.454149056
Short name T895
Test name
Test status
Simulation time 120302051 ps
CPU time 2.32 seconds
Started Jul 20 07:17:01 PM PDT 24
Finished Jul 20 07:17:05 PM PDT 24
Peak memory 215548 kb
Host smart-51ab720f-08e5-4547-ab34-4ab0b129e871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454149056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.454149056
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.1536655917
Short name T749
Test name
Test status
Simulation time 490150507 ps
CPU time 11.07 seconds
Started Jul 20 07:17:00 PM PDT 24
Finished Jul 20 07:17:12 PM PDT 24
Peak memory 208896 kb
Host smart-34c74df2-6c86-47a7-9603-311e5015cf6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536655917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.1536655917
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.428959856
Short name T703
Test name
Test status
Simulation time 123863833 ps
CPU time 1.74 seconds
Started Jul 20 07:16:56 PM PDT 24
Finished Jul 20 07:16:59 PM PDT 24
Peak memory 214076 kb
Host smart-cf419cec-f451-45ba-8cb8-e23c83394ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428959856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.428959856
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.1396715379
Short name T94
Test name
Test status
Simulation time 74873885 ps
CPU time 2.91 seconds
Started Jul 20 07:16:57 PM PDT 24
Finished Jul 20 07:17:00 PM PDT 24
Peak memory 214076 kb
Host smart-48006044-bda9-4bc5-8271-8370ced5d55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396715379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.1396715379
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_random.1465993635
Short name T371
Test name
Test status
Simulation time 176270031 ps
CPU time 3.1 seconds
Started Jul 20 07:16:59 PM PDT 24
Finished Jul 20 07:17:04 PM PDT 24
Peak memory 207260 kb
Host smart-a2131607-4e7e-4476-bfe1-8143014de483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465993635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.1465993635
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.9148222
Short name T304
Test name
Test status
Simulation time 56660315 ps
CPU time 2.55 seconds
Started Jul 20 07:16:57 PM PDT 24
Finished Jul 20 07:17:00 PM PDT 24
Peak memory 206532 kb
Host smart-46d9d8dd-a8e2-4117-be5e-20ca8def6db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9148222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.9148222
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.2753445201
Short name T740
Test name
Test status
Simulation time 118076045 ps
CPU time 4.48 seconds
Started Jul 20 07:16:57 PM PDT 24
Finished Jul 20 07:17:03 PM PDT 24
Peak memory 206536 kb
Host smart-969630f8-03a6-4dfa-b643-27e298a8c472
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753445201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.2753445201
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.4031049088
Short name T574
Test name
Test status
Simulation time 262237032 ps
CPU time 5.22 seconds
Started Jul 20 07:16:56 PM PDT 24
Finished Jul 20 07:17:02 PM PDT 24
Peak memory 207764 kb
Host smart-89e38092-b082-4d30-8e40-3bb332e14088
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031049088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.4031049088
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.18177635
Short name T187
Test name
Test status
Simulation time 762204582 ps
CPU time 5.72 seconds
Started Jul 20 07:17:00 PM PDT 24
Finished Jul 20 07:17:08 PM PDT 24
Peak memory 207612 kb
Host smart-dd7619b2-867e-4fc3-9d7a-8dbcdb7fd0c6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18177635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.18177635
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.2439178712
Short name T854
Test name
Test status
Simulation time 3667829969 ps
CPU time 21.57 seconds
Started Jul 20 07:16:57 PM PDT 24
Finished Jul 20 07:17:20 PM PDT 24
Peak memory 209676 kb
Host smart-051a3ea3-fa96-4ded-8124-c8a5ad67dabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439178712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2439178712
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.2854507098
Short name T889
Test name
Test status
Simulation time 66207043 ps
CPU time 2.21 seconds
Started Jul 20 07:16:58 PM PDT 24
Finished Jul 20 07:17:01 PM PDT 24
Peak memory 206656 kb
Host smart-66bef70b-bf37-4772-a213-5d57f2ccb319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854507098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.2854507098
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.2057421405
Short name T555
Test name
Test status
Simulation time 115691120 ps
CPU time 5.52 seconds
Started Jul 20 07:16:59 PM PDT 24
Finished Jul 20 07:17:06 PM PDT 24
Peak memory 208516 kb
Host smart-1c73f19f-f5c9-455a-827e-7567dfe0683e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057421405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2057421405
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.2869365249
Short name T95
Test name
Test status
Simulation time 42189314 ps
CPU time 1.97 seconds
Started Jul 20 07:16:57 PM PDT 24
Finished Jul 20 07:17:01 PM PDT 24
Peak memory 209704 kb
Host smart-e8c0356e-e74a-474e-9725-1e6247d24b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869365249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2869365249
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.2617743455
Short name T512
Test name
Test status
Simulation time 8868841 ps
CPU time 0.8 seconds
Started Jul 20 07:17:10 PM PDT 24
Finished Jul 20 07:17:11 PM PDT 24
Peak memory 205844 kb
Host smart-5c86a20c-f7d4-4f3b-993e-f088fdd8fbca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617743455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.2617743455
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.1025072093
Short name T202
Test name
Test status
Simulation time 109564463 ps
CPU time 3.03 seconds
Started Jul 20 07:17:07 PM PDT 24
Finished Jul 20 07:17:11 PM PDT 24
Peak memory 218108 kb
Host smart-189248b9-fe5e-4865-a63b-3f021b8c9c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025072093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.1025072093
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.1709006950
Short name T321
Test name
Test status
Simulation time 1195861658 ps
CPU time 4.76 seconds
Started Jul 20 07:17:06 PM PDT 24
Finished Jul 20 07:17:11 PM PDT 24
Peak memory 218136 kb
Host smart-f974a6b2-3f74-4e9d-a35b-e0975fd9d931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709006950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1709006950
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.340798421
Short name T591
Test name
Test status
Simulation time 269960529 ps
CPU time 3.73 seconds
Started Jul 20 07:17:07 PM PDT 24
Finished Jul 20 07:17:12 PM PDT 24
Peak memory 214016 kb
Host smart-e91fb8d1-9b5f-4b1b-a92a-730487a157c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340798421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.340798421
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.2059685364
Short name T57
Test name
Test status
Simulation time 138309172 ps
CPU time 2.84 seconds
Started Jul 20 07:17:10 PM PDT 24
Finished Jul 20 07:17:13 PM PDT 24
Peak memory 219900 kb
Host smart-238c781f-e93b-4648-8250-e49e195bf45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059685364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.2059685364
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.1990379115
Short name T119
Test name
Test status
Simulation time 1618107253 ps
CPU time 26.04 seconds
Started Jul 20 07:17:09 PM PDT 24
Finished Jul 20 07:17:36 PM PDT 24
Peak memory 208768 kb
Host smart-e88a2e7d-b6cd-4fdc-bef1-8c54a8270369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990379115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.1990379115
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.1055341038
Short name T666
Test name
Test status
Simulation time 176714453 ps
CPU time 4.94 seconds
Started Jul 20 07:17:07 PM PDT 24
Finished Jul 20 07:17:13 PM PDT 24
Peak memory 207628 kb
Host smart-e2945573-8d1f-40c3-9468-69539e2b848c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055341038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.1055341038
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.2749438027
Short name T537
Test name
Test status
Simulation time 67086153 ps
CPU time 2.27 seconds
Started Jul 20 07:17:07 PM PDT 24
Finished Jul 20 07:17:11 PM PDT 24
Peak memory 206588 kb
Host smart-bec1c7c4-f1c7-46fa-a861-276d266d2d84
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749438027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.2749438027
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.3529112710
Short name T731
Test name
Test status
Simulation time 263824599 ps
CPU time 5.83 seconds
Started Jul 20 07:17:07 PM PDT 24
Finished Jul 20 07:17:14 PM PDT 24
Peak memory 208768 kb
Host smart-c29d0297-6d8c-4973-b939-646c35d96c84
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529112710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.3529112710
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.1532494161
Short name T905
Test name
Test status
Simulation time 570941803 ps
CPU time 12.44 seconds
Started Jul 20 07:17:08 PM PDT 24
Finished Jul 20 07:17:21 PM PDT 24
Peak memory 208628 kb
Host smart-a9f0bd24-c5c0-4a6e-9c03-ad04edc7049b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532494161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.1532494161
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.1356646746
Short name T734
Test name
Test status
Simulation time 177928450 ps
CPU time 4.26 seconds
Started Jul 20 07:17:08 PM PDT 24
Finished Jul 20 07:17:13 PM PDT 24
Peak memory 209800 kb
Host smart-c902a8b4-ee4e-4eae-a733-9c21ffdce26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356646746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.1356646746
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.158117842
Short name T680
Test name
Test status
Simulation time 146631979 ps
CPU time 4.61 seconds
Started Jul 20 07:16:58 PM PDT 24
Finished Jul 20 07:17:05 PM PDT 24
Peak memory 207636 kb
Host smart-d52d69f2-4f8f-481e-bba5-daadb731f927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158117842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.158117842
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.2841670653
Short name T260
Test name
Test status
Simulation time 530340455 ps
CPU time 5.29 seconds
Started Jul 20 07:17:12 PM PDT 24
Finished Jul 20 07:17:18 PM PDT 24
Peak memory 209788 kb
Host smart-783c56e1-1a9b-4e1a-8993-7ac1e83afdb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841670653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.2841670653
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.2257083298
Short name T618
Test name
Test status
Simulation time 144527722 ps
CPU time 2.31 seconds
Started Jul 20 07:17:10 PM PDT 24
Finished Jul 20 07:17:12 PM PDT 24
Peak memory 214136 kb
Host smart-4437a557-61c6-48e4-a33d-c3b1d1dfefbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257083298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.2257083298
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.2091836198
Short name T575
Test name
Test status
Simulation time 17100358 ps
CPU time 0.84 seconds
Started Jul 20 07:17:21 PM PDT 24
Finished Jul 20 07:17:23 PM PDT 24
Peak memory 205868 kb
Host smart-2c666c63-c499-4217-a28d-72f85d0e5706
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091836198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.2091836198
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.670826179
Short name T862
Test name
Test status
Simulation time 69573387 ps
CPU time 2.38 seconds
Started Jul 20 07:17:22 PM PDT 24
Finished Jul 20 07:17:25 PM PDT 24
Peak memory 214108 kb
Host smart-22ec9693-83bf-4fa4-91fa-d721e7b97250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670826179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.670826179
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.1922729547
Short name T646
Test name
Test status
Simulation time 165630527 ps
CPU time 3.56 seconds
Started Jul 20 07:17:27 PM PDT 24
Finished Jul 20 07:17:32 PM PDT 24
Peak memory 207756 kb
Host smart-9bb930d5-cd12-4a2d-bb7b-4d687f7be0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922729547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.1922729547
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.1858610811
Short name T333
Test name
Test status
Simulation time 186883928 ps
CPU time 3.2 seconds
Started Jul 20 07:17:19 PM PDT 24
Finished Jul 20 07:17:23 PM PDT 24
Peak memory 214012 kb
Host smart-ed4cfaef-e436-43b3-a3cc-318138385506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858610811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.1858610811
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.2481463240
Short name T528
Test name
Test status
Simulation time 710880971 ps
CPU time 7.13 seconds
Started Jul 20 07:17:20 PM PDT 24
Finished Jul 20 07:17:29 PM PDT 24
Peak memory 214076 kb
Host smart-17bd47e6-c056-4820-ba9e-76eb6213dbca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481463240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.2481463240
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.3660731801
Short name T291
Test name
Test status
Simulation time 1216249337 ps
CPU time 30.77 seconds
Started Jul 20 07:17:26 PM PDT 24
Finished Jul 20 07:17:58 PM PDT 24
Peak memory 208740 kb
Host smart-a5f68d12-db27-4fc8-aa9c-6a8db004bd91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660731801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3660731801
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.1178524156
Short name T745
Test name
Test status
Simulation time 153487450 ps
CPU time 3.74 seconds
Started Jul 20 07:17:11 PM PDT 24
Finished Jul 20 07:17:15 PM PDT 24
Peak memory 208356 kb
Host smart-6ca86760-8644-493d-849c-2f349a38f3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178524156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.1178524156
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.2388810896
Short name T484
Test name
Test status
Simulation time 4935046695 ps
CPU time 17.84 seconds
Started Jul 20 07:17:19 PM PDT 24
Finished Jul 20 07:17:38 PM PDT 24
Peak memory 207940 kb
Host smart-91f69fef-d66b-410a-921f-c7970ed6b6ce
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388810896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.2388810896
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.2729075180
Short name T186
Test name
Test status
Simulation time 364200304 ps
CPU time 4.39 seconds
Started Jul 20 07:17:20 PM PDT 24
Finished Jul 20 07:17:26 PM PDT 24
Peak memory 206696 kb
Host smart-d2be48bf-3002-4d2a-8116-94248f38cda2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729075180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2729075180
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.2844382165
Short name T826
Test name
Test status
Simulation time 404991515 ps
CPU time 2.66 seconds
Started Jul 20 07:17:19 PM PDT 24
Finished Jul 20 07:17:22 PM PDT 24
Peak memory 208976 kb
Host smart-edbae94b-c5b1-4e7e-8e9d-2876db31cd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844382165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2844382165
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.1828673358
Short name T376
Test name
Test status
Simulation time 631253512 ps
CPU time 12.56 seconds
Started Jul 20 07:17:09 PM PDT 24
Finished Jul 20 07:17:22 PM PDT 24
Peak memory 208064 kb
Host smart-2cef30c3-4139-4bc9-a5e0-e9aac5cdaa86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828673358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.1828673358
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.911156289
Short name T106
Test name
Test status
Simulation time 329117920 ps
CPU time 10.38 seconds
Started Jul 20 07:17:19 PM PDT 24
Finished Jul 20 07:17:30 PM PDT 24
Peak memory 222340 kb
Host smart-bfa021a8-f072-4d85-9b92-3627fbbb83e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911156289 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.911156289
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.1950385189
Short name T629
Test name
Test status
Simulation time 406392134 ps
CPU time 3.66 seconds
Started Jul 20 07:17:21 PM PDT 24
Finished Jul 20 07:17:26 PM PDT 24
Peak memory 207820 kb
Host smart-dbde6ab1-e39e-404d-b40e-22e12f112471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950385189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.1950385189
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.3305315825
Short name T145
Test name
Test status
Simulation time 244078920 ps
CPU time 2.19 seconds
Started Jul 20 07:17:19 PM PDT 24
Finished Jul 20 07:17:22 PM PDT 24
Peak memory 209848 kb
Host smart-e046a19b-736d-4d74-964b-db0c9155ff96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305315825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.3305315825
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.1841370030
Short name T536
Test name
Test status
Simulation time 30180192 ps
CPU time 0.78 seconds
Started Jul 20 07:17:29 PM PDT 24
Finished Jul 20 07:17:32 PM PDT 24
Peak memory 205800 kb
Host smart-404042c2-409a-4fd3-a965-02f35acc8ecb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841370030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1841370030
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.1534192191
Short name T886
Test name
Test status
Simulation time 100970810 ps
CPU time 2.76 seconds
Started Jul 20 07:17:21 PM PDT 24
Finished Jul 20 07:17:25 PM PDT 24
Peak memory 207832 kb
Host smart-8c501f5b-c2af-4ec7-bbad-466762042afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534192191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.1534192191
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.3523474785
Short name T850
Test name
Test status
Simulation time 200379339 ps
CPU time 4.97 seconds
Started Jul 20 07:17:18 PM PDT 24
Finished Jul 20 07:17:23 PM PDT 24
Peak memory 209604 kb
Host smart-c95d8d05-355d-4f49-9dd2-879e0529100a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523474785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.3523474785
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.4156972599
Short name T294
Test name
Test status
Simulation time 155712921 ps
CPU time 2.13 seconds
Started Jul 20 07:17:29 PM PDT 24
Finished Jul 20 07:17:34 PM PDT 24
Peak memory 214120 kb
Host smart-c2f52090-5a9a-4199-9aab-352e141b4903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156972599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.4156972599
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.2405120658
Short name T623
Test name
Test status
Simulation time 362239599 ps
CPU time 3.2 seconds
Started Jul 20 07:17:20 PM PDT 24
Finished Jul 20 07:17:24 PM PDT 24
Peak memory 215048 kb
Host smart-e9fa0b97-57c4-486e-a2a6-4c9dcf97e2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405120658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.2405120658
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.82876316
Short name T878
Test name
Test status
Simulation time 35983595 ps
CPU time 2.44 seconds
Started Jul 20 07:17:27 PM PDT 24
Finished Jul 20 07:17:31 PM PDT 24
Peak memory 207452 kb
Host smart-9d83550e-1a4c-45be-8109-31b4356d2b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82876316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.82876316
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.3737955040
Short name T500
Test name
Test status
Simulation time 123454047 ps
CPU time 2.2 seconds
Started Jul 20 07:17:26 PM PDT 24
Finished Jul 20 07:17:29 PM PDT 24
Peak memory 206816 kb
Host smart-b8d9f4e5-cd79-4cf8-894b-1459c9b7771d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737955040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.3737955040
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.4109503290
Short name T373
Test name
Test status
Simulation time 66539114 ps
CPU time 3.35 seconds
Started Jul 20 07:17:20 PM PDT 24
Finished Jul 20 07:17:24 PM PDT 24
Peak memory 207788 kb
Host smart-899e45e2-0358-41af-933b-1f8ca4a53777
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109503290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.4109503290
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.3090163020
Short name T698
Test name
Test status
Simulation time 32468667 ps
CPU time 2.28 seconds
Started Jul 20 07:17:18 PM PDT 24
Finished Jul 20 07:17:20 PM PDT 24
Peak memory 206668 kb
Host smart-1e316261-5ed7-40d7-aec6-6837835c8e28
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090163020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3090163020
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.1566460351
Short name T327
Test name
Test status
Simulation time 547298883 ps
CPU time 2.98 seconds
Started Jul 20 07:17:20 PM PDT 24
Finished Jul 20 07:17:24 PM PDT 24
Peak memory 206720 kb
Host smart-8690709a-87c7-4eee-b3ce-1d433c7c476b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566460351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.1566460351
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2245242921
Short name T519
Test name
Test status
Simulation time 28718511 ps
CPU time 1.96 seconds
Started Jul 20 07:17:28 PM PDT 24
Finished Jul 20 07:17:32 PM PDT 24
Peak memory 207288 kb
Host smart-cd1d9119-6eb4-4b90-b40f-5a9ad147378e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245242921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2245242921
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.2944625109
Short name T409
Test name
Test status
Simulation time 235188042 ps
CPU time 2.31 seconds
Started Jul 20 07:17:20 PM PDT 24
Finished Jul 20 07:17:24 PM PDT 24
Peak memory 206608 kb
Host smart-676502e0-c126-4e74-8bc3-ce4d4340f99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944625109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.2944625109
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.916590254
Short name T177
Test name
Test status
Simulation time 600055040 ps
CPU time 21.93 seconds
Started Jul 20 07:17:30 PM PDT 24
Finished Jul 20 07:17:54 PM PDT 24
Peak memory 216612 kb
Host smart-b25089fe-3f72-43c9-8cb7-e011156d37ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916590254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.916590254
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.947692072
Short name T755
Test name
Test status
Simulation time 281476022 ps
CPU time 19.83 seconds
Started Jul 20 07:17:28 PM PDT 24
Finished Jul 20 07:17:50 PM PDT 24
Peak memory 222508 kb
Host smart-efe01dcb-91d8-4eb6-bfa4-24f4758402e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947692072 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.947692072
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.1260723637
Short name T630
Test name
Test status
Simulation time 73729553 ps
CPU time 2.6 seconds
Started Jul 20 07:17:19 PM PDT 24
Finished Jul 20 07:17:22 PM PDT 24
Peak memory 207180 kb
Host smart-f064f3c5-973a-4004-9be8-8da854be6f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260723637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1260723637
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.3007983791
Short name T635
Test name
Test status
Simulation time 17285336 ps
CPU time 0.71 seconds
Started Jul 20 07:17:27 PM PDT 24
Finished Jul 20 07:17:29 PM PDT 24
Peak memory 205860 kb
Host smart-cf0fb90d-8904-4a67-81bc-124b3ade9240
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007983791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.3007983791
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.487632041
Short name T259
Test name
Test status
Simulation time 225221570 ps
CPU time 11.39 seconds
Started Jul 20 07:17:30 PM PDT 24
Finished Jul 20 07:17:44 PM PDT 24
Peak memory 214040 kb
Host smart-6865317d-8f0e-482d-bfd3-c7574b5d5213
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=487632041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.487632041
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.418874437
Short name T712
Test name
Test status
Simulation time 384727471 ps
CPU time 4.95 seconds
Started Jul 20 07:17:29 PM PDT 24
Finished Jul 20 07:17:36 PM PDT 24
Peak memory 214088 kb
Host smart-02597541-3423-496d-be7f-be17057c3d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418874437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.418874437
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.2345459374
Short name T431
Test name
Test status
Simulation time 559106249 ps
CPU time 5.33 seconds
Started Jul 20 07:17:29 PM PDT 24
Finished Jul 20 07:17:37 PM PDT 24
Peak memory 207200 kb
Host smart-0bbe7da6-bb0f-49a4-8321-a10aed691929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345459374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.2345459374
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.3095585432
Short name T648
Test name
Test status
Simulation time 44449752 ps
CPU time 2.58 seconds
Started Jul 20 07:17:34 PM PDT 24
Finished Jul 20 07:17:39 PM PDT 24
Peak memory 222136 kb
Host smart-63f26642-e629-4364-9986-edfa1c61de7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095585432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.3095585432
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.4250108977
Short name T717
Test name
Test status
Simulation time 836586743 ps
CPU time 2.72 seconds
Started Jul 20 07:17:29 PM PDT 24
Finished Jul 20 07:17:33 PM PDT 24
Peak memory 217736 kb
Host smart-6278774f-6928-45e6-9015-58ad33ee2874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250108977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.4250108977
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.2297499475
Short name T549
Test name
Test status
Simulation time 679800819 ps
CPU time 6 seconds
Started Jul 20 07:17:28 PM PDT 24
Finished Jul 20 07:17:36 PM PDT 24
Peak memory 207960 kb
Host smart-4f6b8403-27a4-4040-8a7f-14ca93210e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297499475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.2297499475
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.1664151746
Short name T806
Test name
Test status
Simulation time 253591354 ps
CPU time 3.59 seconds
Started Jul 20 07:17:32 PM PDT 24
Finished Jul 20 07:17:38 PM PDT 24
Peak memory 208304 kb
Host smart-1fab7393-287d-4ac5-8106-a64283c6e799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664151746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.1664151746
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.2939585067
Short name T810
Test name
Test status
Simulation time 819447370 ps
CPU time 26.72 seconds
Started Jul 20 07:17:27 PM PDT 24
Finished Jul 20 07:17:56 PM PDT 24
Peak memory 208204 kb
Host smart-51034910-cd14-4f2c-9a72-65abb9db787a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939585067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.2939585067
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.1247247089
Short name T796
Test name
Test status
Simulation time 751136649 ps
CPU time 6.17 seconds
Started Jul 20 07:17:28 PM PDT 24
Finished Jul 20 07:17:36 PM PDT 24
Peak memory 207864 kb
Host smart-be9b80ae-aea4-47a4-beb9-beefbeefed0e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247247089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.1247247089
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.91405809
Short name T709
Test name
Test status
Simulation time 160966078 ps
CPU time 3.03 seconds
Started Jul 20 07:17:34 PM PDT 24
Finished Jul 20 07:17:40 PM PDT 24
Peak memory 206744 kb
Host smart-d7406eb6-e2d1-4e16-af0d-d8de427f763d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91405809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.91405809
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.600081080
Short name T896
Test name
Test status
Simulation time 258935791 ps
CPU time 2.47 seconds
Started Jul 20 07:17:33 PM PDT 24
Finished Jul 20 07:17:38 PM PDT 24
Peak memory 208076 kb
Host smart-675166f1-c7b1-4557-8dac-d3338da28bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600081080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.600081080
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.363658306
Short name T624
Test name
Test status
Simulation time 2177442361 ps
CPU time 17.32 seconds
Started Jul 20 07:17:30 PM PDT 24
Finished Jul 20 07:17:50 PM PDT 24
Peak memory 208496 kb
Host smart-edcddb43-7aee-4893-be3e-110c3e6b1566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363658306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.363658306
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.439789369
Short name T812
Test name
Test status
Simulation time 657058682 ps
CPU time 13.01 seconds
Started Jul 20 07:17:28 PM PDT 24
Finished Jul 20 07:17:43 PM PDT 24
Peak memory 222132 kb
Host smart-657c8aa0-7946-44f1-8bf5-cfd28079625e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439789369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.439789369
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.2302101717
Short name T267
Test name
Test status
Simulation time 38223449 ps
CPU time 2.84 seconds
Started Jul 20 07:17:31 PM PDT 24
Finished Jul 20 07:17:36 PM PDT 24
Peak memory 208076 kb
Host smart-510bc061-6049-4e1f-951e-cc8312ecfd4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302101717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.2302101717
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.337004417
Short name T508
Test name
Test status
Simulation time 47657500 ps
CPU time 1.99 seconds
Started Jul 20 07:17:33 PM PDT 24
Finished Jul 20 07:17:37 PM PDT 24
Peak memory 209612 kb
Host smart-4fa41e49-d2cf-45ac-bc72-f4226f90bce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337004417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.337004417
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.581611505
Short name T718
Test name
Test status
Simulation time 35180663 ps
CPU time 0.73 seconds
Started Jul 20 07:17:38 PM PDT 24
Finished Jul 20 07:17:43 PM PDT 24
Peak memory 205864 kb
Host smart-59dd5e5d-b876-4627-ad61-732dacedf00d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581611505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.581611505
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.1653343772
Short name T328
Test name
Test status
Simulation time 698446167 ps
CPU time 17.25 seconds
Started Jul 20 07:17:48 PM PDT 24
Finished Jul 20 07:18:15 PM PDT 24
Peak memory 215040 kb
Host smart-4e600339-b649-4088-aa75-1f20a78c6606
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1653343772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.1653343772
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.3443696770
Short name T852
Test name
Test status
Simulation time 3564024479 ps
CPU time 35.59 seconds
Started Jul 20 07:17:38 PM PDT 24
Finished Jul 20 07:18:19 PM PDT 24
Peak memory 220152 kb
Host smart-7963137c-c059-4c2e-9a57-91c81ea27d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443696770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.3443696770
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.1290746820
Short name T444
Test name
Test status
Simulation time 116631007 ps
CPU time 1.92 seconds
Started Jul 20 07:17:37 PM PDT 24
Finished Jul 20 07:17:43 PM PDT 24
Peak memory 214368 kb
Host smart-436fc9c0-4cd8-4ef4-9a26-1af039bcc04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290746820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1290746820
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.3536091477
Short name T473
Test name
Test status
Simulation time 829611600 ps
CPU time 5.54 seconds
Started Jul 20 07:17:36 PM PDT 24
Finished Jul 20 07:17:46 PM PDT 24
Peak memory 222164 kb
Host smart-771ddec0-a2b4-49c7-aa73-621bb9a5a63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536091477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.3536091477
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.685298411
Short name T200
Test name
Test status
Simulation time 57776523 ps
CPU time 2.89 seconds
Started Jul 20 07:17:47 PM PDT 24
Finished Jul 20 07:18:00 PM PDT 24
Peak memory 222156 kb
Host smart-7e1c64f3-b541-4c88-82cd-49f572c2d8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685298411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.685298411
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.4228510128
Short name T655
Test name
Test status
Simulation time 185275016 ps
CPU time 1.96 seconds
Started Jul 20 07:17:42 PM PDT 24
Finished Jul 20 07:17:53 PM PDT 24
Peak memory 207152 kb
Host smart-74a9bb16-8a99-4bfa-8cee-e62f657659b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228510128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.4228510128
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.1422857738
Short name T638
Test name
Test status
Simulation time 502661448 ps
CPU time 13.45 seconds
Started Jul 20 07:17:34 PM PDT 24
Finished Jul 20 07:17:50 PM PDT 24
Peak memory 208208 kb
Host smart-bc1cb4ef-1754-4482-b440-b41483817d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422857738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.1422857738
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.3308328388
Short name T626
Test name
Test status
Simulation time 1289615671 ps
CPU time 10.21 seconds
Started Jul 20 07:17:48 PM PDT 24
Finished Jul 20 07:18:08 PM PDT 24
Peak memory 206788 kb
Host smart-58760f5c-a46e-4603-8f2a-44295310d9d6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308328388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.3308328388
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.1213689243
Short name T647
Test name
Test status
Simulation time 865364709 ps
CPU time 28.18 seconds
Started Jul 20 07:17:41 PM PDT 24
Finished Jul 20 07:18:17 PM PDT 24
Peak memory 207872 kb
Host smart-f203d9d6-9a0a-4f9d-8dd4-bfde3751839a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213689243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1213689243
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.3570136787
Short name T362
Test name
Test status
Simulation time 586886448 ps
CPU time 4.82 seconds
Started Jul 20 07:17:39 PM PDT 24
Finished Jul 20 07:17:49 PM PDT 24
Peak memory 206536 kb
Host smart-bf918572-9b99-4952-b708-fb697fb463ec
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570136787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.3570136787
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.1910522522
Short name T250
Test name
Test status
Simulation time 74064113 ps
CPU time 3.94 seconds
Started Jul 20 07:17:37 PM PDT 24
Finished Jul 20 07:17:45 PM PDT 24
Peak memory 214072 kb
Host smart-116da86b-262b-4de4-b277-3d7ecb4b81da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910522522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.1910522522
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.2482683739
Short name T902
Test name
Test status
Simulation time 112177837 ps
CPU time 1.69 seconds
Started Jul 20 07:17:31 PM PDT 24
Finished Jul 20 07:17:35 PM PDT 24
Peak memory 206592 kb
Host smart-ffeef47b-fcfd-4a86-9577-6f12357660f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482683739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.2482683739
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.287556687
Short name T266
Test name
Test status
Simulation time 545826951 ps
CPU time 10.46 seconds
Started Jul 20 07:17:37 PM PDT 24
Finished Jul 20 07:17:52 PM PDT 24
Peak memory 208008 kb
Host smart-4382a9cf-cb6d-4b43-830f-af42f34beb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287556687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.287556687
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.1027663868
Short name T12
Test name
Test status
Simulation time 76856137 ps
CPU time 2.89 seconds
Started Jul 20 07:17:37 PM PDT 24
Finished Jul 20 07:17:45 PM PDT 24
Peak memory 209892 kb
Host smart-b9360e99-4675-4428-9404-a88952afc68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027663868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.1027663868
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.280659803
Short name T469
Test name
Test status
Simulation time 14328527 ps
CPU time 0.86 seconds
Started Jul 20 07:17:49 PM PDT 24
Finished Jul 20 07:18:00 PM PDT 24
Peak memory 205864 kb
Host smart-ce02a5f5-5e32-4f0e-a7b1-147683d7aa6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280659803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.280659803
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.906326049
Short name T134
Test name
Test status
Simulation time 56666393 ps
CPU time 3.7 seconds
Started Jul 20 07:17:37 PM PDT 24
Finished Jul 20 07:17:45 PM PDT 24
Peak memory 214092 kb
Host smart-492200dc-1a42-4cb3-91bc-b73bbc505ac5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=906326049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.906326049
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.2501357450
Short name T822
Test name
Test status
Simulation time 36204686 ps
CPU time 1.63 seconds
Started Jul 20 07:17:47 PM PDT 24
Finished Jul 20 07:17:59 PM PDT 24
Peak memory 215980 kb
Host smart-a4451570-b0b7-4398-8629-23e80cde0a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501357450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.2501357450
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.3105494880
Short name T11
Test name
Test status
Simulation time 129520508 ps
CPU time 2.96 seconds
Started Jul 20 07:17:40 PM PDT 24
Finished Jul 20 07:17:51 PM PDT 24
Peak memory 214144 kb
Host smart-425dff67-a75c-4370-a8bc-d59a8c0928cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105494880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.3105494880
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.1462125076
Short name T318
Test name
Test status
Simulation time 112495573 ps
CPU time 2.27 seconds
Started Jul 20 07:17:46 PM PDT 24
Finished Jul 20 07:17:58 PM PDT 24
Peak memory 214092 kb
Host smart-7402e99c-a249-48f1-b4c0-0baa721fd018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462125076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.1462125076
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.1749866130
Short name T855
Test name
Test status
Simulation time 114444279 ps
CPU time 3.84 seconds
Started Jul 20 07:17:49 PM PDT 24
Finished Jul 20 07:18:02 PM PDT 24
Peak memory 214000 kb
Host smart-29448119-08d9-4b3a-9d08-97c341806580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749866130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.1749866130
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_random.3547226541
Short name T799
Test name
Test status
Simulation time 1155197609 ps
CPU time 8.48 seconds
Started Jul 20 07:17:37 PM PDT 24
Finished Jul 20 07:17:49 PM PDT 24
Peak memory 207620 kb
Host smart-b514b214-854e-4341-84c0-36c7d467b482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547226541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.3547226541
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.3076068799
Short name T768
Test name
Test status
Simulation time 74189730 ps
CPU time 3.37 seconds
Started Jul 20 07:17:37 PM PDT 24
Finished Jul 20 07:17:44 PM PDT 24
Peak memory 208196 kb
Host smart-5d88f532-5d46-42df-817c-16cd186ee95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076068799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.3076068799
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.353918934
Short name T853
Test name
Test status
Simulation time 92225447 ps
CPU time 3.93 seconds
Started Jul 20 07:17:38 PM PDT 24
Finished Jul 20 07:17:46 PM PDT 24
Peak memory 208404 kb
Host smart-ce8651ca-44c6-4e7a-9455-55d200d992b5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353918934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.353918934
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.1836440620
Short name T585
Test name
Test status
Simulation time 22355278 ps
CPU time 1.81 seconds
Started Jul 20 07:17:37 PM PDT 24
Finished Jul 20 07:17:42 PM PDT 24
Peak memory 208176 kb
Host smart-66d4ed68-7c5e-4cd6-bccd-c47639fb16aa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836440620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.1836440620
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.4202466832
Short name T463
Test name
Test status
Simulation time 343357235 ps
CPU time 9.82 seconds
Started Jul 20 07:17:38 PM PDT 24
Finished Jul 20 07:17:53 PM PDT 24
Peak memory 207960 kb
Host smart-3bb8caaa-fd37-4500-9c34-b422792e8743
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202466832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.4202466832
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.3809383483
Short name T231
Test name
Test status
Simulation time 721350456 ps
CPU time 2.78 seconds
Started Jul 20 07:17:49 PM PDT 24
Finished Jul 20 07:18:01 PM PDT 24
Peak memory 217944 kb
Host smart-12b1c9fa-e0db-4ddd-bb9c-2ca9ebd62879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809383483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.3809383483
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.1397397877
Short name T846
Test name
Test status
Simulation time 436953207 ps
CPU time 7.84 seconds
Started Jul 20 07:17:34 PM PDT 24
Finished Jul 20 07:17:44 PM PDT 24
Peak memory 207752 kb
Host smart-b857bc43-bf6d-41a4-be61-582ab8a7cc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397397877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1397397877
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.495041087
Short name T784
Test name
Test status
Simulation time 4908334331 ps
CPU time 40.24 seconds
Started Jul 20 07:17:48 PM PDT 24
Finished Jul 20 07:18:38 PM PDT 24
Peak memory 222456 kb
Host smart-e6f55a0e-cf40-4a3f-8838-a1a732b33c7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495041087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.495041087
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.3794343475
Short name T111
Test name
Test status
Simulation time 196494396 ps
CPU time 7.24 seconds
Started Jul 20 07:17:48 PM PDT 24
Finished Jul 20 07:18:05 PM PDT 24
Peak memory 218064 kb
Host smart-96a66c2d-f604-47dd-ae94-3c58f5240c6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794343475 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.3794343475
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.725984587
Short name T640
Test name
Test status
Simulation time 261024822 ps
CPU time 9.55 seconds
Started Jul 20 07:17:48 PM PDT 24
Finished Jul 20 07:18:07 PM PDT 24
Peak memory 217964 kb
Host smart-6a9584a7-29d4-484c-b381-b37953d1e145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725984587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.725984587
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.2908296903
Short name T164
Test name
Test status
Simulation time 183999522 ps
CPU time 4.27 seconds
Started Jul 20 07:17:50 PM PDT 24
Finished Jul 20 07:18:04 PM PDT 24
Peak memory 210704 kb
Host smart-2605ed35-13d8-4f3e-a124-9ce718d7d61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908296903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.2908296903
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.2776999922
Short name T696
Test name
Test status
Simulation time 20455731 ps
CPU time 1 seconds
Started Jul 20 07:15:41 PM PDT 24
Finished Jul 20 07:15:45 PM PDT 24
Peak memory 205916 kb
Host smart-55ec3dab-b98b-4e3b-89b5-60522aff8487
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776999922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.2776999922
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.1118580172
Short name T869
Test name
Test status
Simulation time 58928504 ps
CPU time 2.98 seconds
Started Jul 20 07:15:35 PM PDT 24
Finished Jul 20 07:15:39 PM PDT 24
Peak memory 213980 kb
Host smart-532a12b9-c8e4-4373-a255-b0b28d65172c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118580172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.1118580172
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.443921005
Short name T438
Test name
Test status
Simulation time 225443837 ps
CPU time 3.08 seconds
Started Jul 20 07:15:31 PM PDT 24
Finished Jul 20 07:15:35 PM PDT 24
Peak memory 214000 kb
Host smart-d4148828-cb5a-418e-8ac3-48dd68761bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443921005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.443921005
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.3259659941
Short name T251
Test name
Test status
Simulation time 80076194 ps
CPU time 3.84 seconds
Started Jul 20 07:15:34 PM PDT 24
Finished Jul 20 07:15:39 PM PDT 24
Peak memory 209024 kb
Host smart-37c0f564-ee0b-40bd-851f-ad25d4d69834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259659941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3259659941
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sideload.2534417582
Short name T858
Test name
Test status
Simulation time 7483679930 ps
CPU time 28.57 seconds
Started Jul 20 07:15:34 PM PDT 24
Finished Jul 20 07:16:04 PM PDT 24
Peak memory 209024 kb
Host smart-c154ffe1-d9a2-478a-9499-3e7d41ebc676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534417582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.2534417582
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.719920404
Short name T661
Test name
Test status
Simulation time 118489648 ps
CPU time 3.01 seconds
Started Jul 20 07:15:33 PM PDT 24
Finished Jul 20 07:15:37 PM PDT 24
Peak memory 206672 kb
Host smart-d1b2fdb7-7b6b-47d5-8ec1-596001aa15c2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719920404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.719920404
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.3317511830
Short name T824
Test name
Test status
Simulation time 142585921 ps
CPU time 4.68 seconds
Started Jul 20 07:15:36 PM PDT 24
Finished Jul 20 07:15:41 PM PDT 24
Peak memory 206728 kb
Host smart-cbdd63d0-dc06-4fa7-ab31-5c73486c4dc8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317511830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.3317511830
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.1528589424
Short name T513
Test name
Test status
Simulation time 5748204754 ps
CPU time 41.52 seconds
Started Jul 20 07:15:33 PM PDT 24
Finished Jul 20 07:16:16 PM PDT 24
Peak memory 209020 kb
Host smart-b9eaaf14-ceaf-4314-b7e7-d57e7ce17b48
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528589424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.1528589424
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.1792540265
Short name T488
Test name
Test status
Simulation time 51702198 ps
CPU time 2.8 seconds
Started Jul 20 07:15:50 PM PDT 24
Finished Jul 20 07:15:54 PM PDT 24
Peak memory 207280 kb
Host smart-60833abf-5fdf-4680-82b9-196d1316668e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792540265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.1792540265
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.2903461028
Short name T545
Test name
Test status
Simulation time 419295237 ps
CPU time 4.52 seconds
Started Jul 20 07:15:33 PM PDT 24
Finished Jul 20 07:15:38 PM PDT 24
Peak memory 208048 kb
Host smart-3f26f345-8972-4a64-8dbd-e8922bad8f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903461028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.2903461028
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.2010321956
Short name T429
Test name
Test status
Simulation time 1909494116 ps
CPU time 15.15 seconds
Started Jul 20 07:15:41 PM PDT 24
Finished Jul 20 07:15:57 PM PDT 24
Peak memory 214096 kb
Host smart-99a198ea-661b-47e6-b668-bd566a307314
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010321956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.2010321956
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.3903042274
Short name T167
Test name
Test status
Simulation time 246039108 ps
CPU time 9.32 seconds
Started Jul 20 07:15:40 PM PDT 24
Finished Jul 20 07:15:51 PM PDT 24
Peak memory 222288 kb
Host smart-ce1e320a-92f4-4a4b-9e58-6a8407da690f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903042274 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.3903042274
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.1871663951
Short name T686
Test name
Test status
Simulation time 805874875 ps
CPU time 22.04 seconds
Started Jul 20 07:15:33 PM PDT 24
Finished Jul 20 07:15:56 PM PDT 24
Peak memory 208928 kb
Host smart-ae4cf5f7-3dde-4781-90b1-27076d328f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871663951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.1871663951
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.1427721571
Short name T117
Test name
Test status
Simulation time 125881976 ps
CPU time 1.82 seconds
Started Jul 20 07:15:41 PM PDT 24
Finished Jul 20 07:15:44 PM PDT 24
Peak memory 209404 kb
Host smart-145eada6-4865-4770-9fad-97fd04b6e58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427721571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.1427721571
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.3164205448
Short name T773
Test name
Test status
Simulation time 45614546 ps
CPU time 0.9 seconds
Started Jul 20 07:17:50 PM PDT 24
Finished Jul 20 07:18:00 PM PDT 24
Peak memory 205836 kb
Host smart-ce506b4b-a07a-4d31-8c6e-309ae90a9abc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164205448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.3164205448
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.374380329
Short name T669
Test name
Test status
Simulation time 386269959 ps
CPU time 2.81 seconds
Started Jul 20 07:17:48 PM PDT 24
Finished Jul 20 07:18:00 PM PDT 24
Peak memory 207196 kb
Host smart-7ceccff1-85af-4f48-8d7e-da3b0c2d32cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374380329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.374380329
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.994305208
Short name T801
Test name
Test status
Simulation time 73741067 ps
CPU time 3.76 seconds
Started Jul 20 07:17:50 PM PDT 24
Finished Jul 20 07:18:03 PM PDT 24
Peak memory 214132 kb
Host smart-deabde04-3330-4685-8df5-338fce08ff23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994305208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.994305208
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2903045617
Short name T735
Test name
Test status
Simulation time 454485034 ps
CPU time 3.93 seconds
Started Jul 20 07:17:49 PM PDT 24
Finished Jul 20 07:18:02 PM PDT 24
Peak memory 222120 kb
Host smart-36d95007-2b5a-4368-8c02-a614b1fce21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903045617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2903045617
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.822957132
Short name T551
Test name
Test status
Simulation time 133967347 ps
CPU time 2 seconds
Started Jul 20 07:17:51 PM PDT 24
Finished Jul 20 07:18:02 PM PDT 24
Peak memory 214616 kb
Host smart-cbe70143-b263-44d6-ab10-f0a5d7fd316c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822957132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.822957132
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.1116799301
Short name T285
Test name
Test status
Simulation time 28525836 ps
CPU time 2.31 seconds
Started Jul 20 07:17:51 PM PDT 24
Finished Jul 20 07:18:03 PM PDT 24
Peak memory 208148 kb
Host smart-d3af8654-3283-4113-b842-8f3e51f62f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116799301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1116799301
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.3805631564
Short name T871
Test name
Test status
Simulation time 70699485 ps
CPU time 2.16 seconds
Started Jul 20 07:17:50 PM PDT 24
Finished Jul 20 07:18:02 PM PDT 24
Peak memory 206628 kb
Host smart-6cf72d65-17f6-433e-8a05-20c437e5bd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805631564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.3805631564
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.3974797484
Short name T518
Test name
Test status
Simulation time 215256157 ps
CPU time 5.93 seconds
Started Jul 20 07:17:49 PM PDT 24
Finished Jul 20 07:18:04 PM PDT 24
Peak memory 208580 kb
Host smart-9dea3e6e-064f-4e9b-80f3-e30d343883f6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974797484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.3974797484
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.3757818735
Short name T287
Test name
Test status
Simulation time 65262206 ps
CPU time 2.44 seconds
Started Jul 20 07:17:48 PM PDT 24
Finished Jul 20 07:18:00 PM PDT 24
Peak memory 206912 kb
Host smart-ad874bdc-0de1-4c6b-b44a-b89c22f60e4f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757818735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.3757818735
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.3839330579
Short name T726
Test name
Test status
Simulation time 30985482 ps
CPU time 2.35 seconds
Started Jul 20 07:17:49 PM PDT 24
Finished Jul 20 07:18:01 PM PDT 24
Peak memory 206676 kb
Host smart-b77d7649-9e2f-41bf-8496-0d2e5ddd31a7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839330579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.3839330579
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.1495125537
Short name T679
Test name
Test status
Simulation time 69760909 ps
CPU time 1.8 seconds
Started Jul 20 07:17:50 PM PDT 24
Finished Jul 20 07:18:01 PM PDT 24
Peak memory 207640 kb
Host smart-88c37bce-8d90-4c59-9bc6-d649eb1c6209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495125537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.1495125537
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.3580143241
Short name T691
Test name
Test status
Simulation time 165709211 ps
CPU time 2.55 seconds
Started Jul 20 07:17:49 PM PDT 24
Finished Jul 20 07:18:01 PM PDT 24
Peak memory 206592 kb
Host smart-dad34ef9-9248-4ae7-ae30-2316d7ad5831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580143241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.3580143241
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.962610691
Short name T881
Test name
Test status
Simulation time 36755764308 ps
CPU time 192.34 seconds
Started Jul 20 07:17:49 PM PDT 24
Finished Jul 20 07:21:11 PM PDT 24
Peak memory 222036 kb
Host smart-fce38b4e-3a21-4f40-a7ff-5509d5f43bb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962610691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.962610691
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.2850088083
Short name T713
Test name
Test status
Simulation time 6751045615 ps
CPU time 16.77 seconds
Started Jul 20 07:17:48 PM PDT 24
Finished Jul 20 07:18:15 PM PDT 24
Peak memory 208572 kb
Host smart-855855e3-720e-4c6d-a173-4ed9cd259c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850088083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.2850088083
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.283872074
Short name T597
Test name
Test status
Simulation time 163651955 ps
CPU time 3.38 seconds
Started Jul 20 07:17:50 PM PDT 24
Finished Jul 20 07:18:03 PM PDT 24
Peak memory 210076 kb
Host smart-61438a64-711f-4299-95b2-06d82a15caf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283872074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.283872074
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.4113954751
Short name T382
Test name
Test status
Simulation time 222251281 ps
CPU time 4.4 seconds
Started Jul 20 07:18:05 PM PDT 24
Finished Jul 20 07:18:25 PM PDT 24
Peak memory 215164 kb
Host smart-cae9353d-b24b-497e-9297-05fe1fa4f002
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4113954751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.4113954751
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.2719087406
Short name T20
Test name
Test status
Simulation time 64656835 ps
CPU time 1.99 seconds
Started Jul 20 07:18:05 PM PDT 24
Finished Jul 20 07:18:23 PM PDT 24
Peak memory 218172 kb
Host smart-cd36315a-f134-4c09-aa8e-4dfd3eee5310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719087406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.2719087406
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.2465568513
Short name T622
Test name
Test status
Simulation time 244502346 ps
CPU time 2.69 seconds
Started Jul 20 07:17:57 PM PDT 24
Finished Jul 20 07:18:09 PM PDT 24
Peak memory 210312 kb
Host smart-9e4c66e7-4bb9-4a67-ba72-6e94dfa28656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465568513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.2465568513
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.1794460942
Short name T86
Test name
Test status
Simulation time 525709095 ps
CPU time 5.93 seconds
Started Jul 20 07:18:03 PM PDT 24
Finished Jul 20 07:18:23 PM PDT 24
Peak memory 222300 kb
Host smart-19117950-c856-4139-9cea-795c713d31e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794460942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.1794460942
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.565069573
Short name T420
Test name
Test status
Simulation time 90661889 ps
CPU time 4.11 seconds
Started Jul 20 07:18:00 PM PDT 24
Finished Jul 20 07:18:15 PM PDT 24
Peak memory 214004 kb
Host smart-3c84c026-d160-48ed-bb13-4519454ed076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565069573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.565069573
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.2123285240
Short name T387
Test name
Test status
Simulation time 93438240 ps
CPU time 4.62 seconds
Started Jul 20 07:18:00 PM PDT 24
Finished Jul 20 07:18:15 PM PDT 24
Peak memory 220248 kb
Host smart-144970a9-c66f-4571-b24a-84c5ec4ce5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123285240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.2123285240
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.1012754629
Short name T319
Test name
Test status
Simulation time 271775144 ps
CPU time 3.71 seconds
Started Jul 20 07:18:00 PM PDT 24
Finished Jul 20 07:18:14 PM PDT 24
Peak memory 218288 kb
Host smart-efd154a5-ebbd-42e1-ae38-271ed0965d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012754629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.1012754629
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.2012840036
Short name T861
Test name
Test status
Simulation time 53700323 ps
CPU time 2.8 seconds
Started Jul 20 07:17:59 PM PDT 24
Finished Jul 20 07:18:11 PM PDT 24
Peak memory 208200 kb
Host smart-db29f304-5034-4e39-bf9d-1d939cd3a025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012840036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.2012840036
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.2372350568
Short name T888
Test name
Test status
Simulation time 72160585 ps
CPU time 2.33 seconds
Started Jul 20 07:18:03 PM PDT 24
Finished Jul 20 07:18:19 PM PDT 24
Peak memory 206760 kb
Host smart-bf5e219b-6ea5-4620-b184-1d384e3957a3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372350568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.2372350568
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.2688910135
Short name T675
Test name
Test status
Simulation time 126345234 ps
CPU time 3.24 seconds
Started Jul 20 07:18:00 PM PDT 24
Finished Jul 20 07:18:14 PM PDT 24
Peak memory 208576 kb
Host smart-baf856f6-b095-4bac-9cc9-f124a1f07e35
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688910135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2688910135
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.1850281106
Short name T849
Test name
Test status
Simulation time 358185345 ps
CPU time 9.81 seconds
Started Jul 20 07:18:02 PM PDT 24
Finished Jul 20 07:18:26 PM PDT 24
Peak memory 207848 kb
Host smart-38d04e3e-2e76-4756-a50a-efab24d53e64
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850281106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1850281106
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.2444556352
Short name T688
Test name
Test status
Simulation time 120523022 ps
CPU time 2.38 seconds
Started Jul 20 07:17:59 PM PDT 24
Finished Jul 20 07:18:11 PM PDT 24
Peak memory 207388 kb
Host smart-64c071da-645e-443f-b7c1-3846b8a5e6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444556352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.2444556352
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.3971402322
Short name T532
Test name
Test status
Simulation time 548115399 ps
CPU time 3.39 seconds
Started Jul 20 07:17:58 PM PDT 24
Finished Jul 20 07:18:11 PM PDT 24
Peak memory 206596 kb
Host smart-07cad01b-dbaf-4f01-8849-55e621e6aeaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971402322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3971402322
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.89289020
Short name T653
Test name
Test status
Simulation time 11286935032 ps
CPU time 322.69 seconds
Started Jul 20 07:18:01 PM PDT 24
Finished Jul 20 07:23:35 PM PDT 24
Peak memory 221156 kb
Host smart-24cd1f07-6c2f-4326-8cb8-59cbe65b1bc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89289020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.89289020
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.867019592
Short name T705
Test name
Test status
Simulation time 516218871 ps
CPU time 22.38 seconds
Started Jul 20 07:17:57 PM PDT 24
Finished Jul 20 07:18:28 PM PDT 24
Peak memory 222420 kb
Host smart-db93a731-ec34-4c50-ab69-16a47c46a42e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867019592 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.867019592
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.200678592
Short name T772
Test name
Test status
Simulation time 737981859 ps
CPU time 6.3 seconds
Started Jul 20 07:18:00 PM PDT 24
Finished Jul 20 07:18:18 PM PDT 24
Peak memory 214096 kb
Host smart-7b0c9524-e086-46a1-ba95-22d4fcadcc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200678592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.200678592
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.3693627441
Short name T561
Test name
Test status
Simulation time 1030943868 ps
CPU time 4.99 seconds
Started Jul 20 07:17:59 PM PDT 24
Finished Jul 20 07:18:15 PM PDT 24
Peak memory 210836 kb
Host smart-cb4308cf-65e2-4e22-8918-9e60f974d788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693627441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.3693627441
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.141720044
Short name T593
Test name
Test status
Simulation time 18479678 ps
CPU time 0.83 seconds
Started Jul 20 07:18:08 PM PDT 24
Finished Jul 20 07:18:26 PM PDT 24
Peak memory 205444 kb
Host smart-026830c8-ce48-4351-9c2e-f953c67dad04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141720044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.141720044
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.2642855790
Short name T397
Test name
Test status
Simulation time 4109293383 ps
CPU time 53.43 seconds
Started Jul 20 07:18:07 PM PDT 24
Finished Jul 20 07:19:16 PM PDT 24
Peak memory 214204 kb
Host smart-f6b73c84-640f-4688-b893-c853df52ffd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2642855790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.2642855790
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.1524513074
Short name T37
Test name
Test status
Simulation time 201712442 ps
CPU time 3.63 seconds
Started Jul 20 07:18:06 PM PDT 24
Finished Jul 20 07:18:26 PM PDT 24
Peak memory 214100 kb
Host smart-fadff203-5b3b-4a8a-ba45-3385aa107cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524513074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.1524513074
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.3105020098
Short name T699
Test name
Test status
Simulation time 30560152 ps
CPU time 1.75 seconds
Started Jul 20 07:18:08 PM PDT 24
Finished Jul 20 07:18:28 PM PDT 24
Peak memory 208732 kb
Host smart-72ac5d09-d584-4185-baac-72d03a17b95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105020098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.3105020098
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.3922337526
Short name T236
Test name
Test status
Simulation time 148628542 ps
CPU time 5.73 seconds
Started Jul 20 07:18:07 PM PDT 24
Finished Jul 20 07:18:29 PM PDT 24
Peak memory 208924 kb
Host smart-78005a9f-9112-462e-b9d5-9f888f053cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922337526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.3922337526
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.1555950438
Short name T742
Test name
Test status
Simulation time 234809896 ps
CPU time 7.01 seconds
Started Jul 20 07:18:05 PM PDT 24
Finished Jul 20 07:18:28 PM PDT 24
Peak memory 222124 kb
Host smart-9d93a6cb-7180-4799-85da-6c02c5843a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555950438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.1555950438
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.2115229249
Short name T201
Test name
Test status
Simulation time 119756329 ps
CPU time 4.44 seconds
Started Jul 20 07:18:07 PM PDT 24
Finished Jul 20 07:18:29 PM PDT 24
Peak memory 219804 kb
Host smart-972b3f5d-b7f8-44bc-a1dd-eabd27400c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115229249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.2115229249
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.3922321974
Short name T364
Test name
Test status
Simulation time 345480755 ps
CPU time 4.42 seconds
Started Jul 20 07:17:58 PM PDT 24
Finished Jul 20 07:18:12 PM PDT 24
Peak memory 207308 kb
Host smart-7f0d5d80-d105-4ce7-a42c-a559175edfb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922321974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.3922321974
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.1314016465
Short name T276
Test name
Test status
Simulation time 404377987 ps
CPU time 7.08 seconds
Started Jul 20 07:17:59 PM PDT 24
Finished Jul 20 07:18:17 PM PDT 24
Peak memory 208340 kb
Host smart-127945b6-b4ca-4c2c-9253-4ea360bb6caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314016465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1314016465
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.1652097130
Short name T542
Test name
Test status
Simulation time 22906500 ps
CPU time 2.03 seconds
Started Jul 20 07:17:58 PM PDT 24
Finished Jul 20 07:18:09 PM PDT 24
Peak memory 208376 kb
Host smart-4545171c-a23b-4546-a656-2ba01b906733
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652097130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1652097130
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.3747615438
Short name T499
Test name
Test status
Simulation time 124688842 ps
CPU time 3.13 seconds
Started Jul 20 07:17:57 PM PDT 24
Finished Jul 20 07:18:09 PM PDT 24
Peak memory 208600 kb
Host smart-dbc7a138-e144-4cad-837e-68c1453c38a8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747615438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.3747615438
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.3442835720
Short name T687
Test name
Test status
Simulation time 53512971 ps
CPU time 2.78 seconds
Started Jul 20 07:17:59 PM PDT 24
Finished Jul 20 07:18:11 PM PDT 24
Peak memory 206728 kb
Host smart-8caa1a42-04f2-458a-921c-9b12e770c201
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442835720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.3442835720
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_smoke.2959708199
Short name T405
Test name
Test status
Simulation time 61864240 ps
CPU time 2.68 seconds
Started Jul 20 07:17:57 PM PDT 24
Finished Jul 20 07:18:09 PM PDT 24
Peak memory 208244 kb
Host smart-64cc6cf4-8514-40da-ae08-27d9c3e8f512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959708199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.2959708199
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.3477188931
Short name T195
Test name
Test status
Simulation time 8085549903 ps
CPU time 55.95 seconds
Started Jul 20 07:18:07 PM PDT 24
Finished Jul 20 07:19:20 PM PDT 24
Peak memory 215584 kb
Host smart-aea12df6-9d72-4df2-8541-955ef881b618
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477188931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.3477188931
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1853961336
Short name T233
Test name
Test status
Simulation time 162067879 ps
CPU time 5.38 seconds
Started Jul 20 07:18:07 PM PDT 24
Finished Jul 20 07:18:30 PM PDT 24
Peak memory 209472 kb
Host smart-2f6de8df-fcc9-4205-b1b0-4c5f4587284f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853961336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1853961336
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.1704716631
Short name T355
Test name
Test status
Simulation time 96994517 ps
CPU time 2.19 seconds
Started Jul 20 07:18:06 PM PDT 24
Finished Jul 20 07:18:24 PM PDT 24
Peak memory 209376 kb
Host smart-c6f8eca4-e99c-4b6e-a6a0-5f0b409e31be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704716631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.1704716631
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.3595911414
Short name T408
Test name
Test status
Simulation time 16435593 ps
CPU time 0.78 seconds
Started Jul 20 07:18:06 PM PDT 24
Finished Jul 20 07:18:23 PM PDT 24
Peak memory 205992 kb
Host smart-3ab2710b-1c06-4236-9f5f-eed41364aa8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595911414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.3595911414
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.529149326
Short name T283
Test name
Test status
Simulation time 142600292 ps
CPU time 8.24 seconds
Started Jul 20 07:18:06 PM PDT 24
Finished Jul 20 07:18:30 PM PDT 24
Peak memory 222164 kb
Host smart-64f0eb59-41ad-452f-ad1a-e031d19fb932
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=529149326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.529149326
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.671134150
Short name T19
Test name
Test status
Simulation time 615842353 ps
CPU time 5.29 seconds
Started Jul 20 07:18:06 PM PDT 24
Finished Jul 20 07:18:27 PM PDT 24
Peak memory 214476 kb
Host smart-d0a60114-07e4-4abc-97d8-60b1ef7be16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671134150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.671134150
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.1493204341
Short name T914
Test name
Test status
Simulation time 217510058 ps
CPU time 2.82 seconds
Started Jul 20 07:18:07 PM PDT 24
Finished Jul 20 07:18:26 PM PDT 24
Peak memory 207524 kb
Host smart-db3de324-7bbb-4b33-918e-6e66ae667f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493204341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.1493204341
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.2977748535
Short name T779
Test name
Test status
Simulation time 574147228 ps
CPU time 6.88 seconds
Started Jul 20 07:18:07 PM PDT 24
Finished Jul 20 07:18:30 PM PDT 24
Peak memory 222100 kb
Host smart-cceebb0e-7575-40ad-80b8-a89fbddce602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977748535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.2977748535
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.4232406084
Short name T199
Test name
Test status
Simulation time 181897732 ps
CPU time 3.7 seconds
Started Jul 20 07:18:08 PM PDT 24
Finished Jul 20 07:18:29 PM PDT 24
Peak memory 219080 kb
Host smart-8e571229-c4de-4275-b182-300362faf297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232406084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.4232406084
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.200411412
Short name T455
Test name
Test status
Simulation time 1511402646 ps
CPU time 5.14 seconds
Started Jul 20 07:18:07 PM PDT 24
Finished Jul 20 07:18:28 PM PDT 24
Peak memory 209788 kb
Host smart-8759253c-6abd-4b03-a5c4-4e16c99609f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200411412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.200411412
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.744273948
Short name T338
Test name
Test status
Simulation time 98799522 ps
CPU time 2.78 seconds
Started Jul 20 07:18:07 PM PDT 24
Finished Jul 20 07:18:26 PM PDT 24
Peak memory 206452 kb
Host smart-cd03e257-1dfa-4daf-b311-02f9f12fa2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744273948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.744273948
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.4269835553
Short name T407
Test name
Test status
Simulation time 119705973 ps
CPU time 3.02 seconds
Started Jul 20 07:18:07 PM PDT 24
Finished Jul 20 07:18:27 PM PDT 24
Peak memory 206744 kb
Host smart-10208f78-8ed6-4a4f-819f-7875ffeedb07
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269835553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.4269835553
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.1122156615
Short name T838
Test name
Test status
Simulation time 3219031734 ps
CPU time 59.21 seconds
Started Jul 20 07:18:10 PM PDT 24
Finished Jul 20 07:19:27 PM PDT 24
Peak memory 208200 kb
Host smart-286dd815-50a1-4e12-8b5d-01f511706740
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122156615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.1122156615
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.1073887669
Short name T529
Test name
Test status
Simulation time 721306115 ps
CPU time 5.52 seconds
Started Jul 20 07:18:06 PM PDT 24
Finished Jul 20 07:18:27 PM PDT 24
Peak memory 208136 kb
Host smart-980c902d-6010-4254-8c06-16a8d5966f46
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073887669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.1073887669
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.2841507216
Short name T426
Test name
Test status
Simulation time 29760070 ps
CPU time 2.25 seconds
Started Jul 20 07:18:05 PM PDT 24
Finished Jul 20 07:18:23 PM PDT 24
Peak memory 208004 kb
Host smart-fa6bafb2-0243-4216-8666-fec7b2fe1e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841507216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2841507216
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.3100881444
Short name T874
Test name
Test status
Simulation time 232151871 ps
CPU time 5.11 seconds
Started Jul 20 07:18:05 PM PDT 24
Finished Jul 20 07:18:26 PM PDT 24
Peak memory 206400 kb
Host smart-10943f67-783c-43ab-89c2-3d9c5501e5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100881444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.3100881444
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.1194790516
Short name T706
Test name
Test status
Simulation time 123062549 ps
CPU time 1.75 seconds
Started Jul 20 07:18:09 PM PDT 24
Finished Jul 20 07:18:28 PM PDT 24
Peak memory 208216 kb
Host smart-66f6fbf9-96fb-4e36-922d-abb73202e0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194790516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.1194790516
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.341973272
Short name T505
Test name
Test status
Simulation time 50198646 ps
CPU time 0.79 seconds
Started Jul 20 07:18:15 PM PDT 24
Finished Jul 20 07:18:36 PM PDT 24
Peak memory 205840 kb
Host smart-1ee24d7f-d5e5-4dc4-839f-7d47fc6be8ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341973272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.341973272
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.6626222
Short name T578
Test name
Test status
Simulation time 66862374 ps
CPU time 2.57 seconds
Started Jul 20 07:18:16 PM PDT 24
Finished Jul 20 07:18:40 PM PDT 24
Peak memory 209144 kb
Host smart-3cdd32e9-9299-4a89-8b55-23aa9a4b9fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6626222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.6626222
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.774126210
Short name T558
Test name
Test status
Simulation time 62898370 ps
CPU time 2.23 seconds
Started Jul 20 07:18:15 PM PDT 24
Finished Jul 20 07:18:38 PM PDT 24
Peak memory 207312 kb
Host smart-839ab2bb-72e5-484c-bd62-724596669ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774126210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.774126210
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.157454855
Short name T210
Test name
Test status
Simulation time 1086439737 ps
CPU time 8.15 seconds
Started Jul 20 07:18:15 PM PDT 24
Finished Jul 20 07:18:43 PM PDT 24
Peak memory 214136 kb
Host smart-96477f9e-c14c-4633-b864-b6a0b634c5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157454855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.157454855
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.1664087636
Short name T606
Test name
Test status
Simulation time 249593269 ps
CPU time 2.59 seconds
Started Jul 20 07:18:14 PM PDT 24
Finished Jul 20 07:18:37 PM PDT 24
Peak memory 214092 kb
Host smart-bd07d9ed-372e-4175-8f48-84e71f8ac82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664087636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.1664087636
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.2458478978
Short name T384
Test name
Test status
Simulation time 59666320 ps
CPU time 3.84 seconds
Started Jul 20 07:18:13 PM PDT 24
Finished Jul 20 07:18:37 PM PDT 24
Peak memory 214072 kb
Host smart-33224752-d5f0-41b1-8ace-8ff96abfac3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458478978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.2458478978
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.1462387571
Short name T856
Test name
Test status
Simulation time 116597735 ps
CPU time 5.82 seconds
Started Jul 20 07:18:13 PM PDT 24
Finished Jul 20 07:18:40 PM PDT 24
Peak memory 207372 kb
Host smart-6a779326-c329-425d-b7bd-93b7872c5729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462387571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.1462387571
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.3316493870
Short name T685
Test name
Test status
Simulation time 5286674857 ps
CPU time 29.33 seconds
Started Jul 20 07:18:14 PM PDT 24
Finished Jul 20 07:19:04 PM PDT 24
Peak memory 207860 kb
Host smart-64f5bd8f-7c3d-4751-b5cb-5ae16eef530f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316493870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.3316493870
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.1095868577
Short name T778
Test name
Test status
Simulation time 144208841 ps
CPU time 4.22 seconds
Started Jul 20 07:18:14 PM PDT 24
Finished Jul 20 07:18:39 PM PDT 24
Peak memory 208600 kb
Host smart-cd685cfe-028e-4b26-9cc0-b0505de85076
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095868577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.1095868577
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.2180305043
Short name T238
Test name
Test status
Simulation time 815648277 ps
CPU time 4.14 seconds
Started Jul 20 07:18:17 PM PDT 24
Finished Jul 20 07:18:43 PM PDT 24
Peak memory 208780 kb
Host smart-16699301-da7d-4aae-94b4-4e9dab710e16
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180305043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.2180305043
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.4644108
Short name T272
Test name
Test status
Simulation time 229683988 ps
CPU time 2.99 seconds
Started Jul 20 07:18:17 PM PDT 24
Finished Jul 20 07:18:41 PM PDT 24
Peak memory 208772 kb
Host smart-79eeb454-91e2-40c9-bb31-558e08773980
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4644108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.4644108
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.2657578712
Short name T310
Test name
Test status
Simulation time 976108724 ps
CPU time 5.24 seconds
Started Jul 20 07:18:15 PM PDT 24
Finished Jul 20 07:18:40 PM PDT 24
Peak memory 218224 kb
Host smart-fe685ba3-6ca1-4ba3-8df5-c8da3d58de8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657578712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.2657578712
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.887237802
Short name T588
Test name
Test status
Simulation time 93443030 ps
CPU time 1.98 seconds
Started Jul 20 07:18:08 PM PDT 24
Finished Jul 20 07:18:27 PM PDT 24
Peak memory 208232 kb
Host smart-18371bf3-db1f-49de-b235-e44bd956eb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887237802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.887237802
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.2440207586
Short name T517
Test name
Test status
Simulation time 176530203 ps
CPU time 5.3 seconds
Started Jul 20 07:18:14 PM PDT 24
Finished Jul 20 07:18:40 PM PDT 24
Peak memory 214076 kb
Host smart-82b3c36e-70b0-4a89-8807-fc73b98e477f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440207586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.2440207586
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.1958934609
Short name T791
Test name
Test status
Simulation time 4082985426 ps
CPU time 14.1 seconds
Started Jul 20 07:18:19 PM PDT 24
Finished Jul 20 07:18:55 PM PDT 24
Peak memory 222492 kb
Host smart-78fcb277-6aa4-4df8-aa72-5b450987d80d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958934609 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.1958934609
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.526181620
Short name T523
Test name
Test status
Simulation time 205936520 ps
CPU time 7.04 seconds
Started Jul 20 07:18:17 PM PDT 24
Finished Jul 20 07:18:46 PM PDT 24
Peak memory 214148 kb
Host smart-12710b88-5118-4236-904b-a04e9b2ce4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526181620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.526181620
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.2940670637
Short name T352
Test name
Test status
Simulation time 159148514 ps
CPU time 2.84 seconds
Started Jul 20 07:18:14 PM PDT 24
Finished Jul 20 07:18:37 PM PDT 24
Peak memory 210252 kb
Host smart-053a9e9c-fca1-423e-8bb4-45a7ce643609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940670637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.2940670637
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.2502609341
Short name T872
Test name
Test status
Simulation time 23870354 ps
CPU time 0.79 seconds
Started Jul 20 07:18:23 PM PDT 24
Finished Jul 20 07:18:47 PM PDT 24
Peak memory 205856 kb
Host smart-cd922e11-b43c-43b8-9eed-15b98b5c7258
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502609341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.2502609341
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.3857332625
Short name T394
Test name
Test status
Simulation time 2975469422 ps
CPU time 41.71 seconds
Started Jul 20 07:18:24 PM PDT 24
Finished Jul 20 07:19:30 PM PDT 24
Peak memory 214380 kb
Host smart-54211aa5-6738-45fd-915a-c9bd522fed62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3857332625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.3857332625
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.3054019818
Short name T29
Test name
Test status
Simulation time 284766714 ps
CPU time 2.79 seconds
Started Jul 20 07:18:21 PM PDT 24
Finished Jul 20 07:18:46 PM PDT 24
Peak memory 209212 kb
Host smart-cf16a03f-b095-401a-931a-dd963cf107a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054019818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.3054019818
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.3067000687
Short name T582
Test name
Test status
Simulation time 195121718 ps
CPU time 2.67 seconds
Started Jul 20 07:18:21 PM PDT 24
Finished Jul 20 07:18:45 PM PDT 24
Peak memory 208752 kb
Host smart-44c3b5d7-73ed-428b-822b-e2490b566a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067000687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3067000687
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.1743340052
Short name T213
Test name
Test status
Simulation time 3288237141 ps
CPU time 6.24 seconds
Started Jul 20 07:18:22 PM PDT 24
Finished Jul 20 07:18:50 PM PDT 24
Peak memory 208896 kb
Host smart-342663a9-909d-407a-a067-4b362edad2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743340052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.1743340052
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.2439554511
Short name T547
Test name
Test status
Simulation time 152617472 ps
CPU time 1.64 seconds
Started Jul 20 07:18:23 PM PDT 24
Finished Jul 20 07:18:49 PM PDT 24
Peak memory 214076 kb
Host smart-db6ee3d3-3334-42a4-be36-ec1d923fe890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439554511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.2439554511
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.1159981977
Short name T58
Test name
Test status
Simulation time 180168789 ps
CPU time 3.61 seconds
Started Jul 20 07:18:23 PM PDT 24
Finished Jul 20 07:18:49 PM PDT 24
Peak memory 220196 kb
Host smart-3701c5c4-b01a-4a1e-b9e7-64e68130a6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159981977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.1159981977
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.1239652695
Short name T482
Test name
Test status
Simulation time 1418515076 ps
CPU time 6.8 seconds
Started Jul 20 07:18:24 PM PDT 24
Finished Jul 20 07:18:55 PM PDT 24
Peak memory 207668 kb
Host smart-3fc5a9e2-2140-4643-a9ac-8ec13d0b0696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239652695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.1239652695
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.3931592977
Short name T365
Test name
Test status
Simulation time 329502955 ps
CPU time 3.07 seconds
Started Jul 20 07:18:16 PM PDT 24
Finished Jul 20 07:18:41 PM PDT 24
Peak memory 206608 kb
Host smart-742d8209-5bab-4b23-8b78-cab48fbdc7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931592977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.3931592977
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.2718747026
Short name T450
Test name
Test status
Simulation time 62252888 ps
CPU time 3.07 seconds
Started Jul 20 07:18:19 PM PDT 24
Finished Jul 20 07:18:44 PM PDT 24
Peak memory 208288 kb
Host smart-4d8d292b-a6f7-49d6-a81f-8c90fbb434fa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718747026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.2718747026
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2640245288
Short name T615
Test name
Test status
Simulation time 467120061 ps
CPU time 13.89 seconds
Started Jul 20 07:18:16 PM PDT 24
Finished Jul 20 07:18:51 PM PDT 24
Peak memory 208764 kb
Host smart-8095fc00-d2f6-434a-bfca-918ed8256c67
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640245288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2640245288
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1254152328
Short name T427
Test name
Test status
Simulation time 23726040 ps
CPU time 1.99 seconds
Started Jul 20 07:18:14 PM PDT 24
Finished Jul 20 07:18:36 PM PDT 24
Peak memory 207188 kb
Host smart-00461f71-9749-4a68-841b-5427db8e8c08
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254152328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1254152328
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.3385241520
Short name T442
Test name
Test status
Simulation time 455454660 ps
CPU time 2.59 seconds
Started Jul 20 07:18:22 PM PDT 24
Finished Jul 20 07:18:47 PM PDT 24
Peak memory 206768 kb
Host smart-aadeea87-3cb3-4e48-ad66-2171b4bb50cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385241520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.3385241520
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.1248059583
Short name T441
Test name
Test status
Simulation time 129056003 ps
CPU time 2.96 seconds
Started Jul 20 07:18:19 PM PDT 24
Finished Jul 20 07:18:44 PM PDT 24
Peak memory 207656 kb
Host smart-7222349c-f94b-4e60-b3d5-766c0d144cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248059583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.1248059583
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.3696630342
Short name T670
Test name
Test status
Simulation time 213044459 ps
CPU time 9.96 seconds
Started Jul 20 07:18:23 PM PDT 24
Finished Jul 20 07:18:56 PM PDT 24
Peak memory 216088 kb
Host smart-4eb04c0b-d693-403b-8bb9-7580b9c5b563
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696630342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.3696630342
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.343101299
Short name T110
Test name
Test status
Simulation time 204684714 ps
CPU time 7.23 seconds
Started Jul 20 07:18:22 PM PDT 24
Finished Jul 20 07:18:52 PM PDT 24
Peak memory 222300 kb
Host smart-2f289b9c-3c55-4d9d-9a7c-90cfabbe8c32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343101299 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.343101299
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.1366336717
Short name T840
Test name
Test status
Simulation time 110657961 ps
CPU time 4.71 seconds
Started Jul 20 07:18:22 PM PDT 24
Finished Jul 20 07:18:49 PM PDT 24
Peak memory 207144 kb
Host smart-ef142743-d6ba-4088-9f84-50870e19ce6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366336717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.1366336717
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.721306145
Short name T887
Test name
Test status
Simulation time 42525127 ps
CPU time 2.05 seconds
Started Jul 20 07:18:21 PM PDT 24
Finished Jul 20 07:18:45 PM PDT 24
Peak memory 209552 kb
Host smart-4754200d-0941-4fb8-952a-4d6cf9136a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721306145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.721306145
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.1915932693
Short name T641
Test name
Test status
Simulation time 42821477 ps
CPU time 0.84 seconds
Started Jul 20 07:18:38 PM PDT 24
Finished Jul 20 07:19:05 PM PDT 24
Peak memory 205852 kb
Host smart-7b011eaa-7a3c-48a1-a798-d24d2423d4e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915932693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1915932693
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.3919331624
Short name T242
Test name
Test status
Simulation time 149914091 ps
CPU time 2.05 seconds
Started Jul 20 07:18:23 PM PDT 24
Finished Jul 20 07:18:48 PM PDT 24
Peak memory 208504 kb
Host smart-b6c3b2be-3ce1-4522-8270-9c54afa07244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919331624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.3919331624
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.2494899131
Short name T572
Test name
Test status
Simulation time 30092700 ps
CPU time 2.51 seconds
Started Jul 20 07:18:34 PM PDT 24
Finished Jul 20 07:19:01 PM PDT 24
Peak memory 222140 kb
Host smart-ad8bb62b-040b-4c3c-ae3a-41832bc2f235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494899131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.2494899131
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.2599148334
Short name T873
Test name
Test status
Simulation time 126893259 ps
CPU time 4.37 seconds
Started Jul 20 07:18:31 PM PDT 24
Finished Jul 20 07:19:00 PM PDT 24
Peak memory 222180 kb
Host smart-974cda92-f19b-4530-9f3b-8a1a5fe5d8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599148334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.2599148334
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.8224218
Short name T209
Test name
Test status
Simulation time 233567209 ps
CPU time 4.14 seconds
Started Jul 20 07:18:32 PM PDT 24
Finished Jul 20 07:19:01 PM PDT 24
Peak memory 210384 kb
Host smart-7c78ac18-c7c9-4116-b48d-70d924ba5874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8224218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.8224218
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.2801600820
Short name T645
Test name
Test status
Simulation time 258664594 ps
CPU time 5.4 seconds
Started Jul 20 07:18:23 PM PDT 24
Finished Jul 20 07:18:53 PM PDT 24
Peak memory 209516 kb
Host smart-9a20b38f-4625-4195-925b-b37f7340e4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801600820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.2801600820
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.270811382
Short name T424
Test name
Test status
Simulation time 74970397 ps
CPU time 3.43 seconds
Started Jul 20 07:18:23 PM PDT 24
Finished Jul 20 07:18:50 PM PDT 24
Peak memory 208212 kb
Host smart-bba0e7da-39f9-47ee-be99-f63af57319e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270811382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.270811382
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2293025083
Short name T492
Test name
Test status
Simulation time 244016236 ps
CPU time 2.62 seconds
Started Jul 20 07:18:24 PM PDT 24
Finished Jul 20 07:18:51 PM PDT 24
Peak memory 206720 kb
Host smart-d2076746-5e58-406b-8497-7700cc1d22b9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293025083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2293025083
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.3777252666
Short name T544
Test name
Test status
Simulation time 2116084988 ps
CPU time 15.42 seconds
Started Jul 20 07:18:21 PM PDT 24
Finished Jul 20 07:18:59 PM PDT 24
Peak memory 207760 kb
Host smart-d1738fde-2732-4a10-aeef-4016b75d7dcb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777252666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.3777252666
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.4098602166
Short name T323
Test name
Test status
Simulation time 499342185 ps
CPU time 5.51 seconds
Started Jul 20 07:18:22 PM PDT 24
Finished Jul 20 07:18:51 PM PDT 24
Peak memory 207908 kb
Host smart-4bf27628-412a-4761-8890-74c7d1145d77
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098602166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.4098602166
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.3438142855
Short name T883
Test name
Test status
Simulation time 921869172 ps
CPU time 4 seconds
Started Jul 20 07:18:33 PM PDT 24
Finished Jul 20 07:19:01 PM PDT 24
Peak memory 207744 kb
Host smart-34fb0451-99e2-40c3-a707-78417bbe9d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438142855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.3438142855
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.1644317545
Short name T515
Test name
Test status
Simulation time 285788536 ps
CPU time 2.41 seconds
Started Jul 20 07:18:22 PM PDT 24
Finished Jul 20 07:18:47 PM PDT 24
Peak memory 206460 kb
Host smart-86840fba-1cf2-4c42-8287-8e2c58a571b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644317545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.1644317545
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.1077388391
Short name T288
Test name
Test status
Simulation time 1604584699 ps
CPU time 22.45 seconds
Started Jul 20 07:18:33 PM PDT 24
Finished Jul 20 07:19:20 PM PDT 24
Peak memory 215108 kb
Host smart-3208b8b3-cb07-43c5-bef1-711e3cc620d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077388391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.1077388391
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.1844573096
Short name T594
Test name
Test status
Simulation time 998368395 ps
CPU time 27.31 seconds
Started Jul 20 07:18:38 PM PDT 24
Finished Jul 20 07:19:32 PM PDT 24
Peak memory 214092 kb
Host smart-dbc9f4dd-3a3d-48fb-97c1-55cdf56df95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844573096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.1844573096
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.259594926
Short name T181
Test name
Test status
Simulation time 249248623 ps
CPU time 3.46 seconds
Started Jul 20 07:18:32 PM PDT 24
Finished Jul 20 07:19:00 PM PDT 24
Peak memory 210168 kb
Host smart-1b6d4e2d-d631-4f49-be5c-4bef5d9e2baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259594926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.259594926
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.2632695360
Short name T682
Test name
Test status
Simulation time 27047662 ps
CPU time 1.04 seconds
Started Jul 20 07:18:41 PM PDT 24
Finished Jul 20 07:19:08 PM PDT 24
Peak memory 205936 kb
Host smart-ae8d42af-960e-42a5-ad50-89e3c35690cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632695360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.2632695360
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.4084539137
Short name T777
Test name
Test status
Simulation time 59012105 ps
CPU time 2.68 seconds
Started Jul 20 07:18:41 PM PDT 24
Finished Jul 20 07:19:11 PM PDT 24
Peak memory 214076 kb
Host smart-ad08b64b-4df1-4e47-b335-b745bd8ea34f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4084539137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.4084539137
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.1747404049
Short name T695
Test name
Test status
Simulation time 127701426 ps
CPU time 4.59 seconds
Started Jul 20 07:18:42 PM PDT 24
Finished Jul 20 07:19:14 PM PDT 24
Peak memory 209328 kb
Host smart-f208558b-8196-4f09-a8a9-480db68939ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747404049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.1747404049
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.3683334959
Short name T215
Test name
Test status
Simulation time 1169174066 ps
CPU time 5.64 seconds
Started Jul 20 07:18:42 PM PDT 24
Finished Jul 20 07:19:15 PM PDT 24
Peak memory 214152 kb
Host smart-8e411b7e-2fc0-4c82-b81d-155684291388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683334959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.3683334959
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.3090185598
Short name T639
Test name
Test status
Simulation time 145538678 ps
CPU time 6.17 seconds
Started Jul 20 07:18:40 PM PDT 24
Finished Jul 20 07:19:13 PM PDT 24
Peak memory 222108 kb
Host smart-1e4ad7f0-f22e-418d-bef2-a2af298c0f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090185598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.3090185598
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.2243900041
Short name T191
Test name
Test status
Simulation time 415439567 ps
CPU time 2.51 seconds
Started Jul 20 07:18:40 PM PDT 24
Finished Jul 20 07:19:10 PM PDT 24
Peak memory 219816 kb
Host smart-34f71e14-c3ce-4f28-8176-e2ae1e95bf59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243900041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.2243900041
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.1887775569
Short name T218
Test name
Test status
Simulation time 77340413 ps
CPU time 3.48 seconds
Started Jul 20 07:18:42 PM PDT 24
Finished Jul 20 07:19:13 PM PDT 24
Peak memory 208404 kb
Host smart-52840f6a-a7ed-4f42-94f2-7a9362b744cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887775569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.1887775569
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.1407392696
Short name T378
Test name
Test status
Simulation time 875500859 ps
CPU time 19.37 seconds
Started Jul 20 07:18:35 PM PDT 24
Finished Jul 20 07:19:21 PM PDT 24
Peak memory 207948 kb
Host smart-ce30817c-419a-451d-8021-a5061b67c0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407392696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.1407392696
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.2280781911
Short name T456
Test name
Test status
Simulation time 122886640 ps
CPU time 3.21 seconds
Started Jul 20 07:18:33 PM PDT 24
Finished Jul 20 07:19:01 PM PDT 24
Peak memory 207152 kb
Host smart-864c3fa5-28e9-4bb3-94f1-5ab4aed7f5fb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280781911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2280781911
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.3862330107
Short name T595
Test name
Test status
Simulation time 37980897 ps
CPU time 2.55 seconds
Started Jul 20 07:18:35 PM PDT 24
Finished Jul 20 07:19:03 PM PDT 24
Peak memory 208684 kb
Host smart-55e48817-f63f-41a8-b385-28dc28daa1db
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862330107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.3862330107
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.687631584
Short name T526
Test name
Test status
Simulation time 239053445 ps
CPU time 4.78 seconds
Started Jul 20 07:18:41 PM PDT 24
Finished Jul 20 07:19:12 PM PDT 24
Peak memory 218224 kb
Host smart-674f06b2-eb17-4b63-b527-c5e50417f44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687631584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.687631584
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.319101504
Short name T475
Test name
Test status
Simulation time 150293889 ps
CPU time 2.05 seconds
Started Jul 20 07:18:32 PM PDT 24
Finished Jul 20 07:18:59 PM PDT 24
Peak memory 206592 kb
Host smart-30fb5a30-b242-45da-a4f8-51a4b9e75357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319101504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.319101504
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.1031907161
Short name T794
Test name
Test status
Simulation time 596784872 ps
CPU time 21.72 seconds
Started Jul 20 07:18:42 PM PDT 24
Finished Jul 20 07:19:31 PM PDT 24
Peak memory 219120 kb
Host smart-24cc9b74-fc16-47b4-bceb-829144a2c1fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031907161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.1031907161
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.3465028004
Short name T834
Test name
Test status
Simulation time 388375730 ps
CPU time 4.46 seconds
Started Jul 20 07:18:41 PM PDT 24
Finished Jul 20 07:19:12 PM PDT 24
Peak memory 209136 kb
Host smart-bc39e384-cb7d-4a28-b005-9039f3b554e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465028004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.3465028004
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.2328500596
Short name T891
Test name
Test status
Simulation time 62960682 ps
CPU time 2.15 seconds
Started Jul 20 07:18:44 PM PDT 24
Finished Jul 20 07:19:13 PM PDT 24
Peak memory 210020 kb
Host smart-4c823175-ed78-4e3a-bc9a-0e6c702bca44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328500596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.2328500596
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.535341178
Short name T428
Test name
Test status
Simulation time 19943489 ps
CPU time 0.75 seconds
Started Jul 20 07:18:44 PM PDT 24
Finished Jul 20 07:19:12 PM PDT 24
Peak memory 205880 kb
Host smart-5deb88d2-ecec-47d1-a67c-dddee0338174
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535341178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.535341178
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.1524243617
Short name T576
Test name
Test status
Simulation time 327602332 ps
CPU time 2.62 seconds
Started Jul 20 07:18:45 PM PDT 24
Finished Jul 20 07:19:15 PM PDT 24
Peak memory 207436 kb
Host smart-6f7d56f4-a88d-4b84-bf28-87a19dc1f175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524243617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.1524243617
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.3656619063
Short name T916
Test name
Test status
Simulation time 1421190233 ps
CPU time 4.1 seconds
Started Jul 20 07:18:41 PM PDT 24
Finished Jul 20 07:19:12 PM PDT 24
Peak memory 214240 kb
Host smart-215f1969-c621-46d7-b897-275f6e08cee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656619063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.3656619063
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.1208230710
Short name T315
Test name
Test status
Simulation time 108407262 ps
CPU time 2.89 seconds
Started Jul 20 07:18:40 PM PDT 24
Finished Jul 20 07:19:10 PM PDT 24
Peak memory 214092 kb
Host smart-66deedc6-2cd4-4073-9070-fe4ecc2c8f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208230710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.1208230710
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_random.2116223118
Short name T689
Test name
Test status
Simulation time 556334264 ps
CPU time 4.94 seconds
Started Jul 20 07:18:41 PM PDT 24
Finished Jul 20 07:19:13 PM PDT 24
Peak memory 214132 kb
Host smart-e04b7eca-9176-4234-ad81-5e8d9247d645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116223118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.2116223118
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.1358858366
Short name T841
Test name
Test status
Simulation time 200595004 ps
CPU time 5.68 seconds
Started Jul 20 07:18:41 PM PDT 24
Finished Jul 20 07:19:13 PM PDT 24
Peak memory 207652 kb
Host smart-56f5e45f-f2cd-4ae6-9676-88b72e5181f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358858366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.1358858366
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.1221900067
Short name T329
Test name
Test status
Simulation time 875857811 ps
CPU time 6.67 seconds
Started Jul 20 07:18:40 PM PDT 24
Finished Jul 20 07:19:13 PM PDT 24
Peak memory 207784 kb
Host smart-dc4974c2-6fa9-482f-b50c-05102ae0683d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221900067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.1221900067
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.1802711451
Short name T890
Test name
Test status
Simulation time 170150333 ps
CPU time 4.24 seconds
Started Jul 20 07:18:45 PM PDT 24
Finished Jul 20 07:19:16 PM PDT 24
Peak memory 207548 kb
Host smart-5bf8bf8d-b0a7-41ea-b8e6-adbe45609ddc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802711451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.1802711451
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.3640523577
Short name T268
Test name
Test status
Simulation time 21993506 ps
CPU time 1.9 seconds
Started Jul 20 07:18:42 PM PDT 24
Finished Jul 20 07:19:11 PM PDT 24
Peak memory 208316 kb
Host smart-0ec29825-503a-4688-8d26-3c9f72cfc9bd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640523577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.3640523577
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_smoke.847984580
Short name T608
Test name
Test status
Simulation time 102161982 ps
CPU time 1.85 seconds
Started Jul 20 07:18:45 PM PDT 24
Finished Jul 20 07:19:14 PM PDT 24
Peak memory 208244 kb
Host smart-616c3aaf-00f0-49a3-b050-35935ae0dee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847984580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.847984580
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.2135668750
Short name T786
Test name
Test status
Simulation time 1309307518 ps
CPU time 36.66 seconds
Started Jul 20 07:18:42 PM PDT 24
Finished Jul 20 07:19:46 PM PDT 24
Peak memory 216252 kb
Host smart-711e3e0c-1419-4b1e-bbcf-4d9243780f7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135668750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.2135668750
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.1221421144
Short name T440
Test name
Test status
Simulation time 373361555 ps
CPU time 5.46 seconds
Started Jul 20 07:18:42 PM PDT 24
Finished Jul 20 07:19:15 PM PDT 24
Peak memory 207820 kb
Host smart-04f97b3b-0218-4800-bd09-ee9febe1f144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221421144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1221421144
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.1592332827
Short name T913
Test name
Test status
Simulation time 23761305 ps
CPU time 0.87 seconds
Started Jul 20 07:18:48 PM PDT 24
Finished Jul 20 07:19:17 PM PDT 24
Peak memory 205868 kb
Host smart-b92607b3-a3d3-4eea-89c5-524106b833e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592332827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1592332827
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.3137399648
Short name T308
Test name
Test status
Simulation time 756591075 ps
CPU time 10.35 seconds
Started Jul 20 07:18:50 PM PDT 24
Finished Jul 20 07:19:29 PM PDT 24
Peak memory 214120 kb
Host smart-e5bfe391-035b-47d0-ad82-7a88c3c27adf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3137399648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.3137399648
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.2832351581
Short name T489
Test name
Test status
Simulation time 644341435 ps
CPU time 15.91 seconds
Started Jul 20 07:18:49 PM PDT 24
Finished Jul 20 07:19:32 PM PDT 24
Peak memory 214064 kb
Host smart-13f732cc-7ce8-4560-a281-2cc759da71aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832351581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.2832351581
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.1518674306
Short name T795
Test name
Test status
Simulation time 55895190 ps
CPU time 2.37 seconds
Started Jul 20 07:18:51 PM PDT 24
Finished Jul 20 07:19:24 PM PDT 24
Peak memory 209536 kb
Host smart-26e18747-7844-48a1-a0c7-d0732a81845c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518674306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.1518674306
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.1531598553
Short name T743
Test name
Test status
Simulation time 428089198 ps
CPU time 5.38 seconds
Started Jul 20 07:18:49 PM PDT 24
Finished Jul 20 07:19:23 PM PDT 24
Peak memory 214064 kb
Host smart-fd87db5f-5ce2-4f3c-9fac-497ddf28e9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531598553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.1531598553
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.865075387
Short name T317
Test name
Test status
Simulation time 609644143 ps
CPU time 3.55 seconds
Started Jul 20 07:18:50 PM PDT 24
Finished Jul 20 07:19:22 PM PDT 24
Peak memory 214044 kb
Host smart-86b6c23c-e844-428f-a1aa-e7b7478bb7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865075387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.865075387
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.2214348076
Short name T203
Test name
Test status
Simulation time 2091752173 ps
CPU time 3.98 seconds
Started Jul 20 07:18:54 PM PDT 24
Finished Jul 20 07:19:27 PM PDT 24
Peak memory 219980 kb
Host smart-681e29df-b546-4f31-b4b6-87ade6e0b6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214348076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2214348076
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.1606635475
Short name T839
Test name
Test status
Simulation time 553502917 ps
CPU time 9.54 seconds
Started Jul 20 07:18:51 PM PDT 24
Finished Jul 20 07:19:31 PM PDT 24
Peak memory 209672 kb
Host smart-a4685572-24cb-470e-a0e1-15f6806e8ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606635475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1606635475
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.1779226560
Short name T481
Test name
Test status
Simulation time 662184590 ps
CPU time 4.14 seconds
Started Jul 20 07:18:48 PM PDT 24
Finished Jul 20 07:19:18 PM PDT 24
Peak memory 208192 kb
Host smart-a5991ecc-4927-4063-b97a-3457bbff8467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779226560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.1779226560
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.1392835367
Short name T263
Test name
Test status
Simulation time 474207362 ps
CPU time 3.17 seconds
Started Jul 20 07:18:49 PM PDT 24
Finished Jul 20 07:19:19 PM PDT 24
Peak memory 206704 kb
Host smart-6c6906da-b6cc-4d55-95b5-01a4d70af2a8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392835367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.1392835367
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.2131825131
Short name T534
Test name
Test status
Simulation time 2951583610 ps
CPU time 6.34 seconds
Started Jul 20 07:18:53 PM PDT 24
Finished Jul 20 07:19:29 PM PDT 24
Peak memory 207764 kb
Host smart-36015906-f71c-4455-9e25-f39d758c4ed9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131825131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.2131825131
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.3147154613
Short name T580
Test name
Test status
Simulation time 183087187 ps
CPU time 2.64 seconds
Started Jul 20 07:18:51 PM PDT 24
Finished Jul 20 07:19:24 PM PDT 24
Peak memory 206728 kb
Host smart-aeeabc46-e81f-4571-81e9-aec8f9aa2c17
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147154613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.3147154613
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.1873986991
Short name T836
Test name
Test status
Simulation time 331139446 ps
CPU time 3.42 seconds
Started Jul 20 07:18:54 PM PDT 24
Finished Jul 20 07:19:26 PM PDT 24
Peak memory 217984 kb
Host smart-bf85ea4a-437d-4a5f-89c3-9e9d80152098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873986991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.1873986991
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.2548524794
Short name T543
Test name
Test status
Simulation time 681466119 ps
CPU time 12.2 seconds
Started Jul 20 07:18:52 PM PDT 24
Finished Jul 20 07:19:34 PM PDT 24
Peak memory 207768 kb
Host smart-5814ebc7-5fc2-4de9-8a85-f03ffe45df7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548524794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.2548524794
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.1161678383
Short name T264
Test name
Test status
Simulation time 348647561 ps
CPU time 14.63 seconds
Started Jul 20 07:18:48 PM PDT 24
Finished Jul 20 07:19:29 PM PDT 24
Peak memory 214776 kb
Host smart-05f2e4ba-cd7e-40c0-ac99-a85791a3a405
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161678383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.1161678383
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.882770394
Short name T644
Test name
Test status
Simulation time 821949810 ps
CPU time 9.67 seconds
Started Jul 20 07:18:50 PM PDT 24
Finished Jul 20 07:19:28 PM PDT 24
Peak memory 222328 kb
Host smart-b4803e72-e26d-40d8-9dc3-9976c1ad87d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882770394 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.882770394
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.1202248782
Short name T467
Test name
Test status
Simulation time 196693612 ps
CPU time 3.83 seconds
Started Jul 20 07:18:50 PM PDT 24
Finished Jul 20 07:19:22 PM PDT 24
Peak memory 209088 kb
Host smart-6bbffe21-b6ab-4bc5-a483-89333d1e3171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202248782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.1202248782
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.355717310
Short name T625
Test name
Test status
Simulation time 87439382 ps
CPU time 2.36 seconds
Started Jul 20 07:18:52 PM PDT 24
Finished Jul 20 07:19:25 PM PDT 24
Peak memory 209752 kb
Host smart-3af3a5d3-96c7-41dd-b49d-c9b98ed0b920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355717310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.355717310
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.3522851685
Short name T415
Test name
Test status
Simulation time 49721811 ps
CPU time 0.72 seconds
Started Jul 20 07:15:41 PM PDT 24
Finished Jul 20 07:15:43 PM PDT 24
Peak memory 205852 kb
Host smart-d53171d8-d060-4180-8381-6980248a0e88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522851685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.3522851685
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.3380221761
Short name T736
Test name
Test status
Simulation time 149118087 ps
CPU time 2.8 seconds
Started Jul 20 07:15:49 PM PDT 24
Finished Jul 20 07:15:53 PM PDT 24
Peak memory 222232 kb
Host smart-43cd5167-3251-4479-bd88-97c0e58be129
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3380221761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.3380221761
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.3024634267
Short name T35
Test name
Test status
Simulation time 623223378 ps
CPU time 7.11 seconds
Started Jul 20 07:15:43 PM PDT 24
Finished Jul 20 07:15:52 PM PDT 24
Peak memory 214088 kb
Host smart-4bed1a2b-b36d-414e-a003-b26fcbe4a6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024634267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.3024634267
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.3702039045
Short name T361
Test name
Test status
Simulation time 1235615614 ps
CPU time 3.82 seconds
Started Jul 20 07:15:40 PM PDT 24
Finished Jul 20 07:15:45 PM PDT 24
Peak memory 218192 kb
Host smart-b92707db-8016-47e4-941e-49bdb8226250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702039045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.3702039045
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.2519465936
Short name T223
Test name
Test status
Simulation time 229175437 ps
CPU time 5.15 seconds
Started Jul 20 07:15:40 PM PDT 24
Finished Jul 20 07:15:46 PM PDT 24
Peak memory 222212 kb
Host smart-5241258e-abaf-47d6-b1b7-401be0110646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519465936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.2519465936
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.4106411038
Short name T316
Test name
Test status
Simulation time 239586792 ps
CPU time 2.58 seconds
Started Jul 20 07:15:41 PM PDT 24
Finished Jul 20 07:15:45 PM PDT 24
Peak memory 214012 kb
Host smart-cc32b812-3ac6-4663-8358-b54e643ae642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106411038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.4106411038
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.3614683222
Short name T843
Test name
Test status
Simulation time 390636277 ps
CPU time 4.78 seconds
Started Jul 20 07:15:40 PM PDT 24
Finished Jul 20 07:15:46 PM PDT 24
Peak memory 214056 kb
Host smart-62121177-46dd-4e1b-945c-d401d7fd5339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614683222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.3614683222
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.2755455438
Short name T590
Test name
Test status
Simulation time 694640372 ps
CPU time 5.87 seconds
Started Jul 20 07:15:50 PM PDT 24
Finished Jul 20 07:15:57 PM PDT 24
Peak memory 214064 kb
Host smart-c660b336-3a3e-4b13-8cf8-ffb6f40445d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755455438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.2755455438
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.180520109
Short name T38
Test name
Test status
Simulation time 1586719914 ps
CPU time 12.19 seconds
Started Jul 20 07:15:50 PM PDT 24
Finished Jul 20 07:16:03 PM PDT 24
Peak memory 238120 kb
Host smart-7e28d7ea-b147-4e30-8f93-29be6f824da8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180520109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.180520109
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.585912314
Short name T498
Test name
Test status
Simulation time 236338865 ps
CPU time 3.04 seconds
Started Jul 20 07:15:52 PM PDT 24
Finished Jul 20 07:15:55 PM PDT 24
Peak memory 206628 kb
Host smart-db23b46c-fd3c-4ba8-b0d3-2df1359bb0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585912314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.585912314
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.2921305780
Short name T522
Test name
Test status
Simulation time 331774275 ps
CPU time 4.07 seconds
Started Jul 20 07:15:41 PM PDT 24
Finished Jul 20 07:15:48 PM PDT 24
Peak memory 208352 kb
Host smart-d0b48d2c-150b-4d08-9eb3-b134eb95f490
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921305780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.2921305780
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.572500944
Short name T503
Test name
Test status
Simulation time 130727004 ps
CPU time 2.67 seconds
Started Jul 20 07:15:40 PM PDT 24
Finished Jul 20 07:15:44 PM PDT 24
Peak memory 207160 kb
Host smart-79376b07-91e7-4f4c-ae93-1415a3244fdc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572500944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.572500944
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.2596505792
Short name T651
Test name
Test status
Simulation time 283737330 ps
CPU time 3.1 seconds
Started Jul 20 07:15:42 PM PDT 24
Finished Jul 20 07:15:47 PM PDT 24
Peak memory 206700 kb
Host smart-05a6a0a8-1712-4d52-ac4f-025911319a28
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596505792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.2596505792
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.602698216
Short name T219
Test name
Test status
Simulation time 81197529 ps
CPU time 3.08 seconds
Started Jul 20 07:15:41 PM PDT 24
Finished Jul 20 07:15:46 PM PDT 24
Peak memory 214068 kb
Host smart-6638d201-b7d0-47e9-8279-efd7e72052b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602698216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.602698216
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.2926619843
Short name T436
Test name
Test status
Simulation time 227169941 ps
CPU time 4.3 seconds
Started Jul 20 07:15:50 PM PDT 24
Finished Jul 20 07:15:55 PM PDT 24
Peak memory 208164 kb
Host smart-1d9bbcf7-281f-4428-92c6-b2f5719e8d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926619843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.2926619843
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.1336433554
Short name T65
Test name
Test status
Simulation time 11902394542 ps
CPU time 102.69 seconds
Started Jul 20 07:15:40 PM PDT 24
Finished Jul 20 07:17:23 PM PDT 24
Peak memory 218892 kb
Host smart-0098b010-2b83-4a0d-a307-d44b921f3cc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336433554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1336433554
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.3658007533
Short name T541
Test name
Test status
Simulation time 295368785 ps
CPU time 3.26 seconds
Started Jul 20 07:15:41 PM PDT 24
Finished Jul 20 07:15:47 PM PDT 24
Peak memory 208420 kb
Host smart-f28e203e-664c-40d9-a3bd-4c7b8bb6f853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658007533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.3658007533
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.783614938
Short name T353
Test name
Test status
Simulation time 125721670 ps
CPU time 2.93 seconds
Started Jul 20 07:15:49 PM PDT 24
Finished Jul 20 07:15:53 PM PDT 24
Peak memory 210100 kb
Host smart-ec3ae4e7-8d57-431c-b479-ae668053c1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783614938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.783614938
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.1400161363
Short name T406
Test name
Test status
Simulation time 28518868 ps
CPU time 0.72 seconds
Started Jul 20 07:19:11 PM PDT 24
Finished Jul 20 07:19:46 PM PDT 24
Peak memory 205828 kb
Host smart-72fd5423-7922-4308-9a4b-328e6c779f19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400161363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.1400161363
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.3423801661
Short name T798
Test name
Test status
Simulation time 761081177 ps
CPU time 4.39 seconds
Started Jul 20 07:18:59 PM PDT 24
Finished Jul 20 07:19:35 PM PDT 24
Peak memory 211032 kb
Host smart-74970bfb-a2bf-493c-ae95-698c83ac4f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423801661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.3423801661
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.2689454121
Short name T751
Test name
Test status
Simulation time 1381392162 ps
CPU time 7.02 seconds
Started Jul 20 07:18:59 PM PDT 24
Finished Jul 20 07:19:37 PM PDT 24
Peak memory 209848 kb
Host smart-4eddd047-7fd1-4197-ab55-53b3e570ce4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689454121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.2689454121
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.2749552883
Short name T345
Test name
Test status
Simulation time 244925659 ps
CPU time 3.13 seconds
Started Jul 20 07:19:02 PM PDT 24
Finished Jul 20 07:19:36 PM PDT 24
Peak memory 222212 kb
Host smart-52da6f38-0d52-47ff-9586-b5298415d834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749552883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.2749552883
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.3444467217
Short name T275
Test name
Test status
Simulation time 2405272870 ps
CPU time 17.22 seconds
Started Jul 20 07:18:58 PM PDT 24
Finished Jul 20 07:19:45 PM PDT 24
Peak memory 214152 kb
Host smart-1420baf2-e2df-4aa9-9d22-50c48304cc4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444467217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.3444467217
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.2257365913
Short name T620
Test name
Test status
Simulation time 103812457 ps
CPU time 1.93 seconds
Started Jul 20 07:19:00 PM PDT 24
Finished Jul 20 07:19:33 PM PDT 24
Peak memory 214072 kb
Host smart-d5764762-f492-4e47-8576-ab0ecb4299fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257365913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.2257365913
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.2616807891
Short name T245
Test name
Test status
Simulation time 615673233 ps
CPU time 4.66 seconds
Started Jul 20 07:18:58 PM PDT 24
Finished Jul 20 07:19:32 PM PDT 24
Peak memory 219368 kb
Host smart-a7ed28a0-58c6-49da-b988-a31b31d64d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616807891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.2616807891
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.1729846333
Short name T676
Test name
Test status
Simulation time 124641639 ps
CPU time 3.78 seconds
Started Jul 20 07:18:58 PM PDT 24
Finished Jul 20 07:19:32 PM PDT 24
Peak memory 208504 kb
Host smart-2dd3e71b-ae0c-4d11-8424-2fc6130a51f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729846333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.1729846333
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.3577098105
Short name T471
Test name
Test status
Simulation time 261546129 ps
CPU time 7.1 seconds
Started Jul 20 07:18:58 PM PDT 24
Finished Jul 20 07:19:35 PM PDT 24
Peak memory 208860 kb
Host smart-a0fde99b-2541-4c4f-9ae5-53018a6ee297
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577098105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3577098105
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.3870087795
Short name T614
Test name
Test status
Simulation time 104981259 ps
CPU time 2.19 seconds
Started Jul 20 07:18:58 PM PDT 24
Finished Jul 20 07:19:30 PM PDT 24
Peak memory 206724 kb
Host smart-4227dcfb-844c-4412-9d8e-4bf32aa306ef
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870087795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.3870087795
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.429171343
Short name T487
Test name
Test status
Simulation time 30642091 ps
CPU time 2.31 seconds
Started Jul 20 07:18:58 PM PDT 24
Finished Jul 20 07:19:30 PM PDT 24
Peak memory 208128 kb
Host smart-406c3dbf-812e-4283-b357-af8b90209767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429171343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.429171343
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.2184389680
Short name T617
Test name
Test status
Simulation time 106594761 ps
CPU time 2.58 seconds
Started Jul 20 07:19:00 PM PDT 24
Finished Jul 20 07:19:33 PM PDT 24
Peak memory 208224 kb
Host smart-1407d94c-3884-4ebf-a084-94c4ab476ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184389680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.2184389680
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.2452661326
Short name T596
Test name
Test status
Simulation time 195334934 ps
CPU time 10.95 seconds
Started Jul 20 07:19:07 PM PDT 24
Finished Jul 20 07:19:50 PM PDT 24
Peak memory 222296 kb
Host smart-646beb8f-5ab4-4023-94ca-c3ef7be09ee3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452661326 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.2452661326
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.668885218
Short name T232
Test name
Test status
Simulation time 713516014 ps
CPU time 7.05 seconds
Started Jul 20 07:19:03 PM PDT 24
Finished Jul 20 07:19:41 PM PDT 24
Peak memory 207304 kb
Host smart-a0de8f94-c68d-4420-9ca5-a40b9c4c0ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668885218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.668885218
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.3026500588
Short name T115
Test name
Test status
Simulation time 298925148 ps
CPU time 3.08 seconds
Started Jul 20 07:19:08 PM PDT 24
Finished Jul 20 07:19:44 PM PDT 24
Peak memory 209980 kb
Host smart-2609d6f2-edd6-49ba-b8d5-775909818257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026500588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3026500588
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.376806812
Short name T813
Test name
Test status
Simulation time 43096634 ps
CPU time 0.87 seconds
Started Jul 20 07:19:08 PM PDT 24
Finished Jul 20 07:19:42 PM PDT 24
Peak memory 205844 kb
Host smart-6a309b6a-fcea-4df5-ba23-13250bd63849
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376806812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.376806812
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.1385535251
Short name T358
Test name
Test status
Simulation time 57613889 ps
CPU time 2.31 seconds
Started Jul 20 07:19:09 PM PDT 24
Finished Jul 20 07:19:45 PM PDT 24
Peak memory 214068 kb
Host smart-c47c8847-9596-47cf-b6c9-4ad1772da530
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1385535251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.1385535251
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.359787170
Short name T17
Test name
Test status
Simulation time 456584231 ps
CPU time 4.77 seconds
Started Jul 20 07:19:07 PM PDT 24
Finished Jul 20 07:19:45 PM PDT 24
Peak memory 214356 kb
Host smart-ae1e848c-bcff-4357-a3a7-fc22fda5fda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359787170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.359787170
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.864938463
Short name T70
Test name
Test status
Simulation time 66651431 ps
CPU time 1.55 seconds
Started Jul 20 07:19:08 PM PDT 24
Finished Jul 20 07:19:43 PM PDT 24
Peak memory 214204 kb
Host smart-45a6db51-2895-461c-ae66-b8e91e5444ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864938463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.864938463
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.1341575641
Short name T81
Test name
Test status
Simulation time 84998034 ps
CPU time 3.04 seconds
Started Jul 20 07:19:08 PM PDT 24
Finished Jul 20 07:19:45 PM PDT 24
Peak memory 214160 kb
Host smart-ba208801-e0f9-414a-b803-ab09dfe8507c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341575641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.1341575641
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.2997484218
Short name T375
Test name
Test status
Simulation time 59156688 ps
CPU time 2.35 seconds
Started Jul 20 07:19:08 PM PDT 24
Finished Jul 20 07:19:43 PM PDT 24
Peak memory 214004 kb
Host smart-ed4a3135-7f91-4308-a5f1-c4be87364a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997484218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.2997484218
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.2405802665
Short name T474
Test name
Test status
Simulation time 195657208 ps
CPU time 4.78 seconds
Started Jul 20 07:19:06 PM PDT 24
Finished Jul 20 07:19:43 PM PDT 24
Peak memory 220256 kb
Host smart-c49e85b7-5ff2-4a2f-9835-fdfe3002a6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405802665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.2405802665
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.3162119681
Short name T389
Test name
Test status
Simulation time 402395873 ps
CPU time 4.91 seconds
Started Jul 20 07:19:07 PM PDT 24
Finished Jul 20 07:19:45 PM PDT 24
Peak memory 207132 kb
Host smart-97553206-1a9f-4cad-b1f9-f3576b0004ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162119681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.3162119681
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.1735740780
Short name T797
Test name
Test status
Simulation time 201627281 ps
CPU time 2.64 seconds
Started Jul 20 07:19:07 PM PDT 24
Finished Jul 20 07:19:42 PM PDT 24
Peak memory 207860 kb
Host smart-ff20b738-a3b2-482a-b640-a9af71463d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735740780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.1735740780
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.851082362
Short name T845
Test name
Test status
Simulation time 40507586 ps
CPU time 1.81 seconds
Started Jul 20 07:19:07 PM PDT 24
Finished Jul 20 07:19:41 PM PDT 24
Peak memory 206500 kb
Host smart-5583cf09-4fc8-479b-932c-223144eab7a6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851082362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.851082362
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.1708021299
Short name T664
Test name
Test status
Simulation time 464804014 ps
CPU time 2.36 seconds
Started Jul 20 07:19:07 PM PDT 24
Finished Jul 20 07:19:42 PM PDT 24
Peak memory 207188 kb
Host smart-f0c80987-7b04-4a99-90c5-072eb8e1bd80
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708021299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.1708021299
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.1828013220
Short name T75
Test name
Test status
Simulation time 67002920 ps
CPU time 2.58 seconds
Started Jul 20 07:19:08 PM PDT 24
Finished Jul 20 07:19:45 PM PDT 24
Peak memory 208312 kb
Host smart-81a01a16-3bac-47ec-ba2c-2286261962d3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828013220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.1828013220
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.1336586983
Short name T627
Test name
Test status
Simulation time 101242124 ps
CPU time 4.3 seconds
Started Jul 20 07:19:11 PM PDT 24
Finished Jul 20 07:19:49 PM PDT 24
Peak memory 214180 kb
Host smart-e6cc9375-9184-49ae-a916-8c355d24dc06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336586983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1336586983
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.2602297819
Short name T721
Test name
Test status
Simulation time 390899994 ps
CPU time 2.02 seconds
Started Jul 20 07:19:09 PM PDT 24
Finished Jul 20 07:19:44 PM PDT 24
Peak memory 208404 kb
Host smart-2160196b-08a4-4b65-9a3a-b7381201f42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602297819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.2602297819
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.2518282427
Short name T632
Test name
Test status
Simulation time 184672803 ps
CPU time 4.71 seconds
Started Jul 20 07:19:11 PM PDT 24
Finished Jul 20 07:19:50 PM PDT 24
Peak memory 214024 kb
Host smart-ecb7a668-951a-4def-b656-46693aa58d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518282427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2518282427
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.3754063087
Short name T367
Test name
Test status
Simulation time 31489573 ps
CPU time 1.81 seconds
Started Jul 20 07:19:08 PM PDT 24
Finished Jul 20 07:19:43 PM PDT 24
Peak memory 209456 kb
Host smart-417254f9-99e4-40c0-b036-d41af6ed2754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754063087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.3754063087
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.1619620397
Short name T465
Test name
Test status
Simulation time 46807644 ps
CPU time 0.85 seconds
Started Jul 20 07:19:20 PM PDT 24
Finished Jul 20 07:19:55 PM PDT 24
Peak memory 205888 kb
Host smart-3c8e6a49-9d09-4eac-a9f7-a7f61ea81fb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619620397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.1619620397
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.475261694
Short name T567
Test name
Test status
Simulation time 70050197 ps
CPU time 3.14 seconds
Started Jul 20 07:19:19 PM PDT 24
Finished Jul 20 07:19:57 PM PDT 24
Peak memory 207412 kb
Host smart-1ca233e2-cf18-4be8-a429-067175c42788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475261694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.475261694
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.3465173791
Short name T220
Test name
Test status
Simulation time 23337016 ps
CPU time 1.94 seconds
Started Jul 20 07:19:17 PM PDT 24
Finished Jul 20 07:19:54 PM PDT 24
Peak memory 214156 kb
Host smart-60a8499c-9dfe-49b8-aded-31c58f9db6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465173791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3465173791
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.2670368669
Short name T347
Test name
Test status
Simulation time 274341110 ps
CPU time 5.95 seconds
Started Jul 20 07:19:18 PM PDT 24
Finished Jul 20 07:20:00 PM PDT 24
Peak memory 220344 kb
Host smart-ca057496-2cb9-4952-9625-ce550b8f8957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670368669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.2670368669
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.1147294959
Short name T767
Test name
Test status
Simulation time 225166866 ps
CPU time 3.57 seconds
Started Jul 20 07:19:20 PM PDT 24
Finished Jul 20 07:19:58 PM PDT 24
Peak memory 207532 kb
Host smart-c464545e-366e-41b8-8704-ddc174689461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147294959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.1147294959
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.562227975
Short name T76
Test name
Test status
Simulation time 59048710 ps
CPU time 2.83 seconds
Started Jul 20 07:19:17 PM PDT 24
Finished Jul 20 07:19:57 PM PDT 24
Peak memory 207516 kb
Host smart-03d081a1-9e40-4c88-a1c3-ae81344b9472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562227975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.562227975
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.4023312002
Short name T604
Test name
Test status
Simulation time 125396750 ps
CPU time 2.2 seconds
Started Jul 20 07:19:07 PM PDT 24
Finished Jul 20 07:19:42 PM PDT 24
Peak memory 206916 kb
Host smart-83d6031a-e885-428a-8d69-761c69df8400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023312002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.4023312002
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.3806906226
Short name T803
Test name
Test status
Simulation time 1136354327 ps
CPU time 8.08 seconds
Started Jul 20 07:19:22 PM PDT 24
Finished Jul 20 07:20:05 PM PDT 24
Peak memory 208320 kb
Host smart-3ef3765a-c6d3-4f82-95de-48f5586dcdd4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806906226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.3806906226
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.2884320854
Short name T866
Test name
Test status
Simulation time 64106276 ps
CPU time 2.45 seconds
Started Jul 20 07:19:17 PM PDT 24
Finished Jul 20 07:19:54 PM PDT 24
Peak memory 206528 kb
Host smart-7dced21a-1734-4329-ac7e-4d11657d3f31
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884320854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.2884320854
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.2788023042
Short name T792
Test name
Test status
Simulation time 572263125 ps
CPU time 19.33 seconds
Started Jul 20 07:19:16 PM PDT 24
Finished Jul 20 07:20:10 PM PDT 24
Peak memory 208316 kb
Host smart-1acfbcb9-e045-480b-b2b9-82364e052b70
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788023042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.2788023042
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.148463978
Short name T557
Test name
Test status
Simulation time 325190283 ps
CPU time 3.84 seconds
Started Jul 20 07:19:19 PM PDT 24
Finished Jul 20 07:19:58 PM PDT 24
Peak memory 218364 kb
Host smart-94155e99-3483-42f5-9ad8-f1dbfb124ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148463978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.148463978
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.3729249793
Short name T454
Test name
Test status
Simulation time 285441640 ps
CPU time 6.23 seconds
Started Jul 20 07:19:09 PM PDT 24
Finished Jul 20 07:19:49 PM PDT 24
Peak memory 208652 kb
Host smart-ca04826a-8958-4cb6-af85-f64f276104dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729249793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.3729249793
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.2144838066
Short name T51
Test name
Test status
Simulation time 238328510 ps
CPU time 9.18 seconds
Started Jul 20 07:19:16 PM PDT 24
Finished Jul 20 07:20:00 PM PDT 24
Peak memory 219576 kb
Host smart-1b370bf1-48a5-4437-b1ab-31eba4902cd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144838066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.2144838066
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.1118545715
Short name T437
Test name
Test status
Simulation time 1300896533 ps
CPU time 16.94 seconds
Started Jul 20 07:19:21 PM PDT 24
Finished Jul 20 07:20:13 PM PDT 24
Peak memory 208028 kb
Host smart-d57c28ea-a498-43a7-9c3b-b20fb87e7173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118545715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1118545715
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.2024545182
Short name T157
Test name
Test status
Simulation time 41307875 ps
CPU time 2.26 seconds
Started Jul 20 07:19:18 PM PDT 24
Finished Jul 20 07:19:56 PM PDT 24
Peak memory 209940 kb
Host smart-4a98b6a1-270b-45be-83ab-7877010aa56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024545182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2024545182
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.4238477770
Short name T403
Test name
Test status
Simulation time 19646242 ps
CPU time 0.95 seconds
Started Jul 20 07:19:28 PM PDT 24
Finished Jul 20 07:20:05 PM PDT 24
Peak memory 205932 kb
Host smart-f81b6e9d-5197-47d1-8c33-218c1ed123be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238477770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.4238477770
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.458964659
Short name T395
Test name
Test status
Simulation time 681028821 ps
CPU time 34.46 seconds
Started Jul 20 07:19:28 PM PDT 24
Finished Jul 20 07:20:39 PM PDT 24
Peak memory 214084 kb
Host smart-1e586f56-98d6-4d4b-9b6b-c90c7bb801fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=458964659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.458964659
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.559335672
Short name T18
Test name
Test status
Simulation time 519998887 ps
CPU time 3.38 seconds
Started Jul 20 07:19:28 PM PDT 24
Finished Jul 20 07:20:07 PM PDT 24
Peak memory 222552 kb
Host smart-ea5918e2-30e9-4142-af19-896275516311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559335672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.559335672
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.1953570101
Short name T62
Test name
Test status
Simulation time 551372830 ps
CPU time 13.62 seconds
Started Jul 20 07:19:26 PM PDT 24
Finished Jul 20 07:20:16 PM PDT 24
Peak memory 208472 kb
Host smart-6a9e9a1d-a602-4389-8af4-aaa036f736ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953570101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.1953570101
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.3621214759
Short name T659
Test name
Test status
Simulation time 280113242 ps
CPU time 3.17 seconds
Started Jul 20 07:19:26 PM PDT 24
Finished Jul 20 07:20:06 PM PDT 24
Peak memory 214172 kb
Host smart-e0ff2249-2815-4cea-88de-0011696e1250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621214759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.3621214759
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.947828408
Short name T52
Test name
Test status
Simulation time 284871474 ps
CPU time 3.12 seconds
Started Jul 20 07:19:26 PM PDT 24
Finished Jul 20 07:20:06 PM PDT 24
Peak memory 222204 kb
Host smart-f842533b-8290-42ad-b54d-c7c466330d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947828408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.947828408
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.3360134092
Short name T565
Test name
Test status
Simulation time 79533202 ps
CPU time 2.94 seconds
Started Jul 20 07:19:27 PM PDT 24
Finished Jul 20 07:20:07 PM PDT 24
Peak memory 217920 kb
Host smart-a136d82e-8b32-47ec-a517-fd6c9718c567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360134092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.3360134092
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.427112122
Short name T226
Test name
Test status
Simulation time 453661933 ps
CPU time 5.97 seconds
Started Jul 20 07:19:27 PM PDT 24
Finished Jul 20 07:20:10 PM PDT 24
Peak memory 214068 kb
Host smart-cdf1ee52-d837-442f-895c-1008fbd69bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427112122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.427112122
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.2326987005
Short name T789
Test name
Test status
Simulation time 81997800 ps
CPU time 3.23 seconds
Started Jul 20 07:19:17 PM PDT 24
Finished Jul 20 07:19:55 PM PDT 24
Peak memory 208420 kb
Host smart-b88d67cb-d54e-412c-b0de-c2ca12705af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326987005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.2326987005
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.3052990972
Short name T719
Test name
Test status
Simulation time 723702767 ps
CPU time 8.34 seconds
Started Jul 20 07:19:29 PM PDT 24
Finished Jul 20 07:20:14 PM PDT 24
Peak memory 208624 kb
Host smart-0d6c1b8b-fa40-440a-bdbc-a4e39bb8d3d7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052990972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.3052990972
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.1560263044
Short name T16
Test name
Test status
Simulation time 123954417 ps
CPU time 3.97 seconds
Started Jul 20 07:19:17 PM PDT 24
Finished Jul 20 07:19:57 PM PDT 24
Peak memory 208512 kb
Host smart-5fb85115-191e-421b-a1b1-a4e7fb23a390
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560263044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.1560263044
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.3962160373
Short name T189
Test name
Test status
Simulation time 251486580 ps
CPU time 7.13 seconds
Started Jul 20 07:19:28 PM PDT 24
Finished Jul 20 07:20:11 PM PDT 24
Peak memory 208488 kb
Host smart-0c953014-13ee-4122-b9bd-01668577bcf7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962160373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.3962160373
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.4180091492
Short name T337
Test name
Test status
Simulation time 1995212901 ps
CPU time 20.79 seconds
Started Jul 20 07:19:30 PM PDT 24
Finished Jul 20 07:20:27 PM PDT 24
Peak memory 210292 kb
Host smart-573ac275-fed9-45ea-94a2-b154c96718c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180091492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.4180091492
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.2321700394
Short name T775
Test name
Test status
Simulation time 246346970 ps
CPU time 2.61 seconds
Started Jul 20 07:19:21 PM PDT 24
Finished Jul 20 07:19:59 PM PDT 24
Peak memory 206596 kb
Host smart-b11243c0-d846-4721-a13d-e7996c3ec709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321700394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.2321700394
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.1558675640
Short name T68
Test name
Test status
Simulation time 2312572515 ps
CPU time 33.62 seconds
Started Jul 20 07:19:29 PM PDT 24
Finished Jul 20 07:20:39 PM PDT 24
Peak memory 215008 kb
Host smart-6b2de0a6-1ebe-4bcc-a1e5-4a0e2c4e7a91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558675640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1558675640
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.3125578619
Short name T681
Test name
Test status
Simulation time 854118388 ps
CPU time 6.54 seconds
Started Jul 20 07:19:26 PM PDT 24
Finished Jul 20 07:20:09 PM PDT 24
Peak memory 209992 kb
Host smart-b922f0a7-1abe-4d9f-b4e7-224a8fce1478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125578619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.3125578619
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.2674883413
Short name T737
Test name
Test status
Simulation time 96113511 ps
CPU time 2.37 seconds
Started Jul 20 07:19:26 PM PDT 24
Finished Jul 20 07:20:05 PM PDT 24
Peak memory 209684 kb
Host smart-e920896e-dc64-479c-9f8c-af67ddc4fd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674883413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.2674883413
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.2515150516
Short name T510
Test name
Test status
Simulation time 51543616 ps
CPU time 0.91 seconds
Started Jul 20 07:19:36 PM PDT 24
Finished Jul 20 07:20:14 PM PDT 24
Peak memory 205804 kb
Host smart-83daf6b3-e535-439d-b17e-9c897c6f4109
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515150516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.2515150516
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.3250452246
Short name T279
Test name
Test status
Simulation time 292763845 ps
CPU time 4.41 seconds
Started Jul 20 07:19:26 PM PDT 24
Finished Jul 20 07:20:07 PM PDT 24
Peak memory 214952 kb
Host smart-5646796a-ab2c-4999-9a01-d1e16cf3793d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3250452246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3250452246
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.1970008374
Short name T46
Test name
Test status
Simulation time 559773271 ps
CPU time 5.4 seconds
Started Jul 20 07:19:30 PM PDT 24
Finished Jul 20 07:20:12 PM PDT 24
Peak memory 222208 kb
Host smart-03c9e23e-8bf1-4841-bf03-7010dd271e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970008374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.1970008374
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.926961563
Short name T80
Test name
Test status
Simulation time 1024371235 ps
CPU time 3.05 seconds
Started Jul 20 07:19:27 PM PDT 24
Finished Jul 20 07:20:06 PM PDT 24
Peak memory 208360 kb
Host smart-a5223e0b-0a55-4fe3-b156-748bb53d94d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926961563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.926961563
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.3463102645
Short name T476
Test name
Test status
Simulation time 174905903 ps
CPU time 4.22 seconds
Started Jul 20 07:19:37 PM PDT 24
Finished Jul 20 07:20:19 PM PDT 24
Peak memory 213996 kb
Host smart-73085cf4-1210-41c1-a057-fb28caee35f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463102645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.3463102645
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.4029472860
Short name T41
Test name
Test status
Simulation time 147442614 ps
CPU time 6.96 seconds
Started Jul 20 07:19:27 PM PDT 24
Finished Jul 20 07:20:11 PM PDT 24
Peak memory 222228 kb
Host smart-d8f3f174-8c6a-484a-aca6-db2f8d86eab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029472860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.4029472860
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.2425518084
Short name T414
Test name
Test status
Simulation time 370488713 ps
CPU time 4.28 seconds
Started Jul 20 07:19:26 PM PDT 24
Finished Jul 20 07:20:06 PM PDT 24
Peak memory 207220 kb
Host smart-6ae69de9-9493-420b-a7a4-364704943f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425518084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.2425518084
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2880909677
Short name T851
Test name
Test status
Simulation time 834669075 ps
CPU time 6.23 seconds
Started Jul 20 07:19:30 PM PDT 24
Finished Jul 20 07:20:13 PM PDT 24
Peak memory 207784 kb
Host smart-bbd1ac64-704d-4200-a381-39fc58c69e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880909677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2880909677
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.1366583574
Short name T634
Test name
Test status
Simulation time 39480511 ps
CPU time 2.4 seconds
Started Jul 20 07:19:30 PM PDT 24
Finished Jul 20 07:20:09 PM PDT 24
Peak memory 206676 kb
Host smart-208cb6bd-b491-4032-8e95-a0850fa2708e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366583574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.1366583574
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.1896859732
Short name T918
Test name
Test status
Simulation time 190945301 ps
CPU time 5.46 seconds
Started Jul 20 07:19:33 PM PDT 24
Finished Jul 20 07:20:14 PM PDT 24
Peak memory 208456 kb
Host smart-8c101242-7014-4a77-a239-58c5550278fe
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896859732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.1896859732
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.404217779
Short name T451
Test name
Test status
Simulation time 191446065 ps
CPU time 3.62 seconds
Started Jul 20 07:19:26 PM PDT 24
Finished Jul 20 07:20:06 PM PDT 24
Peak memory 208300 kb
Host smart-1a13ce3a-7008-45c0-8fdb-b785e74e3091
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404217779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.404217779
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.3277324592
Short name T649
Test name
Test status
Simulation time 21612792 ps
CPU time 1.84 seconds
Started Jul 20 07:19:40 PM PDT 24
Finished Jul 20 07:20:19 PM PDT 24
Peak memory 215204 kb
Host smart-54feb818-48dc-4b34-a195-917677216041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277324592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.3277324592
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.2052415927
Short name T821
Test name
Test status
Simulation time 351057266 ps
CPU time 2.86 seconds
Started Jul 20 07:19:27 PM PDT 24
Finished Jul 20 07:20:06 PM PDT 24
Peak memory 206464 kb
Host smart-3be47ac5-d638-413c-88b7-5d99925d784b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052415927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.2052415927
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.1943351161
Short name T257
Test name
Test status
Simulation time 200277557 ps
CPU time 6.72 seconds
Started Jul 20 07:19:26 PM PDT 24
Finished Jul 20 07:20:09 PM PDT 24
Peak memory 209820 kb
Host smart-c0d71796-9aaf-49e2-b7ce-5c5e67c4bd3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943351161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.1943351161
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.2330361856
Short name T715
Test name
Test status
Simulation time 1882446986 ps
CPU time 15.27 seconds
Started Jul 20 07:19:42 PM PDT 24
Finished Jul 20 07:20:35 PM PDT 24
Peak memory 210580 kb
Host smart-ab2d67bb-67a9-4fdd-a346-2d2c85a6275d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330361856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.2330361856
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.1526590435
Short name T636
Test name
Test status
Simulation time 40485311 ps
CPU time 0.8 seconds
Started Jul 20 07:19:45 PM PDT 24
Finished Jul 20 07:20:26 PM PDT 24
Peak memory 205824 kb
Host smart-127ff063-0b1b-42b8-af8c-d7fa0a2bf74c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526590435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1526590435
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.3302544065
Short name T860
Test name
Test status
Simulation time 110282204 ps
CPU time 2.21 seconds
Started Jul 20 07:19:35 PM PDT 24
Finished Jul 20 07:20:16 PM PDT 24
Peak memory 209888 kb
Host smart-5dc32006-1a97-41d3-81af-e5f4a5422f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302544065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.3302544065
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.1793259752
Short name T297
Test name
Test status
Simulation time 107553312 ps
CPU time 2.86 seconds
Started Jul 20 07:19:35 PM PDT 24
Finished Jul 20 07:20:16 PM PDT 24
Peak memory 209296 kb
Host smart-c30ad6be-9303-427c-b40b-dff6b4f5926c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793259752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.1793259752
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.1428790240
Short name T790
Test name
Test status
Simulation time 29866142 ps
CPU time 1.8 seconds
Started Jul 20 07:19:35 PM PDT 24
Finished Jul 20 07:20:15 PM PDT 24
Peak memory 214012 kb
Host smart-9196ec49-489b-4b92-a9bb-e9158f6d9666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428790240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.1428790240
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_random.1329643057
Short name T388
Test name
Test status
Simulation time 9714994954 ps
CPU time 47.48 seconds
Started Jul 20 07:19:35 PM PDT 24
Finished Jul 20 07:21:01 PM PDT 24
Peak memory 208560 kb
Host smart-35e3cbed-b196-4fee-b96e-97ed96885e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329643057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1329643057
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.193538031
Short name T325
Test name
Test status
Simulation time 151990588 ps
CPU time 2.23 seconds
Started Jul 20 07:19:36 PM PDT 24
Finished Jul 20 07:20:17 PM PDT 24
Peak memory 206712 kb
Host smart-8c2a4834-1a81-44c8-914d-54790af4f56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193538031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.193538031
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.1842540667
Short name T377
Test name
Test status
Simulation time 7361447849 ps
CPU time 48.44 seconds
Started Jul 20 07:19:35 PM PDT 24
Finished Jul 20 07:21:02 PM PDT 24
Peak memory 208220 kb
Host smart-91b63fd8-cc0f-4cc2-b347-bb66c1107914
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842540667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.1842540667
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.414783628
Short name T560
Test name
Test status
Simulation time 128248175 ps
CPU time 2.56 seconds
Started Jul 20 07:19:39 PM PDT 24
Finished Jul 20 07:20:19 PM PDT 24
Peak memory 206764 kb
Host smart-57074bc8-7732-470c-8fd6-5a8f428c8a49
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414783628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.414783628
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.552628388
Short name T434
Test name
Test status
Simulation time 1647793384 ps
CPU time 3.79 seconds
Started Jul 20 07:19:35 PM PDT 24
Finished Jul 20 07:20:17 PM PDT 24
Peak memory 208732 kb
Host smart-84efa462-161a-4535-aaa5-a2cdbf30dc3e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552628388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.552628388
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.3458777510
Short name T521
Test name
Test status
Simulation time 473187988 ps
CPU time 7.3 seconds
Started Jul 20 07:19:40 PM PDT 24
Finished Jul 20 07:20:24 PM PDT 24
Peak memory 218308 kb
Host smart-a0ae77b6-edc4-468b-bcfc-c087fe71ebd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458777510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3458777510
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.64646989
Short name T829
Test name
Test status
Simulation time 188189910 ps
CPU time 2.03 seconds
Started Jul 20 07:19:34 PM PDT 24
Finished Jul 20 07:20:14 PM PDT 24
Peak memory 208292 kb
Host smart-62a7b740-fa7d-4108-9121-5dfa9c494204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64646989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.64646989
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2829474133
Short name T349
Test name
Test status
Simulation time 54375682 ps
CPU time 1.93 seconds
Started Jul 20 07:19:45 PM PDT 24
Finished Jul 20 07:20:27 PM PDT 24
Peak memory 210252 kb
Host smart-136323cb-f223-426b-9af8-6d3d37c43019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829474133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2829474133
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.2087846705
Short name T566
Test name
Test status
Simulation time 35826159 ps
CPU time 0.74 seconds
Started Jul 20 07:20:01 PM PDT 24
Finished Jul 20 07:20:42 PM PDT 24
Peak memory 205840 kb
Host smart-bb1a204b-d0f8-4653-9d51-483f23a4543c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087846705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.2087846705
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.508449101
Short name T385
Test name
Test status
Simulation time 61253845 ps
CPU time 4.11 seconds
Started Jul 20 07:19:46 PM PDT 24
Finished Jul 20 07:20:30 PM PDT 24
Peak memory 215512 kb
Host smart-da1c20c5-a866-4589-bd48-bd8e272542f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=508449101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.508449101
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.2978440543
Short name T885
Test name
Test status
Simulation time 400824536 ps
CPU time 4.48 seconds
Started Jul 20 07:19:54 PM PDT 24
Finished Jul 20 07:20:37 PM PDT 24
Peak memory 221160 kb
Host smart-0ae11677-6851-4a2c-b464-74a20531570d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978440543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2978440543
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2343194180
Short name T674
Test name
Test status
Simulation time 50497051 ps
CPU time 2.35 seconds
Started Jul 20 07:19:44 PM PDT 24
Finished Jul 20 07:20:27 PM PDT 24
Peak memory 207348 kb
Host smart-fa66d042-f813-4340-8e26-614b0ef93f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343194180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2343194180
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.523862639
Short name T255
Test name
Test status
Simulation time 30989374 ps
CPU time 2.23 seconds
Started Jul 20 07:19:45 PM PDT 24
Finished Jul 20 07:20:27 PM PDT 24
Peak memory 214072 kb
Host smart-ad1f2223-1bc1-4fa0-a931-70236473bc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523862639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.523862639
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.2522949462
Short name T837
Test name
Test status
Simulation time 246037934 ps
CPU time 2.81 seconds
Started Jul 20 07:19:44 PM PDT 24
Finished Jul 20 07:20:27 PM PDT 24
Peak memory 219736 kb
Host smart-f16ddb57-b6b1-4c8c-b3bc-d3fc800a42c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522949462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.2522949462
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.188748156
Short name T863
Test name
Test status
Simulation time 42733301 ps
CPU time 2.61 seconds
Started Jul 20 07:19:44 PM PDT 24
Finished Jul 20 07:20:27 PM PDT 24
Peak memory 209584 kb
Host smart-a7438202-b762-4efd-bd7e-def81e479a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188748156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.188748156
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.3309535353
Short name T727
Test name
Test status
Simulation time 145450621 ps
CPU time 2.84 seconds
Started Jul 20 07:19:46 PM PDT 24
Finished Jul 20 07:20:28 PM PDT 24
Peak memory 210168 kb
Host smart-c34cdd38-6c8b-4914-9931-77fd73dd15fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309535353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.3309535353
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.347847500
Short name T184
Test name
Test status
Simulation time 483473751 ps
CPU time 3.68 seconds
Started Jul 20 07:19:44 PM PDT 24
Finished Jul 20 07:20:27 PM PDT 24
Peak memory 205876 kb
Host smart-d8e8310d-5ddc-41aa-a19b-d5942535f8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347847500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.347847500
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.3407465882
Short name T694
Test name
Test status
Simulation time 546149107 ps
CPU time 4.9 seconds
Started Jul 20 07:19:47 PM PDT 24
Finished Jul 20 07:20:32 PM PDT 24
Peak memory 208208 kb
Host smart-0e985342-3bda-431c-a708-c2594ed1e8f5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407465882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.3407465882
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.373601320
Short name T507
Test name
Test status
Simulation time 90650113 ps
CPU time 3.93 seconds
Started Jul 20 07:19:45 PM PDT 24
Finished Jul 20 07:20:29 PM PDT 24
Peak memory 208840 kb
Host smart-eb8834f1-2184-430e-b7cf-e56f413bfd7b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373601320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.373601320
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.459116575
Short name T702
Test name
Test status
Simulation time 2307057392 ps
CPU time 6.76 seconds
Started Jul 20 07:19:45 PM PDT 24
Finished Jul 20 07:20:32 PM PDT 24
Peak memory 208136 kb
Host smart-eeee8f17-980a-42b8-b921-67df8b1dd3fc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459116575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.459116575
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.1959404214
Short name T605
Test name
Test status
Simulation time 49789064 ps
CPU time 1.98 seconds
Started Jul 20 07:19:53 PM PDT 24
Finished Jul 20 07:20:33 PM PDT 24
Peak memory 214076 kb
Host smart-eefb1e8e-7f2b-4343-9f94-a1b6845df23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959404214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.1959404214
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.461777806
Short name T418
Test name
Test status
Simulation time 68386475 ps
CPU time 1.61 seconds
Started Jul 20 07:19:46 PM PDT 24
Finished Jul 20 07:20:28 PM PDT 24
Peak memory 205860 kb
Host smart-4df3b61c-5833-44bf-84b1-3e778b0c9e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461777806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.461777806
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.459291444
Short name T818
Test name
Test status
Simulation time 510836976 ps
CPU time 4.26 seconds
Started Jul 20 07:19:54 PM PDT 24
Finished Jul 20 07:20:37 PM PDT 24
Peak memory 215156 kb
Host smart-e409a3d8-b64c-4077-82ff-5898211be6fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459291444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.459291444
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.3653515188
Short name T759
Test name
Test status
Simulation time 228354247 ps
CPU time 3.96 seconds
Started Jul 20 07:19:45 PM PDT 24
Finished Jul 20 07:20:29 PM PDT 24
Peak memory 206740 kb
Host smart-960b4196-7e33-40f2-b0f7-a75515dbfb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653515188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.3653515188
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.3662341599
Short name T892
Test name
Test status
Simulation time 94468155 ps
CPU time 1.68 seconds
Started Jul 20 07:20:01 PM PDT 24
Finished Jul 20 07:20:43 PM PDT 24
Peak memory 209888 kb
Host smart-283f0242-7968-47e2-a29c-b1bd03c6df18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662341599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.3662341599
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.1411388047
Short name T563
Test name
Test status
Simulation time 9258083 ps
CPU time 0.7 seconds
Started Jul 20 07:19:54 PM PDT 24
Finished Jul 20 07:20:34 PM PDT 24
Peak memory 205844 kb
Host smart-3a37786d-ee43-4b29-8075-fa842dc9656f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411388047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.1411388047
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.1650207278
Short name T359
Test name
Test status
Simulation time 56361206 ps
CPU time 3.77 seconds
Started Jul 20 07:20:02 PM PDT 24
Finished Jul 20 07:20:46 PM PDT 24
Peak memory 214092 kb
Host smart-2b246ba2-1ee5-444b-b4dd-2cc2a880fc55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1650207278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1650207278
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.1345593108
Short name T453
Test name
Test status
Simulation time 151346029 ps
CPU time 3.71 seconds
Started Jul 20 07:19:53 PM PDT 24
Finished Jul 20 07:20:35 PM PDT 24
Peak memory 214076 kb
Host smart-7062aae3-3d4a-45e7-9fc9-b656058e3cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345593108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1345593108
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.2795914637
Short name T253
Test name
Test status
Simulation time 54947081 ps
CPU time 1.97 seconds
Started Jul 20 07:20:02 PM PDT 24
Finished Jul 20 07:20:44 PM PDT 24
Peak memory 214380 kb
Host smart-6a9446c3-c3b5-45d4-97ec-e9a4cea04e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795914637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.2795914637
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.286200896
Short name T249
Test name
Test status
Simulation time 144692250 ps
CPU time 4.75 seconds
Started Jul 20 07:19:52 PM PDT 24
Finished Jul 20 07:20:35 PM PDT 24
Peak memory 211328 kb
Host smart-177b966e-0587-443a-b3f8-8f67e980a678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286200896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.286200896
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.385634012
Short name T273
Test name
Test status
Simulation time 54571686 ps
CPU time 3.62 seconds
Started Jul 20 07:19:51 PM PDT 24
Finished Jul 20 07:20:34 PM PDT 24
Peak memory 208920 kb
Host smart-4785fb62-98dd-4c26-a1ae-037d3df75520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385634012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.385634012
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.4092688205
Short name T589
Test name
Test status
Simulation time 179633485 ps
CPU time 3.79 seconds
Started Jul 20 07:19:52 PM PDT 24
Finished Jul 20 07:20:34 PM PDT 24
Peak memory 208304 kb
Host smart-7573b4df-8607-4524-9192-072edba45a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092688205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.4092688205
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.1358299918
Short name T299
Test name
Test status
Simulation time 198524043 ps
CPU time 2.89 seconds
Started Jul 20 07:19:54 PM PDT 24
Finished Jul 20 07:20:35 PM PDT 24
Peak memory 206588 kb
Host smart-96de4833-3d40-4c1f-ab6b-6c48a8a07ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358299918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.1358299918
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.3487807747
Short name T650
Test name
Test status
Simulation time 88713566 ps
CPU time 2.13 seconds
Started Jul 20 07:19:53 PM PDT 24
Finished Jul 20 07:20:34 PM PDT 24
Peak memory 207200 kb
Host smart-6f50e3b4-e5d2-4e24-b0fe-65a411887eec
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487807747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3487807747
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.2671204557
Short name T776
Test name
Test status
Simulation time 303794458 ps
CPU time 7.69 seconds
Started Jul 20 07:19:53 PM PDT 24
Finished Jul 20 07:20:39 PM PDT 24
Peak memory 206668 kb
Host smart-b003d6a6-cb02-43bb-9aed-4b7d39818f86
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671204557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.2671204557
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.634149776
Short name T678
Test name
Test status
Simulation time 76314445 ps
CPU time 1.88 seconds
Started Jul 20 07:19:53 PM PDT 24
Finished Jul 20 07:20:34 PM PDT 24
Peak memory 206808 kb
Host smart-822b04f4-c68b-43c6-ace0-ac8492250433
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634149776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.634149776
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.893014031
Short name T120
Test name
Test status
Simulation time 627295709 ps
CPU time 3.58 seconds
Started Jul 20 07:20:03 PM PDT 24
Finished Jul 20 07:20:46 PM PDT 24
Peak memory 207300 kb
Host smart-d475a6ad-e646-4792-bedf-c059b602ab1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893014031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.893014031
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.2480951585
Short name T511
Test name
Test status
Simulation time 121346651 ps
CPU time 2.45 seconds
Started Jul 20 07:19:52 PM PDT 24
Finished Jul 20 07:20:33 PM PDT 24
Peak memory 208432 kb
Host smart-67037f44-d766-4ecd-b96c-9349683a8206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480951585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.2480951585
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.1595004314
Short name T732
Test name
Test status
Simulation time 186192828 ps
CPU time 4.13 seconds
Started Jul 20 07:19:53 PM PDT 24
Finished Jul 20 07:20:36 PM PDT 24
Peak memory 208944 kb
Host smart-33ba1dc3-9fed-44d9-81e0-ba8230d8365c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595004314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.1595004314
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3575614935
Short name T472
Test name
Test status
Simulation time 478571086 ps
CPU time 12.33 seconds
Started Jul 20 07:19:53 PM PDT 24
Finished Jul 20 07:20:43 PM PDT 24
Peak memory 209416 kb
Host smart-c2ebb29a-0423-4ac8-bf16-b7a931a4ff53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575614935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3575614935
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.1187150130
Short name T173
Test name
Test status
Simulation time 370242426 ps
CPU time 3.49 seconds
Started Jul 20 07:20:02 PM PDT 24
Finished Jul 20 07:20:45 PM PDT 24
Peak memory 210060 kb
Host smart-03196874-49a7-4b93-a2dc-3ae4bc67e720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187150130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.1187150130
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.2224892549
Short name T701
Test name
Test status
Simulation time 20070401 ps
CPU time 0.79 seconds
Started Jul 20 07:20:00 PM PDT 24
Finished Jul 20 07:20:41 PM PDT 24
Peak memory 205812 kb
Host smart-c7b864e7-d47f-4f15-a371-094a9defeb3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224892549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.2224892549
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.460287571
Short name T870
Test name
Test status
Simulation time 71993824 ps
CPU time 3.24 seconds
Started Jul 20 07:20:00 PM PDT 24
Finished Jul 20 07:20:43 PM PDT 24
Peak memory 218312 kb
Host smart-000811cf-16a1-43c3-84af-c1c2e46f7ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460287571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.460287571
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.2204334875
Short name T677
Test name
Test status
Simulation time 39731539 ps
CPU time 1.7 seconds
Started Jul 20 07:20:03 PM PDT 24
Finished Jul 20 07:20:44 PM PDT 24
Peak memory 208548 kb
Host smart-49b85cca-dbdc-4ed9-8aab-4dd6861b2466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204334875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.2204334875
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.633336191
Short name T816
Test name
Test status
Simulation time 24449924 ps
CPU time 1.75 seconds
Started Jul 20 07:20:03 PM PDT 24
Finished Jul 20 07:20:44 PM PDT 24
Peak memory 214128 kb
Host smart-c15a2568-d434-4fca-9273-41281cf56c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633336191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.633336191
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.368022529
Short name T808
Test name
Test status
Simulation time 318034383 ps
CPU time 3.49 seconds
Started Jul 20 07:20:00 PM PDT 24
Finished Jul 20 07:20:44 PM PDT 24
Peak memory 213976 kb
Host smart-2a3a88e4-661a-4d96-aaac-d32e6e53c909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368022529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.368022529
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.489865870
Short name T366
Test name
Test status
Simulation time 89097423 ps
CPU time 1.66 seconds
Started Jul 20 07:20:04 PM PDT 24
Finished Jul 20 07:20:45 PM PDT 24
Peak memory 214072 kb
Host smart-da0ff68d-3b14-4350-b575-aed55e5d64b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489865870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.489865870
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.1736233152
Short name T884
Test name
Test status
Simulation time 259004307 ps
CPU time 3.16 seconds
Started Jul 20 07:20:00 PM PDT 24
Finished Jul 20 07:20:44 PM PDT 24
Peak memory 214088 kb
Host smart-b038015b-635d-4558-8e2d-696a264a5e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736233152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.1736233152
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.3399922117
Short name T725
Test name
Test status
Simulation time 95936364 ps
CPU time 2.08 seconds
Started Jul 20 07:20:03 PM PDT 24
Finished Jul 20 07:20:44 PM PDT 24
Peak memory 206640 kb
Host smart-9a2d542b-b537-45fc-b03c-9cbe0558082e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399922117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.3399922117
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.1726126484
Short name T524
Test name
Test status
Simulation time 569710179 ps
CPU time 5.88 seconds
Started Jul 20 07:20:02 PM PDT 24
Finished Jul 20 07:20:48 PM PDT 24
Peak memory 208604 kb
Host smart-481f694d-2e60-40eb-818d-3f20aae6e2ed
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726126484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.1726126484
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.123537372
Short name T246
Test name
Test status
Simulation time 173674592 ps
CPU time 2.67 seconds
Started Jul 20 07:19:53 PM PDT 24
Finished Jul 20 07:20:34 PM PDT 24
Peak memory 207060 kb
Host smart-b50cf2ce-27e5-44e4-973a-25b552e90e13
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123537372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.123537372
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.1547087237
Short name T470
Test name
Test status
Simulation time 184438320 ps
CPU time 6.14 seconds
Started Jul 20 07:20:00 PM PDT 24
Finished Jul 20 07:20:46 PM PDT 24
Peak memory 206540 kb
Host smart-7c798272-f59a-4c4a-8262-b825f4e572cf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547087237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.1547087237
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.3009527684
Short name T322
Test name
Test status
Simulation time 5219866846 ps
CPU time 21.59 seconds
Started Jul 20 07:20:02 PM PDT 24
Finished Jul 20 07:21:03 PM PDT 24
Peak memory 208496 kb
Host smart-41a60075-8d86-46d3-933a-abafea9348e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009527684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.3009527684
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.32367499
Short name T720
Test name
Test status
Simulation time 757467677 ps
CPU time 14.54 seconds
Started Jul 20 07:19:52 PM PDT 24
Finished Jul 20 07:20:45 PM PDT 24
Peak memory 208284 kb
Host smart-001475d9-a8a8-4982-8c3f-882e6eebb418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32367499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.32367499
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.4207161452
Short name T910
Test name
Test status
Simulation time 2739392536 ps
CPU time 81.48 seconds
Started Jul 20 07:20:02 PM PDT 24
Finished Jul 20 07:22:03 PM PDT 24
Peak memory 216892 kb
Host smart-652f8204-de45-4b25-b090-18c2ea9d9e53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207161452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.4207161452
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.3042305757
Short name T108
Test name
Test status
Simulation time 2595028274 ps
CPU time 24.36 seconds
Started Jul 20 07:20:01 PM PDT 24
Finished Jul 20 07:21:06 PM PDT 24
Peak memory 222492 kb
Host smart-f1ca0aad-ceb3-47ff-a9e1-91fe9d59283c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042305757 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.3042305757
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.380438025
Short name T847
Test name
Test status
Simulation time 1034289671 ps
CPU time 24.76 seconds
Started Jul 20 07:20:00 PM PDT 24
Finished Jul 20 07:21:05 PM PDT 24
Peak memory 214152 kb
Host smart-4729de10-2d9b-41a6-ab54-344a330ddd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380438025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.380438025
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.1583748901
Short name T658
Test name
Test status
Simulation time 501312419 ps
CPU time 1.95 seconds
Started Jul 20 07:20:01 PM PDT 24
Finished Jul 20 07:20:43 PM PDT 24
Peak memory 209520 kb
Host smart-b8d1124e-eb0a-4b57-aec9-ced1960d3aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583748901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.1583748901
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.4194114197
Short name T907
Test name
Test status
Simulation time 18094206 ps
CPU time 0.79 seconds
Started Jul 20 07:20:08 PM PDT 24
Finished Jul 20 07:20:48 PM PDT 24
Peak memory 205848 kb
Host smart-18d8cf38-2956-4023-bec5-d1e7ed4f83e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194114197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.4194114197
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.563808593
Short name T281
Test name
Test status
Simulation time 1906309071 ps
CPU time 25.88 seconds
Started Jul 20 07:20:09 PM PDT 24
Finished Jul 20 07:21:14 PM PDT 24
Peak memory 214956 kb
Host smart-5ddddfb4-3822-499d-859a-aba71e5d9bb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=563808593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.563808593
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.1731220333
Short name T69
Test name
Test status
Simulation time 262336978 ps
CPU time 3.13 seconds
Started Jul 20 07:20:08 PM PDT 24
Finished Jul 20 07:20:50 PM PDT 24
Peak memory 208060 kb
Host smart-20ce5b47-2c6b-4aba-995e-1b2b4c53d438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731220333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.1731220333
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.2996322169
Short name T217
Test name
Test status
Simulation time 97718846 ps
CPU time 3.34 seconds
Started Jul 20 07:20:08 PM PDT 24
Finished Jul 20 07:20:50 PM PDT 24
Peak memory 213996 kb
Host smart-3f163a9c-7e58-471d-85f4-f46aeb81b2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996322169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2996322169
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.271129986
Short name T190
Test name
Test status
Simulation time 57296074 ps
CPU time 2.39 seconds
Started Jul 20 07:20:08 PM PDT 24
Finished Jul 20 07:20:50 PM PDT 24
Peak memory 219100 kb
Host smart-61bc4a5a-c927-4aad-a867-e9f3869d5614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271129986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.271129986
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.2983241126
Short name T819
Test name
Test status
Simulation time 118904363 ps
CPU time 5.17 seconds
Started Jul 20 07:20:10 PM PDT 24
Finished Jul 20 07:20:53 PM PDT 24
Peak memory 207280 kb
Host smart-0141376a-2d1f-48e7-8c3a-17388b285f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983241126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.2983241126
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.2774338167
Short name T569
Test name
Test status
Simulation time 274847952 ps
CPU time 3.11 seconds
Started Jul 20 07:20:02 PM PDT 24
Finished Jul 20 07:20:45 PM PDT 24
Peak memory 208392 kb
Host smart-d76bd2a9-94e0-4a64-b252-379f3d2a5196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774338167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.2774338167
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.595750779
Short name T369
Test name
Test status
Simulation time 193181283 ps
CPU time 3.92 seconds
Started Jul 20 07:20:02 PM PDT 24
Finished Jul 20 07:20:46 PM PDT 24
Peak memory 206728 kb
Host smart-e667044d-cd5c-4f50-aea9-6bf19f92c3e4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595750779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.595750779
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.1321109280
Short name T785
Test name
Test status
Simulation time 436042115 ps
CPU time 6.99 seconds
Started Jul 20 07:20:03 PM PDT 24
Finished Jul 20 07:20:50 PM PDT 24
Peak memory 206724 kb
Host smart-0f013573-658e-4418-b7fe-f018d8fb47af
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321109280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.1321109280
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.2561759775
Short name T832
Test name
Test status
Simulation time 908340956 ps
CPU time 3.89 seconds
Started Jul 20 07:20:08 PM PDT 24
Finished Jul 20 07:20:51 PM PDT 24
Peak memory 206652 kb
Host smart-044fb31d-7847-4160-a6e2-b9e48905c795
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561759775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.2561759775
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.1984441188
Short name T533
Test name
Test status
Simulation time 587419764 ps
CPU time 17.76 seconds
Started Jul 20 07:20:13 PM PDT 24
Finished Jul 20 07:21:07 PM PDT 24
Peak memory 214036 kb
Host smart-2c12d865-fd66-44e4-ba1c-668371158329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984441188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.1984441188
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.1251114613
Short name T690
Test name
Test status
Simulation time 188305297 ps
CPU time 2.71 seconds
Started Jul 20 07:20:03 PM PDT 24
Finished Jul 20 07:20:46 PM PDT 24
Peak memory 208468 kb
Host smart-188e76b2-f6bb-4415-87ce-6a3771ee4d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251114613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.1251114613
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.2123452282
Short name T828
Test name
Test status
Simulation time 277826708 ps
CPU time 11.83 seconds
Started Jul 20 07:20:08 PM PDT 24
Finished Jul 20 07:20:59 PM PDT 24
Peak memory 222268 kb
Host smart-488ff25e-adc6-4485-ae9c-f54b37e3a033
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123452282 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.2123452282
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.3517136236
Short name T584
Test name
Test status
Simulation time 121495693 ps
CPU time 4.06 seconds
Started Jul 20 07:20:08 PM PDT 24
Finished Jul 20 07:20:51 PM PDT 24
Peak memory 207892 kb
Host smart-169bfb59-cf5e-46df-8074-7f0d2830b9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517136236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.3517136236
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.3808712289
Short name T116
Test name
Test status
Simulation time 327783060 ps
CPU time 3.05 seconds
Started Jul 20 07:20:09 PM PDT 24
Finished Jul 20 07:20:51 PM PDT 24
Peak memory 210316 kb
Host smart-ab5941b7-ebc0-46bd-aafa-20ee9e47e2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808712289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.3808712289
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.3653514209
Short name T93
Test name
Test status
Simulation time 108720848 ps
CPU time 0.69 seconds
Started Jul 20 07:15:59 PM PDT 24
Finished Jul 20 07:16:00 PM PDT 24
Peak memory 205860 kb
Host smart-303225ab-2f13-42f5-942a-1a28f07371ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653514209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.3653514209
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.3769357600
Short name T781
Test name
Test status
Simulation time 62724266 ps
CPU time 4.06 seconds
Started Jul 20 07:15:50 PM PDT 24
Finished Jul 20 07:15:55 PM PDT 24
Peak memory 214140 kb
Host smart-82e63f7f-48b7-498e-8f87-f740f90bb91b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3769357600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.3769357600
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.283201553
Short name T192
Test name
Test status
Simulation time 524770804 ps
CPU time 3.66 seconds
Started Jul 20 07:15:57 PM PDT 24
Finished Jul 20 07:16:01 PM PDT 24
Peak memory 215688 kb
Host smart-d50ea76f-0cf9-4f03-b42d-e853dc9303b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283201553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.283201553
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.1484870568
Short name T802
Test name
Test status
Simulation time 84944323 ps
CPU time 1.96 seconds
Started Jul 20 07:15:49 PM PDT 24
Finished Jul 20 07:15:51 PM PDT 24
Peak memory 208132 kb
Host smart-96905a15-fb69-4f5a-8606-94e10fc22a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484870568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.1484870568
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.2130542794
Short name T90
Test name
Test status
Simulation time 186623854 ps
CPU time 4.43 seconds
Started Jul 20 07:15:57 PM PDT 24
Finished Jul 20 07:16:02 PM PDT 24
Peak memory 208784 kb
Host smart-2cce5298-e137-42ba-a279-caee06342f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130542794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.2130542794
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.4090121120
Short name T637
Test name
Test status
Simulation time 211569463 ps
CPU time 3.07 seconds
Started Jul 20 07:15:50 PM PDT 24
Finished Jul 20 07:15:54 PM PDT 24
Peak memory 214076 kb
Host smart-23975ed6-7c2f-4208-bdad-e2681a813c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090121120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.4090121120
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.1893301201
Short name T771
Test name
Test status
Simulation time 1724671473 ps
CPU time 41.43 seconds
Started Jul 20 07:15:52 PM PDT 24
Finished Jul 20 07:16:34 PM PDT 24
Peak memory 208508 kb
Host smart-2e8daa3c-b549-4fdc-a978-12b7f22e7bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893301201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.1893301201
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.1338369756
Short name T10
Test name
Test status
Simulation time 1971899764 ps
CPU time 15.64 seconds
Started Jul 20 07:15:57 PM PDT 24
Finished Jul 20 07:16:14 PM PDT 24
Peak memory 231956 kb
Host smart-7e481b0c-2ae3-478f-abb8-b9b3a922cf3f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338369756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.1338369756
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.3853887990
Short name T509
Test name
Test status
Simulation time 91526260 ps
CPU time 1.97 seconds
Started Jul 20 07:15:48 PM PDT 24
Finished Jul 20 07:15:51 PM PDT 24
Peak memory 208220 kb
Host smart-4074ab05-132d-4eeb-b3df-57c60349b543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853887990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.3853887990
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.30275734
Short name T452
Test name
Test status
Simulation time 71311836 ps
CPU time 3.45 seconds
Started Jul 20 07:15:49 PM PDT 24
Finished Jul 20 07:15:54 PM PDT 24
Peak memory 208752 kb
Host smart-159a0bc7-22f3-4e56-8057-d62e33d4f499
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30275734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.30275734
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.725332606
Short name T587
Test name
Test status
Simulation time 626406413 ps
CPU time 5.2 seconds
Started Jul 20 07:15:48 PM PDT 24
Finished Jul 20 07:15:54 PM PDT 24
Peak memory 208284 kb
Host smart-e0ec7b5a-78e3-45ad-a6af-5f3a5149a715
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725332606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.725332606
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.4083530831
Short name T374
Test name
Test status
Simulation time 169833478 ps
CPU time 2.61 seconds
Started Jul 20 07:15:49 PM PDT 24
Finished Jul 20 07:15:53 PM PDT 24
Peak memory 208224 kb
Host smart-bf6d51d9-51f7-4606-b846-c8be9804efde
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083530831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.4083530831
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.4016311098
Short name T419
Test name
Test status
Simulation time 17111529 ps
CPU time 1.43 seconds
Started Jul 20 07:15:59 PM PDT 24
Finished Jul 20 07:16:01 PM PDT 24
Peak memory 207460 kb
Host smart-2239846f-ef2b-40e3-9e68-6e87c7665599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016311098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.4016311098
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.1834270737
Short name T912
Test name
Test status
Simulation time 1190643929 ps
CPU time 13.84 seconds
Started Jul 20 07:15:52 PM PDT 24
Finished Jul 20 07:16:06 PM PDT 24
Peak memory 208156 kb
Host smart-cc35f9e5-ecba-46c2-8ab0-bc8267a0c846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834270737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.1834270737
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.1687497327
Short name T151
Test name
Test status
Simulation time 203236100 ps
CPU time 13.74 seconds
Started Jul 20 07:15:57 PM PDT 24
Finished Jul 20 07:16:11 PM PDT 24
Peak memory 219916 kb
Host smart-8ba9dac6-506d-4e00-a047-214848dba34d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687497327 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.1687497327
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.3837260458
Short name T769
Test name
Test status
Simulation time 150594231 ps
CPU time 5.35 seconds
Started Jul 20 07:15:50 PM PDT 24
Finished Jul 20 07:15:56 PM PDT 24
Peak memory 209156 kb
Host smart-9fa06b89-ad40-4e55-bcd9-803055dd26c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837260458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.3837260458
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.1420449942
Short name T552
Test name
Test status
Simulation time 100496306 ps
CPU time 2.89 seconds
Started Jul 20 07:15:57 PM PDT 24
Finished Jul 20 07:16:00 PM PDT 24
Peak memory 209972 kb
Host smart-d8548635-cbf5-4491-b41f-531cfd8c08fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420449942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.1420449942
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.3883554659
Short name T92
Test name
Test status
Simulation time 18491389 ps
CPU time 0.76 seconds
Started Jul 20 07:20:26 PM PDT 24
Finished Jul 20 07:20:59 PM PDT 24
Peak memory 205836 kb
Host smart-43b58f2d-9c3b-4c2b-a3d9-d8da943da0a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883554659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.3883554659
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.150199849
Short name T237
Test name
Test status
Simulation time 59873085 ps
CPU time 4.01 seconds
Started Jul 20 07:20:17 PM PDT 24
Finished Jul 20 07:20:57 PM PDT 24
Peak memory 215188 kb
Host smart-8e755059-8499-4df7-8f4c-465e45099602
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=150199849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.150199849
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.2687048074
Short name T478
Test name
Test status
Simulation time 84570792 ps
CPU time 2.74 seconds
Started Jul 20 07:20:18 PM PDT 24
Finished Jul 20 07:20:57 PM PDT 24
Peak memory 218188 kb
Host smart-08679ed1-e84b-46a0-b8ae-85bf660c3583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687048074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.2687048074
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.3802922018
Short name T756
Test name
Test status
Simulation time 219661581 ps
CPU time 5.25 seconds
Started Jul 20 07:20:18 PM PDT 24
Finished Jul 20 07:20:59 PM PDT 24
Peak memory 214148 kb
Host smart-72806314-11f2-42c3-b348-c5c7e709024c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802922018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3802922018
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.2172845176
Short name T222
Test name
Test status
Simulation time 94386189 ps
CPU time 4.45 seconds
Started Jul 20 07:20:18 PM PDT 24
Finished Jul 20 07:20:58 PM PDT 24
Peak memory 214104 kb
Host smart-55cda1ad-7ad4-4944-823a-fb29eb1c29ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172845176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.2172845176
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.3480137004
Short name T225
Test name
Test status
Simulation time 75316590 ps
CPU time 3.71 seconds
Started Jul 20 07:20:19 PM PDT 24
Finished Jul 20 07:20:58 PM PDT 24
Peak memory 218052 kb
Host smart-2a0ec8a6-0ae4-4e95-a047-02b3a6e039b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480137004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3480137004
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.1662267592
Short name T490
Test name
Test status
Simulation time 101142356 ps
CPU time 3.15 seconds
Started Jul 20 07:20:19 PM PDT 24
Finished Jul 20 07:20:58 PM PDT 24
Peak memory 215180 kb
Host smart-3807ce35-0e1b-4ad7-8e02-934a27516964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662267592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.1662267592
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.2603778632
Short name T449
Test name
Test status
Simulation time 64674108 ps
CPU time 3.99 seconds
Started Jul 20 07:20:20 PM PDT 24
Finished Jul 20 07:20:59 PM PDT 24
Peak memory 209648 kb
Host smart-09932494-4e56-491a-aafa-a32c031ddd94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603778632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.2603778632
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.1073732832
Short name T804
Test name
Test status
Simulation time 929095706 ps
CPU time 25.97 seconds
Started Jul 20 07:20:10 PM PDT 24
Finished Jul 20 07:21:14 PM PDT 24
Peak memory 207708 kb
Host smart-006b461d-f2cf-4536-b0f1-b1914914c5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073732832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.1073732832
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.2761927591
Short name T752
Test name
Test status
Simulation time 122298374 ps
CPU time 2.34 seconds
Started Jul 20 07:20:18 PM PDT 24
Finished Jul 20 07:20:56 PM PDT 24
Peak memory 207100 kb
Host smart-42baaf49-2767-4197-a07f-04c97529607f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761927591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2761927591
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.2210837212
Short name T300
Test name
Test status
Simulation time 80113501 ps
CPU time 3.1 seconds
Started Jul 20 07:20:09 PM PDT 24
Finished Jul 20 07:20:51 PM PDT 24
Peak memory 206676 kb
Host smart-155add2c-baa0-4efa-bdb9-04a564c0510f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210837212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.2210837212
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1465261647
Short name T535
Test name
Test status
Simulation time 126261553 ps
CPU time 2.35 seconds
Started Jul 20 07:20:17 PM PDT 24
Finished Jul 20 07:20:56 PM PDT 24
Peak memory 206756 kb
Host smart-9d5f5339-04f2-4f56-90ec-fba2ece3bc5f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465261647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1465261647
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.239620503
Short name T867
Test name
Test status
Simulation time 23493532 ps
CPU time 1.91 seconds
Started Jul 20 07:20:18 PM PDT 24
Finished Jul 20 07:20:56 PM PDT 24
Peak memory 207140 kb
Host smart-cc27a5cd-18f9-44d3-bd6e-0c5d3f2d5c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239620503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.239620503
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.3042390103
Short name T724
Test name
Test status
Simulation time 214569381 ps
CPU time 2.62 seconds
Started Jul 20 07:20:10 PM PDT 24
Finished Jul 20 07:20:51 PM PDT 24
Peak memory 206684 kb
Host smart-8bf6b0aa-943d-4b91-8347-22d8cafcc3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042390103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.3042390103
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.49742028
Short name T64
Test name
Test status
Simulation time 316744715 ps
CPU time 11.53 seconds
Started Jul 20 07:20:25 PM PDT 24
Finished Jul 20 07:21:10 PM PDT 24
Peak memory 220020 kb
Host smart-77487794-aa41-4dfe-a2b4-dad9c9e1a9b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49742028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.49742028
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.3280936745
Short name T435
Test name
Test status
Simulation time 408512792 ps
CPU time 6.4 seconds
Started Jul 20 07:20:18 PM PDT 24
Finished Jul 20 07:21:00 PM PDT 24
Peak memory 207744 kb
Host smart-895844bd-4c1e-46c2-bf33-ec07bd9993e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280936745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.3280936745
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.199247839
Short name T445
Test name
Test status
Simulation time 89984529 ps
CPU time 2.61 seconds
Started Jul 20 07:20:24 PM PDT 24
Finished Jul 20 07:21:00 PM PDT 24
Peak memory 209676 kb
Host smart-8c04e4ef-7a04-40eb-ba83-1b5b6ea95ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199247839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.199247839
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.2885389066
Short name T443
Test name
Test status
Simulation time 38422159 ps
CPU time 0.8 seconds
Started Jul 20 07:20:26 PM PDT 24
Finished Jul 20 07:20:59 PM PDT 24
Peak memory 205888 kb
Host smart-8aebcc48-adc0-4fae-ba08-6f1ddbb326f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885389066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2885389066
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.1499299602
Short name T330
Test name
Test status
Simulation time 27179834 ps
CPU time 1.73 seconds
Started Jul 20 07:20:26 PM PDT 24
Finished Jul 20 07:21:01 PM PDT 24
Peak memory 217944 kb
Host smart-25972f78-e0e6-4ffa-8af5-290652759062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499299602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.1499299602
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.3448923745
Short name T212
Test name
Test status
Simulation time 33581856 ps
CPU time 2.53 seconds
Started Jul 20 07:20:26 PM PDT 24
Finished Jul 20 07:21:02 PM PDT 24
Peak memory 222204 kb
Host smart-5e6ce59e-820a-416a-8cee-fabef726c423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448923745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.3448923745
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.2536225126
Short name T504
Test name
Test status
Simulation time 111741769 ps
CPU time 3.52 seconds
Started Jul 20 07:20:31 PM PDT 24
Finished Jul 20 07:21:04 PM PDT 24
Peak memory 206900 kb
Host smart-7b4326ae-9c39-4554-9729-71da111e7327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536225126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.2536225126
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.1557670675
Short name T298
Test name
Test status
Simulation time 244195401 ps
CPU time 4.22 seconds
Started Jul 20 07:20:26 PM PDT 24
Finished Jul 20 07:21:04 PM PDT 24
Peak memory 209944 kb
Host smart-567a4d77-e034-403c-b6f7-6fbf17e82e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557670675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.1557670675
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.700560802
Short name T324
Test name
Test status
Simulation time 105807384 ps
CPU time 3.81 seconds
Started Jul 20 07:20:24 PM PDT 24
Finished Jul 20 07:21:01 PM PDT 24
Peak memory 208312 kb
Host smart-4a03ce18-190e-46eb-9c18-bfc1e2a95e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700560802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.700560802
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.3409287715
Short name T722
Test name
Test status
Simulation time 712941081 ps
CPU time 4.58 seconds
Started Jul 20 07:20:25 PM PDT 24
Finished Jul 20 07:21:03 PM PDT 24
Peak memory 208284 kb
Host smart-565c47c3-2dc0-46d0-8265-b3e78e5cda7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409287715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.3409287715
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.610688504
Short name T815
Test name
Test status
Simulation time 407526605 ps
CPU time 6.11 seconds
Started Jul 20 07:20:26 PM PDT 24
Finished Jul 20 07:21:06 PM PDT 24
Peak memory 207596 kb
Host smart-c2b2751a-d697-4429-b41a-e7095438fc15
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610688504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.610688504
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.3940149137
Short name T480
Test name
Test status
Simulation time 278397936 ps
CPU time 4.57 seconds
Started Jul 20 07:20:26 PM PDT 24
Finished Jul 20 07:21:04 PM PDT 24
Peak memory 208236 kb
Host smart-20ab9010-150b-42ba-b625-3154b1fa68d0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940149137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3940149137
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.2903458375
Short name T494
Test name
Test status
Simulation time 213680770 ps
CPU time 2.01 seconds
Started Jul 20 07:20:24 PM PDT 24
Finished Jul 20 07:21:00 PM PDT 24
Peak memory 208380 kb
Host smart-d5810f83-0e49-4dc8-9013-987742b4159d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903458375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.2903458375
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.723458897
Short name T4
Test name
Test status
Simulation time 219150553 ps
CPU time 4.84 seconds
Started Jul 20 07:20:25 PM PDT 24
Finished Jul 20 07:21:03 PM PDT 24
Peak memory 214060 kb
Host smart-16f00496-e262-42e5-b7ef-3c5d3a0df299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723458897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.723458897
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.3057557802
Short name T1
Test name
Test status
Simulation time 134693540 ps
CPU time 2.88 seconds
Started Jul 20 07:20:27 PM PDT 24
Finished Jul 20 07:21:02 PM PDT 24
Peak memory 208308 kb
Host smart-e5cac11d-4c43-4df7-8661-4078814ae663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057557802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.3057557802
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.3699181136
Short name T40
Test name
Test status
Simulation time 24055257077 ps
CPU time 52.8 seconds
Started Jul 20 07:20:26 PM PDT 24
Finished Jul 20 07:21:51 PM PDT 24
Peak memory 216476 kb
Host smart-53e32c1d-e9cc-4fa0-a3a1-6d6fd963fb30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699181136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.3699181136
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.1599430041
Short name T657
Test name
Test status
Simulation time 626386825 ps
CPU time 7.54 seconds
Started Jul 20 07:20:25 PM PDT 24
Finished Jul 20 07:21:05 PM PDT 24
Peak memory 208204 kb
Host smart-d1c6b8b3-ca27-4df0-af62-452385f71bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599430041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.1599430041
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.931688655
Short name T356
Test name
Test status
Simulation time 52585673 ps
CPU time 1.45 seconds
Started Jul 20 07:20:27 PM PDT 24
Finished Jul 20 07:21:01 PM PDT 24
Peak memory 209352 kb
Host smart-17fe404c-82c9-435c-990e-44c70cfc499a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931688655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.931688655
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.1121509659
Short name T404
Test name
Test status
Simulation time 11332603 ps
CPU time 0.77 seconds
Started Jul 20 07:20:40 PM PDT 24
Finished Jul 20 07:21:05 PM PDT 24
Peak memory 205860 kb
Host smart-66ce96ce-978e-4eee-b697-6b912937fb03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121509659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1121509659
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.1663113754
Short name T398
Test name
Test status
Simulation time 181508049 ps
CPU time 3.41 seconds
Started Jul 20 07:20:35 PM PDT 24
Finished Jul 20 07:21:05 PM PDT 24
Peak memory 214140 kb
Host smart-7cde6c71-d90d-438a-94cd-b849d1b2fc67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1663113754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1663113754
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.3742103965
Short name T539
Test name
Test status
Simulation time 91880246 ps
CPU time 3.14 seconds
Started Jul 20 07:20:41 PM PDT 24
Finished Jul 20 07:21:08 PM PDT 24
Peak memory 209376 kb
Host smart-f88fdc1c-56b9-450c-b708-8b171b094efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742103965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3742103965
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.1641426852
Short name T692
Test name
Test status
Simulation time 128067666 ps
CPU time 2.41 seconds
Started Jul 20 07:20:33 PM PDT 24
Finished Jul 20 07:21:04 PM PDT 24
Peak memory 214008 kb
Host smart-5ef79e45-2566-4c17-9129-3c19e292a24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641426852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.1641426852
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.2397014990
Short name T401
Test name
Test status
Simulation time 150030758 ps
CPU time 5.71 seconds
Started Jul 20 07:20:41 PM PDT 24
Finished Jul 20 07:21:11 PM PDT 24
Peak memory 214068 kb
Host smart-132948fa-d54c-4b3b-8fc5-d04d5d099a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397014990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.2397014990
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.1494759946
Short name T48
Test name
Test status
Simulation time 33825476 ps
CPU time 2.31 seconds
Started Jul 20 07:20:41 PM PDT 24
Finished Jul 20 07:21:07 PM PDT 24
Peak memory 219380 kb
Host smart-c7b56a25-ce59-4259-adf4-2736ae4eb4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494759946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.1494759946
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.2606826040
Short name T554
Test name
Test status
Simulation time 158942373 ps
CPU time 4.36 seconds
Started Jul 20 07:20:35 PM PDT 24
Finished Jul 20 07:21:07 PM PDT 24
Peak memory 214136 kb
Host smart-9e7c2691-fddc-4b1f-aee6-9a2c6af72102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606826040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.2606826040
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.570403963
Short name T256
Test name
Test status
Simulation time 2161966313 ps
CPU time 23.56 seconds
Started Jul 20 07:20:32 PM PDT 24
Finished Jul 20 07:21:25 PM PDT 24
Peak memory 214208 kb
Host smart-cb4eba4c-7770-4c53-af6a-715d66702562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570403963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.570403963
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.3918259682
Short name T182
Test name
Test status
Simulation time 40041023 ps
CPU time 2.3 seconds
Started Jul 20 07:20:31 PM PDT 24
Finished Jul 20 07:21:03 PM PDT 24
Peak memory 206608 kb
Host smart-5cb3f587-5887-434d-80a7-d0cee4368a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918259682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.3918259682
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3992600713
Short name T496
Test name
Test status
Simulation time 245977562 ps
CPU time 3.29 seconds
Started Jul 20 07:20:32 PM PDT 24
Finished Jul 20 07:21:05 PM PDT 24
Peak memory 207196 kb
Host smart-7e547ad9-4e7c-43fa-911f-22378cd0f535
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992600713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3992600713
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.3233084242
Short name T704
Test name
Test status
Simulation time 58146488 ps
CPU time 3.04 seconds
Started Jul 20 07:20:32 PM PDT 24
Finished Jul 20 07:21:04 PM PDT 24
Peak memory 206660 kb
Host smart-e8dc6b5f-4c45-454f-a4ee-62ae59a9e569
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233084242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.3233084242
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.791300921
Short name T289
Test name
Test status
Simulation time 82826177 ps
CPU time 2.47 seconds
Started Jul 20 07:20:32 PM PDT 24
Finished Jul 20 07:21:04 PM PDT 24
Peak memory 206716 kb
Host smart-b0fc7619-3336-4227-bee3-ef6b644be198
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791300921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.791300921
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.1181831814
Short name T760
Test name
Test status
Simulation time 93297038 ps
CPU time 1.96 seconds
Started Jul 20 07:20:40 PM PDT 24
Finished Jul 20 07:21:07 PM PDT 24
Peak memory 208956 kb
Host smart-f9780317-b62c-485a-8715-8ad8d6b646f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181831814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.1181831814
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.3710938077
Short name T379
Test name
Test status
Simulation time 39749594 ps
CPU time 2.53 seconds
Started Jul 20 07:20:31 PM PDT 24
Finished Jul 20 07:21:04 PM PDT 24
Peak memory 208056 kb
Host smart-e70005e4-b2ce-4c17-ab91-7fb2d6359a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710938077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3710938077
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.4136414047
Short name T198
Test name
Test status
Simulation time 11927854905 ps
CPU time 204.39 seconds
Started Jul 20 07:20:40 PM PDT 24
Finished Jul 20 07:24:29 PM PDT 24
Peak memory 218492 kb
Host smart-fca5162d-58c4-406b-8e61-7165ee29dcc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136414047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.4136414047
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.1674406836
Short name T109
Test name
Test status
Simulation time 1004408536 ps
CPU time 9.09 seconds
Started Jul 20 07:20:40 PM PDT 24
Finished Jul 20 07:21:14 PM PDT 24
Peak memory 218680 kb
Host smart-db826c24-d49e-4804-ad06-3927d544e4db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674406836 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.1674406836
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.3916268623
Short name T774
Test name
Test status
Simulation time 117489650 ps
CPU time 3.68 seconds
Started Jul 20 07:20:36 PM PDT 24
Finished Jul 20 07:21:06 PM PDT 24
Peak memory 206676 kb
Host smart-45f22e0d-3fba-4cb7-be76-03124ca6efa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916268623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.3916268623
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.65797592
Short name T411
Test name
Test status
Simulation time 11524315 ps
CPU time 0.87 seconds
Started Jul 20 07:20:49 PM PDT 24
Finished Jul 20 07:21:08 PM PDT 24
Peak memory 205988 kb
Host smart-e453bd1f-99e6-4974-8b9d-a83df969319f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65797592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.65797592
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.4129427925
Short name T336
Test name
Test status
Simulation time 57749100 ps
CPU time 4.19 seconds
Started Jul 20 07:20:41 PM PDT 24
Finished Jul 20 07:21:09 PM PDT 24
Peak memory 215228 kb
Host smart-032add8c-58f9-4cc4-8a20-b7e67aa432d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4129427925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.4129427925
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.3778951787
Short name T793
Test name
Test status
Simulation time 355165875 ps
CPU time 2.86 seconds
Started Jul 20 07:20:50 PM PDT 24
Finished Jul 20 07:21:11 PM PDT 24
Peak memory 215724 kb
Host smart-17e99085-3083-4463-bc33-6f758e207617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778951787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.3778951787
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.2819531127
Short name T417
Test name
Test status
Simulation time 325686204 ps
CPU time 1.79 seconds
Started Jul 20 07:20:40 PM PDT 24
Finished Jul 20 07:21:06 PM PDT 24
Peak memory 207340 kb
Host smart-64a399dc-e26c-424a-83ad-d19ed2dd136a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819531127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.2819531127
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.2691149950
Short name T87
Test name
Test status
Simulation time 80820066 ps
CPU time 4.47 seconds
Started Jul 20 07:20:50 PM PDT 24
Finished Jul 20 07:21:12 PM PDT 24
Peak memory 222228 kb
Host smart-c123eed4-75c6-4636-8f4b-0a438b39a1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691149950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.2691149950
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.2042046343
Short name T372
Test name
Test status
Simulation time 106628576 ps
CPU time 4.74 seconds
Started Jul 20 07:20:51 PM PDT 24
Finished Jul 20 07:21:13 PM PDT 24
Peak memory 216580 kb
Host smart-aabe1670-7e61-4b99-b146-df4b77a6f06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042046343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.2042046343
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.2184222986
Short name T765
Test name
Test status
Simulation time 71747590 ps
CPU time 2.7 seconds
Started Jul 20 07:20:49 PM PDT 24
Finished Jul 20 07:21:10 PM PDT 24
Peak memory 219800 kb
Host smart-7a260062-6929-445b-864a-bdc8eb10c0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184222986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.2184222986
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.85712512
Short name T750
Test name
Test status
Simulation time 360679901 ps
CPU time 6.9 seconds
Started Jul 20 07:20:40 PM PDT 24
Finished Jul 20 07:21:12 PM PDT 24
Peak memory 209160 kb
Host smart-265ca7c7-72c5-4201-8c44-f6ed6716026b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85712512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.85712512
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.2200880685
Short name T430
Test name
Test status
Simulation time 244271617 ps
CPU time 2.6 seconds
Started Jul 20 07:20:39 PM PDT 24
Finished Jul 20 07:21:07 PM PDT 24
Peak memory 206740 kb
Host smart-18ba9e94-0478-4fc9-9115-ff0b9aa02bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200880685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.2200880685
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.3292854371
Short name T464
Test name
Test status
Simulation time 437720614 ps
CPU time 12.02 seconds
Started Jul 20 07:20:46 PM PDT 24
Finished Jul 20 07:21:18 PM PDT 24
Peak memory 208280 kb
Host smart-f109d5a4-fa22-4f5d-b5d3-813a413e33ca
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292854371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.3292854371
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.2140797212
Short name T530
Test name
Test status
Simulation time 1952457716 ps
CPU time 13.91 seconds
Started Jul 20 07:20:40 PM PDT 24
Finished Jul 20 07:21:19 PM PDT 24
Peak memory 208320 kb
Host smart-253d9e0c-bc36-481f-9761-d5dac7b9c42a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140797212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.2140797212
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.284915627
Short name T619
Test name
Test status
Simulation time 94844262 ps
CPU time 2.64 seconds
Started Jul 20 07:20:40 PM PDT 24
Finished Jul 20 07:21:07 PM PDT 24
Peak memory 206760 kb
Host smart-e60560ec-01d8-4e88-b350-1e40c857bb41
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284915627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.284915627
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.500882932
Short name T410
Test name
Test status
Simulation time 53588028 ps
CPU time 2.35 seconds
Started Jul 20 07:20:50 PM PDT 24
Finished Jul 20 07:21:10 PM PDT 24
Peak memory 207420 kb
Host smart-09f7f970-990f-48fb-9937-91926fcf56ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500882932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.500882932
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.1335169463
Short name T577
Test name
Test status
Simulation time 40746015 ps
CPU time 2.6 seconds
Started Jul 20 07:20:42 PM PDT 24
Finished Jul 20 07:21:08 PM PDT 24
Peak memory 208288 kb
Host smart-51e8264a-e2c9-4a62-bcd1-7898fda72d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335169463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.1335169463
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.2084513033
Short name T206
Test name
Test status
Simulation time 1066131229 ps
CPU time 29.49 seconds
Started Jul 20 07:20:50 PM PDT 24
Finished Jul 20 07:21:37 PM PDT 24
Peak memory 215748 kb
Host smart-d3b0c4f8-6c81-4287-944a-42df6fa2f23c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084513033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.2084513033
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.1767865171
Short name T764
Test name
Test status
Simulation time 1396117091 ps
CPU time 16.74 seconds
Started Jul 20 07:20:49 PM PDT 24
Finished Jul 20 07:21:24 PM PDT 24
Peak memory 222268 kb
Host smart-8a1648f7-8cc0-4fd9-9417-e404247c95fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767865171 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.1767865171
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.2468504193
Short name T763
Test name
Test status
Simulation time 70050011 ps
CPU time 3.51 seconds
Started Jul 20 07:20:48 PM PDT 24
Finished Jul 20 07:21:11 PM PDT 24
Peak memory 207584 kb
Host smart-61efcd41-2ddb-4cd6-a4a4-38c94678a75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468504193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.2468504193
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.2679729614
Short name T56
Test name
Test status
Simulation time 174041676 ps
CPU time 3.91 seconds
Started Jul 20 07:20:49 PM PDT 24
Finished Jul 20 07:21:11 PM PDT 24
Peak memory 210264 kb
Host smart-7108e535-8635-453b-ad95-79317eb889ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679729614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.2679729614
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.1858736708
Short name T833
Test name
Test status
Simulation time 17824639 ps
CPU time 0.72 seconds
Started Jul 20 07:20:56 PM PDT 24
Finished Jul 20 07:21:10 PM PDT 24
Peak memory 205852 kb
Host smart-bf7eb779-6ad3-4c62-bc62-3424402f0e81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858736708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.1858736708
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.3727450734
Short name T879
Test name
Test status
Simulation time 435208511 ps
CPU time 3.58 seconds
Started Jul 20 07:20:55 PM PDT 24
Finished Jul 20 07:21:13 PM PDT 24
Peak memory 221696 kb
Host smart-64bf0766-cf0b-4820-acc3-85f92d19c638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727450734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3727450734
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.2445009385
Short name T728
Test name
Test status
Simulation time 21286775 ps
CPU time 1.7 seconds
Started Jul 20 07:20:57 PM PDT 24
Finished Jul 20 07:21:12 PM PDT 24
Peak memory 207168 kb
Host smart-43db18f6-d8d1-4198-90ba-00dad09b0600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445009385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.2445009385
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.917432399
Short name T332
Test name
Test status
Simulation time 492728621 ps
CPU time 3.12 seconds
Started Jul 20 07:20:56 PM PDT 24
Finished Jul 20 07:21:13 PM PDT 24
Peak memory 214076 kb
Host smart-56449666-5413-4280-82bd-ee79dc332c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917432399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.917432399
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.2938613129
Short name T710
Test name
Test status
Simulation time 311725661 ps
CPU time 4.58 seconds
Started Jul 20 07:20:57 PM PDT 24
Finished Jul 20 07:21:15 PM PDT 24
Peak memory 222168 kb
Host smart-b27de7b0-c744-4d7a-9d18-9d8ed0b01ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938613129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.2938613129
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.1054802746
Short name T831
Test name
Test status
Simulation time 133341284 ps
CPU time 2.95 seconds
Started Jul 20 07:20:59 PM PDT 24
Finished Jul 20 07:21:14 PM PDT 24
Peak memory 218512 kb
Host smart-0901570b-c9cb-4ac9-a3f0-d98c6a0b773a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054802746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.1054802746
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.2638665087
Short name T729
Test name
Test status
Simulation time 943444509 ps
CPU time 10.41 seconds
Started Jul 20 07:20:48 PM PDT 24
Finished Jul 20 07:21:18 PM PDT 24
Peak memory 214016 kb
Host smart-e03d14db-8660-487a-b398-46fc48eecebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638665087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.2638665087
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.220014773
Short name T820
Test name
Test status
Simulation time 348026117 ps
CPU time 4.12 seconds
Started Jul 20 07:20:49 PM PDT 24
Finished Jul 20 07:21:11 PM PDT 24
Peak memory 208288 kb
Host smart-de63c894-c8d7-4983-90be-69c4df95bf0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220014773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.220014773
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1061108449
Short name T562
Test name
Test status
Simulation time 45054694 ps
CPU time 1.98 seconds
Started Jul 20 07:20:51 PM PDT 24
Finished Jul 20 07:21:10 PM PDT 24
Peak memory 208528 kb
Host smart-9cb6b135-c0a1-4ea6-a20e-bd29753b3423
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061108449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1061108449
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.1572409175
Short name T835
Test name
Test status
Simulation time 189269903 ps
CPU time 4.85 seconds
Started Jul 20 07:20:50 PM PDT 24
Finished Jul 20 07:21:13 PM PDT 24
Peak memory 208400 kb
Host smart-5d6e59e0-2c99-4975-b17c-9084b8d51c9f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572409175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.1572409175
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.1714938457
Short name T506
Test name
Test status
Simulation time 30968694 ps
CPU time 2.21 seconds
Started Jul 20 07:20:50 PM PDT 24
Finished Jul 20 07:21:10 PM PDT 24
Peak memory 206708 kb
Host smart-a5676a66-ec6f-4b5e-909c-ac7df65ac7b9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714938457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.1714938457
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.594817589
Short name T483
Test name
Test status
Simulation time 35007833 ps
CPU time 1.64 seconds
Started Jul 20 07:20:58 PM PDT 24
Finished Jul 20 07:21:12 PM PDT 24
Peak memory 207520 kb
Host smart-f246a8a8-d206-4dea-b640-71637e41fc13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594817589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.594817589
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3375062392
Short name T600
Test name
Test status
Simulation time 688466822 ps
CPU time 12.05 seconds
Started Jul 20 07:20:53 PM PDT 24
Finished Jul 20 07:21:21 PM PDT 24
Peak memory 207948 kb
Host smart-17c7f0c4-0e77-4e0e-885f-5e8bb4089896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375062392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3375062392
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.1777636364
Short name T906
Test name
Test status
Simulation time 8961245888 ps
CPU time 72.39 seconds
Started Jul 20 07:21:00 PM PDT 24
Finished Jul 20 07:22:24 PM PDT 24
Peak memory 215704 kb
Host smart-38b6b6da-b92d-4252-ac5d-68301958af5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777636364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.1777636364
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.468302355
Short name T107
Test name
Test status
Simulation time 319960893 ps
CPU time 7.3 seconds
Started Jul 20 07:20:58 PM PDT 24
Finished Jul 20 07:21:18 PM PDT 24
Peak memory 222312 kb
Host smart-0a0418bf-fa69-4f3a-a398-2fe988ea43ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468302355 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.468302355
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.1743782303
Short name T493
Test name
Test status
Simulation time 572190391 ps
CPU time 3.44 seconds
Started Jul 20 07:20:59 PM PDT 24
Finished Jul 20 07:21:15 PM PDT 24
Peak memory 214040 kb
Host smart-ec12da2e-2f5e-4526-84be-18d4a97196db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743782303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.1743782303
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.2410626626
Short name T54
Test name
Test status
Simulation time 230399427 ps
CPU time 2.85 seconds
Started Jul 20 07:20:56 PM PDT 24
Finished Jul 20 07:21:13 PM PDT 24
Peak memory 209536 kb
Host smart-d600b97a-745a-4243-a921-505f9b2c3346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410626626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.2410626626
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.2744471338
Short name T423
Test name
Test status
Simulation time 24079955 ps
CPU time 0.74 seconds
Started Jul 20 07:21:05 PM PDT 24
Finished Jul 20 07:21:14 PM PDT 24
Peak memory 205848 kb
Host smart-41cd94a4-c4fc-4a3d-8c2e-d3e4cabc913c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744471338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2744471338
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.2808124429
Short name T381
Test name
Test status
Simulation time 236140006 ps
CPU time 3.15 seconds
Started Jul 20 07:20:58 PM PDT 24
Finished Jul 20 07:21:14 PM PDT 24
Peak memory 214088 kb
Host smart-87571191-b711-4e0e-b576-650caec6438e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2808124429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.2808124429
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.1922324659
Short name T875
Test name
Test status
Simulation time 302926745 ps
CPU time 4.81 seconds
Started Jul 20 07:21:03 PM PDT 24
Finished Jul 20 07:21:17 PM PDT 24
Peak memory 209364 kb
Host smart-a934088a-17f1-4cd5-8b8f-970252e59027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922324659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.1922324659
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.1001662603
Short name T313
Test name
Test status
Simulation time 382866971 ps
CPU time 4.75 seconds
Started Jul 20 07:20:58 PM PDT 24
Finished Jul 20 07:21:15 PM PDT 24
Peak memory 214076 kb
Host smart-c1d13870-a782-4d7d-a693-c75958e4a523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001662603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.1001662603
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.2560269759
Short name T344
Test name
Test status
Simulation time 972066263 ps
CPU time 2.57 seconds
Started Jul 20 07:20:57 PM PDT 24
Finished Jul 20 07:21:13 PM PDT 24
Peak memory 214056 kb
Host smart-a028dcd3-fd83-4d17-85f0-40a99a4ac89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560269759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.2560269759
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.2668075476
Short name T254
Test name
Test status
Simulation time 76409200 ps
CPU time 2.39 seconds
Started Jul 20 07:20:58 PM PDT 24
Finished Jul 20 07:21:13 PM PDT 24
Peak memory 205840 kb
Host smart-fc7d6842-2467-4240-b47d-e49abfbb0c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668075476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.2668075476
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1802434746
Short name T44
Test name
Test status
Simulation time 108004112 ps
CPU time 2.75 seconds
Started Jul 20 07:21:00 PM PDT 24
Finished Jul 20 07:21:14 PM PDT 24
Peak memory 214132 kb
Host smart-32fe7bc4-63d1-4884-a1b7-1753f73a0fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802434746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1802434746
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.1992886181
Short name T859
Test name
Test status
Simulation time 570513947 ps
CPU time 11.8 seconds
Started Jul 20 07:20:58 PM PDT 24
Finished Jul 20 07:21:23 PM PDT 24
Peak memory 218300 kb
Host smart-651ed2ec-ddf9-4312-b117-a16f21f44701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992886181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.1992886181
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.3031993635
Short name T228
Test name
Test status
Simulation time 59634482 ps
CPU time 2.72 seconds
Started Jul 20 07:21:00 PM PDT 24
Finished Jul 20 07:21:14 PM PDT 24
Peak memory 207188 kb
Host smart-e694cbbb-42fa-4a71-a7f3-ca8b5c801eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031993635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.3031993635
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.232705487
Short name T761
Test name
Test status
Simulation time 69104285 ps
CPU time 3.58 seconds
Started Jul 20 07:20:58 PM PDT 24
Finished Jul 20 07:21:14 PM PDT 24
Peak memory 208308 kb
Host smart-81e62d06-15d1-4ccb-8ac1-aa6f42eced23
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232705487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.232705487
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.1919705937
Short name T485
Test name
Test status
Simulation time 158198792 ps
CPU time 2.23 seconds
Started Jul 20 07:20:58 PM PDT 24
Finished Jul 20 07:21:13 PM PDT 24
Peak memory 206660 kb
Host smart-4a411386-6916-471b-ad46-4b8c7a738be0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919705937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.1919705937
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.3314244447
Short name T413
Test name
Test status
Simulation time 131790639 ps
CPU time 3.54 seconds
Started Jul 20 07:21:03 PM PDT 24
Finished Jul 20 07:21:16 PM PDT 24
Peak memory 207820 kb
Host smart-faf220ef-a2b2-45f0-bda6-d8eb54ab9e4e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314244447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.3314244447
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.1021272724
Short name T113
Test name
Test status
Simulation time 22135158 ps
CPU time 2.05 seconds
Started Jul 20 07:21:06 PM PDT 24
Finished Jul 20 07:21:16 PM PDT 24
Peak memory 215380 kb
Host smart-c113c164-7937-46a4-ae85-9205ea6b20ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021272724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.1021272724
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.499282616
Short name T363
Test name
Test status
Simulation time 48596553 ps
CPU time 1.99 seconds
Started Jul 20 07:20:58 PM PDT 24
Finished Jul 20 07:21:13 PM PDT 24
Peak memory 208484 kb
Host smart-824efa23-ed11-423a-88b0-a4c5ab16db28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499282616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.499282616
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.1974353351
Short name T312
Test name
Test status
Simulation time 335108528 ps
CPU time 15.93 seconds
Started Jul 20 07:21:09 PM PDT 24
Finished Jul 20 07:21:32 PM PDT 24
Peak memory 215956 kb
Host smart-6ba736d4-2958-499a-a500-c9a7f252871a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974353351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.1974353351
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.2782202768
Short name T800
Test name
Test status
Simulation time 925539571 ps
CPU time 18.7 seconds
Started Jul 20 07:21:09 PM PDT 24
Finished Jul 20 07:21:35 PM PDT 24
Peak memory 220328 kb
Host smart-1d218803-df90-4324-8e80-1d78b82c3d94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782202768 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.2782202768
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3026357710
Short name T762
Test name
Test status
Simulation time 779966901 ps
CPU time 5.42 seconds
Started Jul 20 07:20:58 PM PDT 24
Finished Jul 20 07:21:16 PM PDT 24
Peak memory 210244 kb
Host smart-ca317436-44cc-457a-aab5-6055a32fdf1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026357710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3026357710
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.2435292330
Short name T911
Test name
Test status
Simulation time 53257100 ps
CPU time 1.84 seconds
Started Jul 20 07:21:03 PM PDT 24
Finished Jul 20 07:21:15 PM PDT 24
Peak memory 209620 kb
Host smart-6e9bdee9-3058-4918-86dd-e82c059b8217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435292330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.2435292330
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.1143459038
Short name T754
Test name
Test status
Simulation time 14487545 ps
CPU time 0.89 seconds
Started Jul 20 07:21:15 PM PDT 24
Finished Jul 20 07:21:19 PM PDT 24
Peak memory 205924 kb
Host smart-76bd2419-1439-48a4-96e2-8231e835b152
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143459038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.1143459038
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.2791800486
Short name T25
Test name
Test status
Simulation time 357174050 ps
CPU time 3.77 seconds
Started Jul 20 07:21:12 PM PDT 24
Finished Jul 20 07:21:21 PM PDT 24
Peak memory 221260 kb
Host smart-3691dc55-2f01-443b-8c1b-5fb03b82929c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791800486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2791800486
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.2607404217
Short name T421
Test name
Test status
Simulation time 131251344 ps
CPU time 1.92 seconds
Started Jul 20 07:21:14 PM PDT 24
Finished Jul 20 07:21:20 PM PDT 24
Peak memory 206932 kb
Host smart-9a16bd25-946f-4793-9326-67b061250ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607404217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.2607404217
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.228975816
Short name T331
Test name
Test status
Simulation time 1161657156 ps
CPU time 3.16 seconds
Started Jul 20 07:21:12 PM PDT 24
Finished Jul 20 07:21:20 PM PDT 24
Peak memory 214084 kb
Host smart-58075b1f-a8ec-41e0-9d74-94039d5734da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228975816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.228975816
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.4189756353
Short name T568
Test name
Test status
Simulation time 578908934 ps
CPU time 4.99 seconds
Started Jul 20 07:21:15 PM PDT 24
Finished Jul 20 07:21:23 PM PDT 24
Peak memory 214072 kb
Host smart-b07506f9-9b60-4bf3-a026-3573a71fd45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189756353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.4189756353
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.3747260240
Short name T770
Test name
Test status
Simulation time 304875062 ps
CPU time 3.03 seconds
Started Jul 20 07:21:13 PM PDT 24
Finished Jul 20 07:21:20 PM PDT 24
Peak memory 221056 kb
Host smart-d5105249-a978-45f6-9f83-63cd9ded5097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747260240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3747260240
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.3578910994
Short name T284
Test name
Test status
Simulation time 543575318 ps
CPU time 6.42 seconds
Started Jul 20 07:21:05 PM PDT 24
Finished Jul 20 07:21:19 PM PDT 24
Peak memory 209244 kb
Host smart-aa927641-2412-4649-aff4-8cb2b5136262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578910994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.3578910994
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.861457640
Short name T780
Test name
Test status
Simulation time 154440374 ps
CPU time 5.95 seconds
Started Jul 20 07:21:05 PM PDT 24
Finished Jul 20 07:21:19 PM PDT 24
Peak memory 207740 kb
Host smart-e63cc451-e2fc-4822-acbe-d566c6ea5761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861457640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.861457640
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.3791500318
Short name T616
Test name
Test status
Simulation time 832012503 ps
CPU time 6.78 seconds
Started Jul 20 07:21:06 PM PDT 24
Finished Jul 20 07:21:21 PM PDT 24
Peak memory 208544 kb
Host smart-9d8e5a5f-fc2d-4aca-a5f7-e2d762aab0a3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791500318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.3791500318
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.2885216490
Short name T14
Test name
Test status
Simulation time 100596874 ps
CPU time 4.48 seconds
Started Jul 20 07:21:07 PM PDT 24
Finished Jul 20 07:21:19 PM PDT 24
Peak memory 208344 kb
Host smart-b7fd31c3-d2d4-44c3-bea0-94d5c9d29efb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885216490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.2885216490
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.4294739087
Short name T716
Test name
Test status
Simulation time 209466975 ps
CPU time 3.15 seconds
Started Jul 20 07:21:07 PM PDT 24
Finished Jul 20 07:21:18 PM PDT 24
Peak memory 208812 kb
Host smart-8e98d4a8-e448-421f-b104-8517e0e27fd4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294739087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.4294739087
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2682173473
Short name T753
Test name
Test status
Simulation time 459300129 ps
CPU time 3.26 seconds
Started Jul 20 07:21:17 PM PDT 24
Finished Jul 20 07:21:23 PM PDT 24
Peak memory 216020 kb
Host smart-568bad37-cd9b-4b7b-aa50-1e598f1dce34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682173473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2682173473
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.764107872
Short name T486
Test name
Test status
Simulation time 536082678 ps
CPU time 2.4 seconds
Started Jul 20 07:21:04 PM PDT 24
Finished Jul 20 07:21:15 PM PDT 24
Peak memory 206592 kb
Host smart-b2c5a998-aa34-46eb-ac08-e4d3618e465e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764107872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.764107872
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.2978697169
Short name T607
Test name
Test status
Simulation time 488559724 ps
CPU time 17.95 seconds
Started Jul 20 07:21:12 PM PDT 24
Finished Jul 20 07:21:35 PM PDT 24
Peak memory 215104 kb
Host smart-13bc0d2c-3615-4264-aaa2-4001729fe71c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978697169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2978697169
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.2372095790
Short name T118
Test name
Test status
Simulation time 249609691 ps
CPU time 7.04 seconds
Started Jul 20 07:21:12 PM PDT 24
Finished Jul 20 07:21:24 PM PDT 24
Peak memory 208404 kb
Host smart-2f05a391-39de-4fcb-b3e4-01f152c437f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372095790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.2372095790
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.804174074
Short name T354
Test name
Test status
Simulation time 110497370 ps
CPU time 2.74 seconds
Started Jul 20 07:21:10 PM PDT 24
Finished Jul 20 07:21:19 PM PDT 24
Peak memory 209924 kb
Host smart-34317780-cbec-41e6-ad3e-132c784848de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804174074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.804174074
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.228232975
Short name T599
Test name
Test status
Simulation time 23092352 ps
CPU time 0.78 seconds
Started Jul 20 07:21:23 PM PDT 24
Finished Jul 20 07:21:26 PM PDT 24
Peak memory 205832 kb
Host smart-1ae6b6d0-ec4e-4ff7-a807-189b4f9317eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228232975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.228232975
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.2446241526
Short name T396
Test name
Test status
Simulation time 2822252112 ps
CPU time 47.83 seconds
Started Jul 20 07:21:12 PM PDT 24
Finished Jul 20 07:22:05 PM PDT 24
Peak memory 214200 kb
Host smart-9125bcbd-e03b-4b99-b355-463a2d341bca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2446241526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.2446241526
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.3681047937
Short name T252
Test name
Test status
Simulation time 668732026 ps
CPU time 5.34 seconds
Started Jul 20 07:21:15 PM PDT 24
Finished Jul 20 07:21:24 PM PDT 24
Peak memory 209340 kb
Host smart-5ecc5e5b-2a58-4963-8e0a-1eb73826c4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681047937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3681047937
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.3733379472
Short name T82
Test name
Test status
Simulation time 29144175 ps
CPU time 2.02 seconds
Started Jul 20 07:21:22 PM PDT 24
Finished Jul 20 07:21:25 PM PDT 24
Peak memory 214164 kb
Host smart-50d2b5cd-6317-4ab0-a828-0b21a1e0a564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733379472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.3733379472
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.4283595968
Short name T747
Test name
Test status
Simulation time 198860205 ps
CPU time 3.36 seconds
Started Jul 20 07:21:12 PM PDT 24
Finished Jul 20 07:21:20 PM PDT 24
Peak memory 222276 kb
Host smart-a800840e-597c-42a6-8eb3-cbad40582288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283595968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.4283595968
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.3211097468
Short name T227
Test name
Test status
Simulation time 325590182 ps
CPU time 5.83 seconds
Started Jul 20 07:21:12 PM PDT 24
Finished Jul 20 07:21:23 PM PDT 24
Peak memory 218316 kb
Host smart-3ea768f1-bd3c-4037-8064-cee5dec005a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211097468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.3211097468
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.30113973
Short name T432
Test name
Test status
Simulation time 123154922 ps
CPU time 3.13 seconds
Started Jul 20 07:21:14 PM PDT 24
Finished Jul 20 07:21:21 PM PDT 24
Peak memory 208520 kb
Host smart-157b643c-aef5-49b7-9041-ab0f4c5cb651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30113973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.30113973
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.2571296562
Short name T739
Test name
Test status
Simulation time 122676639 ps
CPU time 1.67 seconds
Started Jul 20 07:21:11 PM PDT 24
Finished Jul 20 07:21:18 PM PDT 24
Peak memory 206696 kb
Host smart-73b8ebce-9741-4587-aba3-5e21a29d8db7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571296562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.2571296562
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.2937211825
Short name T683
Test name
Test status
Simulation time 51992833 ps
CPU time 2.56 seconds
Started Jul 20 07:21:14 PM PDT 24
Finished Jul 20 07:21:20 PM PDT 24
Peak memory 206692 kb
Host smart-937693cb-a70b-466c-8c30-975997624405
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937211825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.2937211825
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.2230457260
Short name T738
Test name
Test status
Simulation time 63214235 ps
CPU time 3.44 seconds
Started Jul 20 07:21:17 PM PDT 24
Finished Jul 20 07:21:23 PM PDT 24
Peak memory 208228 kb
Host smart-8badae2f-5de0-4b32-a876-053c81c05f38
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230457260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2230457260
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.1198513903
Short name T531
Test name
Test status
Simulation time 204279116 ps
CPU time 2.84 seconds
Started Jul 20 07:21:22 PM PDT 24
Finished Jul 20 07:21:26 PM PDT 24
Peak memory 208288 kb
Host smart-f1ad8941-1af8-4d24-9e8a-2e9856c107f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198513903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.1198513903
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.2837067762
Short name T825
Test name
Test status
Simulation time 1654935580 ps
CPU time 28.56 seconds
Started Jul 20 07:21:15 PM PDT 24
Finished Jul 20 07:21:47 PM PDT 24
Peak memory 208524 kb
Host smart-b14bc1f8-8fa9-410d-aae6-b293ac3d4342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837067762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.2837067762
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.1406978150
Short name T876
Test name
Test status
Simulation time 3776114069 ps
CPU time 31.16 seconds
Started Jul 20 07:21:21 PM PDT 24
Finished Jul 20 07:21:54 PM PDT 24
Peak memory 215636 kb
Host smart-4f1898ea-527e-4687-9618-0c8ec09d2f82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406978150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.1406978150
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.3714444401
Short name T306
Test name
Test status
Simulation time 341627201 ps
CPU time 4.04 seconds
Started Jul 20 07:21:16 PM PDT 24
Finished Jul 20 07:21:23 PM PDT 24
Peak memory 215512 kb
Host smart-0d90871a-666d-4a1b-87ac-2bb9ee3c57c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714444401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.3714444401
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2540815687
Short name T570
Test name
Test status
Simulation time 84770894 ps
CPU time 2.67 seconds
Started Jul 20 07:21:19 PM PDT 24
Finished Jul 20 07:21:24 PM PDT 24
Peak memory 209592 kb
Host smart-559bca01-b637-47e0-b35c-1e4b78a6e520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540815687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2540815687
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.3318458416
Short name T684
Test name
Test status
Simulation time 69061565 ps
CPU time 0.79 seconds
Started Jul 20 07:21:32 PM PDT 24
Finished Jul 20 07:21:34 PM PDT 24
Peak memory 205852 kb
Host smart-4c1ea7b9-2885-42d5-81e3-d5d98dd3c1fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318458416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.3318458416
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.3578887963
Short name T295
Test name
Test status
Simulation time 404694015 ps
CPU time 22.54 seconds
Started Jul 20 07:21:21 PM PDT 24
Finished Jul 20 07:21:45 PM PDT 24
Peak memory 215388 kb
Host smart-44618598-b4c8-4bbe-9a17-9fc098e80d38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3578887963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.3578887963
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.3469827358
Short name T643
Test name
Test status
Simulation time 99739314 ps
CPU time 4.02 seconds
Started Jul 20 07:21:36 PM PDT 24
Finished Jul 20 07:21:42 PM PDT 24
Peak memory 209604 kb
Host smart-eea97f23-3048-45a4-9141-7e3d3a80fc9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469827358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3469827358
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.266123134
Short name T602
Test name
Test status
Simulation time 50683951 ps
CPU time 2.41 seconds
Started Jul 20 07:21:22 PM PDT 24
Finished Jul 20 07:21:26 PM PDT 24
Peak memory 209864 kb
Host smart-51a98194-155f-49be-9093-cc828e6f7af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266123134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.266123134
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.1751119416
Short name T446
Test name
Test status
Simulation time 79019764 ps
CPU time 2.81 seconds
Started Jul 20 07:21:35 PM PDT 24
Finished Jul 20 07:21:39 PM PDT 24
Peak memory 214076 kb
Host smart-2a3fde2e-0580-47ab-acc8-8400d3fef0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751119416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.1751119416
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.799390566
Short name T461
Test name
Test status
Simulation time 43372182 ps
CPU time 2.36 seconds
Started Jul 20 07:21:33 PM PDT 24
Finished Jul 20 07:21:37 PM PDT 24
Peak memory 219764 kb
Host smart-8feebf96-e599-42b3-9fa1-432628f07375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799390566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.799390566
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.3376137453
Short name T668
Test name
Test status
Simulation time 1354787262 ps
CPU time 10.21 seconds
Started Jul 20 07:21:22 PM PDT 24
Finished Jul 20 07:21:35 PM PDT 24
Peak memory 218400 kb
Host smart-3617eb8f-58d2-41ec-8eb0-ff9c3b7aaa74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376137453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3376137453
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.2557275910
Short name T71
Test name
Test status
Simulation time 215702470 ps
CPU time 2.71 seconds
Started Jul 20 07:21:23 PM PDT 24
Finished Jul 20 07:21:27 PM PDT 24
Peak memory 206704 kb
Host smart-87724b89-ec3b-4835-9826-a97d1d51f6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557275910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.2557275910
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.2870310894
Short name T258
Test name
Test status
Simulation time 373762312 ps
CPU time 7.99 seconds
Started Jul 20 07:21:22 PM PDT 24
Finished Jul 20 07:21:32 PM PDT 24
Peak memory 208656 kb
Host smart-828a7511-996a-4204-a710-53b3feaad5ff
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870310894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.2870310894
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.1335422542
Short name T301
Test name
Test status
Simulation time 168665375 ps
CPU time 4.57 seconds
Started Jul 20 07:21:21 PM PDT 24
Finished Jul 20 07:21:27 PM PDT 24
Peak memory 207788 kb
Host smart-4bba99d7-67f4-4545-98a8-f7f0fbbc6156
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335422542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.1335422542
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.50440216
Short name T586
Test name
Test status
Simulation time 604437294 ps
CPU time 5.35 seconds
Started Jul 20 07:21:23 PM PDT 24
Finished Jul 20 07:21:30 PM PDT 24
Peak memory 208504 kb
Host smart-95402c18-0a6c-4160-a57a-3a5756376e84
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50440216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.50440216
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.3055589301
Short name T663
Test name
Test status
Simulation time 258809609 ps
CPU time 5.22 seconds
Started Jul 20 07:21:33 PM PDT 24
Finished Jul 20 07:21:39 PM PDT 24
Peak memory 209052 kb
Host smart-1a7a319d-4da2-4264-a0f1-f5fbc9839632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055589301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.3055589301
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.4184513124
Short name T830
Test name
Test status
Simulation time 77776793 ps
CPU time 3.13 seconds
Started Jul 20 07:21:23 PM PDT 24
Finished Jul 20 07:21:28 PM PDT 24
Peak memory 208000 kb
Host smart-649e7b84-9a74-4118-92df-f5f0490aa796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184513124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.4184513124
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.3682834899
Short name T67
Test name
Test status
Simulation time 539269336 ps
CPU time 19.18 seconds
Started Jul 20 07:21:37 PM PDT 24
Finished Jul 20 07:21:58 PM PDT 24
Peak memory 215588 kb
Host smart-2d01ce56-0bca-4321-9807-1286956f4327
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682834899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.3682834899
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.4024778846
Short name T917
Test name
Test status
Simulation time 960985216 ps
CPU time 7.01 seconds
Started Jul 20 07:21:37 PM PDT 24
Finished Jul 20 07:21:45 PM PDT 24
Peak memory 222384 kb
Host smart-04ba0bfc-b4be-4c9c-97bb-3f56a96b4bbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024778846 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.4024778846
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.517804844
Short name T342
Test name
Test status
Simulation time 373554727 ps
CPU time 4.31 seconds
Started Jul 20 07:21:33 PM PDT 24
Finished Jul 20 07:21:38 PM PDT 24
Peak memory 214100 kb
Host smart-ca489fe3-f4a7-4cd7-abd6-fbe1ebee2502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517804844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.517804844
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1812792499
Short name T53
Test name
Test status
Simulation time 116349825 ps
CPU time 2.78 seconds
Started Jul 20 07:21:34 PM PDT 24
Finished Jul 20 07:21:38 PM PDT 24
Peak memory 209796 kb
Host smart-4a201ff0-bce9-489f-83ad-5bc61ba61732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812792499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1812792499
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.1240986063
Short name T631
Test name
Test status
Simulation time 106240444 ps
CPU time 0.97 seconds
Started Jul 20 07:21:32 PM PDT 24
Finished Jul 20 07:21:34 PM PDT 24
Peak memory 205916 kb
Host smart-ea0937f7-d711-4999-9b8d-3c4303fd6879
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240986063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.1240986063
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.3323584195
Short name T274
Test name
Test status
Simulation time 51928875 ps
CPU time 3.32 seconds
Started Jul 20 07:21:31 PM PDT 24
Finished Jul 20 07:21:36 PM PDT 24
Peak memory 214068 kb
Host smart-2b816431-7ec2-4711-b9a5-1ace80a11443
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3323584195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3323584195
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.2149932362
Short name T844
Test name
Test status
Simulation time 593851959 ps
CPU time 5.82 seconds
Started Jul 20 07:21:36 PM PDT 24
Finished Jul 20 07:21:44 PM PDT 24
Peak memory 214052 kb
Host smart-88ddf1bf-2385-495a-adbb-e9713bebc4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149932362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.2149932362
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.3385028421
Short name T880
Test name
Test status
Simulation time 107394408 ps
CPU time 2.25 seconds
Started Jul 20 07:21:37 PM PDT 24
Finished Jul 20 07:21:40 PM PDT 24
Peak memory 207852 kb
Host smart-29e7b1ca-9f79-4f34-92ac-5a4cf9f42610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385028421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.3385028421
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.230645648
Short name T214
Test name
Test status
Simulation time 134191473 ps
CPU time 3.61 seconds
Started Jul 20 07:21:32 PM PDT 24
Finished Jul 20 07:21:36 PM PDT 24
Peak memory 214020 kb
Host smart-a12d61eb-4c6e-4ccc-917c-4685e85e9f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230645648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.230645648
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.3381009667
Short name T827
Test name
Test status
Simulation time 575405125 ps
CPU time 3.53 seconds
Started Jul 20 07:21:34 PM PDT 24
Finished Jul 20 07:21:39 PM PDT 24
Peak memory 209508 kb
Host smart-8d75fc8f-0f2c-415d-96de-f2343e63a0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381009667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.3381009667
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.1058217738
Short name T901
Test name
Test status
Simulation time 555073664 ps
CPU time 5.86 seconds
Started Jul 20 07:21:33 PM PDT 24
Finished Jul 20 07:21:40 PM PDT 24
Peak memory 207536 kb
Host smart-afced56f-7763-47ca-8987-44c0c02fb20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058217738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.1058217738
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.2246677172
Short name T711
Test name
Test status
Simulation time 36384238 ps
CPU time 1.79 seconds
Started Jul 20 07:21:40 PM PDT 24
Finished Jul 20 07:21:42 PM PDT 24
Peak memory 206660 kb
Host smart-6b24d4d5-31ba-4f00-839e-41ad04305d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246677172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.2246677172
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.1945235211
Short name T787
Test name
Test status
Simulation time 274311657 ps
CPU time 3.88 seconds
Started Jul 20 07:21:31 PM PDT 24
Finished Jul 20 07:21:36 PM PDT 24
Peak memory 208492 kb
Host smart-71b5f7bc-5ae1-429e-8f7f-cac6449d68d1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945235211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.1945235211
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.1095817267
Short name T865
Test name
Test status
Simulation time 65130740 ps
CPU time 3.3 seconds
Started Jul 20 07:21:37 PM PDT 24
Finished Jul 20 07:21:41 PM PDT 24
Peak memory 207672 kb
Host smart-ff1020fe-256d-4125-8952-c4d3b9c9d0ad
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095817267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.1095817267
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.544696273
Short name T708
Test name
Test status
Simulation time 135441783 ps
CPU time 2.73 seconds
Started Jul 20 07:21:31 PM PDT 24
Finished Jul 20 07:21:35 PM PDT 24
Peak memory 206792 kb
Host smart-d2de56f2-375b-47d4-8168-1402195c1097
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544696273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.544696273
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.1510579935
Short name T805
Test name
Test status
Simulation time 78123248 ps
CPU time 2.67 seconds
Started Jul 20 07:21:35 PM PDT 24
Finished Jul 20 07:21:38 PM PDT 24
Peak memory 208484 kb
Host smart-4ebf0d39-22b8-49a9-9086-394a49a616ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510579935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.1510579935
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.1831636808
Short name T402
Test name
Test status
Simulation time 31289078 ps
CPU time 2.09 seconds
Started Jul 20 07:21:34 PM PDT 24
Finished Jul 20 07:21:37 PM PDT 24
Peak memory 208200 kb
Host smart-b0f303ac-20e3-498a-a4c4-093e9732c34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831636808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.1831636808
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.272110479
Short name T462
Test name
Test status
Simulation time 156239038 ps
CPU time 3.67 seconds
Started Jul 20 07:21:36 PM PDT 24
Finished Jul 20 07:21:41 PM PDT 24
Peak memory 209224 kb
Host smart-873dfe67-4c2f-41b3-9e3c-6d37e2643de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272110479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.272110479
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.3283425314
Short name T592
Test name
Test status
Simulation time 149921007 ps
CPU time 2.34 seconds
Started Jul 20 07:21:33 PM PDT 24
Finished Jul 20 07:21:36 PM PDT 24
Peak memory 209724 kb
Host smart-147c2990-b890-48e3-b621-eb1b3c207b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283425314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.3283425314
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.1876196228
Short name T894
Test name
Test status
Simulation time 13234628 ps
CPU time 0.92 seconds
Started Jul 20 07:16:06 PM PDT 24
Finished Jul 20 07:16:08 PM PDT 24
Peak memory 205816 kb
Host smart-50bf9e79-f90a-4509-96b8-52ed58be838b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876196228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.1876196228
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.676179792
Short name T2
Test name
Test status
Simulation time 183432633 ps
CPU time 3.62 seconds
Started Jul 20 07:16:07 PM PDT 24
Finished Jul 20 07:16:11 PM PDT 24
Peak memory 214084 kb
Host smart-ce313565-44d1-4f77-b60d-da3d451d4a3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=676179792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.676179792
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.2508292817
Short name T579
Test name
Test status
Simulation time 150879160 ps
CPU time 1.69 seconds
Started Jul 20 07:16:07 PM PDT 24
Finished Jul 20 07:16:09 PM PDT 24
Peak memory 207008 kb
Host smart-83af15ef-423d-4f76-9b11-8f5f0e0dd36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508292817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.2508292817
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.2315750202
Short name T697
Test name
Test status
Simulation time 40990126 ps
CPU time 2.4 seconds
Started Jul 20 07:16:08 PM PDT 24
Finished Jul 20 07:16:11 PM PDT 24
Peak memory 214092 kb
Host smart-ff1f0f65-25ef-43ff-8116-be09ac6bcf79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315750202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.2315750202
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.1293212792
Short name T224
Test name
Test status
Simulation time 105986748 ps
CPU time 3.36 seconds
Started Jul 20 07:16:06 PM PDT 24
Finished Jul 20 07:16:10 PM PDT 24
Peak memory 220180 kb
Host smart-832fe6e5-4826-45ea-a56c-ef8deefd71f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293212792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.1293212792
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.2908872249
Short name T466
Test name
Test status
Simulation time 244658101 ps
CPU time 5.17 seconds
Started Jul 20 07:16:08 PM PDT 24
Finished Jul 20 07:16:14 PM PDT 24
Peak memory 215308 kb
Host smart-11857926-6f26-4d2e-a13d-2b24b1ebc057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908872249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.2908872249
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.2605127802
Short name T230
Test name
Test status
Simulation time 526289943 ps
CPU time 7.88 seconds
Started Jul 20 07:16:07 PM PDT 24
Finished Jul 20 07:16:15 PM PDT 24
Peak memory 209648 kb
Host smart-2e7e04d4-2f7a-4af3-8d67-22f45590e8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605127802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.2605127802
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.2849675543
Short name T700
Test name
Test status
Simulation time 2243775821 ps
CPU time 17.26 seconds
Started Jul 20 07:16:00 PM PDT 24
Finished Jul 20 07:16:18 PM PDT 24
Peak memory 208444 kb
Host smart-54353d7b-fb75-42f5-818a-b7031ae332a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849675543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.2849675543
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.2847004801
Short name T758
Test name
Test status
Simulation time 827773104 ps
CPU time 6.06 seconds
Started Jul 20 07:15:57 PM PDT 24
Finished Jul 20 07:16:04 PM PDT 24
Peak memory 207744 kb
Host smart-7d1ca55a-7c13-4184-bbf6-73e9d992c18f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847004801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2847004801
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.664299320
Short name T904
Test name
Test status
Simulation time 251357909 ps
CPU time 2.73 seconds
Started Jul 20 07:15:57 PM PDT 24
Finished Jul 20 07:16:01 PM PDT 24
Peak memory 206660 kb
Host smart-8270e2a8-c90a-4d4b-96a3-e109e651c58c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664299320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.664299320
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.2385241326
Short name T286
Test name
Test status
Simulation time 64348056 ps
CPU time 3.12 seconds
Started Jul 20 07:15:59 PM PDT 24
Finished Jul 20 07:16:02 PM PDT 24
Peak memory 208184 kb
Host smart-0c14b39f-2cfb-4197-a3e2-2de5a7aafac6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385241326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.2385241326
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.1873658816
Short name T497
Test name
Test status
Simulation time 32343512 ps
CPU time 1.62 seconds
Started Jul 20 07:16:07 PM PDT 24
Finished Jul 20 07:16:09 PM PDT 24
Peak memory 208448 kb
Host smart-390f0266-940f-4578-af51-a026898fa121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873658816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1873658816
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.3926634389
Short name T900
Test name
Test status
Simulation time 3503295544 ps
CPU time 4.67 seconds
Started Jul 20 07:15:57 PM PDT 24
Finished Jul 20 07:16:03 PM PDT 24
Peak memory 207908 kb
Host smart-bab23006-0165-4235-a03e-c29eb945382c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926634389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.3926634389
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.1993852478
Short name T271
Test name
Test status
Simulation time 634454476 ps
CPU time 4.89 seconds
Started Jul 20 07:16:08 PM PDT 24
Finished Jul 20 07:16:13 PM PDT 24
Peak memory 209628 kb
Host smart-f99d99d8-3432-44a0-a6b2-f6bb1f2f93be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993852478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.1993852478
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.3346293803
Short name T882
Test name
Test status
Simulation time 1201165756 ps
CPU time 26.44 seconds
Started Jul 20 07:16:06 PM PDT 24
Finished Jul 20 07:16:33 PM PDT 24
Peak memory 219936 kb
Host smart-4e153217-29d5-4605-a37f-1d328c7ec6b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346293803 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.3346293803
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.3354889645
Short name T613
Test name
Test status
Simulation time 152234950 ps
CPU time 3.59 seconds
Started Jul 20 07:16:08 PM PDT 24
Finished Jul 20 07:16:12 PM PDT 24
Peak memory 214076 kb
Host smart-871b4e80-e53c-4d55-88ba-737ccba00e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354889645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.3354889645
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.3505368636
Short name T179
Test name
Test status
Simulation time 97855244 ps
CPU time 2.52 seconds
Started Jul 20 07:16:09 PM PDT 24
Finished Jul 20 07:16:12 PM PDT 24
Peak memory 209980 kb
Host smart-a90c66eb-4616-4ab9-8ae9-9105569fe93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505368636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.3505368636
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.3502277865
Short name T502
Test name
Test status
Simulation time 18137766 ps
CPU time 0.96 seconds
Started Jul 20 07:16:16 PM PDT 24
Finished Jul 20 07:16:18 PM PDT 24
Peak memory 205904 kb
Host smart-25477c2b-e919-4670-b8c4-ca9b290b67c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502277865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.3502277865
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2733357815
Short name T24
Test name
Test status
Simulation time 1393225088 ps
CPU time 3.23 seconds
Started Jul 20 07:16:14 PM PDT 24
Finished Jul 20 07:16:19 PM PDT 24
Peak memory 209308 kb
Host smart-bc57c4cd-6784-45e6-bbe6-0b15544c3cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733357815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2733357815
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.2595568898
Short name T292
Test name
Test status
Simulation time 63871595 ps
CPU time 2.95 seconds
Started Jul 20 07:16:14 PM PDT 24
Finished Jul 20 07:16:18 PM PDT 24
Peak memory 214068 kb
Host smart-cbadcace-86bf-4066-ae7b-418ea70eb333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595568898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.2595568898
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.2659000906
Short name T667
Test name
Test status
Simulation time 165295078 ps
CPU time 1.85 seconds
Started Jul 20 07:16:16 PM PDT 24
Finished Jul 20 07:16:19 PM PDT 24
Peak memory 214072 kb
Host smart-515dccb8-68ba-4365-8fcd-dbb23c14d76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659000906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2659000906
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.4096488213
Short name T47
Test name
Test status
Simulation time 36538939 ps
CPU time 2.83 seconds
Started Jul 20 07:16:13 PM PDT 24
Finished Jul 20 07:16:17 PM PDT 24
Peak memory 209272 kb
Host smart-bd1e8740-28f0-4655-94f2-ee5fe19948f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096488213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.4096488213
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.1802782129
Short name T448
Test name
Test status
Simulation time 141270101 ps
CPU time 2.42 seconds
Started Jul 20 07:16:12 PM PDT 24
Finished Jul 20 07:16:15 PM PDT 24
Peak memory 214644 kb
Host smart-437eb65e-c9ae-4509-9ea0-6cbd2c6d9baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802782129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.1802782129
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.3142139833
Short name T609
Test name
Test status
Simulation time 81870997 ps
CPU time 3.98 seconds
Started Jul 20 07:16:14 PM PDT 24
Finished Jul 20 07:16:19 PM PDT 24
Peak memory 214060 kb
Host smart-70816b07-0fe0-4cfd-826d-d237bf73aa83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142139833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.3142139833
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.989798496
Short name T339
Test name
Test status
Simulation time 175479494 ps
CPU time 4.11 seconds
Started Jul 20 07:16:16 PM PDT 24
Finished Jul 20 07:16:22 PM PDT 24
Peak memory 208252 kb
Host smart-40af261f-1d6c-42af-9854-266a557a8e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989798496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.989798496
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.1019681195
Short name T744
Test name
Test status
Simulation time 221613129 ps
CPU time 6.29 seconds
Started Jul 20 07:16:14 PM PDT 24
Finished Jul 20 07:16:22 PM PDT 24
Peak memory 208616 kb
Host smart-fb35d4d7-417c-4b33-ab3f-d5a068c96e4a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019681195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.1019681195
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.600044145
Short name T733
Test name
Test status
Simulation time 239208353 ps
CPU time 2.97 seconds
Started Jul 20 07:16:13 PM PDT 24
Finished Jul 20 07:16:17 PM PDT 24
Peak memory 208548 kb
Host smart-6fbd3cce-56f0-4c53-b098-c9858daece57
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600044145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.600044145
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.1627220985
Short name T628
Test name
Test status
Simulation time 3016436579 ps
CPU time 7.86 seconds
Started Jul 20 07:16:15 PM PDT 24
Finished Jul 20 07:16:25 PM PDT 24
Peak memory 208468 kb
Host smart-28bb437d-e957-4923-860b-11071ff6fa0e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627220985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.1627220985
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.1163041790
Short name T782
Test name
Test status
Simulation time 137338803 ps
CPU time 4.73 seconds
Started Jul 20 07:16:14 PM PDT 24
Finished Jul 20 07:16:20 PM PDT 24
Peak memory 216052 kb
Host smart-5acbe93e-8ff0-4551-8698-31fb776afbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163041790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.1163041790
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.2665506778
Short name T766
Test name
Test status
Simulation time 105968294 ps
CPU time 2.85 seconds
Started Jul 20 07:16:09 PM PDT 24
Finished Jul 20 07:16:12 PM PDT 24
Peak memory 206476 kb
Host smart-91bcf6fa-a3fc-4674-bf7f-6ef7d88ad5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665506778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2665506778
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.2823812564
Short name T205
Test name
Test status
Simulation time 836082275 ps
CPU time 31.63 seconds
Started Jul 20 07:16:15 PM PDT 24
Finished Jul 20 07:16:48 PM PDT 24
Peak memory 216568 kb
Host smart-2b8645f3-d617-446c-af53-82f0f4e02ce8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823812564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.2823812564
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.744329674
Short name T652
Test name
Test status
Simulation time 450765367 ps
CPU time 5.7 seconds
Started Jul 20 07:16:17 PM PDT 24
Finished Jul 20 07:16:24 PM PDT 24
Peak memory 208104 kb
Host smart-99522861-0286-45b9-b161-4601426762c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744329674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.744329674
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.3517203625
Short name T114
Test name
Test status
Simulation time 120291488 ps
CPU time 2.61 seconds
Started Jul 20 07:16:18 PM PDT 24
Finished Jul 20 07:16:22 PM PDT 24
Peak memory 210072 kb
Host smart-4e789238-f155-4acc-a8c3-bef3918c22ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517203625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3517203625
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.481808081
Short name T868
Test name
Test status
Simulation time 14978993 ps
CPU time 0.73 seconds
Started Jul 20 07:16:25 PM PDT 24
Finished Jul 20 07:16:26 PM PDT 24
Peak memory 205872 kb
Host smart-3458f385-deb1-429b-a1d0-35c04d1210a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481808081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.481808081
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.1413670562
Short name T360
Test name
Test status
Simulation time 47356225 ps
CPU time 3.65 seconds
Started Jul 20 07:16:16 PM PDT 24
Finished Jul 20 07:16:21 PM PDT 24
Peak memory 214060 kb
Host smart-feb0f20e-dbfd-455f-a348-37fc285b3031
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1413670562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.1413670562
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.496162906
Short name T583
Test name
Test status
Simulation time 29387640 ps
CPU time 1.36 seconds
Started Jul 20 07:16:19 PM PDT 24
Finished Jul 20 07:16:21 PM PDT 24
Peak memory 207992 kb
Host smart-85b802bc-4811-4e18-8b2f-6a7ad6c2e907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496162906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.496162906
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.486152935
Short name T43
Test name
Test status
Simulation time 47539143 ps
CPU time 2.16 seconds
Started Jul 20 07:16:15 PM PDT 24
Finished Jul 20 07:16:19 PM PDT 24
Peak memory 214160 kb
Host smart-9e5649b8-5986-4342-bf29-324eb4b80431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486152935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.486152935
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.914950022
Short name T516
Test name
Test status
Simulation time 1082019963 ps
CPU time 4.42 seconds
Started Jul 20 07:16:27 PM PDT 24
Finished Jul 20 07:16:32 PM PDT 24
Peak memory 214032 kb
Host smart-0232057a-0d45-48fa-ae4a-574b22cca1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914950022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.914950022
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.1429349003
Short name T823
Test name
Test status
Simulation time 97614393 ps
CPU time 3.43 seconds
Started Jul 20 07:16:19 PM PDT 24
Finished Jul 20 07:16:23 PM PDT 24
Peak memory 207920 kb
Host smart-58ce3b09-a4a5-46d9-8423-e04d7e9bd885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429349003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.1429349003
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.3741763662
Short name T809
Test name
Test status
Simulation time 81238685 ps
CPU time 4.17 seconds
Started Jul 20 07:16:15 PM PDT 24
Finished Jul 20 07:16:20 PM PDT 24
Peak memory 209560 kb
Host smart-c9142b95-222c-4eb1-9e77-13615a6ee72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741763662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.3741763662
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.3779725850
Short name T848
Test name
Test status
Simulation time 206190591 ps
CPU time 2.7 seconds
Started Jul 20 07:16:17 PM PDT 24
Finished Jul 20 07:16:20 PM PDT 24
Peak memory 206784 kb
Host smart-3b790eee-42fb-4485-be50-7c6909afb053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779725850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.3779725850
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.334441303
Short name T603
Test name
Test status
Simulation time 545327949 ps
CPU time 13.97 seconds
Started Jul 20 07:16:15 PM PDT 24
Finished Jul 20 07:16:30 PM PDT 24
Peak memory 207648 kb
Host smart-5b306d8e-11d4-4bd1-8c6d-69e89ef61924
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334441303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.334441303
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.2936296640
Short name T693
Test name
Test status
Simulation time 218842233 ps
CPU time 4.02 seconds
Started Jul 20 07:16:16 PM PDT 24
Finished Jul 20 07:16:21 PM PDT 24
Peak memory 206600 kb
Host smart-586a11a7-797a-4fbf-8c50-df6f05b771df
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936296640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.2936296640
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.2230293411
Short name T72
Test name
Test status
Simulation time 275007019 ps
CPU time 4.38 seconds
Started Jul 20 07:16:16 PM PDT 24
Finished Jul 20 07:16:22 PM PDT 24
Peak memory 206672 kb
Host smart-3153d74a-5e3a-4ab8-948b-6b546c9300a0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230293411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.2230293411
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.1694142739
Short name T714
Test name
Test status
Simulation time 209558390 ps
CPU time 3.16 seconds
Started Jul 20 07:16:24 PM PDT 24
Finished Jul 20 07:16:28 PM PDT 24
Peak memory 217956 kb
Host smart-b61b68d3-5212-4079-95c3-a04c15a79de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694142739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.1694142739
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.1639407715
Short name T553
Test name
Test status
Simulation time 325881595 ps
CPU time 2.66 seconds
Started Jul 20 07:16:16 PM PDT 24
Finished Jul 20 07:16:19 PM PDT 24
Peak memory 206464 kb
Host smart-427c9456-9781-4b5e-9906-70f3cee41b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639407715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1639407715
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.3299545407
Short name T241
Test name
Test status
Simulation time 1845065021 ps
CPU time 21.9 seconds
Started Jul 20 07:16:22 PM PDT 24
Finished Jul 20 07:16:45 PM PDT 24
Peak memory 216388 kb
Host smart-fa262ead-37a9-45c2-80d5-ef1ac555141a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299545407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.3299545407
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.545474874
Short name T654
Test name
Test status
Simulation time 546237714 ps
CPU time 4.28 seconds
Started Jul 20 07:16:14 PM PDT 24
Finished Jul 20 07:16:19 PM PDT 24
Peak memory 208944 kb
Host smart-1e4dcb4e-23f3-4426-b11b-9fe611796256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545474874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.545474874
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3167297731
Short name T34
Test name
Test status
Simulation time 901697464 ps
CPU time 2.26 seconds
Started Jul 20 07:16:23 PM PDT 24
Finished Jul 20 07:16:26 PM PDT 24
Peak memory 209464 kb
Host smart-284a711c-9104-4d43-9ef2-2b0058e1218f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167297731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3167297731
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.2502916758
Short name T457
Test name
Test status
Simulation time 15067154 ps
CPU time 0.95 seconds
Started Jul 20 07:16:32 PM PDT 24
Finished Jul 20 07:16:34 PM PDT 24
Peak memory 205924 kb
Host smart-2420bd56-06cf-40f6-aa01-610a9698d16e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502916758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.2502916758
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.3307546727
Short name T399
Test name
Test status
Simulation time 92516754 ps
CPU time 3.51 seconds
Started Jul 20 07:16:23 PM PDT 24
Finished Jul 20 07:16:28 PM PDT 24
Peak memory 214044 kb
Host smart-3ca290f0-f3ec-4fa5-8461-f129fa5e86e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3307546727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.3307546727
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.3232579834
Short name T814
Test name
Test status
Simulation time 46129682 ps
CPU time 2.45 seconds
Started Jul 20 07:16:22 PM PDT 24
Finished Jul 20 07:16:25 PM PDT 24
Peak memory 209644 kb
Host smart-811af735-26f6-49e5-924c-68059102f588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232579834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.3232579834
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.1319911586
Short name T477
Test name
Test status
Simulation time 291721240 ps
CPU time 6.47 seconds
Started Jul 20 07:16:23 PM PDT 24
Finished Jul 20 07:16:30 PM PDT 24
Peak memory 220896 kb
Host smart-f254c46f-07a2-4be3-8ed5-8e79200d25a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319911586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1319911586
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.3757323484
Short name T243
Test name
Test status
Simulation time 46582942 ps
CPU time 2.42 seconds
Started Jul 20 07:16:22 PM PDT 24
Finished Jul 20 07:16:26 PM PDT 24
Peak memory 222140 kb
Host smart-ecb41777-93e5-4f96-915f-801498833c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757323484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.3757323484
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.988502309
Short name T598
Test name
Test status
Simulation time 220096889 ps
CPU time 2.72 seconds
Started Jul 20 07:16:23 PM PDT 24
Finished Jul 20 07:16:27 PM PDT 24
Peak memory 222320 kb
Host smart-bc0ce1e9-6302-44df-aa6d-60886fb5b611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988502309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.988502309
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.3650071237
Short name T612
Test name
Test status
Simulation time 150480427 ps
CPU time 5.19 seconds
Started Jul 20 07:16:23 PM PDT 24
Finished Jul 20 07:16:30 PM PDT 24
Peak memory 218064 kb
Host smart-ace17371-957e-4b36-84ed-7780965ce11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650071237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.3650071237
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.2625813417
Short name T857
Test name
Test status
Simulation time 231175473 ps
CPU time 2.84 seconds
Started Jul 20 07:16:22 PM PDT 24
Finished Jul 20 07:16:27 PM PDT 24
Peak memory 208532 kb
Host smart-e6511ab9-01d8-489d-8f3d-80952491bfc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625813417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.2625813417
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.716251340
Short name T188
Test name
Test status
Simulation time 30499959 ps
CPU time 2.22 seconds
Started Jul 20 07:16:22 PM PDT 24
Finished Jul 20 07:16:26 PM PDT 24
Peak memory 207124 kb
Host smart-991de999-4743-4729-99fc-dfad96074d16
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716251340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.716251340
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.807364697
Short name T610
Test name
Test status
Simulation time 4642158634 ps
CPU time 51.12 seconds
Started Jul 20 07:16:22 PM PDT 24
Finished Jul 20 07:17:14 PM PDT 24
Peak memory 208372 kb
Host smart-0f71a917-326b-45be-9e02-f4964367623f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807364697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.807364697
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.176695733
Short name T425
Test name
Test status
Simulation time 116481987 ps
CPU time 4.13 seconds
Started Jul 20 07:16:23 PM PDT 24
Finished Jul 20 07:16:28 PM PDT 24
Peak memory 206784 kb
Host smart-733b3619-d022-42aa-abf0-da1df97ad015
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176695733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.176695733
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.681978091
Short name T74
Test name
Test status
Simulation time 346051190 ps
CPU time 2.37 seconds
Started Jul 20 07:16:27 PM PDT 24
Finished Jul 20 07:16:30 PM PDT 24
Peak memory 209572 kb
Host smart-12e46a87-10ed-4134-a2e7-7b97bb673b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681978091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.681978091
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.1561847387
Short name T520
Test name
Test status
Simulation time 73150070 ps
CPU time 2.15 seconds
Started Jul 20 07:16:23 PM PDT 24
Finished Jul 20 07:16:26 PM PDT 24
Peak memory 206504 kb
Host smart-24b6fdf5-68c5-4f65-ba81-c375d22b2662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561847387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.1561847387
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.3532101986
Short name T335
Test name
Test status
Simulation time 338180169 ps
CPU time 12.05 seconds
Started Jul 20 07:16:37 PM PDT 24
Finished Jul 20 07:16:50 PM PDT 24
Peak memory 220372 kb
Host smart-99bb4fe5-cb24-4b46-8e29-bb346eab8697
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532101986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.3532101986
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.357249203
Short name T383
Test name
Test status
Simulation time 16882065099 ps
CPU time 37.62 seconds
Started Jul 20 07:16:22 PM PDT 24
Finished Jul 20 07:17:01 PM PDT 24
Peak memory 208496 kb
Host smart-41f5aa33-b66c-4f17-88e1-e6eebe8759e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357249203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.357249203
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.1096112576
Short name T898
Test name
Test status
Simulation time 50803720 ps
CPU time 2.89 seconds
Started Jul 20 07:16:22 PM PDT 24
Finished Jul 20 07:16:26 PM PDT 24
Peak memory 210212 kb
Host smart-b0ba0184-f86c-4527-b782-ef7f1e3baf84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096112576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.1096112576
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.2260350985
Short name T412
Test name
Test status
Simulation time 13887960 ps
CPU time 0.74 seconds
Started Jul 20 07:16:36 PM PDT 24
Finished Jul 20 07:16:38 PM PDT 24
Peak memory 205908 kb
Host smart-203cd0f2-3faa-4627-92b3-da9cd118bea2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260350985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.2260350985
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.3947437054
Short name T400
Test name
Test status
Simulation time 34579125 ps
CPU time 2.52 seconds
Started Jul 20 07:16:37 PM PDT 24
Finished Jul 20 07:16:40 PM PDT 24
Peak memory 214056 kb
Host smart-2d94a1b7-f2ac-4135-9cac-97faaea7c28d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3947437054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3947437054
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.2463570103
Short name T730
Test name
Test status
Simulation time 211078078 ps
CPU time 7.95 seconds
Started Jul 20 07:16:37 PM PDT 24
Finished Jul 20 07:16:45 PM PDT 24
Peak memory 219300 kb
Host smart-09ea5ff4-6b7a-4e92-b18d-4fc2f04cefb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463570103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.2463570103
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.878633532
Short name T307
Test name
Test status
Simulation time 157777589 ps
CPU time 2.59 seconds
Started Jul 20 07:16:36 PM PDT 24
Finished Jul 20 07:16:39 PM PDT 24
Peak memory 209536 kb
Host smart-4b44f63d-d54d-40b0-a0cb-540282adef40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878633532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.878633532
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.2222152060
Short name T495
Test name
Test status
Simulation time 61587396 ps
CPU time 2.03 seconds
Started Jul 20 07:16:35 PM PDT 24
Finished Jul 20 07:16:38 PM PDT 24
Peak memory 213976 kb
Host smart-2dcdb6fe-bdd5-463c-bc92-4d94b8504e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222152060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.2222152060
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.3748715502
Short name T842
Test name
Test status
Simulation time 202300222 ps
CPU time 2.83 seconds
Started Jul 20 07:16:37 PM PDT 24
Finished Jul 20 07:16:40 PM PDT 24
Peak memory 221220 kb
Host smart-0c73101c-11ab-484a-9a41-7a02a53f355c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748715502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.3748715502
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.442599027
Short name T527
Test name
Test status
Simulation time 395243184 ps
CPU time 4.74 seconds
Started Jul 20 07:16:32 PM PDT 24
Finished Jul 20 07:16:38 PM PDT 24
Peak memory 208048 kb
Host smart-db2aa97d-afda-49f2-bbdb-351210eabb93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442599027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.442599027
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.58335571
Short name T422
Test name
Test status
Simulation time 52397152 ps
CPU time 2.68 seconds
Started Jul 20 07:16:33 PM PDT 24
Finished Jul 20 07:16:36 PM PDT 24
Peak memory 206628 kb
Host smart-551a7941-49f3-455d-b74f-a89b574c849d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58335571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.58335571
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.3732580047
Short name T656
Test name
Test status
Simulation time 400781087 ps
CPU time 4.06 seconds
Started Jul 20 07:16:35 PM PDT 24
Finished Jul 20 07:16:40 PM PDT 24
Peak memory 208828 kb
Host smart-cbec4ed1-6091-4075-8cc3-917c1dab94d5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732580047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.3732580047
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.2736038944
Short name T642
Test name
Test status
Simulation time 431173809 ps
CPU time 3.52 seconds
Started Jul 20 07:16:34 PM PDT 24
Finished Jul 20 07:16:38 PM PDT 24
Peak memory 208444 kb
Host smart-c0d64c8b-99f9-4e67-a63b-3dc7298f111a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736038944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2736038944
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.2320540137
Short name T326
Test name
Test status
Simulation time 314153739 ps
CPU time 3.07 seconds
Started Jul 20 07:16:34 PM PDT 24
Finished Jul 20 07:16:38 PM PDT 24
Peak memory 206856 kb
Host smart-a3c62292-097c-481e-9098-3bce2094dadb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320540137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.2320540137
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_smoke.3719136263
Short name T185
Test name
Test status
Simulation time 2846943369 ps
CPU time 16.61 seconds
Started Jul 20 07:16:35 PM PDT 24
Finished Jul 20 07:16:52 PM PDT 24
Peak memory 208504 kb
Host smart-870db954-3fec-41e6-b460-48730961dfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719136263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.3719136263
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.3988585347
Short name T302
Test name
Test status
Simulation time 2975782268 ps
CPU time 26.72 seconds
Started Jul 20 07:16:35 PM PDT 24
Finished Jul 20 07:17:03 PM PDT 24
Peak memory 216204 kb
Host smart-88bfe200-569c-48e1-8272-3ee5e7e04287
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988585347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.3988585347
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.3352980197
Short name T660
Test name
Test status
Simulation time 1122992113 ps
CPU time 11.47 seconds
Started Jul 20 07:16:33 PM PDT 24
Finished Jul 20 07:16:46 PM PDT 24
Peak memory 222364 kb
Host smart-97a07aff-cf62-4128-8ac5-760de76b42b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352980197 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.3352980197
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.3886028084
Short name T909
Test name
Test status
Simulation time 1549029947 ps
CPU time 11.08 seconds
Started Jul 20 07:16:36 PM PDT 24
Finished Jul 20 07:16:48 PM PDT 24
Peak memory 208884 kb
Host smart-ea294caf-f258-4b39-9412-d8c24775ccf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886028084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.3886028084
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.2028886258
Short name T350
Test name
Test status
Simulation time 40526793 ps
CPU time 2.03 seconds
Started Jul 20 07:16:36 PM PDT 24
Finished Jul 20 07:16:39 PM PDT 24
Peak memory 209704 kb
Host smart-4e0408f3-4399-4d66-aebc-3b42474f6c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028886258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.2028886258
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%