Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
73.02	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	16	33	67.35

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	15	20	57.14	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	49	1			T51	1		T52	1		T53	1
auto[OpGenId]	15	1			T58	1		T101	1		T54	1
auto[OpGenSwOut]	22	1			T101	1		T217	1		T158	1
auto[OpGenHwOut]	29	1			T21	1		T7	1		T62	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1665	1			T5	1		T6	2		T31	1
auto[StInit]	92	1			T55	1		T58	1		T41	1
auto[StCreatorRootKey]	63	1			T6	1		T45	1		T62	1
auto[StOwnerIntKey]	52	1			T31	2		T22	1		T9	1
auto[StOwnerKey]	25	1			T70	1		T53	1		T32	1
auto[StDisabled]	419	1			T6	2		T55	4		T30	3
auto[StInvalid]	48	1			T20	1		T42	1		T43	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3330

1

T1

1

T2

1

T3

1

auto[1]

115

1

T58

1

T21

1

T51

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1662	1			T5	1		T6	2		T31	1
auto[StReset]	auto[1]	3	1			T21	1		T218	1		T57	1
auto[StInit]	auto[0]	41	1			T55	1		T41	1		T59	1
auto[StInit]	auto[1]	51	1			T58	1		T51	1		T101	2
auto[StCreatorRootKey]	auto[0]	34	1			T6	1		T45	1		T54	1
auto[StCreatorRootKey]	auto[1]	29	1			T62	1		T8	1		T54	3
auto[StOwnerIntKey]	auto[0]	34	1			T31	2		T22	1		T66	1
auto[StOwnerIntKey]	auto[1]	18	1			T9	1		T67	1		T219	1
auto[StOwnerKey]	auto[0]	21	1			T70	1		T77	1		T37	1
auto[StOwnerKey]	auto[1]	4	1			T53	1		T32	1		T73	1
auto[StDisabled]	auto[0]	409	1			T6	2		T55	4		T30	3
auto[StDisabled]	auto[1]	10	1			T74	1		T220	1		T221	1
auto[StInvalid]	auto[0]	48	1			T20	1		T42	1		T43	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	15	20	57.14	15

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId] , auto[OpGenSwOut]]	--	--	2
[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey]]	[auto[OpDisable]]	--	--	3
[auto[StOwnerKey]]	[auto[OpGenId] , auto[OpGenSwOut]]	--	--	2
[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[StDisabled]]	[auto[OpDisable]]	0	1	1

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	2	1			T218	1		T57	1		-	-
auto[StReset]	auto[OpGenHwOut]	1	1			T21	1		-	-		-	-
auto[StInit]	auto[OpAdvance]	19	1			T51	1		T52	1		T54	1
auto[StInit]	auto[OpGenId]	6	1			T58	1		T101	1		T73	1
auto[StInit]	auto[OpGenSwOut]	16	1			T101	1		T217	1		T158	1
auto[StInit]	auto[OpGenHwOut]	10	1			T7	1		T54	1		T217	1
auto[StCreatorRootKey]	auto[OpAdvance]	13	1			T54	2		T103	1		T222	1
auto[StCreatorRootKey]	auto[OpGenId]	4	1			T54	1		T223	1		T224	1
auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T225	1		T226	1		T227	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	8	1			T62	1		T8	1		T228	1
auto[StOwnerIntKey]	auto[OpAdvance]	10	1			T9	1		T67	1		T229	1
auto[StOwnerIntKey]	auto[OpGenId]	1	1			T230	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpGenSwOut]	1	1			T231	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpGenHwOut]	6	1			T219	1		T81	1		T232	1
auto[StOwnerKey]	auto[OpAdvance]	1	1			T53	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	3	1			T32	1		T73	1		T233	1
auto[StDisabled]	auto[OpAdvance]	4	1			T221	1		T234	1		T235	1
auto[StDisabled]	auto[OpGenId]	4	1			T220	1		T232	1		T236	1
auto[StDisabled]	auto[OpGenSwOut]	1	1			T84	1		-	-		-	-
auto[StDisabled]	auto[OpGenHwOut]	1	1			T74	1		-	-		-	-