Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10849

1

T2

11

T3

4

T4

5

auto[Attestation]

7358

1

T2

2

T3

5

T4

3

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2726	1			T3	2		T5	1		T6	6
auto[Aes]	3292	1			T3	2		T18	8		T5	2
auto[Kmac]	3268	1			T2	13		T3	1		T4	8
auto[Otbn]	3229	1			T3	3		T5	3		T39	8

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7437	1			T2	8		T3	3		T4	8
auto[OpGenId]	5692	1			T3	1		T16	1		T5	9
auto[OpGenSwOut]	5824	1			T3	2		T5	2		T6	9
auto[OpGenHwOut]	6691	1			T2	13		T3	6		T4	8
auto[OpDisable]	129	1			T6	1		T55	1		T56	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10376

1

T2

8

T3

12

T4

8

auto[OpDoneFail]

15397

1

T2

13

T4

8

T16

2

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6305	1			T2	6		T3	1		T4	1
auto[StInit]	3592	1			T2	2		T3	1		T4	2
auto[StCreatorRootKey]	3159	1			T2	2		T3	2		T4	2
auto[StOwnerIntKey]	2648	1			T2	2		T3	8		T4	2
auto[StOwnerKey]	2420	1			T2	2		T4	2		T17	2
auto[StDisabled]	7649	1			T2	7		T4	7		T17	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	341	1			T6	1		T29	4		T129	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	105	1			T55	1		T58	1		T31	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	84	1			T134	1		T62	1		T206	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	83	1			T3	1		T134	1		T135	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	64	1			T29	1		T85	1		T206	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	225	1			T6	1		T30	1		T131	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	324	1			T56	2		T85	1		T30	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	94	1			T29	1		T127	1		T55	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	82	1			T25	1		T30	1		T45	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	65	1			T85	1		T69	1		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	59	1			T132	1		T60	2		T101	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	210	1			T29	2		T30	1		T60	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	338	1			T6	1		T129	2		T56	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	96	1			T25	2		T43	1		T61	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	89	1			T87	1		T30	1		T31	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	75	1			T129	1		T132	1		T60	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	59	1			T55	1		T30	1		T101	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	212	1			T127	3		T55	1		T129	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	313	1			T56	1		T25	1		T30	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	94	1			T25	1		T31	1		T60	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	90	1			T127	1		T56	1		T31	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	64	1			T6	1		T31	1		T131	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	62	1			T85	1		T131	1		T60	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	207	1			T30	2		T61	1		T101	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	69	1			T55	1		T60	3		T101	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	98	1			T6	1		T128	1		T60	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	85	1			T29	1		T129	1		T31	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	70	1			T62	1		T79	1		T22	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	78	1			T129	1		T133	2		T70	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	191	1			T122	1		T129	1		T199	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	85	1			T55	1		T30	3		T60	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	105	1			T31	2		T62	1		T207	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	84	1			T55	2		T30	1		T31	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	50	1			T101	1		T69	1		T208	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	75	1			T55	1		T131	1		T206	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	203	1			T122	1		T55	1		T128	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	73	1			T6	1		T55	3		T30	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	92	1			T6	1		T127	1		T55	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	67	1			T132	1		T133	1		T60	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	69	1			T87	1		T60	2		T135	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	53	1			T122	1		T154	1		T207	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	202	1			T5	1		T55	1		T87	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	65	1			T6	1		T30	1		T60	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	114	1			T198	1		T199	1		T131	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	93	1			T199	1		T133	1		T60	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	67	1			T3	1		T30	2		T89	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	76	1			T30	1		T199	1		T60	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	225	1			T5	1		T6	1		T127	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	319	1			T6	1		T29	2		T85	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	97	1			T31	1		T134	1		T209	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	80	1			T61	1		T60	1		T70	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	58	1			T89	1		T60	2		T70	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	49	1			T89	1		T60	1		T154	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	170	1			T5	1		T29	2		T55	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	413	1			T6	2		T29	2		T90	4
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	118	1			T18	1		T210	1		T56	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	103	1			T90	1		T60	1		T26	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	90	1			T3	1		T6	1		T90	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	86	1			T18	1		T40	1		T90	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	285	1			T18	2		T40	1		T29	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	488	1			T2	5		T16	1		T17	4
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	112	1			T2	1		T17	1		T41	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	103	1			T2	1		T4	1		T45	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	88	1			T2	1		T3	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	86	1			T2	1		T101	1		T211	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	250	1			T2	2		T4	3		T17	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	377	1			T6	1		T29	1		T56	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	108	1			T29	1		T111	1		T212	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	121	1			T29	1		T123	1		T133	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	94	1			T3	1		T5	1		T39	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	76	1			T39	1		T111	1		T85	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	275	1			T39	2		T111	2		T123	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	59	1			T6	1		T62	1		T54	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	78	1			T6	1		T127	1		T85	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	63	1			T60	2		T152	1		T206	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	56	1			T3	1		T199	1		T131	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	46	1			T101	2		T136	1		T77	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	158	1			T127	1		T31	1		T135	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	56	1			T6	1		T60	1		T62	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	122	1			T40	1		T6	1		T90	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	128	1			T18	1		T40	1		T210	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	103	1			T3	1		T18	1		T40	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	89	1			T5	1		T6	1		T29	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	263	1			T18	2		T5	1		T40	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	57	1			T6	2		T55	1		T60	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	109	1			T4	1		T6	1		T88	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	98	1			T17	1		T6	1		T29	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	89	1			T88	1		T134	2		T101	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	85	1			T4	1		T17	1		T87	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	278	1			T2	2		T4	1		T17	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	61	1			T6	2		T55	1		T54	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	124	1			T39	1		T6	1		T55	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	112	1			T39	1		T6	1		T111	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	93	1			T3	1		T111	1		T212	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	84	1			T123	1		T25	1		T212	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	234	1			T5	1		T39	2		T111	2

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	215	1			T3	1		T29	1		T85	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	687	1			T6	2		T29	4		T55	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	196	1			T85	1		T25	1		T30	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	638	1			T29	3		T127	1		T55	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	206	1			T55	1		T129	1		T87	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	663	1			T6	1		T127	3		T55	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	203	1			T6	1		T127	1		T56	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	627	1			T56	1		T25	2		T30	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	218	1			T29	1		T129	2		T31	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	373	1			T6	1		T122	1		T55	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	186	1			T55	3		T30	1		T31	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	416	1			T122	1		T55	2		T128	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	177	1			T122	1		T87	1		T132	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	379	1			T5	1		T6	2		T127	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	220	1			T3	1		T30	3		T89	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	420	1			T5	1		T6	2		T127	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	169	1			T89	2		T61	1		T60	4
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	604	1			T5	1		T6	1		T29	4
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	266	1			T3	1		T18	1		T40	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	829	1			T18	3		T40	1		T6	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	262	1			T2	3		T3	1		T4	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	865	1			T2	8		T4	3		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	268	1			T3	1		T5	1		T39	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	783	1			T39	2		T6	1		T29	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	152	1			T3	1		T199	1		T131	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	308	1			T6	2		T127	2		T85	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	305	1			T3	1		T18	2		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	456	1			T18	2		T5	1		T40	4
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	262	1			T4	1		T17	2		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	454	1			T2	2		T4	2		T17	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	273	1			T3	1		T39	1		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	435	1			T5	1		T39	3		T6	3