Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31783

1

T2

26

T3

15

T4

20

auto[1]

310

1

T131

10

T151

4

T152

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	31790	1			T2	26		T3	15		T4	20
auto[134217728:268435455]	9	1			T137	1		T139	1		T336	1
auto[268435456:402653183]	8	1			T131	2		T141	2		T273	1
auto[402653184:536870911]	11	1			T154	1		T241	1		T374	1
auto[536870912:671088639]	10	1			T153	1		T296	1		T249	1
auto[671088640:805306367]	12	1			T151	2		T154	1		T137	1
auto[805306368:939524095]	11	1			T237	1		T374	1		T273	1
auto[939524096:1073741823]	14	1			T131	1		T151	1		T153	1
auto[1073741824:1207959551]	10	1			T249	1		T237	1		T273	1
auto[1207959552:1342177279]	7	1			T131	1		T153	1		T273	1
auto[1342177280:1476395007]	10	1			T131	1		T154	1		T139	1
auto[1476395008:1610612735]	9	1			T138	1		T297	1		T404	1
auto[1610612736:1744830463]	12	1			T153	1		T155	1		T139	1
auto[1744830464:1879048191]	12	1			T138	1		T139	1		T273	1
auto[1879048192:2013265919]	7	1			T138	1		T237	1		T139	1
auto[2013265920:2147483647]	12	1			T131	1		T155	1		T249	2
auto[2147483648:2281701375]	11	1			T131	1		T152	1		T141	1
auto[2281701376:2415919103]	10	1			T131	1		T154	2		T336	1
auto[2415919104:2550136831]	9	1			T154	1		T404	1		T405	1
auto[2550136832:2684354559]	10	1			T155	1		T136	1		T336	1
auto[2684354560:2818572287]	12	1			T151	1		T152	1		T153	1
auto[2818572288:2952790015]	14	1			T131	1		T152	1		T336	3
auto[2952790016:3087007743]	15	1			T153	1		T155	1		T296	1
auto[3087007744:3221225471]	8	1			T154	1		T296	2		T249	1
auto[3221225472:3355443199]	7	1			T237	1		T297	1		T285	1
auto[3355443200:3489660927]	6	1			T137	1		T296	1		T273	1
auto[3489660928:3623878655]	9	1			T137	1		T141	1		T242	1
auto[3623878656:3758096383]	10	1			T152	1		T249	1		T297	1
auto[3758096384:3892314111]	4	1			T131	1		T243	1		T285	1
auto[3892314112:4026531839]	10	1			T154	1		T273	1		T404	1
auto[4026531840:4160749567]	7	1			T138	1		T139	2		T391	1
auto[4160749568:4294967295]	7	1			T154	1		T136	1		T296	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	31783	1			T2	26		T3	15		T4	20
auto[0:134217727]	auto[1]	7	1			T141	1		T242	1		T243	1
auto[134217728:268435455]	auto[1]	9	1			T137	1		T139	1		T336	1
auto[268435456:402653183]	auto[1]	8	1			T131	2		T141	2		T273	1
auto[402653184:536870911]	auto[1]	11	1			T154	1		T241	1		T374	1
auto[536870912:671088639]	auto[1]	10	1			T153	1		T296	1		T249	1
auto[671088640:805306367]	auto[1]	12	1			T151	2		T154	1		T137	1
auto[805306368:939524095]	auto[1]	11	1			T237	1		T374	1		T273	1
auto[939524096:1073741823]	auto[1]	14	1			T131	1		T151	1		T153	1
auto[1073741824:1207959551]	auto[1]	10	1			T249	1		T237	1		T273	1
auto[1207959552:1342177279]	auto[1]	7	1			T131	1		T153	1		T273	1
auto[1342177280:1476395007]	auto[1]	10	1			T131	1		T154	1		T139	1
auto[1476395008:1610612735]	auto[1]	9	1			T138	1		T297	1		T404	1
auto[1610612736:1744830463]	auto[1]	12	1			T153	1		T155	1		T139	1
auto[1744830464:1879048191]	auto[1]	12	1			T138	1		T139	1		T273	1
auto[1879048192:2013265919]	auto[1]	7	1			T138	1		T237	1		T139	1
auto[2013265920:2147483647]	auto[1]	12	1			T131	1		T155	1		T249	2
auto[2147483648:2281701375]	auto[1]	11	1			T131	1		T152	1		T141	1
auto[2281701376:2415919103]	auto[1]	10	1			T131	1		T154	2		T336	1
auto[2415919104:2550136831]	auto[1]	9	1			T154	1		T404	1		T405	1
auto[2550136832:2684354559]	auto[1]	10	1			T155	1		T136	1		T336	1
auto[2684354560:2818572287]	auto[1]	12	1			T151	1		T152	1		T153	1
auto[2818572288:2952790015]	auto[1]	14	1			T131	1		T152	1		T336	3
auto[2952790016:3087007743]	auto[1]	15	1			T153	1		T155	1		T296	1
auto[3087007744:3221225471]	auto[1]	8	1			T154	1		T296	2		T249	1
auto[3221225472:3355443199]	auto[1]	7	1			T237	1		T297	1		T285	1
auto[3355443200:3489660927]	auto[1]	6	1			T137	1		T296	1		T273	1
auto[3489660928:3623878655]	auto[1]	9	1			T137	1		T141	1		T242	1
auto[3623878656:3758096383]	auto[1]	10	1			T152	1		T249	1		T297	1
auto[3758096384:3892314111]	auto[1]	4	1			T131	1		T243	1		T285	1
auto[3892314112:4026531839]	auto[1]	10	1			T154	1		T273	1		T404	1
auto[4026531840:4160749567]	auto[1]	7	1			T138	1		T139	2		T391	1
auto[4160749568:4294967295]	auto[1]	7	1			T154	1		T136	1		T296	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1545

1

T5

2

T6

8

T29

1

auto[1]

1727

1

T3

2

T16

2

T5

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	100	1			T29	1		T58	1		T59	1
auto[134217728:268435455]	110	1			T58	1		T30	1		T60	1
auto[268435456:402653183]	90	1			T199	2		T101	1		T151	1
auto[402653184:536870911]	105	1			T44	1		T89	1		T31	1
auto[536870912:671088639]	113	1			T58	1		T86	2		T60	1
auto[671088640:805306367]	124	1			T127	1		T55	1		T56	1
auto[805306368:939524095]	89	1			T16	1		T29	1		T60	1
auto[939524096:1073741823]	97	1			T59	1		T31	2		T52	1
auto[1073741824:1207959551]	97	1			T6	1		T30	1		T31	1
auto[1207959552:1342177279]	101	1			T5	2		T42	1		T7	1
auto[1342177280:1476395007]	96	1			T6	1		T30	1		T42	1
auto[1476395008:1610612735]	121	1			T44	1		T25	1		T59	1
auto[1610612736:1744830463]	86	1			T29	1		T131	1		T51	1
auto[1744830464:1879048191]	105	1			T3	1		T20	1		T6	2
auto[1879048192:2013265919]	111	1			T55	1		T30	1		T131	1
auto[2013265920:2147483647]	106	1			T6	1		T55	1		T61	1
auto[2147483648:2281701375]	101	1			T56	1		T25	1		T42	1
auto[2281701376:2415919103]	107	1			T89	1		T31	1		T134	1
auto[2415919104:2550136831]	92	1			T6	1		T127	1		T101	1
auto[2550136832:2684354559]	108	1			T16	1		T55	1		T58	1
auto[2684354560:2818572287]	110	1			T55	1		T86	1		T60	1
auto[2818572288:2952790015]	86	1			T56	1		T30	1		T101	1
auto[2952790016:3087007743]	117	1			T31	1		T43	1		T199	1
auto[3087007744:3221225471]	101	1			T6	1		T55	1		T85	1
auto[3221225472:3355443199]	94	1			T3	1		T6	1		T25	1
auto[3355443200:3489660927]	122	1			T5	1		T58	1		T101	2
auto[3489660928:3623878655]	97	1			T127	1		T44	1		T25	1
auto[3623878656:3758096383]	82	1			T29	1		T30	1		T89	1
auto[3758096384:3892314111]	93	1			T86	1		T60	2		T51	1
auto[3892314112:4026531839]	112	1			T29	1		T58	1		T25	1
auto[4026531840:4160749567]	100	1			T5	1		T6	1		T58	1
auto[4160749568:4294967295]	99	1			T6	1		T56	1		T25	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	49	1			T58	1		T59	1		T101	1
auto[0:134217727]	auto[1]	51	1			T29	1		T42	1		T60	1
auto[134217728:268435455]	auto[0]	51	1			T58	1		T60	1		T264	1
auto[134217728:268435455]	auto[1]	59	1			T30	1		T135	1		T93	1
auto[268435456:402653183]	auto[0]	44	1			T199	1		T101	1		T151	1
auto[268435456:402653183]	auto[1]	46	1			T199	1		T54	2		T302	1
auto[402653184:536870911]	auto[0]	48	1			T31	1		T101	1		T52	1
auto[402653184:536870911]	auto[1]	57	1			T44	1		T89	1		T135	1
auto[536870912:671088639]	auto[0]	60	1			T58	1		T86	2		T60	1
auto[536870912:671088639]	auto[1]	53	1			T101	2		T26	1		T54	1
auto[671088640:805306367]	auto[0]	64	1			T55	1		T56	1		T60	2
auto[671088640:805306367]	auto[1]	60	1			T127	1		T89	1		T31	1
auto[805306368:939524095]	auto[0]	48	1			T60	1		T101	1		T264	1
auto[805306368:939524095]	auto[1]	41	1			T16	1		T29	1		T135	1
auto[939524096:1073741823]	auto[0]	30	1			T31	1		T52	1		T54	1
auto[939524096:1073741823]	auto[1]	67	1			T59	1		T31	1		T27	1
auto[1073741824:1207959551]	auto[0]	38	1			T6	1		T60	1		T79	1
auto[1073741824:1207959551]	auto[1]	59	1			T30	1		T31	1		T135	1
auto[1207959552:1342177279]	auto[0]	49	1			T5	1		T7	1		T152	1
auto[1207959552:1342177279]	auto[1]	52	1			T5	1		T42	1		T103	1
auto[1342177280:1476395007]	auto[0]	48	1			T6	1		T30	1		T42	1
auto[1342177280:1476395007]	auto[1]	48	1			T101	1		T151	1		T291	1
auto[1476395008:1610612735]	auto[0]	53	1			T25	1		T59	1		T43	1
auto[1476395008:1610612735]	auto[1]	68	1			T44	1		T199	1		T133	1
auto[1610612736:1744830463]	auto[0]	42	1			T131	1		T51	1		T101	1
auto[1610612736:1744830463]	auto[1]	44	1			T29	1		T101	1		T8	1
auto[1744830464:1879048191]	auto[0]	45	1			T6	1		T101	1		T54	2
auto[1744830464:1879048191]	auto[1]	60	1			T3	1		T20	1		T6	1
auto[1879048192:2013265919]	auto[0]	54	1			T30	1		T131	1		T206	1
auto[1879048192:2013265919]	auto[1]	57	1			T55	1		T133	1		T26	1
auto[2013265920:2147483647]	auto[0]	50	1			T6	1		T55	1		T131	1
auto[2013265920:2147483647]	auto[1]	56	1			T61	1		T155	1		T278	1
auto[2147483648:2281701375]	auto[0]	53	1			T56	1		T25	1		T42	1
auto[2147483648:2281701375]	auto[1]	48	1			T151	1		T154	1		T251	1
auto[2281701376:2415919103]	auto[0]	54	1			T89	1		T134	1		T51	1
auto[2281701376:2415919103]	auto[1]	53	1			T31	1		T62	1		T54	1
auto[2415919104:2550136831]	auto[0]	45	1			T6	1		T368	1		T54	1
auto[2415919104:2550136831]	auto[1]	47	1			T127	1		T101	1		T251	1
auto[2550136832:2684354559]	auto[0]	42	1			T58	1		T7	1		T94	1
auto[2550136832:2684354559]	auto[1]	66	1			T16	1		T55	1		T60	2
auto[2684354560:2818572287]	auto[0]	50	1			T60	1		T101	1		T93	1
auto[2684354560:2818572287]	auto[1]	60	1			T55	1		T86	1		T101	1
auto[2818572288:2952790015]	auto[0]	43	1			T30	1		T69	1		T103	1
auto[2818572288:2952790015]	auto[1]	43	1			T56	1		T101	1		T152	1
auto[2952790016:3087007743]	auto[0]	68	1			T43	1		T199	1		T52	2
auto[2952790016:3087007743]	auto[1]	49	1			T31	1		T60	1		T101	1
auto[3087007744:3221225471]	auto[0]	43	1			T6	1		T59	1		T42	1
auto[3087007744:3221225471]	auto[1]	58	1			T55	1		T85	1		T21	1
auto[3221225472:3355443199]	auto[0]	46	1			T6	1		T69	1		T154	1
auto[3221225472:3355443199]	auto[1]	48	1			T3	1		T25	1		T61	1
auto[3355443200:3489660927]	auto[0]	56	1			T5	1		T58	1		T101	1
auto[3355443200:3489660927]	auto[1]	66	1			T101	1		T65	1		T256	1
auto[3489660928:3623878655]	auto[0]	43	1			T25	1		T89	1		T62	2
auto[3489660928:3623878655]	auto[1]	54	1			T127	1		T44	1		T62	2
auto[3623878656:3758096383]	auto[0]	45	1			T30	1		T89	1		T42	1
auto[3623878656:3758096383]	auto[1]	37	1			T29	1		T43	1		T217	1
auto[3758096384:3892314111]	auto[0]	42	1			T86	1		T51	1		T207	1
auto[3758096384:3892314111]	auto[1]	51	1			T60	2		T101	1		T93	1
auto[3892314112:4026531839]	auto[0]	49	1			T29	1		T31	1		T43	1
auto[3892314112:4026531839]	auto[1]	63	1			T58	1		T25	1		T199	1
auto[4026531840:4160749567]	auto[0]	40	1			T58	1		T42	1		T43	1
auto[4026531840:4160749567]	auto[1]	60	1			T5	1		T6	1		T89	1
auto[4160749568:4294967295]	auto[0]	53	1			T6	1		T25	1		T101	1
auto[4160749568:4294967295]	auto[1]	46	1			T56	1		T45	1		T65	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1531

1

T5

1

T6

7

T29

1

auto[1]

1741

1

T3

2

T16

2

T5

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	109	1			T89	1		T60	1		T101	2
auto[134217728:268435455]	103	1			T20	1		T58	1		T43	1
auto[268435456:402653183]	95	1			T42	1		T93	1		T79	1
auto[402653184:536870911]	97	1			T89	1		T133	1		T101	1
auto[536870912:671088639]	104	1			T6	1		T199	2		T60	1
auto[671088640:805306367]	112	1			T6	1		T25	1		T42	1
auto[805306368:939524095]	91	1			T127	1		T56	1		T30	1
auto[939524096:1073741823]	105	1			T58	1		T25	1		T42	1
auto[1073741824:1207959551]	89	1			T6	1		T25	1		T89	1
auto[1207959552:1342177279]	111	1			T3	1		T6	1		T30	1
auto[1342177280:1476395007]	112	1			T5	1		T6	1		T133	1
auto[1476395008:1610612735]	93	1			T6	1		T43	1		T60	2
auto[1610612736:1744830463]	109	1			T25	1		T30	1		T89	1
auto[1744830464:1879048191]	122	1			T85	1		T43	2		T131	1
auto[1879048192:2013265919]	97	1			T29	1		T59	1		T43	1
auto[2013265920:2147483647]	96	1			T5	1		T127	1		T58	1
auto[2147483648:2281701375]	103	1			T56	1		T86	1		T89	1
auto[2281701376:2415919103]	83	1			T6	1		T29	1		T30	1
auto[2415919104:2550136831]	102	1			T86	1		T89	1		T26	1
auto[2550136832:2684354559]	111	1			T16	1		T5	1		T6	1
auto[2684354560:2818572287]	114	1			T25	1		T31	2		T60	1
auto[2818572288:2952790015]	89	1			T127	1		T55	1		T60	1
auto[2952790016:3087007743]	106	1			T29	1		T55	2		T56	1
auto[3087007744:3221225471]	110	1			T29	1		T44	1		T25	1
auto[3221225472:3355443199]	94	1			T86	1		T27	1		T256	1
auto[3355443200:3489660927]	107	1			T55	1		T44	1		T86	1
auto[3489660928:3623878655]	99	1			T30	1		T42	1		T199	1
auto[3623878656:3758096383]	90	1			T3	1		T55	1		T58	1
auto[3758096384:3892314111]	113	1			T16	1		T5	1		T42	1
auto[3892314112:4026531839]	105	1			T6	1		T29	1		T58	2
auto[4026531840:4160749567]	103	1			T6	1		T55	1		T31	1
auto[4160749568:4294967295]	98	1			T44	1		T58	1		T101	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	53	1			T60	1		T101	2		T54	1
auto[0:134217727]	auto[1]	56	1			T89	1		T54	2		T67	1
auto[134217728:268435455]	auto[0]	53	1			T58	1		T43	1		T101	1
auto[134217728:268435455]	auto[1]	50	1			T20	1		T101	2		T26	1
auto[268435456:402653183]	auto[0]	43	1			T79	1		T264	1		T386	1
auto[268435456:402653183]	auto[1]	52	1			T42	1		T93	1		T154	1
auto[402653184:536870911]	auto[0]	45	1			T89	1		T93	1		T62	1
auto[402653184:536870911]	auto[1]	52	1			T133	1		T101	1		T103	2
auto[536870912:671088639]	auto[0]	51	1			T6	1		T199	1		T60	1
auto[536870912:671088639]	auto[1]	53	1			T199	1		T8	1		T27	1
auto[671088640:805306367]	auto[0]	43	1			T6	1		T42	1		T79	1
auto[671088640:805306367]	auto[1]	69	1			T25	1		T31	1		T62	1
auto[805306368:939524095]	auto[0]	35	1			T59	1		T69	1		T54	1
auto[805306368:939524095]	auto[1]	56	1			T127	1		T56	1		T30	1
auto[939524096:1073741823]	auto[0]	52	1			T58	1		T25	1		T42	1
auto[939524096:1073741823]	auto[1]	53	1			T31	1		T45	1		T60	1
auto[1073741824:1207959551]	auto[0]	48	1			T6	1		T89	1		T77	1
auto[1073741824:1207959551]	auto[1]	41	1			T25	1		T60	1		T134	1
auto[1207959552:1342177279]	auto[0]	51	1			T6	1		T42	1		T31	1
auto[1207959552:1342177279]	auto[1]	60	1			T3	1		T30	1		T93	1
auto[1342177280:1476395007]	auto[0]	48	1			T133	1		T325	1		T54	1
auto[1342177280:1476395007]	auto[1]	64	1			T5	1		T6	1		T101	2
auto[1476395008:1610612735]	auto[0]	39	1			T43	1		T60	1		T51	1
auto[1476395008:1610612735]	auto[1]	54	1			T6	1		T60	1		T135	1
auto[1610612736:1744830463]	auto[0]	45	1			T25	1		T89	1		T154	1
auto[1610612736:1744830463]	auto[1]	64	1			T30	1		T291	1		T53	1
auto[1744830464:1879048191]	auto[0]	55	1			T43	2		T131	1		T60	1
auto[1744830464:1879048191]	auto[1]	67	1			T85	1		T101	1		T151	1
auto[1879048192:2013265919]	auto[0]	40	1			T101	2		T54	1		T107	1
auto[1879048192:2013265919]	auto[1]	57	1			T29	1		T59	1		T43	1
auto[2013265920:2147483647]	auto[0]	39	1			T127	1		T101	1		T206	2
auto[2013265920:2147483647]	auto[1]	57	1			T5	1		T58	1		T61	1
auto[2147483648:2281701375]	auto[0]	42	1			T86	1		T101	1		T52	1
auto[2147483648:2281701375]	auto[1]	61	1			T56	1		T89	1		T60	1
auto[2281701376:2415919103]	auto[0]	41	1			T6	1		T131	1		T206	1
auto[2281701376:2415919103]	auto[1]	42	1			T29	1		T30	1		T59	1
auto[2415919104:2550136831]	auto[0]	48	1			T86	1		T89	1		T94	1
auto[2415919104:2550136831]	auto[1]	54	1			T26	1		T8	1		T256	1
auto[2550136832:2684354559]	auto[0]	55	1			T6	1		T59	1		T43	1
auto[2550136832:2684354559]	auto[1]	56	1			T16	1		T5	1		T133	1
auto[2684354560:2818572287]	auto[0]	54	1			T25	1		T31	2		T101	1
auto[2684354560:2818572287]	auto[1]	60	1			T60	1		T135	2		T291	1
auto[2818572288:2952790015]	auto[0]	44	1			T55	1		T101	1		T54	1
auto[2818572288:2952790015]	auto[1]	45	1			T127	1		T60	1		T53	1
auto[2952790016:3087007743]	auto[0]	55	1			T29	1		T55	1		T52	2
auto[2952790016:3087007743]	auto[1]	51	1			T55	1		T56	1		T53	1
auto[3087007744:3221225471]	auto[0]	63	1			T25	1		T101	1		T27	1
auto[3087007744:3221225471]	auto[1]	47	1			T29	1		T44	1		T135	1
auto[3221225472:3355443199]	auto[0]	49	1			T86	1		T256	1		T54	1
auto[3221225472:3355443199]	auto[1]	45	1			T27	1		T136	1		T259	1
auto[3355443200:3489660927]	auto[0]	47	1			T55	1		T86	1		T60	1
auto[3355443200:3489660927]	auto[1]	60	1			T44	1		T31	1		T60	1
auto[3489660928:3623878655]	auto[0]	43	1			T30	1		T42	1		T199	1
auto[3489660928:3623878655]	auto[1]	56	1			T26	1		T207	2		T299	1
auto[3623878656:3758096383]	auto[0]	43	1			T58	1		T56	1		T59	1
auto[3623878656:3758096383]	auto[1]	47	1			T3	1		T55	1		T65	1
auto[3758096384:3892314111]	auto[0]	52	1			T5	1		T42	1		T60	1
auto[3758096384:3892314111]	auto[1]	61	1			T16	1		T61	1		T199	1
auto[3892314112:4026531839]	auto[0]	53	1			T6	1		T58	2		T30	1
auto[3892314112:4026531839]	auto[1]	52	1			T29	1		T135	1		T52	1
auto[4026531840:4160749567]	auto[0]	55	1			T55	1		T31	1		T101	1
auto[4026531840:4160749567]	auto[1]	48	1			T6	1		T43	1		T103	1
auto[4160749568:4294967295]	auto[0]	47	1			T58	1		T101	1		T151	1
auto[4160749568:4294967295]	auto[1]	51	1			T44	1		T151	1		T27	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1518

1

T5

2

T20

1

T6

8

auto[1]

1756

1

T3

2

T16

2

T5

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	107	1			T58	2		T25	1		T42	1
auto[134217728:268435455]	109	1			T44	1		T133	1		T134	1
auto[268435456:402653183]	90	1			T127	1		T61	1		T101	1
auto[402653184:536870911]	113	1			T6	1		T58	1		T59	1
auto[536870912:671088639]	93	1			T58	1		T89	2		T61	1
auto[671088640:805306367]	99	1			T20	1		T6	1		T31	1
auto[805306368:939524095]	112	1			T29	1		T55	1		T86	2
auto[939524096:1073741823]	100	1			T6	1		T29	1		T30	1
auto[1073741824:1207959551]	107	1			T16	1		T5	1		T44	1
auto[1207959552:1342177279]	95	1			T5	1		T6	1		T31	1
auto[1342177280:1476395007]	106	1			T25	1		T59	1		T199	1
auto[1476395008:1610612735]	101	1			T29	1		T127	1		T21	1
auto[1610612736:1744830463]	119	1			T31	1		T131	1		T21	1
auto[1744830464:1879048191]	101	1			T55	2		T30	1		T31	1
auto[1879048192:2013265919]	98	1			T6	1		T56	1		T86	1
auto[2013265920:2147483647]	106	1			T25	1		T30	1		T59	1
auto[2147483648:2281701375]	115	1			T6	1		T29	1		T89	2
auto[2281701376:2415919103]	90	1			T131	1		T101	3		T54	2
auto[2415919104:2550136831]	113	1			T56	1		T85	1		T86	1
auto[2550136832:2684354559]	84	1			T5	1		T43	1		T60	4
auto[2684354560:2818572287]	115	1			T6	1		T56	1		T133	1
auto[2818572288:2952790015]	100	1			T16	1		T44	1		T43	1
auto[2952790016:3087007743]	98	1			T58	1		T30	1		T199	1
auto[3087007744:3221225471]	115	1			T3	1		T55	1		T30	1
auto[3221225472:3355443199]	104	1			T42	1		T31	1		T43	1
auto[3355443200:3489660927]	96	1			T127	1		T101	1		T62	1
auto[3489660928:3623878655]	87	1			T6	1		T56	1		T25	1
auto[3623878656:3758096383]	98	1			T55	2		T101	1		T206	1
auto[3758096384:3892314111]	110	1			T3	1		T29	1		T60	2
auto[3892314112:4026531839]	84	1			T58	1		T42	1		T199	1
auto[4026531840:4160749567]	101	1			T6	1		T101	2		T206	1
auto[4160749568:4294967295]	108	1			T5	1		T6	1		T58	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	53	1			T58	2		T25	1		T42	1
auto[0:134217727]	auto[1]	54	1			T153	1		T103	1		T77	1
auto[134217728:268435455]	auto[0]	47	1			T134	1		T52	1		T94	1
auto[134217728:268435455]	auto[1]	62	1			T44	1		T133	1		T101	2
auto[268435456:402653183]	auto[0]	42	1			T101	1		T7	2		T27	1
auto[268435456:402653183]	auto[1]	48	1			T127	1		T61	1		T62	1
auto[402653184:536870911]	auto[0]	55	1			T6	1		T58	1		T59	1
auto[402653184:536870911]	auto[1]	58	1			T151	1		T152	1		T22	1
auto[536870912:671088639]	auto[0]	41	1			T58	1		T89	2		T101	1
auto[536870912:671088639]	auto[1]	52	1			T61	1		T101	1		T152	1
auto[671088640:805306367]	auto[0]	52	1			T20	1		T6	1		T60	1
auto[671088640:805306367]	auto[1]	47	1			T31	1		T199	1		T103	2
auto[805306368:939524095]	auto[0]	46	1			T29	1		T86	2		T256	2
auto[805306368:939524095]	auto[1]	66	1			T55	1		T42	2		T368	1
auto[939524096:1073741823]	auto[0]	49	1			T6	1		T30	1		T59	1
auto[939524096:1073741823]	auto[1]	51	1			T29	1		T31	1		T151	2
auto[1073741824:1207959551]	auto[0]	54	1			T25	1		T43	1		T131	1
auto[1073741824:1207959551]	auto[1]	53	1			T16	1		T5	1		T44	1
auto[1207959552:1342177279]	auto[0]	42	1			T31	1		T101	1		T65	1
auto[1207959552:1342177279]	auto[1]	53	1			T5	1		T6	1		T62	1
auto[1342177280:1476395007]	auto[0]	48	1			T25	1		T199	1		T101	1
auto[1342177280:1476395007]	auto[1]	58	1			T59	1		T60	1		T325	1
auto[1476395008:1610612735]	auto[0]	55	1			T62	1		T206	1		T251	1
auto[1476395008:1610612735]	auto[1]	46	1			T29	1		T127	1		T21	1
auto[1610612736:1744830463]	auto[0]	58	1			T31	1		T131	1		T101	1
auto[1610612736:1744830463]	auto[1]	61	1			T21	1		T93	1		T77	1
auto[1744830464:1879048191]	auto[0]	45	1			T55	1		T60	1		T101	2
auto[1744830464:1879048191]	auto[1]	56	1			T55	1		T30	1		T31	1
auto[1879048192:2013265919]	auto[0]	42	1			T6	1		T86	1		T101	1
auto[1879048192:2013265919]	auto[1]	56	1			T56	1		T43	1		T199	1
auto[2013265920:2147483647]	auto[0]	40	1			T25	1		T30	1		T59	1
auto[2013265920:2147483647]	auto[1]	66	1			T101	2		T26	1		T79	1
auto[2147483648:2281701375]	auto[0]	46	1			T7	1		T93	1		T27	1
auto[2147483648:2281701375]	auto[1]	69	1			T6	1		T29	1		T89	2
auto[2281701376:2415919103]	auto[0]	40	1			T131	1		T101	1		T54	1
auto[2281701376:2415919103]	auto[1]	50	1			T101	2		T54	1		T251	1
auto[2415919104:2550136831]	auto[0]	46	1			T42	1		T101	1		T103	1
auto[2415919104:2550136831]	auto[1]	67	1			T56	1		T85	1		T86	1
auto[2550136832:2684354559]	auto[0]	39	1			T5	1		T60	3		T264	1
auto[2550136832:2684354559]	auto[1]	45	1			T43	1		T60	1		T101	2
auto[2684354560:2818572287]	auto[0]	51	1			T6	1		T56	1		T133	1
auto[2684354560:2818572287]	auto[1]	64	1			T154	1		T54	2		T38	1
auto[2818572288:2952790015]	auto[0]	40	1			T62	1		T207	1		T54	1
auto[2818572288:2952790015]	auto[1]	60	1			T16	1		T44	1		T43	1
auto[2952790016:3087007743]	auto[0]	48	1			T58	1		T199	1		T154	1
auto[2952790016:3087007743]	auto[1]	50	1			T30	1		T51	1		T325	1
auto[3087007744:3221225471]	auto[0]	50	1			T55	1		T59	1		T60	1
auto[3087007744:3221225471]	auto[1]	65	1			T3	1		T30	1		T60	1
auto[3221225472:3355443199]	auto[0]	53	1			T42	1		T31	1		T43	1
auto[3221225472:3355443199]	auto[1]	51	1			T101	1		T152	1		T27	1
auto[3355443200:3489660927]	auto[0]	48	1			T127	1		T101	1		T69	1
auto[3355443200:3489660927]	auto[1]	48	1			T62	1		T208	1		T54	1
auto[3489660928:3623878655]	auto[0]	50	1			T6	1		T56	1		T25	1
auto[3489660928:3623878655]	auto[1]	37	1			T135	1		T101	1		T54	1
auto[3623878656:3758096383]	auto[0]	44	1			T55	2		T101	1		T206	1
auto[3623878656:3758096383]	auto[1]	54	1			T207	1		T217	1		T68	2
auto[3758096384:3892314111]	auto[0]	49	1			T52	2		T264	1		T54	1
auto[3758096384:3892314111]	auto[1]	61	1			T3	1		T29	1		T60	2
auto[3892314112:4026531839]	auto[0]	43	1			T42	1		T199	1		T60	2
auto[3892314112:4026531839]	auto[1]	41	1			T58	1		T325	1		T207	1
auto[4026531840:4160749567]	auto[0]	46	1			T6	1		T101	1		T206	1
auto[4026531840:4160749567]	auto[1]	55	1			T101	1		T264	1		T256	1
auto[4160749568:4294967295]	auto[0]	56	1			T5	1		T6	1		T58	1
auto[4160749568:4294967295]	auto[1]	52	1			T135	1		T62	1		T153	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1525

1

T3

1

T20

1

T6

8

auto[1]

1747

1

T3

1

T16

2

T5

4