Unified Coverage Report :: Group Instance : salt_6

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2818

1

T3

2

T16

2

T5

4

auto[1]

277

1

T131

9

T151

6

T152

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	105	1			T6	1		T29	1		T56	1
auto[134217728:268435455]	85	1			T42	1		T131	1		T101	2
auto[268435456:402653183]	91	1			T30	1		T60	1		T101	2
auto[402653184:536870911]	86	1			T16	1		T5	1		T20	1
auto[536870912:671088639]	86	1			T30	1		T89	2		T60	1
auto[671088640:805306367]	113	1			T55	1		T25	2		T152	1
auto[805306368:939524095]	90	1			T6	1		T29	1		T151	1
auto[939524096:1073741823]	85	1			T42	1		T135	1		T101	1
auto[1073741824:1207959551]	105	1			T6	1		T131	1		T60	1
auto[1207959552:1342177279]	96	1			T127	1		T21	1		T60	2
auto[1342177280:1476395007]	99	1			T58	1		T56	1		T42	1
auto[1476395008:1610612735]	95	1			T16	1		T6	1		T86	1
auto[1610612736:1744830463]	103	1			T127	1		T43	1		T199	1
auto[1744830464:1879048191]	103	1			T29	1		T127	1		T199	2
auto[1879048192:2013265919]	100	1			T25	2		T101	1		T151	1
auto[2013265920:2147483647]	98	1			T6	1		T29	1		T56	1
auto[2147483648:2281701375]	99	1			T3	2		T55	1		T31	2
auto[2281701376:2415919103]	94	1			T5	1		T55	1		T30	1
auto[2415919104:2550136831]	107	1			T86	1		T30	1		T60	2
auto[2550136832:2684354559]	126	1			T5	1		T30	1		T43	1
auto[2684354560:2818572287]	103	1			T6	1		T55	1		T89	1
auto[2818572288:2952790015]	89	1			T55	1		T43	1		T199	1
auto[2952790016:3087007743]	85	1			T31	1		T131	1		T101	1
auto[3087007744:3221225471]	83	1			T131	1		T60	1		T62	1
auto[3221225472:3355443199]	118	1			T89	1		T59	1		T43	1
auto[3355443200:3489660927]	101	1			T6	1		T44	1		T89	1
auto[3489660928:3623878655]	94	1			T5	1		T6	1		T44	2
auto[3623878656:3758096383]	83	1			T55	1		T60	1		T101	1
auto[3758096384:3892314111]	97	1			T60	1		T101	1		T94	1
auto[3892314112:4026531839]	97	1			T86	1		T25	1		T43	1
auto[4026531840:4160749567]	91	1			T6	1		T29	1		T56	1
auto[4160749568:4294967295]	88	1			T61	1		T199	1		T101	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	97	1			T6	1		T29	1		T56	1
auto[0:134217727]	auto[1]	8	1			T151	1		T153	1		T249	1
auto[134217728:268435455]	auto[0]	81	1			T42	1		T131	1		T101	2
auto[134217728:268435455]	auto[1]	4	1			T141	1		T243	1		T404	1
auto[268435456:402653183]	auto[0]	85	1			T30	1		T60	1		T101	2
auto[268435456:402653183]	auto[1]	6	1			T153	1		T237	1		T141	1
auto[402653184:536870911]	auto[0]	76	1			T16	1		T5	1		T20	1
auto[402653184:536870911]	auto[1]	10	1			T131	1		T153	1		T237	1
auto[536870912:671088639]	auto[0]	79	1			T30	1		T89	2		T60	1
auto[536870912:671088639]	auto[1]	7	1			T151	1		T249	1		T287	1
auto[671088640:805306367]	auto[0]	98	1			T55	1		T25	2		T208	1
auto[671088640:805306367]	auto[1]	15	1			T152	1		T237	1		T243	1
auto[805306368:939524095]	auto[0]	81	1			T6	1		T29	1		T291	1
auto[805306368:939524095]	auto[1]	9	1			T151	1		T153	2		T154	1
auto[939524096:1073741823]	auto[0]	74	1			T42	1		T135	1		T101	1
auto[939524096:1073741823]	auto[1]	11	1			T153	2		T296	1		T249	1
auto[1073741824:1207959551]	auto[0]	93	1			T6	1		T60	1		T101	1
auto[1073741824:1207959551]	auto[1]	12	1			T131	1		T296	1		T237	1
auto[1207959552:1342177279]	auto[0]	88	1			T127	1		T21	1		T60	2
auto[1207959552:1342177279]	auto[1]	8	1			T153	2		T154	1		T141	1
auto[1342177280:1476395007]	auto[0]	85	1			T58	1		T56	1		T42	1
auto[1342177280:1476395007]	auto[1]	14	1			T131	2		T137	1		T249	1
auto[1476395008:1610612735]	auto[0]	86	1			T16	1		T6	1		T86	1
auto[1476395008:1610612735]	auto[1]	9	1			T154	1		T241	1		T238	1
auto[1610612736:1744830463]	auto[0]	97	1			T127	1		T43	1		T199	1
auto[1610612736:1744830463]	auto[1]	6	1			T151	2		T152	1		T137	1
auto[1744830464:1879048191]	auto[0]	97	1			T29	1		T127	1		T199	2
auto[1744830464:1879048191]	auto[1]	6	1			T391	1		T273	1		T377	1
auto[1879048192:2013265919]	auto[0]	89	1			T25	2		T101	1		T151	1
auto[1879048192:2013265919]	auto[1]	11	1			T296	1		T402	1		T374	1
auto[2013265920:2147483647]	auto[0]	90	1			T6	1		T29	1		T56	1
auto[2013265920:2147483647]	auto[1]	8	1			T154	1		T136	1		T137	1
auto[2147483648:2281701375]	auto[0]	90	1			T3	2		T55	1		T31	2
auto[2147483648:2281701375]	auto[1]	9	1			T131	1		T137	2		T297	1
auto[2281701376:2415919103]	auto[0]	86	1			T5	1		T55	1		T30	1
auto[2281701376:2415919103]	auto[1]	8	1			T131	1		T296	1		T138	1
auto[2415919104:2550136831]	auto[0]	97	1			T86	1		T30	1		T60	2
auto[2415919104:2550136831]	auto[1]	10	1			T155	1		T141	1		T374	1
auto[2550136832:2684354559]	auto[0]	116	1			T5	1		T30	1		T43	1
auto[2550136832:2684354559]	auto[1]	10	1			T154	1		T241	1		T141	1
auto[2684354560:2818572287]	auto[0]	95	1			T6	1		T55	1		T89	1
auto[2684354560:2818572287]	auto[1]	8	1			T131	1		T155	1		T408	1
auto[2818572288:2952790015]	auto[0]	82	1			T55	1		T43	1		T199	1
auto[2818572288:2952790015]	auto[1]	7	1			T152	1		T315	1		T238	1
auto[2952790016:3087007743]	auto[0]	78	1			T31	1		T101	1		T153	1
auto[2952790016:3087007743]	auto[1]	7	1			T131	1		T136	1		T237	1
auto[3087007744:3221225471]	auto[0]	71	1			T60	1		T62	1		T27	1
auto[3087007744:3221225471]	auto[1]	12	1			T131	1		T153	1		T154	1
auto[3221225472:3355443199]	auto[0]	107	1			T89	1		T59	1		T43	1
auto[3221225472:3355443199]	auto[1]	11	1			T151	1		T152	1		T153	1
auto[3355443200:3489660927]	auto[0]	92	1			T6	1		T44	1		T89	1
auto[3355443200:3489660927]	auto[1]	9	1			T153	1		T296	1		T287	1
auto[3489660928:3623878655]	auto[0]	87	1			T5	1		T6	1		T44	2
auto[3489660928:3623878655]	auto[1]	7	1			T155	1		T336	1		T374	1
auto[3623878656:3758096383]	auto[0]	74	1			T55	1		T60	1		T101	1
auto[3623878656:3758096383]	auto[1]	9	1			T138	1		T336	1		T402	1
auto[3758096384:3892314111]	auto[0]	91	1			T60	1		T101	1		T94	1
auto[3758096384:3892314111]	auto[1]	6	1			T237	1		T139	1		T309	1
auto[3892314112:4026531839]	auto[0]	90	1			T86	1		T25	1		T43	1
auto[3892314112:4026531839]	auto[1]	7	1			T138	1		T139	1		T336	1
auto[4026531840:4160749567]	auto[0]	84	1			T6	1		T29	1		T56	1
auto[4026531840:4160749567]	auto[1]	7	1			T297	1		T336	1		T287	1
auto[4160749568:4294967295]	auto[0]	82	1			T61	1		T199	1		T101	1
auto[4160749568:4294967295]	auto[1]	6	1			T153	1		T408	1		T285	2