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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1532 1 T5 2 T6 6 T29 2
auto[1] 1741 1 T3 2 T16 2 T5 2



Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 93 1 T101 1 T151 1 T325 1
auto[134217728:268435455] 79 1 T55 1 T58 1 T42 1
auto[268435456:402653183] 102 1 T60 2 T291 1 T206 1
auto[402653184:536870911] 97 1 T6 1 T31 1 T43 1
auto[536870912:671088639] 104 1 T5 1 T127 1 T58 1
auto[671088640:805306367] 108 1 T56 1 T42 1 T131 1
auto[805306368:939524095] 104 1 T6 1 T55 1 T25 1
auto[939524096:1073741823] 93 1 T20 1 T199 1 T131 1
auto[1073741824:1207959551] 111 1 T16 1 T86 1 T135 1
auto[1207959552:1342177279] 106 1 T29 1 T58 1 T59 1
auto[1342177280:1476395007] 105 1 T58 1 T31 1 T199 1
auto[1476395008:1610612735] 91 1 T5 1 T60 2 T151 1
auto[1610612736:1744830463] 118 1 T29 1 T44 1 T25 1
auto[1744830464:1879048191] 99 1 T29 1 T58 1 T30 1
auto[1879048192:2013265919] 97 1 T6 1 T55 1 T42 1
auto[2013265920:2147483647] 115 1 T55 1 T86 1 T25 2
auto[2147483648:2281701375] 100 1 T56 2 T43 1 T199 1
auto[2281701376:2415919103] 113 1 T58 1 T135 1 T101 2
auto[2415919104:2550136831] 115 1 T3 1 T6 2 T29 1
auto[2550136832:2684354559] 110 1 T30 1 T42 1 T31 1
auto[2684354560:2818572287] 99 1 T55 1 T89 1 T133 1
auto[2818572288:2952790015] 112 1 T3 1 T5 1 T127 1
auto[2952790016:3087007743] 96 1 T6 1 T29 1 T52 1
auto[3087007744:3221225471] 82 1 T85 1 T30 1 T62 1
auto[3221225472:3355443199] 120 1 T6 1 T127 1 T89 1
auto[3355443200:3489660927] 98 1 T6 2 T44 1 T25 1
auto[3489660928:3623878655] 102 1 T55 1 T30 1 T89 2
auto[3623878656:3758096383] 95 1 T58 1 T86 1 T133 1
auto[3758096384:3892314111] 108 1 T89 1 T60 1 T101 2
auto[3892314112:4026531839] 95 1 T16 1 T5 1 T6 1
auto[4026531840:4160749567] 101 1 T44 1 T60 1 T65 1
auto[4160749568:4294967295] 105 1 T43 1 T101 2 T62 1



Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 39 1 T151 1 T103 1 T77 1
auto[0:134217727] auto[1] 54 1 T101 1 T325 1 T256 1
auto[134217728:268435455] auto[0] 27 1 T58 1 T42 1 T101 2
auto[134217728:268435455] auto[1] 52 1 T55 1 T101 2 T67 1
auto[268435456:402653183] auto[0] 53 1 T60 1 T291 1 T206 1
auto[268435456:402653183] auto[1] 49 1 T60 1 T27 1 T54 1
auto[402653184:536870911] auto[0] 52 1 T6 1 T31 1 T60 1
auto[402653184:536870911] auto[1] 45 1 T43 1 T60 1 T53 1
auto[536870912:671088639] auto[0] 49 1 T5 1 T58 1 T59 1
auto[536870912:671088639] auto[1] 55 1 T127 1 T86 1 T61 1
auto[671088640:805306367] auto[0] 56 1 T56 1 T42 1 T131 1
auto[671088640:805306367] auto[1] 52 1 T54 1 T251 1 T217 1
auto[805306368:939524095] auto[0] 55 1 T55 1 T25 1 T30 1
auto[805306368:939524095] auto[1] 49 1 T6 1 T59 1 T31 1
auto[939524096:1073741823] auto[0] 36 1 T131 1 T52 1 T77 1
auto[939524096:1073741823] auto[1] 57 1 T20 1 T199 1 T101 1
auto[1073741824:1207959551] auto[0] 50 1 T86 1 T154 1 T54 2
auto[1073741824:1207959551] auto[1] 61 1 T16 1 T135 1 T51 1
auto[1207959552:1342177279] auto[0] 48 1 T58 1 T42 1 T31 1
auto[1207959552:1342177279] auto[1] 58 1 T29 1 T59 1 T133 1
auto[1342177280:1476395007] auto[0] 46 1 T58 1 T31 1 T101 1
auto[1342177280:1476395007] auto[1] 59 1 T199 1 T62 1 T154 1
auto[1476395008:1610612735] auto[0] 44 1 T60 2 T7 1 T54 3
auto[1476395008:1610612735] auto[1] 47 1 T5 1 T151 1 T152 2
auto[1610612736:1744830463] auto[0] 61 1 T25 1 T101 1 T52 1
auto[1610612736:1744830463] auto[1] 57 1 T29 1 T44 1 T199 1
auto[1744830464:1879048191] auto[0] 43 1 T29 1 T58 1 T94 1
auto[1744830464:1879048191] auto[1] 56 1 T30 1 T135 1 T251 1
auto[1879048192:2013265919] auto[0] 48 1 T6 1 T199 1 T291 1
auto[1879048192:2013265919] auto[1] 49 1 T55 1 T42 1 T45 1
auto[2013265920:2147483647] auto[0] 55 1 T55 1 T86 1 T25 2
auto[2013265920:2147483647] auto[1] 60 1 T42 1 T208 1 T54 1
auto[2147483648:2281701375] auto[0] 44 1 T56 1 T199 1 T101 1
auto[2147483648:2281701375] auto[1] 56 1 T56 1 T43 1 T101 1
auto[2281701376:2415919103] auto[0] 46 1 T58 1 T101 2 T52 1
auto[2281701376:2415919103] auto[1] 67 1 T135 1 T26 1 T54 3
auto[2415919104:2550136831] auto[0] 58 1 T6 1 T89 1 T59 1
auto[2415919104:2550136831] auto[1] 57 1 T3 1 T6 1 T29 1
auto[2550136832:2684354559] auto[0] 54 1 T30 1 T42 1 T101 1
auto[2550136832:2684354559] auto[1] 56 1 T31 1 T22 1 T8 1
auto[2684354560:2818572287] auto[0] 43 1 T55 1 T52 1 T62 1
auto[2684354560:2818572287] auto[1] 56 1 T89 1 T133 1 T21 1
auto[2818572288:2952790015] auto[0] 50 1 T127 1 T7 1 T256 1
auto[2818572288:2952790015] auto[1] 62 1 T3 1 T5 1 T56 1
auto[2952790016:3087007743] auto[0] 44 1 T29 1 T52 1 T103 1
auto[2952790016:3087007743] auto[1] 52 1 T6 1 T325 1 T54 1
auto[3087007744:3221225471] auto[0] 39 1 T153 1 T54 1 T217 2
auto[3087007744:3221225471] auto[1] 43 1 T85 1 T30 1 T62 1
auto[3221225472:3355443199] auto[0] 61 1 T6 1 T89 1 T31 1
auto[3221225472:3355443199] auto[1] 59 1 T127 1 T43 1 T101 1
auto[3355443200:3489660927] auto[0] 46 1 T6 1 T25 1 T59 1
auto[3355443200:3489660927] auto[1] 52 1 T6 1 T44 1 T31 1
auto[3489660928:3623878655] auto[0] 44 1 T55 1 T89 1 T51 1
auto[3489660928:3623878655] auto[1] 58 1 T30 1 T89 1 T61 1
auto[3623878656:3758096383] auto[0] 54 1 T86 1 T60 1 T101 2
auto[3623878656:3758096383] auto[1] 41 1 T58 1 T133 1 T93 1
auto[3758096384:3892314111] auto[0] 46 1 T89 1 T60 1 T101 2
auto[3758096384:3892314111] auto[1] 62 1 T208 1 T27 1 T38 1
auto[3892314112:4026531839] auto[0] 43 1 T5 1 T6 1 T42 1
auto[3892314112:4026531839] auto[1] 52 1 T16 1 T25 1 T101 1
auto[4026531840:4160749567] auto[0] 50 1 T7 1 T106 1 T383 1
auto[4026531840:4160749567] auto[1] 51 1 T44 1 T60 1 T65 1
auto[4160749568:4294967295] auto[0] 48 1 T43 1 T101 2 T325 1
auto[4160749568:4294967295] auto[1] 57 1 T62 1 T69 1 T155 1

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